1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Freescale eSDHC i.MX controller driver for the platform bus. 4 * 5 * derived from the OF-version. 6 * 7 * Copyright (c) 2010 Pengutronix e.K. 8 * Author: Wolfram Sang <kernel@pengutronix.de> 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/io.h> 13 #include <linux/iopoll.h> 14 #include <linux/delay.h> 15 #include <linux/err.h> 16 #include <linux/clk.h> 17 #include <linux/module.h> 18 #include <linux/slab.h> 19 #include <linux/pm_qos.h> 20 #include <linux/mmc/host.h> 21 #include <linux/mmc/mmc.h> 22 #include <linux/mmc/sdio.h> 23 #include <linux/mmc/slot-gpio.h> 24 #include <linux/of.h> 25 #include <linux/of_device.h> 26 #include <linux/pinctrl/consumer.h> 27 #include <linux/pm_runtime.h> 28 #include "sdhci-cqhci.h" 29 #include "sdhci-pltfm.h" 30 #include "sdhci-esdhc.h" 31 #include "cqhci.h" 32 33 #define ESDHC_SYS_CTRL_DTOCV_MASK 0x0f 34 #define ESDHC_CTRL_D3CD 0x08 35 #define ESDHC_BURST_LEN_EN_INCR (1 << 27) 36 /* VENDOR SPEC register */ 37 #define ESDHC_VENDOR_SPEC 0xc0 38 #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1) 39 #define ESDHC_VENDOR_SPEC_VSELECT (1 << 1) 40 #define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8) 41 #define ESDHC_DEBUG_SEL_AND_STATUS_REG 0xc2 42 #define ESDHC_DEBUG_SEL_REG 0xc3 43 #define ESDHC_DEBUG_SEL_MASK 0xf 44 #define ESDHC_DEBUG_SEL_CMD_STATE 1 45 #define ESDHC_DEBUG_SEL_DATA_STATE 2 46 #define ESDHC_DEBUG_SEL_TRANS_STATE 3 47 #define ESDHC_DEBUG_SEL_DMA_STATE 4 48 #define ESDHC_DEBUG_SEL_ADMA_STATE 5 49 #define ESDHC_DEBUG_SEL_FIFO_STATE 6 50 #define ESDHC_DEBUG_SEL_ASYNC_FIFO_STATE 7 51 #define ESDHC_WTMK_LVL 0x44 52 #define ESDHC_WTMK_DEFAULT_VAL 0x10401040 53 #define ESDHC_WTMK_LVL_RD_WML_MASK 0x000000FF 54 #define ESDHC_WTMK_LVL_RD_WML_SHIFT 0 55 #define ESDHC_WTMK_LVL_WR_WML_MASK 0x00FF0000 56 #define ESDHC_WTMK_LVL_WR_WML_SHIFT 16 57 #define ESDHC_WTMK_LVL_WML_VAL_DEF 64 58 #define ESDHC_WTMK_LVL_WML_VAL_MAX 128 59 #define ESDHC_MIX_CTRL 0x48 60 #define ESDHC_MIX_CTRL_DDREN (1 << 3) 61 #define ESDHC_MIX_CTRL_AC23EN (1 << 7) 62 #define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22) 63 #define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23) 64 #define ESDHC_MIX_CTRL_AUTO_TUNE_EN (1 << 24) 65 #define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25) 66 #define ESDHC_MIX_CTRL_HS400_EN (1 << 26) 67 #define ESDHC_MIX_CTRL_HS400_ES_EN (1 << 27) 68 /* Bits 3 and 6 are not SDHCI standard definitions */ 69 #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7 70 /* Tuning bits */ 71 #define ESDHC_MIX_CTRL_TUNING_MASK 0x03c00000 72 73 /* dll control register */ 74 #define ESDHC_DLL_CTRL 0x60 75 #define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9 76 #define ESDHC_DLL_OVERRIDE_EN_SHIFT 8 77 78 /* tune control register */ 79 #define ESDHC_TUNE_CTRL_STATUS 0x68 80 #define ESDHC_TUNE_CTRL_STEP 1 81 #define ESDHC_TUNE_CTRL_MIN 0 82 #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1) 83 84 /* strobe dll register */ 85 #define ESDHC_STROBE_DLL_CTRL 0x70 86 #define ESDHC_STROBE_DLL_CTRL_ENABLE (1 << 0) 87 #define ESDHC_STROBE_DLL_CTRL_RESET (1 << 1) 88 #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT 0x7 89 #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3 90 #define ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT (4 << 20) 91 92 #define ESDHC_STROBE_DLL_STATUS 0x74 93 #define ESDHC_STROBE_DLL_STS_REF_LOCK (1 << 1) 94 #define ESDHC_STROBE_DLL_STS_SLV_LOCK 0x1 95 96 #define ESDHC_VEND_SPEC2 0xc8 97 #define ESDHC_VEND_SPEC2_EN_BUSY_IRQ (1 << 8) 98 #define ESDHC_VEND_SPEC2_AUTO_TUNE_8BIT_EN (1 << 4) 99 #define ESDHC_VEND_SPEC2_AUTO_TUNE_4BIT_EN (0 << 4) 100 #define ESDHC_VEND_SPEC2_AUTO_TUNE_1BIT_EN (2 << 4) 101 #define ESDHC_VEND_SPEC2_AUTO_TUNE_CMD_EN (1 << 6) 102 #define ESDHC_VEND_SPEC2_AUTO_TUNE_MODE_MASK (7 << 4) 103 104 #define ESDHC_TUNING_CTRL 0xcc 105 #define ESDHC_STD_TUNING_EN (1 << 24) 106 /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */ 107 #define ESDHC_TUNING_START_TAP_DEFAULT 0x1 108 #define ESDHC_TUNING_START_TAP_MASK 0x7f 109 #define ESDHC_TUNING_CMD_CRC_CHECK_DISABLE (1 << 7) 110 #define ESDHC_TUNING_STEP_MASK 0x00070000 111 #define ESDHC_TUNING_STEP_SHIFT 16 112 113 /* pinctrl state */ 114 #define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz" 115 #define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz" 116 117 /* 118 * Our interpretation of the SDHCI_HOST_CONTROL register 119 */ 120 #define ESDHC_CTRL_4BITBUS (0x1 << 1) 121 #define ESDHC_CTRL_8BITBUS (0x2 << 1) 122 #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1) 123 #define USDHC_GET_BUSWIDTH(c) (c & ESDHC_CTRL_BUSWIDTH_MASK) 124 125 /* 126 * There is an INT DMA ERR mismatch between eSDHC and STD SDHC SPEC: 127 * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design, 128 * but bit28 is used as the INT DMA ERR in fsl eSDHC design. 129 * Define this macro DMA error INT for fsl eSDHC 130 */ 131 #define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28) 132 133 /* the address offset of CQHCI */ 134 #define ESDHC_CQHCI_ADDR_OFFSET 0x100 135 136 /* 137 * The CMDTYPE of the CMD register (offset 0xE) should be set to 138 * "11" when the STOP CMD12 is issued on imx53 to abort one 139 * open ended multi-blk IO. Otherwise the TC INT wouldn't 140 * be generated. 141 * In exact block transfer, the controller doesn't complete the 142 * operations automatically as required at the end of the 143 * transfer and remains on hold if the abort command is not sent. 144 * As a result, the TC flag is not asserted and SW received timeout 145 * exception. Bit1 of Vendor Spec register is used to fix it. 146 */ 147 #define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1) 148 /* 149 * The flag tells that the ESDHC controller is an USDHC block that is 150 * integrated on the i.MX6 series. 151 */ 152 #define ESDHC_FLAG_USDHC BIT(3) 153 /* The IP supports manual tuning process */ 154 #define ESDHC_FLAG_MAN_TUNING BIT(4) 155 /* The IP supports standard tuning process */ 156 #define ESDHC_FLAG_STD_TUNING BIT(5) 157 /* The IP has SDHCI_CAPABILITIES_1 register */ 158 #define ESDHC_FLAG_HAVE_CAP1 BIT(6) 159 /* 160 * The IP has erratum ERR004536 161 * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow, 162 * when reading data from the card 163 * This flag is also set for i.MX25 and i.MX35 in order to get 164 * SDHCI_QUIRK_BROKEN_ADMA, but for different reasons (ADMA capability bits). 165 */ 166 #define ESDHC_FLAG_ERR004536 BIT(7) 167 /* The IP supports HS200 mode */ 168 #define ESDHC_FLAG_HS200 BIT(8) 169 /* The IP supports HS400 mode */ 170 #define ESDHC_FLAG_HS400 BIT(9) 171 /* 172 * The IP has errata ERR010450 173 * uSDHC: Due to the I/O timing limit, for SDR mode, SD card clock can't 174 * exceed 150MHz, for DDR mode, SD card clock can't exceed 45MHz. 175 */ 176 #define ESDHC_FLAG_ERR010450 BIT(10) 177 /* The IP supports HS400ES mode */ 178 #define ESDHC_FLAG_HS400_ES BIT(11) 179 /* The IP has Host Controller Interface for Command Queuing */ 180 #define ESDHC_FLAG_CQHCI BIT(12) 181 /* need request pmqos during low power */ 182 #define ESDHC_FLAG_PMQOS BIT(13) 183 /* The IP state got lost in low power mode */ 184 #define ESDHC_FLAG_STATE_LOST_IN_LPMODE BIT(14) 185 /* The IP lost clock rate in PM_RUNTIME */ 186 #define ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME BIT(15) 187 /* 188 * The IP do not support the ACMD23 feature completely when use ADMA mode. 189 * In ADMA mode, it only use the 16 bit block count of the register 0x4 190 * (BLOCK_ATT) as the CMD23's argument for ACMD23 mode, which means it will 191 * ignore the upper 16 bit of the CMD23's argument. This will block the reliable 192 * write operation in RPMB, because RPMB reliable write need to set the bit31 193 * of the CMD23's argument. 194 * imx6qpdl/imx6sx/imx6sl/imx7d has this limitation only for ADMA mode, SDMA 195 * do not has this limitation. so when these SoC use ADMA mode, it need to 196 * disable the ACMD23 feature. 197 */ 198 #define ESDHC_FLAG_BROKEN_AUTO_CMD23 BIT(16) 199 200 /* ERR004536 is not applicable for the IP */ 201 #define ESDHC_FLAG_SKIP_ERR004536 BIT(17) 202 203 enum wp_types { 204 ESDHC_WP_NONE, /* no WP, neither controller nor gpio */ 205 ESDHC_WP_CONTROLLER, /* mmc controller internal WP */ 206 ESDHC_WP_GPIO, /* external gpio pin for WP */ 207 }; 208 209 enum cd_types { 210 ESDHC_CD_NONE, /* no CD, neither controller nor gpio */ 211 ESDHC_CD_CONTROLLER, /* mmc controller internal CD */ 212 ESDHC_CD_GPIO, /* external gpio pin for CD */ 213 ESDHC_CD_PERMANENT, /* no CD, card permanently wired to host */ 214 }; 215 216 /* 217 * struct esdhc_platform_data - platform data for esdhc on i.MX 218 * 219 * ESDHC_WP(CD)_CONTROLLER type is not available on i.MX25/35. 220 * 221 * @wp_type: type of write_protect method (see wp_types enum above) 222 * @cd_type: type of card_detect method (see cd_types enum above) 223 */ 224 225 struct esdhc_platform_data { 226 enum wp_types wp_type; 227 enum cd_types cd_type; 228 int max_bus_width; 229 unsigned int delay_line; 230 unsigned int tuning_step; /* The delay cell steps in tuning procedure */ 231 unsigned int tuning_start_tap; /* The start delay cell point in tuning procedure */ 232 unsigned int strobe_dll_delay_target; /* The delay cell for strobe pad (read clock) */ 233 }; 234 235 struct esdhc_soc_data { 236 u32 flags; 237 }; 238 239 static const struct esdhc_soc_data esdhc_imx25_data = { 240 .flags = ESDHC_FLAG_ERR004536, 241 }; 242 243 static const struct esdhc_soc_data esdhc_imx35_data = { 244 .flags = ESDHC_FLAG_ERR004536, 245 }; 246 247 static const struct esdhc_soc_data esdhc_imx51_data = { 248 .flags = 0, 249 }; 250 251 static const struct esdhc_soc_data esdhc_imx53_data = { 252 .flags = ESDHC_FLAG_MULTIBLK_NO_INT, 253 }; 254 255 static const struct esdhc_soc_data usdhc_imx6q_data = { 256 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING 257 | ESDHC_FLAG_BROKEN_AUTO_CMD23, 258 }; 259 260 static const struct esdhc_soc_data usdhc_imx6sl_data = { 261 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 262 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536 263 | ESDHC_FLAG_HS200 264 | ESDHC_FLAG_BROKEN_AUTO_CMD23, 265 }; 266 267 static const struct esdhc_soc_data usdhc_imx6sll_data = { 268 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 269 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 270 | ESDHC_FLAG_HS400 271 | ESDHC_FLAG_STATE_LOST_IN_LPMODE, 272 }; 273 274 static const struct esdhc_soc_data usdhc_imx6sx_data = { 275 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 276 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 277 | ESDHC_FLAG_STATE_LOST_IN_LPMODE 278 | ESDHC_FLAG_BROKEN_AUTO_CMD23, 279 }; 280 281 static const struct esdhc_soc_data usdhc_imx6ull_data = { 282 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 283 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 284 | ESDHC_FLAG_ERR010450 285 | ESDHC_FLAG_STATE_LOST_IN_LPMODE, 286 }; 287 288 static const struct esdhc_soc_data usdhc_imx7d_data = { 289 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 290 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 291 | ESDHC_FLAG_HS400 292 | ESDHC_FLAG_STATE_LOST_IN_LPMODE 293 | ESDHC_FLAG_BROKEN_AUTO_CMD23, 294 }; 295 296 static struct esdhc_soc_data usdhc_s32g2_data = { 297 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING 298 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 299 | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES 300 | ESDHC_FLAG_SKIP_ERR004536, 301 }; 302 303 static struct esdhc_soc_data usdhc_imx7ulp_data = { 304 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 305 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 306 | ESDHC_FLAG_PMQOS | ESDHC_FLAG_HS400 307 | ESDHC_FLAG_STATE_LOST_IN_LPMODE, 308 }; 309 static struct esdhc_soc_data usdhc_imxrt1050_data = { 310 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 311 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200, 312 }; 313 314 static struct esdhc_soc_data usdhc_imx8qxp_data = { 315 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 316 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 317 | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES 318 | ESDHC_FLAG_STATE_LOST_IN_LPMODE 319 | ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME, 320 }; 321 322 static struct esdhc_soc_data usdhc_imx8mm_data = { 323 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 324 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 325 | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES 326 | ESDHC_FLAG_STATE_LOST_IN_LPMODE, 327 }; 328 329 struct pltfm_imx_data { 330 u32 scratchpad; 331 struct pinctrl *pinctrl; 332 struct pinctrl_state *pins_100mhz; 333 struct pinctrl_state *pins_200mhz; 334 const struct esdhc_soc_data *socdata; 335 struct esdhc_platform_data boarddata; 336 struct clk *clk_ipg; 337 struct clk *clk_ahb; 338 struct clk *clk_per; 339 unsigned int actual_clock; 340 enum { 341 NO_CMD_PENDING, /* no multiblock command pending */ 342 MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */ 343 WAIT_FOR_INT, /* sent CMD12, waiting for response INT */ 344 } multiblock_status; 345 u32 is_ddr; 346 struct pm_qos_request pm_qos_req; 347 }; 348 349 static const struct of_device_id imx_esdhc_dt_ids[] = { 350 { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, }, 351 { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, }, 352 { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, }, 353 { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, }, 354 { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, }, 355 { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, }, 356 { .compatible = "fsl,imx6sll-usdhc", .data = &usdhc_imx6sll_data, }, 357 { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, }, 358 { .compatible = "fsl,imx6ull-usdhc", .data = &usdhc_imx6ull_data, }, 359 { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, }, 360 { .compatible = "fsl,imx7ulp-usdhc", .data = &usdhc_imx7ulp_data, }, 361 { .compatible = "fsl,imx8qxp-usdhc", .data = &usdhc_imx8qxp_data, }, 362 { .compatible = "fsl,imx8mm-usdhc", .data = &usdhc_imx8mm_data, }, 363 { .compatible = "fsl,imxrt1050-usdhc", .data = &usdhc_imxrt1050_data, }, 364 { .compatible = "nxp,s32g2-usdhc", .data = &usdhc_s32g2_data, }, 365 { /* sentinel */ } 366 }; 367 MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids); 368 369 static inline int is_imx25_esdhc(struct pltfm_imx_data *data) 370 { 371 return data->socdata == &esdhc_imx25_data; 372 } 373 374 static inline int is_imx53_esdhc(struct pltfm_imx_data *data) 375 { 376 return data->socdata == &esdhc_imx53_data; 377 } 378 379 static inline int esdhc_is_usdhc(struct pltfm_imx_data *data) 380 { 381 return !!(data->socdata->flags & ESDHC_FLAG_USDHC); 382 } 383 384 static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg) 385 { 386 void __iomem *base = host->ioaddr + (reg & ~0x3); 387 u32 shift = (reg & 0x3) * 8; 388 389 writel(((readl(base) & ~(mask << shift)) | (val << shift)), base); 390 } 391 392 #define DRIVER_NAME "sdhci-esdhc-imx" 393 #define ESDHC_IMX_DUMP(f, x...) \ 394 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x) 395 static void esdhc_dump_debug_regs(struct sdhci_host *host) 396 { 397 int i; 398 char *debug_status[7] = { 399 "cmd debug status", 400 "data debug status", 401 "trans debug status", 402 "dma debug status", 403 "adma debug status", 404 "fifo debug status", 405 "async fifo debug status" 406 }; 407 408 ESDHC_IMX_DUMP("========= ESDHC IMX DEBUG STATUS DUMP =========\n"); 409 for (i = 0; i < 7; i++) { 410 esdhc_clrset_le(host, ESDHC_DEBUG_SEL_MASK, 411 ESDHC_DEBUG_SEL_CMD_STATE + i, ESDHC_DEBUG_SEL_REG); 412 ESDHC_IMX_DUMP("%s: 0x%04x\n", debug_status[i], 413 readw(host->ioaddr + ESDHC_DEBUG_SEL_AND_STATUS_REG)); 414 } 415 416 esdhc_clrset_le(host, ESDHC_DEBUG_SEL_MASK, 0, ESDHC_DEBUG_SEL_REG); 417 418 } 419 420 static inline void esdhc_wait_for_card_clock_gate_off(struct sdhci_host *host) 421 { 422 u32 present_state; 423 int ret; 424 425 ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, present_state, 426 (present_state & ESDHC_CLOCK_GATE_OFF), 2, 100); 427 if (ret == -ETIMEDOUT) 428 dev_warn(mmc_dev(host->mmc), "%s: card clock still not gate off in 100us!.\n", __func__); 429 } 430 431 /* Enable the auto tuning circuit to check the CMD line and BUS line */ 432 static inline void usdhc_auto_tuning_mode_sel(struct sdhci_host *host) 433 { 434 u32 buswidth, auto_tune_buswidth; 435 436 buswidth = USDHC_GET_BUSWIDTH(readl(host->ioaddr + SDHCI_HOST_CONTROL)); 437 438 switch (buswidth) { 439 case ESDHC_CTRL_8BITBUS: 440 auto_tune_buswidth = ESDHC_VEND_SPEC2_AUTO_TUNE_8BIT_EN; 441 break; 442 case ESDHC_CTRL_4BITBUS: 443 auto_tune_buswidth = ESDHC_VEND_SPEC2_AUTO_TUNE_4BIT_EN; 444 break; 445 default: /* 1BITBUS */ 446 auto_tune_buswidth = ESDHC_VEND_SPEC2_AUTO_TUNE_1BIT_EN; 447 break; 448 } 449 450 esdhc_clrset_le(host, ESDHC_VEND_SPEC2_AUTO_TUNE_MODE_MASK, 451 auto_tune_buswidth | ESDHC_VEND_SPEC2_AUTO_TUNE_CMD_EN, 452 ESDHC_VEND_SPEC2); 453 } 454 455 static u32 esdhc_readl_le(struct sdhci_host *host, int reg) 456 { 457 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 458 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 459 u32 val = readl(host->ioaddr + reg); 460 461 if (unlikely(reg == SDHCI_PRESENT_STATE)) { 462 u32 fsl_prss = val; 463 /* save the least 20 bits */ 464 val = fsl_prss & 0x000FFFFF; 465 /* move dat[0-3] bits */ 466 val |= (fsl_prss & 0x0F000000) >> 4; 467 /* move cmd line bit */ 468 val |= (fsl_prss & 0x00800000) << 1; 469 } 470 471 if (unlikely(reg == SDHCI_CAPABILITIES)) { 472 /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */ 473 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) 474 val &= 0xffff0000; 475 476 /* In FSL esdhc IC module, only bit20 is used to indicate the 477 * ADMA2 capability of esdhc, but this bit is messed up on 478 * some SOCs (e.g. on MX25, MX35 this bit is set, but they 479 * don't actually support ADMA2). So set the BROKEN_ADMA 480 * quirk on MX25/35 platforms. 481 */ 482 483 if (val & SDHCI_CAN_DO_ADMA1) { 484 val &= ~SDHCI_CAN_DO_ADMA1; 485 val |= SDHCI_CAN_DO_ADMA2; 486 } 487 } 488 489 if (unlikely(reg == SDHCI_CAPABILITIES_1)) { 490 if (esdhc_is_usdhc(imx_data)) { 491 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) 492 val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF; 493 else 494 /* imx6q/dl does not have cap_1 register, fake one */ 495 val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104 496 | SDHCI_SUPPORT_SDR50 497 | SDHCI_USE_SDR50_TUNING 498 | FIELD_PREP(SDHCI_RETUNING_MODE_MASK, 499 SDHCI_TUNING_MODE_3); 500 501 /* 502 * Do not advertise faster UHS modes if there are no 503 * pinctrl states for 100MHz/200MHz. 504 */ 505 if (IS_ERR_OR_NULL(imx_data->pins_100mhz)) 506 val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50); 507 if (IS_ERR_OR_NULL(imx_data->pins_200mhz)) 508 val &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400); 509 } 510 } 511 512 if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) { 513 val = 0; 514 val |= FIELD_PREP(SDHCI_MAX_CURRENT_330_MASK, 0xFF); 515 val |= FIELD_PREP(SDHCI_MAX_CURRENT_300_MASK, 0xFF); 516 val |= FIELD_PREP(SDHCI_MAX_CURRENT_180_MASK, 0xFF); 517 } 518 519 if (unlikely(reg == SDHCI_INT_STATUS)) { 520 if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) { 521 val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR; 522 val |= SDHCI_INT_ADMA_ERROR; 523 } 524 525 /* 526 * mask off the interrupt we get in response to the manually 527 * sent CMD12 528 */ 529 if ((imx_data->multiblock_status == WAIT_FOR_INT) && 530 ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) { 531 val &= ~SDHCI_INT_RESPONSE; 532 writel(SDHCI_INT_RESPONSE, host->ioaddr + 533 SDHCI_INT_STATUS); 534 imx_data->multiblock_status = NO_CMD_PENDING; 535 } 536 } 537 538 return val; 539 } 540 541 static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg) 542 { 543 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 544 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 545 u32 data; 546 547 if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE || 548 reg == SDHCI_INT_STATUS)) { 549 if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) { 550 /* 551 * Clear and then set D3CD bit to avoid missing the 552 * card interrupt. This is an eSDHC controller problem 553 * so we need to apply the following workaround: clear 554 * and set D3CD bit will make eSDHC re-sample the card 555 * interrupt. In case a card interrupt was lost, 556 * re-sample it by the following steps. 557 */ 558 data = readl(host->ioaddr + SDHCI_HOST_CONTROL); 559 data &= ~ESDHC_CTRL_D3CD; 560 writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 561 data |= ESDHC_CTRL_D3CD; 562 writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 563 } 564 565 if (val & SDHCI_INT_ADMA_ERROR) { 566 val &= ~SDHCI_INT_ADMA_ERROR; 567 val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR; 568 } 569 } 570 571 if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 572 && (reg == SDHCI_INT_STATUS) 573 && (val & SDHCI_INT_DATA_END))) { 574 u32 v; 575 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 576 v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK; 577 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); 578 579 if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS) 580 { 581 /* send a manual CMD12 with RESPTYP=none */ 582 data = MMC_STOP_TRANSMISSION << 24 | 583 SDHCI_CMD_ABORTCMD << 16; 584 writel(data, host->ioaddr + SDHCI_TRANSFER_MODE); 585 imx_data->multiblock_status = WAIT_FOR_INT; 586 } 587 } 588 589 writel(val, host->ioaddr + reg); 590 } 591 592 static u16 esdhc_readw_le(struct sdhci_host *host, int reg) 593 { 594 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 595 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 596 u16 ret = 0; 597 u32 val; 598 599 if (unlikely(reg == SDHCI_HOST_VERSION)) { 600 reg ^= 2; 601 if (esdhc_is_usdhc(imx_data)) { 602 /* 603 * The usdhc register returns a wrong host version. 604 * Correct it here. 605 */ 606 return SDHCI_SPEC_300; 607 } 608 } 609 610 if (unlikely(reg == SDHCI_HOST_CONTROL2)) { 611 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 612 if (val & ESDHC_VENDOR_SPEC_VSELECT) 613 ret |= SDHCI_CTRL_VDD_180; 614 615 if (esdhc_is_usdhc(imx_data)) { 616 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) 617 val = readl(host->ioaddr + ESDHC_MIX_CTRL); 618 else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) 619 /* the std tuning bits is in ACMD12_ERR for imx6sl */ 620 val = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); 621 } 622 623 if (val & ESDHC_MIX_CTRL_EXE_TUNE) 624 ret |= SDHCI_CTRL_EXEC_TUNING; 625 if (val & ESDHC_MIX_CTRL_SMPCLK_SEL) 626 ret |= SDHCI_CTRL_TUNED_CLK; 627 628 ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; 629 630 return ret; 631 } 632 633 if (unlikely(reg == SDHCI_TRANSFER_MODE)) { 634 if (esdhc_is_usdhc(imx_data)) { 635 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 636 ret = m & ESDHC_MIX_CTRL_SDHCI_MASK; 637 /* Swap AC23 bit */ 638 if (m & ESDHC_MIX_CTRL_AC23EN) { 639 ret &= ~ESDHC_MIX_CTRL_AC23EN; 640 ret |= SDHCI_TRNS_AUTO_CMD23; 641 } 642 } else { 643 ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE); 644 } 645 646 return ret; 647 } 648 649 return readw(host->ioaddr + reg); 650 } 651 652 static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) 653 { 654 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 655 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 656 u32 new_val = 0; 657 658 switch (reg) { 659 case SDHCI_CLOCK_CONTROL: 660 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 661 if (val & SDHCI_CLOCK_CARD_EN) 662 new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; 663 else 664 new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; 665 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); 666 if (!(new_val & ESDHC_VENDOR_SPEC_FRC_SDCLK_ON)) 667 esdhc_wait_for_card_clock_gate_off(host); 668 return; 669 case SDHCI_HOST_CONTROL2: 670 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 671 if (val & SDHCI_CTRL_VDD_180) 672 new_val |= ESDHC_VENDOR_SPEC_VSELECT; 673 else 674 new_val &= ~ESDHC_VENDOR_SPEC_VSELECT; 675 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); 676 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 677 u32 v = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); 678 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 679 if (val & SDHCI_CTRL_TUNED_CLK) { 680 v |= ESDHC_MIX_CTRL_SMPCLK_SEL; 681 } else { 682 v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 683 m &= ~ESDHC_MIX_CTRL_FBCLK_SEL; 684 m &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN; 685 } 686 687 if (val & SDHCI_CTRL_EXEC_TUNING) { 688 v |= ESDHC_MIX_CTRL_EXE_TUNE; 689 m |= ESDHC_MIX_CTRL_FBCLK_SEL; 690 m |= ESDHC_MIX_CTRL_AUTO_TUNE_EN; 691 usdhc_auto_tuning_mode_sel(host); 692 } else { 693 v &= ~ESDHC_MIX_CTRL_EXE_TUNE; 694 } 695 696 writel(v, host->ioaddr + SDHCI_AUTO_CMD_STATUS); 697 writel(m, host->ioaddr + ESDHC_MIX_CTRL); 698 } 699 return; 700 case SDHCI_TRANSFER_MODE: 701 if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 702 && (host->cmd->opcode == SD_IO_RW_EXTENDED) 703 && (host->cmd->data->blocks > 1) 704 && (host->cmd->data->flags & MMC_DATA_READ)) { 705 u32 v; 706 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 707 v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK; 708 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); 709 } 710 711 if (esdhc_is_usdhc(imx_data)) { 712 u32 wml; 713 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 714 /* Swap AC23 bit */ 715 if (val & SDHCI_TRNS_AUTO_CMD23) { 716 val &= ~SDHCI_TRNS_AUTO_CMD23; 717 val |= ESDHC_MIX_CTRL_AC23EN; 718 } 719 m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK); 720 writel(m, host->ioaddr + ESDHC_MIX_CTRL); 721 722 /* Set watermark levels for PIO access to maximum value 723 * (128 words) to accommodate full 512 bytes buffer. 724 * For DMA access restore the levels to default value. 725 */ 726 m = readl(host->ioaddr + ESDHC_WTMK_LVL); 727 if (val & SDHCI_TRNS_DMA) { 728 wml = ESDHC_WTMK_LVL_WML_VAL_DEF; 729 } else { 730 u8 ctrl; 731 wml = ESDHC_WTMK_LVL_WML_VAL_MAX; 732 733 /* 734 * Since already disable DMA mode, so also need 735 * to clear the DMASEL. Otherwise, for standard 736 * tuning, when send tuning command, usdhc will 737 * still prefetch the ADMA script from wrong 738 * DMA address, then we will see IOMMU report 739 * some error which show lack of TLB mapping. 740 */ 741 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 742 ctrl &= ~SDHCI_CTRL_DMA_MASK; 743 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 744 } 745 m &= ~(ESDHC_WTMK_LVL_RD_WML_MASK | 746 ESDHC_WTMK_LVL_WR_WML_MASK); 747 m |= (wml << ESDHC_WTMK_LVL_RD_WML_SHIFT) | 748 (wml << ESDHC_WTMK_LVL_WR_WML_SHIFT); 749 writel(m, host->ioaddr + ESDHC_WTMK_LVL); 750 } else { 751 /* 752 * Postpone this write, we must do it together with a 753 * command write that is down below. 754 */ 755 imx_data->scratchpad = val; 756 } 757 return; 758 case SDHCI_COMMAND: 759 if (host->cmd->opcode == MMC_STOP_TRANSMISSION) 760 val |= SDHCI_CMD_ABORTCMD; 761 762 if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) && 763 (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)) 764 imx_data->multiblock_status = MULTIBLK_IN_PROCESS; 765 766 if (esdhc_is_usdhc(imx_data)) 767 writel(val << 16, 768 host->ioaddr + SDHCI_TRANSFER_MODE); 769 else 770 writel(val << 16 | imx_data->scratchpad, 771 host->ioaddr + SDHCI_TRANSFER_MODE); 772 return; 773 case SDHCI_BLOCK_SIZE: 774 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0); 775 break; 776 } 777 esdhc_clrset_le(host, 0xffff, val, reg); 778 } 779 780 static u8 esdhc_readb_le(struct sdhci_host *host, int reg) 781 { 782 u8 ret; 783 u32 val; 784 785 switch (reg) { 786 case SDHCI_HOST_CONTROL: 787 val = readl(host->ioaddr + reg); 788 789 ret = val & SDHCI_CTRL_LED; 790 ret |= (val >> 5) & SDHCI_CTRL_DMA_MASK; 791 ret |= (val & ESDHC_CTRL_4BITBUS); 792 ret |= (val & ESDHC_CTRL_8BITBUS) << 3; 793 return ret; 794 } 795 796 return readb(host->ioaddr + reg); 797 } 798 799 static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) 800 { 801 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 802 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 803 u32 new_val = 0; 804 u32 mask; 805 806 switch (reg) { 807 case SDHCI_POWER_CONTROL: 808 /* 809 * FSL put some DMA bits here 810 * If your board has a regulator, code should be here 811 */ 812 return; 813 case SDHCI_HOST_CONTROL: 814 /* FSL messed up here, so we need to manually compose it. */ 815 new_val = val & SDHCI_CTRL_LED; 816 /* ensure the endianness */ 817 new_val |= ESDHC_HOST_CONTROL_LE; 818 /* bits 8&9 are reserved on mx25 */ 819 if (!is_imx25_esdhc(imx_data)) { 820 /* DMA mode bits are shifted */ 821 new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5; 822 } 823 824 /* 825 * Do not touch buswidth bits here. This is done in 826 * esdhc_pltfm_bus_width. 827 * Do not touch the D3CD bit either which is used for the 828 * SDIO interrupt erratum workaround. 829 */ 830 mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD); 831 832 esdhc_clrset_le(host, mask, new_val, reg); 833 return; 834 case SDHCI_SOFTWARE_RESET: 835 if (val & SDHCI_RESET_DATA) 836 new_val = readl(host->ioaddr + SDHCI_HOST_CONTROL); 837 break; 838 } 839 esdhc_clrset_le(host, 0xff, val, reg); 840 841 if (reg == SDHCI_SOFTWARE_RESET) { 842 if (val & SDHCI_RESET_ALL) { 843 /* 844 * The esdhc has a design violation to SDHC spec which 845 * tells that software reset should not affect card 846 * detection circuit. But esdhc clears its SYSCTL 847 * register bits [0..2] during the software reset. This 848 * will stop those clocks that card detection circuit 849 * relies on. To work around it, we turn the clocks on 850 * back to keep card detection circuit functional. 851 */ 852 esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL); 853 /* 854 * The reset on usdhc fails to clear MIX_CTRL register. 855 * Do it manually here. 856 */ 857 if (esdhc_is_usdhc(imx_data)) { 858 /* 859 * the tuning bits should be kept during reset 860 */ 861 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); 862 writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK, 863 host->ioaddr + ESDHC_MIX_CTRL); 864 imx_data->is_ddr = 0; 865 } 866 } else if (val & SDHCI_RESET_DATA) { 867 /* 868 * The eSDHC DAT line software reset clears at least the 869 * data transfer width on i.MX25, so make sure that the 870 * Host Control register is unaffected. 871 */ 872 esdhc_clrset_le(host, 0xff, new_val, 873 SDHCI_HOST_CONTROL); 874 } 875 } 876 } 877 878 static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host) 879 { 880 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 881 882 return pltfm_host->clock; 883 } 884 885 static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host) 886 { 887 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 888 889 return pltfm_host->clock / 256 / 16; 890 } 891 892 static inline void esdhc_pltfm_set_clock(struct sdhci_host *host, 893 unsigned int clock) 894 { 895 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 896 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 897 unsigned int host_clock = pltfm_host->clock; 898 int ddr_pre_div = imx_data->is_ddr ? 2 : 1; 899 int pre_div = 1; 900 int div = 1; 901 int ret; 902 u32 temp, val; 903 904 if (esdhc_is_usdhc(imx_data)) { 905 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 906 writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 907 host->ioaddr + ESDHC_VENDOR_SPEC); 908 esdhc_wait_for_card_clock_gate_off(host); 909 } 910 911 if (clock == 0) { 912 host->mmc->actual_clock = 0; 913 return; 914 } 915 916 /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */ 917 if (is_imx53_esdhc(imx_data)) { 918 /* 919 * According to the i.MX53 reference manual, if DLLCTRL[10] can 920 * be set, then the controller is eSDHCv3, else it is eSDHCv2. 921 */ 922 val = readl(host->ioaddr + ESDHC_DLL_CTRL); 923 writel(val | BIT(10), host->ioaddr + ESDHC_DLL_CTRL); 924 temp = readl(host->ioaddr + ESDHC_DLL_CTRL); 925 writel(val, host->ioaddr + ESDHC_DLL_CTRL); 926 if (temp & BIT(10)) 927 pre_div = 2; 928 } 929 930 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 931 temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 932 | ESDHC_CLOCK_MASK); 933 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 934 935 if (imx_data->socdata->flags & ESDHC_FLAG_ERR010450) { 936 unsigned int max_clock; 937 938 max_clock = imx_data->is_ddr ? 45000000 : 150000000; 939 940 clock = min(clock, max_clock); 941 } 942 943 while (host_clock / (16 * pre_div * ddr_pre_div) > clock && 944 pre_div < 256) 945 pre_div *= 2; 946 947 while (host_clock / (div * pre_div * ddr_pre_div) > clock && div < 16) 948 div++; 949 950 host->mmc->actual_clock = host_clock / (div * pre_div * ddr_pre_div); 951 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", 952 clock, host->mmc->actual_clock); 953 954 pre_div >>= 1; 955 div--; 956 957 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 958 temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 959 | (div << ESDHC_DIVIDER_SHIFT) 960 | (pre_div << ESDHC_PREDIV_SHIFT)); 961 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 962 963 /* need to wait the bit 3 of the PRSSTAT to be set, make sure card clock is stable */ 964 ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, temp, 965 (temp & ESDHC_CLOCK_STABLE), 2, 100); 966 if (ret == -ETIMEDOUT) 967 dev_warn(mmc_dev(host->mmc), "card clock still not stable in 100us!.\n"); 968 969 if (esdhc_is_usdhc(imx_data)) { 970 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 971 writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 972 host->ioaddr + ESDHC_VENDOR_SPEC); 973 } 974 975 } 976 977 static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host) 978 { 979 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 980 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 981 struct esdhc_platform_data *boarddata = &imx_data->boarddata; 982 983 switch (boarddata->wp_type) { 984 case ESDHC_WP_GPIO: 985 return mmc_gpio_get_ro(host->mmc); 986 case ESDHC_WP_CONTROLLER: 987 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) & 988 SDHCI_WRITE_PROTECT); 989 case ESDHC_WP_NONE: 990 break; 991 } 992 993 return -ENOSYS; 994 } 995 996 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width) 997 { 998 u32 ctrl; 999 1000 switch (width) { 1001 case MMC_BUS_WIDTH_8: 1002 ctrl = ESDHC_CTRL_8BITBUS; 1003 break; 1004 case MMC_BUS_WIDTH_4: 1005 ctrl = ESDHC_CTRL_4BITBUS; 1006 break; 1007 default: 1008 ctrl = 0; 1009 break; 1010 } 1011 1012 esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl, 1013 SDHCI_HOST_CONTROL); 1014 } 1015 1016 static void esdhc_reset_tuning(struct sdhci_host *host) 1017 { 1018 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1019 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1020 u32 ctrl; 1021 int ret; 1022 1023 /* Reset the tuning circuit */ 1024 if (esdhc_is_usdhc(imx_data)) { 1025 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { 1026 ctrl = readl(host->ioaddr + ESDHC_MIX_CTRL); 1027 ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 1028 ctrl &= ~ESDHC_MIX_CTRL_FBCLK_SEL; 1029 writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL); 1030 writel(0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 1031 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 1032 ctrl = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); 1033 ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 1034 ctrl &= ~ESDHC_MIX_CTRL_EXE_TUNE; 1035 writel(ctrl, host->ioaddr + SDHCI_AUTO_CMD_STATUS); 1036 /* Make sure ESDHC_MIX_CTRL_EXE_TUNE cleared */ 1037 ret = readl_poll_timeout(host->ioaddr + SDHCI_AUTO_CMD_STATUS, 1038 ctrl, !(ctrl & ESDHC_MIX_CTRL_EXE_TUNE), 1, 50); 1039 if (ret == -ETIMEDOUT) 1040 dev_warn(mmc_dev(host->mmc), 1041 "Warning! clear execute tuning bit failed\n"); 1042 /* 1043 * SDHCI_INT_DATA_AVAIL is W1C bit, set this bit will clear the 1044 * usdhc IP internal logic flag execute_tuning_with_clr_buf, which 1045 * will finally make sure the normal data transfer logic correct. 1046 */ 1047 ctrl = readl(host->ioaddr + SDHCI_INT_STATUS); 1048 ctrl |= SDHCI_INT_DATA_AVAIL; 1049 writel(ctrl, host->ioaddr + SDHCI_INT_STATUS); 1050 } 1051 } 1052 } 1053 1054 static int usdhc_execute_tuning(struct mmc_host *mmc, u32 opcode) 1055 { 1056 struct sdhci_host *host = mmc_priv(mmc); 1057 1058 /* 1059 * i.MX uSDHC internally already uses a fixed optimized timing for 1060 * DDR50, normally does not require tuning for DDR50 mode. 1061 */ 1062 if (host->timing == MMC_TIMING_UHS_DDR50) 1063 return 0; 1064 1065 /* 1066 * Reset tuning circuit logic. If not, the previous tuning result 1067 * will impact current tuning, make current tuning can't set the 1068 * correct delay cell. 1069 */ 1070 esdhc_reset_tuning(host); 1071 return sdhci_execute_tuning(mmc, opcode); 1072 } 1073 1074 static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val) 1075 { 1076 u32 reg; 1077 u8 sw_rst; 1078 int ret; 1079 1080 /* FIXME: delay a bit for card to be ready for next tuning due to errors */ 1081 mdelay(1); 1082 1083 /* IC suggest to reset USDHC before every tuning command */ 1084 esdhc_clrset_le(host, 0xff, SDHCI_RESET_ALL, SDHCI_SOFTWARE_RESET); 1085 ret = readb_poll_timeout(host->ioaddr + SDHCI_SOFTWARE_RESET, sw_rst, 1086 !(sw_rst & SDHCI_RESET_ALL), 10, 100); 1087 if (ret == -ETIMEDOUT) 1088 dev_warn(mmc_dev(host->mmc), 1089 "warning! RESET_ALL never complete before sending tuning command\n"); 1090 1091 reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 1092 reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL | 1093 ESDHC_MIX_CTRL_FBCLK_SEL; 1094 writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 1095 writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 1096 dev_dbg(mmc_dev(host->mmc), 1097 "tuning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n", 1098 val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS)); 1099 } 1100 1101 static void esdhc_post_tuning(struct sdhci_host *host) 1102 { 1103 u32 reg; 1104 1105 usdhc_auto_tuning_mode_sel(host); 1106 1107 reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 1108 reg &= ~ESDHC_MIX_CTRL_EXE_TUNE; 1109 reg |= ESDHC_MIX_CTRL_AUTO_TUNE_EN; 1110 writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 1111 } 1112 1113 static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode) 1114 { 1115 int min, max, avg, ret; 1116 1117 /* find the mininum delay first which can pass tuning */ 1118 min = ESDHC_TUNE_CTRL_MIN; 1119 while (min < ESDHC_TUNE_CTRL_MAX) { 1120 esdhc_prepare_tuning(host, min); 1121 if (!mmc_send_tuning(host->mmc, opcode, NULL)) 1122 break; 1123 min += ESDHC_TUNE_CTRL_STEP; 1124 } 1125 1126 /* find the maxinum delay which can not pass tuning */ 1127 max = min + ESDHC_TUNE_CTRL_STEP; 1128 while (max < ESDHC_TUNE_CTRL_MAX) { 1129 esdhc_prepare_tuning(host, max); 1130 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 1131 max -= ESDHC_TUNE_CTRL_STEP; 1132 break; 1133 } 1134 max += ESDHC_TUNE_CTRL_STEP; 1135 } 1136 1137 /* use average delay to get the best timing */ 1138 avg = (min + max) / 2; 1139 esdhc_prepare_tuning(host, avg); 1140 ret = mmc_send_tuning(host->mmc, opcode, NULL); 1141 esdhc_post_tuning(host); 1142 1143 dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n", 1144 ret ? "failed" : "passed", avg, ret); 1145 1146 return ret; 1147 } 1148 1149 static void esdhc_hs400_enhanced_strobe(struct mmc_host *mmc, struct mmc_ios *ios) 1150 { 1151 struct sdhci_host *host = mmc_priv(mmc); 1152 u32 m; 1153 1154 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 1155 if (ios->enhanced_strobe) 1156 m |= ESDHC_MIX_CTRL_HS400_ES_EN; 1157 else 1158 m &= ~ESDHC_MIX_CTRL_HS400_ES_EN; 1159 writel(m, host->ioaddr + ESDHC_MIX_CTRL); 1160 } 1161 1162 static int esdhc_change_pinstate(struct sdhci_host *host, 1163 unsigned int uhs) 1164 { 1165 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1166 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1167 struct pinctrl_state *pinctrl; 1168 1169 dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs); 1170 1171 if (IS_ERR(imx_data->pinctrl) || 1172 IS_ERR(imx_data->pins_100mhz) || 1173 IS_ERR(imx_data->pins_200mhz)) 1174 return -EINVAL; 1175 1176 switch (uhs) { 1177 case MMC_TIMING_UHS_SDR50: 1178 case MMC_TIMING_UHS_DDR50: 1179 pinctrl = imx_data->pins_100mhz; 1180 break; 1181 case MMC_TIMING_UHS_SDR104: 1182 case MMC_TIMING_MMC_HS200: 1183 case MMC_TIMING_MMC_HS400: 1184 pinctrl = imx_data->pins_200mhz; 1185 break; 1186 default: 1187 /* back to default state for other legacy timing */ 1188 return pinctrl_select_default_state(mmc_dev(host->mmc)); 1189 } 1190 1191 return pinctrl_select_state(imx_data->pinctrl, pinctrl); 1192 } 1193 1194 /* 1195 * For HS400 eMMC, there is a data_strobe line. This signal is generated 1196 * by the device and used for data output and CRC status response output 1197 * in HS400 mode. The frequency of this signal follows the frequency of 1198 * CLK generated by host. The host receives the data which is aligned to the 1199 * edge of data_strobe line. Due to the time delay between CLK line and 1200 * data_strobe line, if the delay time is larger than one clock cycle, 1201 * then CLK and data_strobe line will be misaligned, read error shows up. 1202 */ 1203 static void esdhc_set_strobe_dll(struct sdhci_host *host) 1204 { 1205 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1206 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1207 u32 strobe_delay; 1208 u32 v; 1209 int ret; 1210 1211 /* disable clock before enabling strobe dll */ 1212 writel(readl(host->ioaddr + ESDHC_VENDOR_SPEC) & 1213 ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 1214 host->ioaddr + ESDHC_VENDOR_SPEC); 1215 esdhc_wait_for_card_clock_gate_off(host); 1216 1217 /* force a reset on strobe dll */ 1218 writel(ESDHC_STROBE_DLL_CTRL_RESET, 1219 host->ioaddr + ESDHC_STROBE_DLL_CTRL); 1220 /* clear the reset bit on strobe dll before any setting */ 1221 writel(0, host->ioaddr + ESDHC_STROBE_DLL_CTRL); 1222 1223 /* 1224 * enable strobe dll ctrl and adjust the delay target 1225 * for the uSDHC loopback read clock 1226 */ 1227 if (imx_data->boarddata.strobe_dll_delay_target) 1228 strobe_delay = imx_data->boarddata.strobe_dll_delay_target; 1229 else 1230 strobe_delay = ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT; 1231 v = ESDHC_STROBE_DLL_CTRL_ENABLE | 1232 ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT | 1233 (strobe_delay << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT); 1234 writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL); 1235 1236 /* wait max 50us to get the REF/SLV lock */ 1237 ret = readl_poll_timeout(host->ioaddr + ESDHC_STROBE_DLL_STATUS, v, 1238 ((v & ESDHC_STROBE_DLL_STS_REF_LOCK) && (v & ESDHC_STROBE_DLL_STS_SLV_LOCK)), 1, 50); 1239 if (ret == -ETIMEDOUT) 1240 dev_warn(mmc_dev(host->mmc), 1241 "warning! HS400 strobe DLL status REF/SLV not lock in 50us, STROBE DLL status is %x!\n", v); 1242 } 1243 1244 static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing) 1245 { 1246 u32 m; 1247 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1248 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1249 struct esdhc_platform_data *boarddata = &imx_data->boarddata; 1250 1251 /* disable ddr mode and disable HS400 mode */ 1252 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 1253 m &= ~(ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN); 1254 imx_data->is_ddr = 0; 1255 1256 switch (timing) { 1257 case MMC_TIMING_UHS_SDR12: 1258 case MMC_TIMING_UHS_SDR25: 1259 case MMC_TIMING_UHS_SDR50: 1260 case MMC_TIMING_UHS_SDR104: 1261 case MMC_TIMING_MMC_HS: 1262 case MMC_TIMING_MMC_HS200: 1263 writel(m, host->ioaddr + ESDHC_MIX_CTRL); 1264 break; 1265 case MMC_TIMING_UHS_DDR50: 1266 case MMC_TIMING_MMC_DDR52: 1267 m |= ESDHC_MIX_CTRL_DDREN; 1268 writel(m, host->ioaddr + ESDHC_MIX_CTRL); 1269 imx_data->is_ddr = 1; 1270 if (boarddata->delay_line) { 1271 u32 v; 1272 v = boarddata->delay_line << 1273 ESDHC_DLL_OVERRIDE_VAL_SHIFT | 1274 (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT); 1275 if (is_imx53_esdhc(imx_data)) 1276 v <<= 1; 1277 writel(v, host->ioaddr + ESDHC_DLL_CTRL); 1278 } 1279 break; 1280 case MMC_TIMING_MMC_HS400: 1281 m |= ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN; 1282 writel(m, host->ioaddr + ESDHC_MIX_CTRL); 1283 imx_data->is_ddr = 1; 1284 /* update clock after enable DDR for strobe DLL lock */ 1285 host->ops->set_clock(host, host->clock); 1286 esdhc_set_strobe_dll(host); 1287 break; 1288 case MMC_TIMING_LEGACY: 1289 default: 1290 esdhc_reset_tuning(host); 1291 break; 1292 } 1293 1294 esdhc_change_pinstate(host, timing); 1295 } 1296 1297 static void esdhc_reset(struct sdhci_host *host, u8 mask) 1298 { 1299 sdhci_and_cqhci_reset(host, mask); 1300 1301 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 1302 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 1303 } 1304 1305 static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host) 1306 { 1307 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1308 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1309 1310 /* Doc Erratum: the uSDHC actual maximum timeout count is 1 << 29 */ 1311 return esdhc_is_usdhc(imx_data) ? 1 << 29 : 1 << 27; 1312 } 1313 1314 static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) 1315 { 1316 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1317 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1318 1319 /* use maximum timeout counter */ 1320 esdhc_clrset_le(host, ESDHC_SYS_CTRL_DTOCV_MASK, 1321 esdhc_is_usdhc(imx_data) ? 0xF : 0xE, 1322 SDHCI_TIMEOUT_CONTROL); 1323 } 1324 1325 static u32 esdhc_cqhci_irq(struct sdhci_host *host, u32 intmask) 1326 { 1327 int cmd_error = 0; 1328 int data_error = 0; 1329 1330 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 1331 return intmask; 1332 1333 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 1334 1335 return 0; 1336 } 1337 1338 static struct sdhci_ops sdhci_esdhc_ops = { 1339 .read_l = esdhc_readl_le, 1340 .read_w = esdhc_readw_le, 1341 .read_b = esdhc_readb_le, 1342 .write_l = esdhc_writel_le, 1343 .write_w = esdhc_writew_le, 1344 .write_b = esdhc_writeb_le, 1345 .set_clock = esdhc_pltfm_set_clock, 1346 .get_max_clock = esdhc_pltfm_get_max_clock, 1347 .get_min_clock = esdhc_pltfm_get_min_clock, 1348 .get_max_timeout_count = esdhc_get_max_timeout_count, 1349 .get_ro = esdhc_pltfm_get_ro, 1350 .set_timeout = esdhc_set_timeout, 1351 .set_bus_width = esdhc_pltfm_set_bus_width, 1352 .set_uhs_signaling = esdhc_set_uhs_signaling, 1353 .reset = esdhc_reset, 1354 .irq = esdhc_cqhci_irq, 1355 .dump_vendor_regs = esdhc_dump_debug_regs, 1356 }; 1357 1358 static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = { 1359 .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT 1360 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC 1361 | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC 1362 | SDHCI_QUIRK_BROKEN_CARD_DETECTION, 1363 .ops = &sdhci_esdhc_ops, 1364 }; 1365 1366 static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host) 1367 { 1368 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1369 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1370 struct cqhci_host *cq_host = host->mmc->cqe_private; 1371 int tmp; 1372 1373 if (esdhc_is_usdhc(imx_data)) { 1374 /* 1375 * The imx6q ROM code will change the default watermark 1376 * level setting to something insane. Change it back here. 1377 */ 1378 writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL); 1379 1380 /* 1381 * ROM code will change the bit burst_length_enable setting 1382 * to zero if this usdhc is chosen to boot system. Change 1383 * it back here, otherwise it will impact the performance a 1384 * lot. This bit is used to enable/disable the burst length 1385 * for the external AHB2AXI bridge. It's useful especially 1386 * for INCR transfer because without burst length indicator, 1387 * the AHB2AXI bridge does not know the burst length in 1388 * advance. And without burst length indicator, AHB INCR 1389 * transfer can only be converted to singles on the AXI side. 1390 */ 1391 writel(readl(host->ioaddr + SDHCI_HOST_CONTROL) 1392 | ESDHC_BURST_LEN_EN_INCR, 1393 host->ioaddr + SDHCI_HOST_CONTROL); 1394 1395 /* 1396 * erratum ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL 1397 * TO1.1, it's harmless for MX6SL 1398 */ 1399 if (!(imx_data->socdata->flags & ESDHC_FLAG_SKIP_ERR004536)) { 1400 writel(readl(host->ioaddr + 0x6c) & ~BIT(7), 1401 host->ioaddr + 0x6c); 1402 } 1403 1404 /* disable DLL_CTRL delay line settings */ 1405 writel(0x0, host->ioaddr + ESDHC_DLL_CTRL); 1406 1407 /* 1408 * For the case of command with busy, if set the bit 1409 * ESDHC_VEND_SPEC2_EN_BUSY_IRQ, USDHC will generate a 1410 * transfer complete interrupt when busy is deasserted. 1411 * When CQHCI use DCMD to send a CMD need R1b respons, 1412 * CQHCI require to set ESDHC_VEND_SPEC2_EN_BUSY_IRQ, 1413 * otherwise DCMD will always meet timeout waiting for 1414 * hardware interrupt issue. 1415 */ 1416 if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) { 1417 tmp = readl(host->ioaddr + ESDHC_VEND_SPEC2); 1418 tmp |= ESDHC_VEND_SPEC2_EN_BUSY_IRQ; 1419 writel(tmp, host->ioaddr + ESDHC_VEND_SPEC2); 1420 1421 host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ; 1422 } 1423 1424 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 1425 tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL); 1426 tmp |= ESDHC_STD_TUNING_EN | 1427 ESDHC_TUNING_START_TAP_DEFAULT; 1428 if (imx_data->boarddata.tuning_start_tap) { 1429 tmp &= ~ESDHC_TUNING_START_TAP_MASK; 1430 tmp |= imx_data->boarddata.tuning_start_tap; 1431 } 1432 1433 if (imx_data->boarddata.tuning_step) { 1434 tmp &= ~ESDHC_TUNING_STEP_MASK; 1435 tmp |= imx_data->boarddata.tuning_step 1436 << ESDHC_TUNING_STEP_SHIFT; 1437 } 1438 1439 /* Disable the CMD CRC check for tuning, if not, need to 1440 * add some delay after every tuning command, because 1441 * hardware standard tuning logic will directly go to next 1442 * step once it detect the CMD CRC error, will not wait for 1443 * the card side to finally send out the tuning data, trigger 1444 * the buffer read ready interrupt immediately. If usdhc send 1445 * the next tuning command some eMMC card will stuck, can't 1446 * response, block the tuning procedure or the first command 1447 * after the whole tuning procedure always can't get any response. 1448 */ 1449 tmp |= ESDHC_TUNING_CMD_CRC_CHECK_DISABLE; 1450 writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL); 1451 } else if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { 1452 /* 1453 * ESDHC_STD_TUNING_EN may be configed in bootloader 1454 * or ROM code, so clear this bit here to make sure 1455 * the manual tuning can work. 1456 */ 1457 tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL); 1458 tmp &= ~ESDHC_STD_TUNING_EN; 1459 writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL); 1460 } 1461 1462 /* 1463 * On i.MX8MM, we are running Dual Linux OS, with 1st Linux using SD Card 1464 * as rootfs storage, 2nd Linux using eMMC as rootfs storage. We let 1465 * the 1st linux configure power/clock for the 2nd Linux. 1466 * 1467 * When the 2nd Linux is booting into rootfs stage, we let the 1st Linux 1468 * to destroy the 2nd linux, then restart the 2nd linux, we met SDHCI dump. 1469 * After we clear the pending interrupt and halt CQCTL, issue gone. 1470 */ 1471 if (cq_host) { 1472 tmp = cqhci_readl(cq_host, CQHCI_IS); 1473 cqhci_writel(cq_host, tmp, CQHCI_IS); 1474 cqhci_writel(cq_host, CQHCI_HALT, CQHCI_CTL); 1475 } 1476 } 1477 } 1478 1479 static void esdhc_cqe_enable(struct mmc_host *mmc) 1480 { 1481 struct sdhci_host *host = mmc_priv(mmc); 1482 struct cqhci_host *cq_host = mmc->cqe_private; 1483 u32 reg; 1484 u16 mode; 1485 int count = 10; 1486 1487 /* 1488 * CQE gets stuck if it sees Buffer Read Enable bit set, which can be 1489 * the case after tuning, so ensure the buffer is drained. 1490 */ 1491 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); 1492 while (reg & SDHCI_DATA_AVAILABLE) { 1493 sdhci_readl(host, SDHCI_BUFFER); 1494 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); 1495 if (count-- == 0) { 1496 dev_warn(mmc_dev(host->mmc), 1497 "CQE may get stuck because the Buffer Read Enable bit is set\n"); 1498 break; 1499 } 1500 mdelay(1); 1501 } 1502 1503 /* 1504 * Runtime resume will reset the entire host controller, which 1505 * will also clear the DMAEN/BCEN of register ESDHC_MIX_CTRL. 1506 * Here set DMAEN and BCEN when enable CMDQ. 1507 */ 1508 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE); 1509 if (host->flags & SDHCI_REQ_USE_DMA) 1510 mode |= SDHCI_TRNS_DMA; 1511 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE)) 1512 mode |= SDHCI_TRNS_BLK_CNT_EN; 1513 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); 1514 1515 /* 1516 * Though Runtime resume reset the entire host controller, 1517 * but do not impact the CQHCI side, need to clear the 1518 * HALT bit, avoid CQHCI stuck in the first request when 1519 * system resume back. 1520 */ 1521 cqhci_writel(cq_host, 0, CQHCI_CTL); 1522 if (cqhci_readl(cq_host, CQHCI_CTL) & CQHCI_HALT) 1523 dev_err(mmc_dev(host->mmc), 1524 "failed to exit halt state when enable CQE\n"); 1525 1526 1527 sdhci_cqe_enable(mmc); 1528 } 1529 1530 static void esdhc_sdhci_dumpregs(struct mmc_host *mmc) 1531 { 1532 sdhci_dumpregs(mmc_priv(mmc)); 1533 } 1534 1535 static const struct cqhci_host_ops esdhc_cqhci_ops = { 1536 .enable = esdhc_cqe_enable, 1537 .disable = sdhci_cqe_disable, 1538 .dumpregs = esdhc_sdhci_dumpregs, 1539 }; 1540 1541 static int 1542 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 1543 struct sdhci_host *host, 1544 struct pltfm_imx_data *imx_data) 1545 { 1546 struct device_node *np = pdev->dev.of_node; 1547 struct esdhc_platform_data *boarddata = &imx_data->boarddata; 1548 int ret; 1549 1550 if (of_get_property(np, "fsl,wp-controller", NULL)) 1551 boarddata->wp_type = ESDHC_WP_CONTROLLER; 1552 1553 /* 1554 * If we have this property, then activate WP check. 1555 * Retrieveing and requesting the actual WP GPIO will happen 1556 * in the call to mmc_of_parse(). 1557 */ 1558 if (of_property_read_bool(np, "wp-gpios")) 1559 boarddata->wp_type = ESDHC_WP_GPIO; 1560 1561 of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step); 1562 of_property_read_u32(np, "fsl,tuning-start-tap", 1563 &boarddata->tuning_start_tap); 1564 1565 of_property_read_u32(np, "fsl,strobe-dll-delay-target", 1566 &boarddata->strobe_dll_delay_target); 1567 if (of_find_property(np, "no-1-8-v", NULL)) 1568 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 1569 1570 if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line)) 1571 boarddata->delay_line = 0; 1572 1573 mmc_of_parse_voltage(host->mmc, &host->ocr_mask); 1574 1575 if (esdhc_is_usdhc(imx_data) && !IS_ERR(imx_data->pinctrl)) { 1576 imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl, 1577 ESDHC_PINCTRL_STATE_100MHZ); 1578 imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl, 1579 ESDHC_PINCTRL_STATE_200MHZ); 1580 } 1581 1582 /* call to generic mmc_of_parse to support additional capabilities */ 1583 ret = mmc_of_parse(host->mmc); 1584 if (ret) 1585 return ret; 1586 1587 if (mmc_gpio_get_cd(host->mmc) >= 0) 1588 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 1589 1590 return 0; 1591 } 1592 1593 static int sdhci_esdhc_imx_probe(struct platform_device *pdev) 1594 { 1595 struct sdhci_pltfm_host *pltfm_host; 1596 struct sdhci_host *host; 1597 struct cqhci_host *cq_host; 1598 int err; 1599 struct pltfm_imx_data *imx_data; 1600 1601 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata, 1602 sizeof(*imx_data)); 1603 if (IS_ERR(host)) 1604 return PTR_ERR(host); 1605 1606 pltfm_host = sdhci_priv(host); 1607 1608 imx_data = sdhci_pltfm_priv(pltfm_host); 1609 1610 imx_data->socdata = device_get_match_data(&pdev->dev); 1611 1612 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 1613 cpu_latency_qos_add_request(&imx_data->pm_qos_req, 0); 1614 1615 imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 1616 if (IS_ERR(imx_data->clk_ipg)) { 1617 err = PTR_ERR(imx_data->clk_ipg); 1618 goto free_sdhci; 1619 } 1620 1621 imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 1622 if (IS_ERR(imx_data->clk_ahb)) { 1623 err = PTR_ERR(imx_data->clk_ahb); 1624 goto free_sdhci; 1625 } 1626 1627 imx_data->clk_per = devm_clk_get(&pdev->dev, "per"); 1628 if (IS_ERR(imx_data->clk_per)) { 1629 err = PTR_ERR(imx_data->clk_per); 1630 goto free_sdhci; 1631 } 1632 1633 pltfm_host->clk = imx_data->clk_per; 1634 pltfm_host->clock = clk_get_rate(pltfm_host->clk); 1635 err = clk_prepare_enable(imx_data->clk_per); 1636 if (err) 1637 goto free_sdhci; 1638 err = clk_prepare_enable(imx_data->clk_ipg); 1639 if (err) 1640 goto disable_per_clk; 1641 err = clk_prepare_enable(imx_data->clk_ahb); 1642 if (err) 1643 goto disable_ipg_clk; 1644 1645 imx_data->pinctrl = devm_pinctrl_get(&pdev->dev); 1646 if (IS_ERR(imx_data->pinctrl)) 1647 dev_warn(mmc_dev(host->mmc), "could not get pinctrl\n"); 1648 1649 if (esdhc_is_usdhc(imx_data)) { 1650 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; 1651 host->mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR; 1652 1653 /* GPIO CD can be set as a wakeup source */ 1654 host->mmc->caps |= MMC_CAP_CD_WAKE; 1655 1656 if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200)) 1657 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; 1658 1659 /* clear tuning bits in case ROM has set it already */ 1660 writel(0x0, host->ioaddr + ESDHC_MIX_CTRL); 1661 writel(0x0, host->ioaddr + SDHCI_AUTO_CMD_STATUS); 1662 writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 1663 1664 /* 1665 * Link usdhc specific mmc_host_ops execute_tuning function, 1666 * to replace the standard one in sdhci_ops. 1667 */ 1668 host->mmc_host_ops.execute_tuning = usdhc_execute_tuning; 1669 } 1670 1671 err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data); 1672 if (err) 1673 goto disable_ahb_clk; 1674 1675 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) 1676 sdhci_esdhc_ops.platform_execute_tuning = 1677 esdhc_executing_tuning; 1678 1679 if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536) 1680 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 1681 1682 if (host->mmc->caps & MMC_CAP_8_BIT_DATA && 1683 imx_data->socdata->flags & ESDHC_FLAG_HS400) 1684 host->mmc->caps2 |= MMC_CAP2_HS400; 1685 1686 if (imx_data->socdata->flags & ESDHC_FLAG_BROKEN_AUTO_CMD23) 1687 host->quirks2 |= SDHCI_QUIRK2_ACMD23_BROKEN; 1688 1689 if (host->mmc->caps & MMC_CAP_8_BIT_DATA && 1690 imx_data->socdata->flags & ESDHC_FLAG_HS400_ES) { 1691 host->mmc->caps2 |= MMC_CAP2_HS400_ES; 1692 host->mmc_host_ops.hs400_enhanced_strobe = 1693 esdhc_hs400_enhanced_strobe; 1694 } 1695 1696 if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) { 1697 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 1698 cq_host = devm_kzalloc(&pdev->dev, sizeof(*cq_host), GFP_KERNEL); 1699 if (!cq_host) { 1700 err = -ENOMEM; 1701 goto disable_ahb_clk; 1702 } 1703 1704 cq_host->mmio = host->ioaddr + ESDHC_CQHCI_ADDR_OFFSET; 1705 cq_host->ops = &esdhc_cqhci_ops; 1706 1707 err = cqhci_init(cq_host, host->mmc, false); 1708 if (err) 1709 goto disable_ahb_clk; 1710 } 1711 1712 sdhci_esdhc_imx_hwinit(host); 1713 1714 err = sdhci_add_host(host); 1715 if (err) 1716 goto disable_ahb_clk; 1717 1718 /* 1719 * Setup the wakeup capability here, let user to decide 1720 * whether need to enable this wakeup through sysfs interface. 1721 */ 1722 if ((host->mmc->pm_caps & MMC_PM_KEEP_POWER) && 1723 (host->mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ)) 1724 device_set_wakeup_capable(&pdev->dev, true); 1725 1726 pm_runtime_set_active(&pdev->dev); 1727 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 1728 pm_runtime_use_autosuspend(&pdev->dev); 1729 pm_suspend_ignore_children(&pdev->dev, 1); 1730 pm_runtime_enable(&pdev->dev); 1731 1732 return 0; 1733 1734 disable_ahb_clk: 1735 clk_disable_unprepare(imx_data->clk_ahb); 1736 disable_ipg_clk: 1737 clk_disable_unprepare(imx_data->clk_ipg); 1738 disable_per_clk: 1739 clk_disable_unprepare(imx_data->clk_per); 1740 free_sdhci: 1741 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 1742 cpu_latency_qos_remove_request(&imx_data->pm_qos_req); 1743 sdhci_pltfm_free(pdev); 1744 return err; 1745 } 1746 1747 static int sdhci_esdhc_imx_remove(struct platform_device *pdev) 1748 { 1749 struct sdhci_host *host = platform_get_drvdata(pdev); 1750 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1751 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1752 int dead; 1753 1754 pm_runtime_get_sync(&pdev->dev); 1755 dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); 1756 pm_runtime_disable(&pdev->dev); 1757 pm_runtime_put_noidle(&pdev->dev); 1758 1759 sdhci_remove_host(host, dead); 1760 1761 clk_disable_unprepare(imx_data->clk_per); 1762 clk_disable_unprepare(imx_data->clk_ipg); 1763 clk_disable_unprepare(imx_data->clk_ahb); 1764 1765 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 1766 cpu_latency_qos_remove_request(&imx_data->pm_qos_req); 1767 1768 sdhci_pltfm_free(pdev); 1769 1770 return 0; 1771 } 1772 1773 #ifdef CONFIG_PM_SLEEP 1774 static int sdhci_esdhc_suspend(struct device *dev) 1775 { 1776 struct sdhci_host *host = dev_get_drvdata(dev); 1777 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1778 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1779 int ret; 1780 1781 if (host->mmc->caps2 & MMC_CAP2_CQE) { 1782 ret = cqhci_suspend(host->mmc); 1783 if (ret) 1784 return ret; 1785 } 1786 1787 if ((imx_data->socdata->flags & ESDHC_FLAG_STATE_LOST_IN_LPMODE) && 1788 (host->tuning_mode != SDHCI_TUNING_MODE_1)) { 1789 mmc_retune_timer_stop(host->mmc); 1790 mmc_retune_needed(host->mmc); 1791 } 1792 1793 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 1794 mmc_retune_needed(host->mmc); 1795 1796 ret = sdhci_suspend_host(host); 1797 if (ret) 1798 return ret; 1799 1800 ret = pinctrl_pm_select_sleep_state(dev); 1801 if (ret) 1802 return ret; 1803 1804 ret = mmc_gpio_set_cd_wake(host->mmc, true); 1805 1806 return ret; 1807 } 1808 1809 static int sdhci_esdhc_resume(struct device *dev) 1810 { 1811 struct sdhci_host *host = dev_get_drvdata(dev); 1812 int ret; 1813 1814 ret = pinctrl_pm_select_default_state(dev); 1815 if (ret) 1816 return ret; 1817 1818 /* re-initialize hw state in case it's lost in low power mode */ 1819 sdhci_esdhc_imx_hwinit(host); 1820 1821 ret = sdhci_resume_host(host); 1822 if (ret) 1823 return ret; 1824 1825 if (host->mmc->caps2 & MMC_CAP2_CQE) 1826 ret = cqhci_resume(host->mmc); 1827 1828 if (!ret) 1829 ret = mmc_gpio_set_cd_wake(host->mmc, false); 1830 1831 return ret; 1832 } 1833 #endif 1834 1835 #ifdef CONFIG_PM 1836 static int sdhci_esdhc_runtime_suspend(struct device *dev) 1837 { 1838 struct sdhci_host *host = dev_get_drvdata(dev); 1839 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1840 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1841 int ret; 1842 1843 if (host->mmc->caps2 & MMC_CAP2_CQE) { 1844 ret = cqhci_suspend(host->mmc); 1845 if (ret) 1846 return ret; 1847 } 1848 1849 ret = sdhci_runtime_suspend_host(host); 1850 if (ret) 1851 return ret; 1852 1853 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 1854 mmc_retune_needed(host->mmc); 1855 1856 imx_data->actual_clock = host->mmc->actual_clock; 1857 esdhc_pltfm_set_clock(host, 0); 1858 clk_disable_unprepare(imx_data->clk_per); 1859 clk_disable_unprepare(imx_data->clk_ipg); 1860 clk_disable_unprepare(imx_data->clk_ahb); 1861 1862 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 1863 cpu_latency_qos_remove_request(&imx_data->pm_qos_req); 1864 1865 return ret; 1866 } 1867 1868 static int sdhci_esdhc_runtime_resume(struct device *dev) 1869 { 1870 struct sdhci_host *host = dev_get_drvdata(dev); 1871 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1872 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1873 int err; 1874 1875 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 1876 cpu_latency_qos_add_request(&imx_data->pm_qos_req, 0); 1877 1878 if (imx_data->socdata->flags & ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME) 1879 clk_set_rate(imx_data->clk_per, pltfm_host->clock); 1880 1881 err = clk_prepare_enable(imx_data->clk_ahb); 1882 if (err) 1883 goto remove_pm_qos_request; 1884 1885 err = clk_prepare_enable(imx_data->clk_per); 1886 if (err) 1887 goto disable_ahb_clk; 1888 1889 err = clk_prepare_enable(imx_data->clk_ipg); 1890 if (err) 1891 goto disable_per_clk; 1892 1893 esdhc_pltfm_set_clock(host, imx_data->actual_clock); 1894 1895 err = sdhci_runtime_resume_host(host, 0); 1896 if (err) 1897 goto disable_ipg_clk; 1898 1899 if (host->mmc->caps2 & MMC_CAP2_CQE) 1900 err = cqhci_resume(host->mmc); 1901 1902 return err; 1903 1904 disable_ipg_clk: 1905 clk_disable_unprepare(imx_data->clk_ipg); 1906 disable_per_clk: 1907 clk_disable_unprepare(imx_data->clk_per); 1908 disable_ahb_clk: 1909 clk_disable_unprepare(imx_data->clk_ahb); 1910 remove_pm_qos_request: 1911 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 1912 cpu_latency_qos_remove_request(&imx_data->pm_qos_req); 1913 return err; 1914 } 1915 #endif 1916 1917 static const struct dev_pm_ops sdhci_esdhc_pmops = { 1918 SET_SYSTEM_SLEEP_PM_OPS(sdhci_esdhc_suspend, sdhci_esdhc_resume) 1919 SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend, 1920 sdhci_esdhc_runtime_resume, NULL) 1921 }; 1922 1923 static struct platform_driver sdhci_esdhc_imx_driver = { 1924 .driver = { 1925 .name = "sdhci-esdhc-imx", 1926 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1927 .of_match_table = imx_esdhc_dt_ids, 1928 .pm = &sdhci_esdhc_pmops, 1929 }, 1930 .probe = sdhci_esdhc_imx_probe, 1931 .remove = sdhci_esdhc_imx_remove, 1932 }; 1933 1934 module_platform_driver(sdhci_esdhc_imx_driver); 1935 1936 MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC"); 1937 MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>"); 1938 MODULE_LICENSE("GPL v2"); 1939