1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/spi/fsl-imx-cspi.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Freescale (Enhanced) Configurable Serial Peripheral Interface (CSPI/eCSPI) for i.MX 8 9maintainers: 10 - Shawn Guo <shawnguo@kernel.org> 11 12allOf: 13 - $ref: "/schemas/spi/spi-controller.yaml#" 14 15properties: 16 compatible: 17 oneOf: 18 - const: fsl,imx1-cspi 19 - const: fsl,imx21-cspi 20 - const: fsl,imx27-cspi 21 - const: fsl,imx31-cspi 22 - const: fsl,imx35-cspi 23 - const: fsl,imx51-ecspi 24 - const: fsl,imx53-ecspi 25 - items: 26 - const: fsl,imx8mp-ecspi 27 - const: fsl,imx6ul-ecspi 28 - items: 29 - enum: 30 - fsl,imx50-ecspi 31 - fsl,imx6q-ecspi 32 - fsl,imx6sx-ecspi 33 - fsl,imx6sl-ecspi 34 - fsl,imx6sll-ecspi 35 - fsl,imx6ul-ecspi 36 - fsl,imx7d-ecspi 37 - fsl,imx8mq-ecspi 38 - fsl,imx8mm-ecspi 39 - fsl,imx8mn-ecspi 40 - const: fsl,imx51-ecspi 41 42 reg: 43 maxItems: 1 44 45 interrupts: 46 maxItems: 1 47 48 clocks: 49 items: 50 - description: SoC SPI ipg clock 51 - description: SoC SPI per clock 52 53 clock-names: 54 items: 55 - const: ipg 56 - const: per 57 58 dmas: 59 items: 60 - description: DMA controller phandle and request line for RX 61 - description: DMA controller phandle and request line for TX 62 63 dma-names: 64 items: 65 - const: rx 66 - const: tx 67 68 fsl,spi-rdy-drctl: 69 $ref: /schemas/types.yaml#/definitions/uint32 70 description: | 71 Integer, representing the value of DRCTL, the register controlling 72 the SPI_READY handling. Note that to enable the DRCTL consideration, 73 the SPI_READY mode-flag needs to be set too. 74 Valid values are: 0 (disabled), 1 (edge-triggered burst) and 2 (level-triggered burst). 75 enum: [0, 1, 2] 76 77required: 78 - compatible 79 - reg 80 - interrupts 81 - clocks 82 - clock-names 83 84unevaluatedProperties: false 85 86examples: 87 - | 88 #include <dt-bindings/clock/imx5-clock.h> 89 90 spi@70010000 { 91 #address-cells = <1>; 92 #size-cells = <0>; 93 compatible = "fsl,imx51-ecspi"; 94 reg = <0x70010000 0x4000>; 95 interrupts = <36>; 96 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>, 97 <&clks IMX5_CLK_ECSPI1_PER_GATE>; 98 clock-names = "ipg", "per"; 99 }; 100