1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (c) 2004 Simtec Electronics 4 * Ben Dooks <ben@simtec.co.uk> 5 * 6 * S3C2410 Watchdog Timer Support 7 * 8 * Based on, softdog.c by Alan Cox, 9 * (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk> 10 */ 11 12 #include <linux/module.h> 13 #include <linux/moduleparam.h> 14 #include <linux/types.h> 15 #include <linux/timer.h> 16 #include <linux/watchdog.h> 17 #include <linux/platform_device.h> 18 #include <linux/interrupt.h> 19 #include <linux/clk.h> 20 #include <linux/uaccess.h> 21 #include <linux/io.h> 22 #include <linux/cpufreq.h> 23 #include <linux/slab.h> 24 #include <linux/err.h> 25 #include <linux/of.h> 26 #include <linux/of_device.h> 27 #include <linux/mfd/syscon.h> 28 #include <linux/regmap.h> 29 #include <linux/delay.h> 30 31 #define S3C2410_WTCON 0x00 32 #define S3C2410_WTDAT 0x04 33 #define S3C2410_WTCNT 0x08 34 #define S3C2410_WTCLRINT 0x0c 35 36 #define S3C2410_WTCNT_MAXCNT 0xffff 37 38 #define S3C2410_WTCON_RSTEN (1 << 0) 39 #define S3C2410_WTCON_INTEN (1 << 2) 40 #define S3C2410_WTCON_ENABLE (1 << 5) 41 42 #define S3C2410_WTCON_DIV16 (0 << 3) 43 #define S3C2410_WTCON_DIV32 (1 << 3) 44 #define S3C2410_WTCON_DIV64 (2 << 3) 45 #define S3C2410_WTCON_DIV128 (3 << 3) 46 47 #define S3C2410_WTCON_MAXDIV 0x80 48 49 #define S3C2410_WTCON_PRESCALE(x) ((x) << 8) 50 #define S3C2410_WTCON_PRESCALE_MASK (0xff << 8) 51 #define S3C2410_WTCON_PRESCALE_MAX 0xff 52 53 #define S3C2410_WATCHDOG_ATBOOT (0) 54 #define S3C2410_WATCHDOG_DEFAULT_TIME (15) 55 56 #define EXYNOS5_RST_STAT_REG_OFFSET 0x0404 57 #define EXYNOS5_WDT_DISABLE_REG_OFFSET 0x0408 58 #define EXYNOS5_WDT_MASK_RESET_REG_OFFSET 0x040c 59 #define EXYNOS850_CLUSTER0_NONCPU_OUT 0x1220 60 #define EXYNOS850_CLUSTER0_NONCPU_INT_EN 0x1244 61 #define EXYNOS850_CLUSTER1_NONCPU_OUT 0x1620 62 #define EXYNOS850_CLUSTER1_NONCPU_INT_EN 0x1644 63 #define EXYNOSAUTOV9_CLUSTER1_NONCPU_OUT 0x1520 64 #define EXYNOSAUTOV9_CLUSTER1_NONCPU_INT_EN 0x1544 65 66 #define EXYNOS850_CLUSTER0_WDTRESET_BIT 24 67 #define EXYNOS850_CLUSTER1_WDTRESET_BIT 23 68 #define EXYNOSAUTOV9_CLUSTER0_WDTRESET_BIT 25 69 #define EXYNOSAUTOV9_CLUSTER1_WDTRESET_BIT 24 70 71 /** 72 * DOC: Quirk flags for different Samsung watchdog IP-cores 73 * 74 * This driver supports multiple Samsung SoCs, each of which might have 75 * different set of registers and features supported. As watchdog block 76 * sometimes requires modifying PMU registers for proper functioning, register 77 * differences in both watchdog and PMU IP-cores should be accounted for. Quirk 78 * flags described below serve the purpose of telling the driver about mentioned 79 * SoC traits, and can be specified in driver data for each particular supported 80 * device. 81 * 82 * %QUIRK_HAS_WTCLRINT_REG: Watchdog block has WTCLRINT register. It's used to 83 * clear the interrupt once the interrupt service routine is complete. It's 84 * write-only, writing any values to this register clears the interrupt, but 85 * reading is not permitted. 86 * 87 * %QUIRK_HAS_PMU_MASK_RESET: PMU block has the register for disabling/enabling 88 * WDT reset request. On old SoCs it's usually called MASK_WDT_RESET_REQUEST, 89 * new SoCs have CLUSTERx_NONCPU_INT_EN register, which 'mask_bit' value is 90 * inverted compared to the former one. 91 * 92 * %QUIRK_HAS_PMU_RST_STAT: PMU block has RST_STAT (reset status) register, 93 * which contains bits indicating the reason for most recent CPU reset. If 94 * present, driver will use this register to check if previous reboot was due to 95 * watchdog timer reset. 96 * 97 * %QUIRK_HAS_PMU_AUTO_DISABLE: PMU block has AUTOMATIC_WDT_RESET_DISABLE 98 * register. If 'mask_bit' bit is set, PMU will disable WDT reset when 99 * corresponding processor is in reset state. 100 * 101 * %QUIRK_HAS_PMU_CNT_EN: PMU block has some register (e.g. CLUSTERx_NONCPU_OUT) 102 * with "watchdog counter enable" bit. That bit should be set to make watchdog 103 * counter running. 104 */ 105 #define QUIRK_HAS_WTCLRINT_REG (1 << 0) 106 #define QUIRK_HAS_PMU_MASK_RESET (1 << 1) 107 #define QUIRK_HAS_PMU_RST_STAT (1 << 2) 108 #define QUIRK_HAS_PMU_AUTO_DISABLE (1 << 3) 109 #define QUIRK_HAS_PMU_CNT_EN (1 << 4) 110 111 /* These quirks require that we have a PMU register map */ 112 #define QUIRKS_HAVE_PMUREG \ 113 (QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_RST_STAT | \ 114 QUIRK_HAS_PMU_AUTO_DISABLE | QUIRK_HAS_PMU_CNT_EN) 115 116 static bool nowayout = WATCHDOG_NOWAYOUT; 117 static int tmr_margin; 118 static int tmr_atboot = S3C2410_WATCHDOG_ATBOOT; 119 static int soft_noboot; 120 121 module_param(tmr_margin, int, 0); 122 module_param(tmr_atboot, int, 0); 123 module_param(nowayout, bool, 0); 124 module_param(soft_noboot, int, 0); 125 126 MODULE_PARM_DESC(tmr_margin, "Watchdog tmr_margin in seconds. (default=" 127 __MODULE_STRING(S3C2410_WATCHDOG_DEFAULT_TIME) ")"); 128 MODULE_PARM_DESC(tmr_atboot, 129 "Watchdog is started at boot time if set to 1, default=" 130 __MODULE_STRING(S3C2410_WATCHDOG_ATBOOT)); 131 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" 132 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); 133 MODULE_PARM_DESC(soft_noboot, "Watchdog action, set to 1 to ignore reboots, 0 to reboot (default 0)"); 134 135 /** 136 * struct s3c2410_wdt_variant - Per-variant config data 137 * 138 * @disable_reg: Offset in pmureg for the register that disables the watchdog 139 * timer reset functionality. 140 * @mask_reset_reg: Offset in pmureg for the register that masks the watchdog 141 * timer reset functionality. 142 * @mask_reset_inv: If set, mask_reset_reg value will have inverted meaning. 143 * @mask_bit: Bit number for the watchdog timer in the disable register and the 144 * mask reset register. 145 * @rst_stat_reg: Offset in pmureg for the register that has the reset status. 146 * @rst_stat_bit: Bit number in the rst_stat register indicating a watchdog 147 * reset. 148 * @cnt_en_reg: Offset in pmureg for the register that enables WDT counter. 149 * @cnt_en_bit: Bit number for "watchdog counter enable" in cnt_en register. 150 * @quirks: A bitfield of quirks. 151 */ 152 153 struct s3c2410_wdt_variant { 154 int disable_reg; 155 int mask_reset_reg; 156 bool mask_reset_inv; 157 int mask_bit; 158 int rst_stat_reg; 159 int rst_stat_bit; 160 int cnt_en_reg; 161 int cnt_en_bit; 162 u32 quirks; 163 }; 164 165 struct s3c2410_wdt { 166 struct device *dev; 167 struct clk *bus_clk; /* for register interface (PCLK) */ 168 struct clk *src_clk; /* for WDT counter */ 169 void __iomem *reg_base; 170 unsigned int count; 171 spinlock_t lock; 172 unsigned long wtcon_save; 173 unsigned long wtdat_save; 174 struct watchdog_device wdt_device; 175 struct notifier_block freq_transition; 176 const struct s3c2410_wdt_variant *drv_data; 177 struct regmap *pmureg; 178 }; 179 180 static const struct s3c2410_wdt_variant drv_data_s3c2410 = { 181 .quirks = 0 182 }; 183 184 #ifdef CONFIG_OF 185 static const struct s3c2410_wdt_variant drv_data_s3c6410 = { 186 .quirks = QUIRK_HAS_WTCLRINT_REG, 187 }; 188 189 static const struct s3c2410_wdt_variant drv_data_exynos5250 = { 190 .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET, 191 .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET, 192 .mask_bit = 20, 193 .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET, 194 .rst_stat_bit = 20, 195 .quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET | \ 196 QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_AUTO_DISABLE, 197 }; 198 199 static const struct s3c2410_wdt_variant drv_data_exynos5420 = { 200 .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET, 201 .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET, 202 .mask_bit = 0, 203 .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET, 204 .rst_stat_bit = 9, 205 .quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET | \ 206 QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_AUTO_DISABLE, 207 }; 208 209 static const struct s3c2410_wdt_variant drv_data_exynos7 = { 210 .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET, 211 .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET, 212 .mask_bit = 23, 213 .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET, 214 .rst_stat_bit = 23, /* A57 WDTRESET */ 215 .quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET | \ 216 QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_AUTO_DISABLE, 217 }; 218 219 static const struct s3c2410_wdt_variant drv_data_exynos850_cl0 = { 220 .mask_reset_reg = EXYNOS850_CLUSTER0_NONCPU_INT_EN, 221 .mask_bit = 2, 222 .mask_reset_inv = true, 223 .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET, 224 .rst_stat_bit = EXYNOS850_CLUSTER0_WDTRESET_BIT, 225 .cnt_en_reg = EXYNOS850_CLUSTER0_NONCPU_OUT, 226 .cnt_en_bit = 7, 227 .quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET | \ 228 QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN, 229 }; 230 231 static const struct s3c2410_wdt_variant drv_data_exynos850_cl1 = { 232 .mask_reset_reg = EXYNOS850_CLUSTER1_NONCPU_INT_EN, 233 .mask_bit = 2, 234 .mask_reset_inv = true, 235 .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET, 236 .rst_stat_bit = EXYNOS850_CLUSTER1_WDTRESET_BIT, 237 .cnt_en_reg = EXYNOS850_CLUSTER1_NONCPU_OUT, 238 .cnt_en_bit = 7, 239 .quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET | \ 240 QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN, 241 }; 242 243 static const struct s3c2410_wdt_variant drv_data_exynosautov9_cl0 = { 244 .mask_reset_reg = EXYNOS850_CLUSTER0_NONCPU_INT_EN, 245 .mask_bit = 2, 246 .mask_reset_inv = true, 247 .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET, 248 .rst_stat_bit = EXYNOSAUTOV9_CLUSTER0_WDTRESET_BIT, 249 .cnt_en_reg = EXYNOS850_CLUSTER0_NONCPU_OUT, 250 .cnt_en_bit = 7, 251 .quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET | 252 QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN, 253 }; 254 255 static const struct s3c2410_wdt_variant drv_data_exynosautov9_cl1 = { 256 .mask_reset_reg = EXYNOSAUTOV9_CLUSTER1_NONCPU_INT_EN, 257 .mask_bit = 2, 258 .mask_reset_inv = true, 259 .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET, 260 .rst_stat_bit = EXYNOSAUTOV9_CLUSTER1_WDTRESET_BIT, 261 .cnt_en_reg = EXYNOSAUTOV9_CLUSTER1_NONCPU_OUT, 262 .cnt_en_bit = 7, 263 .quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET | 264 QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN, 265 }; 266 267 static const struct of_device_id s3c2410_wdt_match[] = { 268 { .compatible = "samsung,s3c2410-wdt", 269 .data = &drv_data_s3c2410 }, 270 { .compatible = "samsung,s3c6410-wdt", 271 .data = &drv_data_s3c6410 }, 272 { .compatible = "samsung,exynos5250-wdt", 273 .data = &drv_data_exynos5250 }, 274 { .compatible = "samsung,exynos5420-wdt", 275 .data = &drv_data_exynos5420 }, 276 { .compatible = "samsung,exynos7-wdt", 277 .data = &drv_data_exynos7 }, 278 { .compatible = "samsung,exynos850-wdt", 279 .data = &drv_data_exynos850_cl0 }, 280 { .compatible = "samsung,exynosautov9-wdt", 281 .data = &drv_data_exynosautov9_cl0 }, 282 {}, 283 }; 284 MODULE_DEVICE_TABLE(of, s3c2410_wdt_match); 285 #endif 286 287 static const struct platform_device_id s3c2410_wdt_ids[] = { 288 { 289 .name = "s3c2410-wdt", 290 .driver_data = (unsigned long)&drv_data_s3c2410, 291 }, 292 {} 293 }; 294 MODULE_DEVICE_TABLE(platform, s3c2410_wdt_ids); 295 296 /* functions */ 297 298 static inline unsigned long s3c2410wdt_get_freq(struct s3c2410_wdt *wdt) 299 { 300 return clk_get_rate(wdt->src_clk ? wdt->src_clk : wdt->bus_clk); 301 } 302 303 static inline unsigned int s3c2410wdt_max_timeout(struct s3c2410_wdt *wdt) 304 { 305 const unsigned long freq = s3c2410wdt_get_freq(wdt); 306 307 return S3C2410_WTCNT_MAXCNT / (freq / (S3C2410_WTCON_PRESCALE_MAX + 1) 308 / S3C2410_WTCON_MAXDIV); 309 } 310 311 static inline struct s3c2410_wdt *freq_to_wdt(struct notifier_block *nb) 312 { 313 return container_of(nb, struct s3c2410_wdt, freq_transition); 314 } 315 316 static int s3c2410wdt_disable_wdt_reset(struct s3c2410_wdt *wdt, bool mask) 317 { 318 const u32 mask_val = BIT(wdt->drv_data->mask_bit); 319 const u32 val = mask ? mask_val : 0; 320 int ret; 321 322 ret = regmap_update_bits(wdt->pmureg, wdt->drv_data->disable_reg, 323 mask_val, val); 324 if (ret < 0) 325 dev_err(wdt->dev, "failed to update reg(%d)\n", ret); 326 327 return ret; 328 } 329 330 static int s3c2410wdt_mask_wdt_reset(struct s3c2410_wdt *wdt, bool mask) 331 { 332 const u32 mask_val = BIT(wdt->drv_data->mask_bit); 333 const bool val_inv = wdt->drv_data->mask_reset_inv; 334 const u32 val = (mask ^ val_inv) ? mask_val : 0; 335 int ret; 336 337 ret = regmap_update_bits(wdt->pmureg, wdt->drv_data->mask_reset_reg, 338 mask_val, val); 339 if (ret < 0) 340 dev_err(wdt->dev, "failed to update reg(%d)\n", ret); 341 342 return ret; 343 } 344 345 static int s3c2410wdt_enable_counter(struct s3c2410_wdt *wdt, bool en) 346 { 347 const u32 mask_val = BIT(wdt->drv_data->cnt_en_bit); 348 const u32 val = en ? mask_val : 0; 349 int ret; 350 351 ret = regmap_update_bits(wdt->pmureg, wdt->drv_data->cnt_en_reg, 352 mask_val, val); 353 if (ret < 0) 354 dev_err(wdt->dev, "failed to update reg(%d)\n", ret); 355 356 return ret; 357 } 358 359 static int s3c2410wdt_enable(struct s3c2410_wdt *wdt, bool en) 360 { 361 int ret; 362 363 if (wdt->drv_data->quirks & QUIRK_HAS_PMU_AUTO_DISABLE) { 364 ret = s3c2410wdt_disable_wdt_reset(wdt, !en); 365 if (ret < 0) 366 return ret; 367 } 368 369 if (wdt->drv_data->quirks & QUIRK_HAS_PMU_MASK_RESET) { 370 ret = s3c2410wdt_mask_wdt_reset(wdt, !en); 371 if (ret < 0) 372 return ret; 373 } 374 375 if (wdt->drv_data->quirks & QUIRK_HAS_PMU_CNT_EN) { 376 ret = s3c2410wdt_enable_counter(wdt, en); 377 if (ret < 0) 378 return ret; 379 } 380 381 return 0; 382 } 383 384 static int s3c2410wdt_keepalive(struct watchdog_device *wdd) 385 { 386 struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); 387 388 spin_lock(&wdt->lock); 389 writel(wdt->count, wdt->reg_base + S3C2410_WTCNT); 390 spin_unlock(&wdt->lock); 391 392 return 0; 393 } 394 395 static void __s3c2410wdt_stop(struct s3c2410_wdt *wdt) 396 { 397 unsigned long wtcon; 398 399 wtcon = readl(wdt->reg_base + S3C2410_WTCON); 400 wtcon &= ~(S3C2410_WTCON_ENABLE | S3C2410_WTCON_RSTEN); 401 writel(wtcon, wdt->reg_base + S3C2410_WTCON); 402 } 403 404 static int s3c2410wdt_stop(struct watchdog_device *wdd) 405 { 406 struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); 407 408 spin_lock(&wdt->lock); 409 __s3c2410wdt_stop(wdt); 410 spin_unlock(&wdt->lock); 411 412 return 0; 413 } 414 415 static int s3c2410wdt_start(struct watchdog_device *wdd) 416 { 417 unsigned long wtcon; 418 struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); 419 420 spin_lock(&wdt->lock); 421 422 __s3c2410wdt_stop(wdt); 423 424 wtcon = readl(wdt->reg_base + S3C2410_WTCON); 425 wtcon |= S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128; 426 427 if (soft_noboot) { 428 wtcon |= S3C2410_WTCON_INTEN; 429 wtcon &= ~S3C2410_WTCON_RSTEN; 430 } else { 431 wtcon &= ~S3C2410_WTCON_INTEN; 432 wtcon |= S3C2410_WTCON_RSTEN; 433 } 434 435 dev_dbg(wdt->dev, "Starting watchdog: count=0x%08x, wtcon=%08lx\n", 436 wdt->count, wtcon); 437 438 writel(wdt->count, wdt->reg_base + S3C2410_WTDAT); 439 writel(wdt->count, wdt->reg_base + S3C2410_WTCNT); 440 writel(wtcon, wdt->reg_base + S3C2410_WTCON); 441 spin_unlock(&wdt->lock); 442 443 return 0; 444 } 445 446 static inline int s3c2410wdt_is_running(struct s3c2410_wdt *wdt) 447 { 448 return readl(wdt->reg_base + S3C2410_WTCON) & S3C2410_WTCON_ENABLE; 449 } 450 451 static int s3c2410wdt_set_heartbeat(struct watchdog_device *wdd, 452 unsigned int timeout) 453 { 454 struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); 455 unsigned long freq = s3c2410wdt_get_freq(wdt); 456 unsigned int count; 457 unsigned int divisor = 1; 458 unsigned long wtcon; 459 460 if (timeout < 1) 461 return -EINVAL; 462 463 freq = DIV_ROUND_UP(freq, 128); 464 count = timeout * freq; 465 466 dev_dbg(wdt->dev, "Heartbeat: count=%d, timeout=%d, freq=%lu\n", 467 count, timeout, freq); 468 469 /* if the count is bigger than the watchdog register, 470 then work out what we need to do (and if) we can 471 actually make this value 472 */ 473 474 if (count >= 0x10000) { 475 divisor = DIV_ROUND_UP(count, 0xffff); 476 477 if (divisor > 0x100) { 478 dev_err(wdt->dev, "timeout %d too big\n", timeout); 479 return -EINVAL; 480 } 481 } 482 483 dev_dbg(wdt->dev, "Heartbeat: timeout=%d, divisor=%d, count=%d (%08x)\n", 484 timeout, divisor, count, DIV_ROUND_UP(count, divisor)); 485 486 count = DIV_ROUND_UP(count, divisor); 487 wdt->count = count; 488 489 /* update the pre-scaler */ 490 wtcon = readl(wdt->reg_base + S3C2410_WTCON); 491 wtcon &= ~S3C2410_WTCON_PRESCALE_MASK; 492 wtcon |= S3C2410_WTCON_PRESCALE(divisor-1); 493 494 writel(count, wdt->reg_base + S3C2410_WTDAT); 495 writel(wtcon, wdt->reg_base + S3C2410_WTCON); 496 497 wdd->timeout = (count * divisor) / freq; 498 499 return 0; 500 } 501 502 static int s3c2410wdt_restart(struct watchdog_device *wdd, unsigned long action, 503 void *data) 504 { 505 struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); 506 void __iomem *wdt_base = wdt->reg_base; 507 508 /* disable watchdog, to be safe */ 509 writel(0, wdt_base + S3C2410_WTCON); 510 511 /* put initial values into count and data */ 512 writel(0x80, wdt_base + S3C2410_WTCNT); 513 writel(0x80, wdt_base + S3C2410_WTDAT); 514 515 /* set the watchdog to go and reset... */ 516 writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV16 | 517 S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x20), 518 wdt_base + S3C2410_WTCON); 519 520 /* wait for reset to assert... */ 521 mdelay(500); 522 523 return 0; 524 } 525 526 #define OPTIONS (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE) 527 528 static const struct watchdog_info s3c2410_wdt_ident = { 529 .options = OPTIONS, 530 .firmware_version = 0, 531 .identity = "S3C2410 Watchdog", 532 }; 533 534 static const struct watchdog_ops s3c2410wdt_ops = { 535 .owner = THIS_MODULE, 536 .start = s3c2410wdt_start, 537 .stop = s3c2410wdt_stop, 538 .ping = s3c2410wdt_keepalive, 539 .set_timeout = s3c2410wdt_set_heartbeat, 540 .restart = s3c2410wdt_restart, 541 }; 542 543 static const struct watchdog_device s3c2410_wdd = { 544 .info = &s3c2410_wdt_ident, 545 .ops = &s3c2410wdt_ops, 546 .timeout = S3C2410_WATCHDOG_DEFAULT_TIME, 547 }; 548 549 /* interrupt handler code */ 550 551 static irqreturn_t s3c2410wdt_irq(int irqno, void *param) 552 { 553 struct s3c2410_wdt *wdt = platform_get_drvdata(param); 554 555 dev_info(wdt->dev, "watchdog timer expired (irq)\n"); 556 557 s3c2410wdt_keepalive(&wdt->wdt_device); 558 559 if (wdt->drv_data->quirks & QUIRK_HAS_WTCLRINT_REG) 560 writel(0x1, wdt->reg_base + S3C2410_WTCLRINT); 561 562 return IRQ_HANDLED; 563 } 564 565 static inline unsigned int s3c2410wdt_get_bootstatus(struct s3c2410_wdt *wdt) 566 { 567 unsigned int rst_stat; 568 int ret; 569 570 if (!(wdt->drv_data->quirks & QUIRK_HAS_PMU_RST_STAT)) 571 return 0; 572 573 ret = regmap_read(wdt->pmureg, wdt->drv_data->rst_stat_reg, &rst_stat); 574 if (ret) 575 dev_warn(wdt->dev, "Couldn't get RST_STAT register\n"); 576 else if (rst_stat & BIT(wdt->drv_data->rst_stat_bit)) 577 return WDIOF_CARDRESET; 578 579 return 0; 580 } 581 582 static inline const struct s3c2410_wdt_variant * 583 s3c2410_get_wdt_drv_data(struct platform_device *pdev) 584 { 585 const struct s3c2410_wdt_variant *variant; 586 struct device *dev = &pdev->dev; 587 588 variant = of_device_get_match_data(dev); 589 if (!variant) { 590 /* Device matched by platform_device_id */ 591 variant = (struct s3c2410_wdt_variant *) 592 platform_get_device_id(pdev)->driver_data; 593 } 594 595 #ifdef CONFIG_OF 596 /* Choose Exynos850/ExynosAutov9 driver data w.r.t. cluster index */ 597 if (variant == &drv_data_exynos850_cl0 || 598 variant == &drv_data_exynosautov9_cl0) { 599 u32 index; 600 int err; 601 602 err = of_property_read_u32(dev->of_node, 603 "samsung,cluster-index", &index); 604 if (err) { 605 dev_err(dev, "failed to get cluster index\n"); 606 return NULL; 607 } 608 609 switch (index) { 610 case 0: 611 return variant; 612 case 1: 613 return (variant == &drv_data_exynos850_cl0) ? 614 &drv_data_exynos850_cl1 : 615 &drv_data_exynosautov9_cl1; 616 default: 617 dev_err(dev, "wrong cluster index: %u\n", index); 618 return NULL; 619 } 620 } 621 #endif 622 623 return variant; 624 } 625 626 static int s3c2410wdt_probe(struct platform_device *pdev) 627 { 628 struct device *dev = &pdev->dev; 629 struct s3c2410_wdt *wdt; 630 unsigned int wtcon; 631 int wdt_irq; 632 int ret; 633 634 wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL); 635 if (!wdt) 636 return -ENOMEM; 637 638 wdt->dev = dev; 639 spin_lock_init(&wdt->lock); 640 wdt->wdt_device = s3c2410_wdd; 641 642 wdt->drv_data = s3c2410_get_wdt_drv_data(pdev); 643 if (!wdt->drv_data) 644 return -EINVAL; 645 646 if (wdt->drv_data->quirks & QUIRKS_HAVE_PMUREG) { 647 wdt->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node, 648 "samsung,syscon-phandle"); 649 if (IS_ERR(wdt->pmureg)) { 650 dev_err(dev, "syscon regmap lookup failed.\n"); 651 return PTR_ERR(wdt->pmureg); 652 } 653 } 654 655 wdt_irq = platform_get_irq(pdev, 0); 656 if (wdt_irq < 0) 657 return wdt_irq; 658 659 /* get the memory region for the watchdog timer */ 660 wdt->reg_base = devm_platform_ioremap_resource(pdev, 0); 661 if (IS_ERR(wdt->reg_base)) 662 return PTR_ERR(wdt->reg_base); 663 664 wdt->bus_clk = devm_clk_get(dev, "watchdog"); 665 if (IS_ERR(wdt->bus_clk)) { 666 dev_err(dev, "failed to find bus clock\n"); 667 return PTR_ERR(wdt->bus_clk); 668 } 669 670 ret = clk_prepare_enable(wdt->bus_clk); 671 if (ret < 0) { 672 dev_err(dev, "failed to enable bus clock\n"); 673 return ret; 674 } 675 676 /* 677 * "watchdog_src" clock is optional; if it's not present -- just skip it 678 * and use "watchdog" clock as both bus and source clock. 679 */ 680 wdt->src_clk = devm_clk_get_optional(dev, "watchdog_src"); 681 if (IS_ERR(wdt->src_clk)) { 682 dev_err_probe(dev, PTR_ERR(wdt->src_clk), 683 "failed to get source clock\n"); 684 ret = PTR_ERR(wdt->src_clk); 685 goto err_bus_clk; 686 } 687 688 ret = clk_prepare_enable(wdt->src_clk); 689 if (ret) { 690 dev_err(dev, "failed to enable source clock\n"); 691 goto err_bus_clk; 692 } 693 694 wdt->wdt_device.min_timeout = 1; 695 wdt->wdt_device.max_timeout = s3c2410wdt_max_timeout(wdt); 696 697 watchdog_set_drvdata(&wdt->wdt_device, wdt); 698 699 /* see if we can actually set the requested timer margin, and if 700 * not, try the default value */ 701 702 watchdog_init_timeout(&wdt->wdt_device, tmr_margin, dev); 703 ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device, 704 wdt->wdt_device.timeout); 705 if (ret) { 706 ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device, 707 S3C2410_WATCHDOG_DEFAULT_TIME); 708 if (ret == 0) { 709 dev_warn(dev, "tmr_margin value out of range, default %d used\n", 710 S3C2410_WATCHDOG_DEFAULT_TIME); 711 } else { 712 dev_err(dev, "failed to use default timeout\n"); 713 goto err_src_clk; 714 } 715 } 716 717 ret = devm_request_irq(dev, wdt_irq, s3c2410wdt_irq, 0, 718 pdev->name, pdev); 719 if (ret != 0) { 720 dev_err(dev, "failed to install irq (%d)\n", ret); 721 goto err_src_clk; 722 } 723 724 watchdog_set_nowayout(&wdt->wdt_device, nowayout); 725 watchdog_set_restart_priority(&wdt->wdt_device, 128); 726 727 wdt->wdt_device.bootstatus = s3c2410wdt_get_bootstatus(wdt); 728 wdt->wdt_device.parent = dev; 729 730 /* 731 * If "tmr_atboot" param is non-zero, start the watchdog right now. Also 732 * set WDOG_HW_RUNNING bit, so that watchdog core can kick the watchdog. 733 * 734 * If we're not enabling the watchdog, then ensure it is disabled if it 735 * has been left running from the bootloader or other source. 736 */ 737 if (tmr_atboot) { 738 dev_info(dev, "starting watchdog timer\n"); 739 s3c2410wdt_start(&wdt->wdt_device); 740 set_bit(WDOG_HW_RUNNING, &wdt->wdt_device.status); 741 } else { 742 s3c2410wdt_stop(&wdt->wdt_device); 743 } 744 745 ret = watchdog_register_device(&wdt->wdt_device); 746 if (ret) 747 goto err_src_clk; 748 749 ret = s3c2410wdt_enable(wdt, true); 750 if (ret < 0) 751 goto err_unregister; 752 753 platform_set_drvdata(pdev, wdt); 754 755 /* print out a statement of readiness */ 756 757 wtcon = readl(wdt->reg_base + S3C2410_WTCON); 758 759 dev_info(dev, "watchdog %sactive, reset %sabled, irq %sabled\n", 760 (wtcon & S3C2410_WTCON_ENABLE) ? "" : "in", 761 (wtcon & S3C2410_WTCON_RSTEN) ? "en" : "dis", 762 (wtcon & S3C2410_WTCON_INTEN) ? "en" : "dis"); 763 764 return 0; 765 766 err_unregister: 767 watchdog_unregister_device(&wdt->wdt_device); 768 769 err_src_clk: 770 clk_disable_unprepare(wdt->src_clk); 771 772 err_bus_clk: 773 clk_disable_unprepare(wdt->bus_clk); 774 775 return ret; 776 } 777 778 static int s3c2410wdt_remove(struct platform_device *dev) 779 { 780 int ret; 781 struct s3c2410_wdt *wdt = platform_get_drvdata(dev); 782 783 ret = s3c2410wdt_enable(wdt, false); 784 if (ret < 0) 785 return ret; 786 787 watchdog_unregister_device(&wdt->wdt_device); 788 789 clk_disable_unprepare(wdt->src_clk); 790 clk_disable_unprepare(wdt->bus_clk); 791 792 return 0; 793 } 794 795 static void s3c2410wdt_shutdown(struct platform_device *dev) 796 { 797 struct s3c2410_wdt *wdt = platform_get_drvdata(dev); 798 799 s3c2410wdt_enable(wdt, false); 800 s3c2410wdt_stop(&wdt->wdt_device); 801 } 802 803 static int s3c2410wdt_suspend(struct device *dev) 804 { 805 int ret; 806 struct s3c2410_wdt *wdt = dev_get_drvdata(dev); 807 808 /* Save watchdog state, and turn it off. */ 809 wdt->wtcon_save = readl(wdt->reg_base + S3C2410_WTCON); 810 wdt->wtdat_save = readl(wdt->reg_base + S3C2410_WTDAT); 811 812 ret = s3c2410wdt_enable(wdt, false); 813 if (ret < 0) 814 return ret; 815 816 /* Note that WTCNT doesn't need to be saved. */ 817 s3c2410wdt_stop(&wdt->wdt_device); 818 819 return 0; 820 } 821 822 static int s3c2410wdt_resume(struct device *dev) 823 { 824 int ret; 825 struct s3c2410_wdt *wdt = dev_get_drvdata(dev); 826 827 /* Restore watchdog state. */ 828 writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTDAT); 829 writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTCNT);/* Reset count */ 830 writel(wdt->wtcon_save, wdt->reg_base + S3C2410_WTCON); 831 832 ret = s3c2410wdt_enable(wdt, true); 833 if (ret < 0) 834 return ret; 835 836 dev_info(dev, "watchdog %sabled\n", 837 (wdt->wtcon_save & S3C2410_WTCON_ENABLE) ? "en" : "dis"); 838 839 return 0; 840 } 841 842 static DEFINE_SIMPLE_DEV_PM_OPS(s3c2410wdt_pm_ops, 843 s3c2410wdt_suspend, s3c2410wdt_resume); 844 845 static struct platform_driver s3c2410wdt_driver = { 846 .probe = s3c2410wdt_probe, 847 .remove = s3c2410wdt_remove, 848 .shutdown = s3c2410wdt_shutdown, 849 .id_table = s3c2410_wdt_ids, 850 .driver = { 851 .name = "s3c2410-wdt", 852 .pm = pm_sleep_ptr(&s3c2410wdt_pm_ops), 853 .of_match_table = of_match_ptr(s3c2410_wdt_match), 854 }, 855 }; 856 857 module_platform_driver(s3c2410wdt_driver); 858 859 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, Dimitry Andric <dimitry.andric@tomtom.com>"); 860 MODULE_DESCRIPTION("S3C2410 Watchdog Device Driver"); 861 MODULE_LICENSE("GPL"); 862