1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/acpi.h> 5 #include <linux/device.h> 6 #include <linux/etherdevice.h> 7 #include <linux/init.h> 8 #include <linux/interrupt.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/netdevice.h> 12 #include <linux/pci.h> 13 #include <linux/platform_device.h> 14 #include <linux/if_vlan.h> 15 #include <linux/crash_dump.h> 16 #include <net/ipv6.h> 17 #include <net/rtnetlink.h> 18 #include "hclge_cmd.h" 19 #include "hclge_dcb.h" 20 #include "hclge_main.h" 21 #include "hclge_mbx.h" 22 #include "hclge_mdio.h" 23 #include "hclge_tm.h" 24 #include "hclge_err.h" 25 #include "hnae3.h" 26 #include "hclge_devlink.h" 27 #include "hclge_comm_cmd.h" 28 29 #define HCLGE_NAME "hclge" 30 31 #define HCLGE_BUF_SIZE_UNIT 256U 32 #define HCLGE_BUF_MUL_BY 2 33 #define HCLGE_BUF_DIV_BY 2 34 #define NEED_RESERVE_TC_NUM 2 35 #define BUF_MAX_PERCENT 100 36 #define BUF_RESERVE_PERCENT 90 37 38 #define HCLGE_RESET_MAX_FAIL_CNT 5 39 #define HCLGE_RESET_SYNC_TIME 100 40 #define HCLGE_PF_RESET_SYNC_TIME 20 41 #define HCLGE_PF_RESET_SYNC_CNT 1500 42 43 /* Get DFX BD number offset */ 44 #define HCLGE_DFX_BIOS_BD_OFFSET 1 45 #define HCLGE_DFX_SSU_0_BD_OFFSET 2 46 #define HCLGE_DFX_SSU_1_BD_OFFSET 3 47 #define HCLGE_DFX_IGU_BD_OFFSET 4 48 #define HCLGE_DFX_RPU_0_BD_OFFSET 5 49 #define HCLGE_DFX_RPU_1_BD_OFFSET 6 50 #define HCLGE_DFX_NCSI_BD_OFFSET 7 51 #define HCLGE_DFX_RTC_BD_OFFSET 8 52 #define HCLGE_DFX_PPP_BD_OFFSET 9 53 #define HCLGE_DFX_RCB_BD_OFFSET 10 54 #define HCLGE_DFX_TQP_BD_OFFSET 11 55 #define HCLGE_DFX_SSU_2_BD_OFFSET 12 56 57 #define HCLGE_LINK_STATUS_MS 10 58 59 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mps); 60 static int hclge_init_vlan_config(struct hclge_dev *hdev); 61 static void hclge_sync_vlan_filter(struct hclge_dev *hdev); 62 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev); 63 static bool hclge_get_hw_reset_stat(struct hnae3_handle *handle); 64 static void hclge_rfs_filter_expire(struct hclge_dev *hdev); 65 static int hclge_clear_arfs_rules(struct hclge_dev *hdev); 66 static enum hnae3_reset_type hclge_get_reset_level(struct hnae3_ae_dev *ae_dev, 67 unsigned long *addr); 68 static int hclge_set_default_loopback(struct hclge_dev *hdev); 69 70 static void hclge_sync_mac_table(struct hclge_dev *hdev); 71 static void hclge_restore_hw_table(struct hclge_dev *hdev); 72 static void hclge_sync_promisc_mode(struct hclge_dev *hdev); 73 static void hclge_sync_fd_table(struct hclge_dev *hdev); 74 static void hclge_update_fec_stats(struct hclge_dev *hdev); 75 76 static struct hnae3_ae_algo ae_algo; 77 78 static struct workqueue_struct *hclge_wq; 79 80 static const struct pci_device_id ae_algo_pci_tbl[] = { 81 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0}, 82 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0}, 83 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0}, 84 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0}, 85 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0}, 86 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0}, 87 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0}, 88 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 0}, 89 /* required last entry */ 90 {0, } 91 }; 92 93 MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl); 94 95 static const u32 cmdq_reg_addr_list[] = {HCLGE_COMM_NIC_CSQ_BASEADDR_L_REG, 96 HCLGE_COMM_NIC_CSQ_BASEADDR_H_REG, 97 HCLGE_COMM_NIC_CSQ_DEPTH_REG, 98 HCLGE_COMM_NIC_CSQ_TAIL_REG, 99 HCLGE_COMM_NIC_CSQ_HEAD_REG, 100 HCLGE_COMM_NIC_CRQ_BASEADDR_L_REG, 101 HCLGE_COMM_NIC_CRQ_BASEADDR_H_REG, 102 HCLGE_COMM_NIC_CRQ_DEPTH_REG, 103 HCLGE_COMM_NIC_CRQ_TAIL_REG, 104 HCLGE_COMM_NIC_CRQ_HEAD_REG, 105 HCLGE_COMM_VECTOR0_CMDQ_SRC_REG, 106 HCLGE_COMM_CMDQ_INTR_STS_REG, 107 HCLGE_COMM_CMDQ_INTR_EN_REG, 108 HCLGE_COMM_CMDQ_INTR_GEN_REG}; 109 110 static const u32 common_reg_addr_list[] = {HCLGE_MISC_VECTOR_REG_BASE, 111 HCLGE_PF_OTHER_INT_REG, 112 HCLGE_MISC_RESET_STS_REG, 113 HCLGE_MISC_VECTOR_INT_STS, 114 HCLGE_GLOBAL_RESET_REG, 115 HCLGE_FUN_RST_ING, 116 HCLGE_GRO_EN_REG}; 117 118 static const u32 ring_reg_addr_list[] = {HCLGE_RING_RX_ADDR_L_REG, 119 HCLGE_RING_RX_ADDR_H_REG, 120 HCLGE_RING_RX_BD_NUM_REG, 121 HCLGE_RING_RX_BD_LENGTH_REG, 122 HCLGE_RING_RX_MERGE_EN_REG, 123 HCLGE_RING_RX_TAIL_REG, 124 HCLGE_RING_RX_HEAD_REG, 125 HCLGE_RING_RX_FBD_NUM_REG, 126 HCLGE_RING_RX_OFFSET_REG, 127 HCLGE_RING_RX_FBD_OFFSET_REG, 128 HCLGE_RING_RX_STASH_REG, 129 HCLGE_RING_RX_BD_ERR_REG, 130 HCLGE_RING_TX_ADDR_L_REG, 131 HCLGE_RING_TX_ADDR_H_REG, 132 HCLGE_RING_TX_BD_NUM_REG, 133 HCLGE_RING_TX_PRIORITY_REG, 134 HCLGE_RING_TX_TC_REG, 135 HCLGE_RING_TX_MERGE_EN_REG, 136 HCLGE_RING_TX_TAIL_REG, 137 HCLGE_RING_TX_HEAD_REG, 138 HCLGE_RING_TX_FBD_NUM_REG, 139 HCLGE_RING_TX_OFFSET_REG, 140 HCLGE_RING_TX_EBD_NUM_REG, 141 HCLGE_RING_TX_EBD_OFFSET_REG, 142 HCLGE_RING_TX_BD_ERR_REG, 143 HCLGE_RING_EN_REG}; 144 145 static const u32 tqp_intr_reg_addr_list[] = {HCLGE_TQP_INTR_CTRL_REG, 146 HCLGE_TQP_INTR_GL0_REG, 147 HCLGE_TQP_INTR_GL1_REG, 148 HCLGE_TQP_INTR_GL2_REG, 149 HCLGE_TQP_INTR_RL_REG}; 150 151 static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = { 152 "External Loopback test", 153 "App Loopback test", 154 "Serdes serial Loopback test", 155 "Serdes parallel Loopback test", 156 "Phy Loopback test" 157 }; 158 159 static const struct hclge_comm_stats_str g_mac_stats_string[] = { 160 {"mac_tx_mac_pause_num", HCLGE_MAC_STATS_MAX_NUM_V1, 161 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)}, 162 {"mac_rx_mac_pause_num", HCLGE_MAC_STATS_MAX_NUM_V1, 163 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)}, 164 {"mac_tx_pause_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 165 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pause_xoff_time)}, 166 {"mac_rx_pause_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 167 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pause_xoff_time)}, 168 {"mac_tx_control_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 169 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_ctrl_pkt_num)}, 170 {"mac_rx_control_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 171 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_ctrl_pkt_num)}, 172 {"mac_tx_pfc_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 173 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pause_pkt_num)}, 174 {"mac_tx_pfc_pri0_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 175 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)}, 176 {"mac_tx_pfc_pri1_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 177 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)}, 178 {"mac_tx_pfc_pri2_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 179 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)}, 180 {"mac_tx_pfc_pri3_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 181 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)}, 182 {"mac_tx_pfc_pri4_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 183 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)}, 184 {"mac_tx_pfc_pri5_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 185 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)}, 186 {"mac_tx_pfc_pri6_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 187 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)}, 188 {"mac_tx_pfc_pri7_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 189 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)}, 190 {"mac_tx_pfc_pri0_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 191 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_xoff_time)}, 192 {"mac_tx_pfc_pri1_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 193 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_xoff_time)}, 194 {"mac_tx_pfc_pri2_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 195 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_xoff_time)}, 196 {"mac_tx_pfc_pri3_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 197 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_xoff_time)}, 198 {"mac_tx_pfc_pri4_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 199 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_xoff_time)}, 200 {"mac_tx_pfc_pri5_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 201 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_xoff_time)}, 202 {"mac_tx_pfc_pri6_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 203 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_xoff_time)}, 204 {"mac_tx_pfc_pri7_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 205 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_xoff_time)}, 206 {"mac_rx_pfc_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 207 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pause_pkt_num)}, 208 {"mac_rx_pfc_pri0_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 209 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)}, 210 {"mac_rx_pfc_pri1_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 211 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)}, 212 {"mac_rx_pfc_pri2_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 213 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)}, 214 {"mac_rx_pfc_pri3_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 215 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)}, 216 {"mac_rx_pfc_pri4_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 217 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)}, 218 {"mac_rx_pfc_pri5_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 219 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)}, 220 {"mac_rx_pfc_pri6_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 221 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)}, 222 {"mac_rx_pfc_pri7_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 223 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)}, 224 {"mac_rx_pfc_pri0_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 225 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_xoff_time)}, 226 {"mac_rx_pfc_pri1_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 227 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_xoff_time)}, 228 {"mac_rx_pfc_pri2_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 229 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_xoff_time)}, 230 {"mac_rx_pfc_pri3_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 231 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_xoff_time)}, 232 {"mac_rx_pfc_pri4_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 233 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_xoff_time)}, 234 {"mac_rx_pfc_pri5_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 235 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_xoff_time)}, 236 {"mac_rx_pfc_pri6_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 237 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_xoff_time)}, 238 {"mac_rx_pfc_pri7_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 239 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_xoff_time)}, 240 {"mac_tx_total_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 241 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)}, 242 {"mac_tx_total_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 243 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)}, 244 {"mac_tx_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 245 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)}, 246 {"mac_tx_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 247 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)}, 248 {"mac_tx_good_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 249 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)}, 250 {"mac_tx_bad_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 251 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)}, 252 {"mac_tx_uni_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 253 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)}, 254 {"mac_tx_multi_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 255 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)}, 256 {"mac_tx_broad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 257 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)}, 258 {"mac_tx_undersize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 259 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)}, 260 {"mac_tx_oversize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 261 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)}, 262 {"mac_tx_64_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 263 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)}, 264 {"mac_tx_65_127_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 265 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)}, 266 {"mac_tx_128_255_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 267 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)}, 268 {"mac_tx_256_511_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 269 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)}, 270 {"mac_tx_512_1023_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 271 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)}, 272 {"mac_tx_1024_1518_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 273 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)}, 274 {"mac_tx_1519_2047_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 275 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num)}, 276 {"mac_tx_2048_4095_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 277 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)}, 278 {"mac_tx_4096_8191_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 279 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)}, 280 {"mac_tx_8192_9216_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 281 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)}, 282 {"mac_tx_9217_12287_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 283 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num)}, 284 {"mac_tx_12288_16383_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 285 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num)}, 286 {"mac_tx_1519_max_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 287 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num)}, 288 {"mac_tx_1519_max_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 289 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num)}, 290 {"mac_rx_total_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 291 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)}, 292 {"mac_rx_total_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 293 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)}, 294 {"mac_rx_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 295 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)}, 296 {"mac_rx_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 297 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)}, 298 {"mac_rx_good_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 299 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)}, 300 {"mac_rx_bad_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 301 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)}, 302 {"mac_rx_uni_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 303 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)}, 304 {"mac_rx_multi_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 305 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)}, 306 {"mac_rx_broad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 307 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)}, 308 {"mac_rx_undersize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 309 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)}, 310 {"mac_rx_oversize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 311 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)}, 312 {"mac_rx_64_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 313 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)}, 314 {"mac_rx_65_127_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 315 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)}, 316 {"mac_rx_128_255_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 317 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)}, 318 {"mac_rx_256_511_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 319 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)}, 320 {"mac_rx_512_1023_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 321 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)}, 322 {"mac_rx_1024_1518_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 323 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)}, 324 {"mac_rx_1519_2047_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 325 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num)}, 326 {"mac_rx_2048_4095_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 327 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)}, 328 {"mac_rx_4096_8191_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 329 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)}, 330 {"mac_rx_8192_9216_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 331 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)}, 332 {"mac_rx_9217_12287_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 333 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num)}, 334 {"mac_rx_12288_16383_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 335 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num)}, 336 {"mac_rx_1519_max_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 337 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num)}, 338 {"mac_rx_1519_max_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 339 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num)}, 340 341 {"mac_tx_fragment_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 342 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)}, 343 {"mac_tx_undermin_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 344 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)}, 345 {"mac_tx_jabber_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 346 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)}, 347 {"mac_tx_err_all_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 348 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)}, 349 {"mac_tx_from_app_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 350 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)}, 351 {"mac_tx_from_app_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 352 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)}, 353 {"mac_rx_fragment_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 354 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)}, 355 {"mac_rx_undermin_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 356 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)}, 357 {"mac_rx_jabber_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 358 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)}, 359 {"mac_rx_fcs_err_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 360 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)}, 361 {"mac_rx_send_app_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 362 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)}, 363 {"mac_rx_send_app_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 364 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)} 365 }; 366 367 static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = { 368 { 369 .flags = HCLGE_MAC_MGR_MASK_VLAN_B, 370 .ethter_type = cpu_to_le16(ETH_P_LLDP), 371 .mac_addr = {0x01, 0x80, 0xc2, 0x00, 0x00, 0x0e}, 372 .i_port_bitmap = 0x1, 373 }, 374 }; 375 376 static const u32 hclge_dfx_bd_offset_list[] = { 377 HCLGE_DFX_BIOS_BD_OFFSET, 378 HCLGE_DFX_SSU_0_BD_OFFSET, 379 HCLGE_DFX_SSU_1_BD_OFFSET, 380 HCLGE_DFX_IGU_BD_OFFSET, 381 HCLGE_DFX_RPU_0_BD_OFFSET, 382 HCLGE_DFX_RPU_1_BD_OFFSET, 383 HCLGE_DFX_NCSI_BD_OFFSET, 384 HCLGE_DFX_RTC_BD_OFFSET, 385 HCLGE_DFX_PPP_BD_OFFSET, 386 HCLGE_DFX_RCB_BD_OFFSET, 387 HCLGE_DFX_TQP_BD_OFFSET, 388 HCLGE_DFX_SSU_2_BD_OFFSET 389 }; 390 391 static const enum hclge_opcode_type hclge_dfx_reg_opcode_list[] = { 392 HCLGE_OPC_DFX_BIOS_COMMON_REG, 393 HCLGE_OPC_DFX_SSU_REG_0, 394 HCLGE_OPC_DFX_SSU_REG_1, 395 HCLGE_OPC_DFX_IGU_EGU_REG, 396 HCLGE_OPC_DFX_RPU_REG_0, 397 HCLGE_OPC_DFX_RPU_REG_1, 398 HCLGE_OPC_DFX_NCSI_REG, 399 HCLGE_OPC_DFX_RTC_REG, 400 HCLGE_OPC_DFX_PPP_REG, 401 HCLGE_OPC_DFX_RCB_REG, 402 HCLGE_OPC_DFX_TQP_REG, 403 HCLGE_OPC_DFX_SSU_REG_2 404 }; 405 406 static const struct key_info meta_data_key_info[] = { 407 { PACKET_TYPE_ID, 6 }, 408 { IP_FRAGEMENT, 1 }, 409 { ROCE_TYPE, 1 }, 410 { NEXT_KEY, 5 }, 411 { VLAN_NUMBER, 2 }, 412 { SRC_VPORT, 12 }, 413 { DST_VPORT, 12 }, 414 { TUNNEL_PACKET, 1 }, 415 }; 416 417 static const struct key_info tuple_key_info[] = { 418 { OUTER_DST_MAC, 48, KEY_OPT_MAC, -1, -1 }, 419 { OUTER_SRC_MAC, 48, KEY_OPT_MAC, -1, -1 }, 420 { OUTER_VLAN_TAG_FST, 16, KEY_OPT_LE16, -1, -1 }, 421 { OUTER_VLAN_TAG_SEC, 16, KEY_OPT_LE16, -1, -1 }, 422 { OUTER_ETH_TYPE, 16, KEY_OPT_LE16, -1, -1 }, 423 { OUTER_L2_RSV, 16, KEY_OPT_LE16, -1, -1 }, 424 { OUTER_IP_TOS, 8, KEY_OPT_U8, -1, -1 }, 425 { OUTER_IP_PROTO, 8, KEY_OPT_U8, -1, -1 }, 426 { OUTER_SRC_IP, 32, KEY_OPT_IP, -1, -1 }, 427 { OUTER_DST_IP, 32, KEY_OPT_IP, -1, -1 }, 428 { OUTER_L3_RSV, 16, KEY_OPT_LE16, -1, -1 }, 429 { OUTER_SRC_PORT, 16, KEY_OPT_LE16, -1, -1 }, 430 { OUTER_DST_PORT, 16, KEY_OPT_LE16, -1, -1 }, 431 { OUTER_L4_RSV, 32, KEY_OPT_LE32, -1, -1 }, 432 { OUTER_TUN_VNI, 24, KEY_OPT_VNI, -1, -1 }, 433 { OUTER_TUN_FLOW_ID, 8, KEY_OPT_U8, -1, -1 }, 434 { INNER_DST_MAC, 48, KEY_OPT_MAC, 435 offsetof(struct hclge_fd_rule, tuples.dst_mac), 436 offsetof(struct hclge_fd_rule, tuples_mask.dst_mac) }, 437 { INNER_SRC_MAC, 48, KEY_OPT_MAC, 438 offsetof(struct hclge_fd_rule, tuples.src_mac), 439 offsetof(struct hclge_fd_rule, tuples_mask.src_mac) }, 440 { INNER_VLAN_TAG_FST, 16, KEY_OPT_LE16, 441 offsetof(struct hclge_fd_rule, tuples.vlan_tag1), 442 offsetof(struct hclge_fd_rule, tuples_mask.vlan_tag1) }, 443 { INNER_VLAN_TAG_SEC, 16, KEY_OPT_LE16, -1, -1 }, 444 { INNER_ETH_TYPE, 16, KEY_OPT_LE16, 445 offsetof(struct hclge_fd_rule, tuples.ether_proto), 446 offsetof(struct hclge_fd_rule, tuples_mask.ether_proto) }, 447 { INNER_L2_RSV, 16, KEY_OPT_LE16, 448 offsetof(struct hclge_fd_rule, tuples.l2_user_def), 449 offsetof(struct hclge_fd_rule, tuples_mask.l2_user_def) }, 450 { INNER_IP_TOS, 8, KEY_OPT_U8, 451 offsetof(struct hclge_fd_rule, tuples.ip_tos), 452 offsetof(struct hclge_fd_rule, tuples_mask.ip_tos) }, 453 { INNER_IP_PROTO, 8, KEY_OPT_U8, 454 offsetof(struct hclge_fd_rule, tuples.ip_proto), 455 offsetof(struct hclge_fd_rule, tuples_mask.ip_proto) }, 456 { INNER_SRC_IP, 32, KEY_OPT_IP, 457 offsetof(struct hclge_fd_rule, tuples.src_ip), 458 offsetof(struct hclge_fd_rule, tuples_mask.src_ip) }, 459 { INNER_DST_IP, 32, KEY_OPT_IP, 460 offsetof(struct hclge_fd_rule, tuples.dst_ip), 461 offsetof(struct hclge_fd_rule, tuples_mask.dst_ip) }, 462 { INNER_L3_RSV, 16, KEY_OPT_LE16, 463 offsetof(struct hclge_fd_rule, tuples.l3_user_def), 464 offsetof(struct hclge_fd_rule, tuples_mask.l3_user_def) }, 465 { INNER_SRC_PORT, 16, KEY_OPT_LE16, 466 offsetof(struct hclge_fd_rule, tuples.src_port), 467 offsetof(struct hclge_fd_rule, tuples_mask.src_port) }, 468 { INNER_DST_PORT, 16, KEY_OPT_LE16, 469 offsetof(struct hclge_fd_rule, tuples.dst_port), 470 offsetof(struct hclge_fd_rule, tuples_mask.dst_port) }, 471 { INNER_L4_RSV, 32, KEY_OPT_LE32, 472 offsetof(struct hclge_fd_rule, tuples.l4_user_def), 473 offsetof(struct hclge_fd_rule, tuples_mask.l4_user_def) }, 474 }; 475 476 /** 477 * hclge_cmd_send - send command to command queue 478 * @hw: pointer to the hw struct 479 * @desc: prefilled descriptor for describing the command 480 * @num : the number of descriptors to be sent 481 * 482 * This is the main send command for command queue, it 483 * sends the queue, cleans the queue, etc 484 **/ 485 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num) 486 { 487 return hclge_comm_cmd_send(&hw->hw, desc, num); 488 } 489 490 static int hclge_mac_update_stats_defective(struct hclge_dev *hdev) 491 { 492 #define HCLGE_MAC_CMD_NUM 21 493 494 u64 *data = (u64 *)(&hdev->mac_stats); 495 struct hclge_desc desc[HCLGE_MAC_CMD_NUM]; 496 __le64 *desc_data; 497 u32 data_size; 498 int ret; 499 u32 i; 500 501 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true); 502 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM); 503 if (ret) { 504 dev_err(&hdev->pdev->dev, 505 "Get MAC pkt stats fail, status = %d.\n", ret); 506 507 return ret; 508 } 509 510 /* The first desc has a 64-bit header, so data size need to minus 1 */ 511 data_size = sizeof(desc) / (sizeof(u64)) - 1; 512 513 desc_data = (__le64 *)(&desc[0].data[0]); 514 for (i = 0; i < data_size; i++) { 515 /* data memory is continuous becase only the first desc has a 516 * header in this command 517 */ 518 *data += le64_to_cpu(*desc_data); 519 data++; 520 desc_data++; 521 } 522 523 return 0; 524 } 525 526 static int hclge_mac_update_stats_complete(struct hclge_dev *hdev) 527 { 528 #define HCLGE_REG_NUM_PER_DESC 4 529 530 u32 reg_num = hdev->ae_dev->dev_specs.mac_stats_num; 531 u64 *data = (u64 *)(&hdev->mac_stats); 532 struct hclge_desc *desc; 533 __le64 *desc_data; 534 u32 data_size; 535 u32 desc_num; 536 int ret; 537 u32 i; 538 539 /* The first desc has a 64-bit header, so need to consider it */ 540 desc_num = reg_num / HCLGE_REG_NUM_PER_DESC + 1; 541 542 /* This may be called inside atomic sections, 543 * so GFP_ATOMIC is more suitalbe here 544 */ 545 desc = kcalloc(desc_num, sizeof(struct hclge_desc), GFP_ATOMIC); 546 if (!desc) 547 return -ENOMEM; 548 549 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC_ALL, true); 550 ret = hclge_cmd_send(&hdev->hw, desc, desc_num); 551 if (ret) { 552 kfree(desc); 553 return ret; 554 } 555 556 data_size = min_t(u32, sizeof(hdev->mac_stats) / sizeof(u64), reg_num); 557 558 desc_data = (__le64 *)(&desc[0].data[0]); 559 for (i = 0; i < data_size; i++) { 560 /* data memory is continuous becase only the first desc has a 561 * header in this command 562 */ 563 *data += le64_to_cpu(*desc_data); 564 data++; 565 desc_data++; 566 } 567 568 kfree(desc); 569 570 return 0; 571 } 572 573 static int hclge_mac_query_reg_num(struct hclge_dev *hdev, u32 *reg_num) 574 { 575 struct hclge_desc desc; 576 int ret; 577 578 /* Driver needs total register number of both valid registers and 579 * reserved registers, but the old firmware only returns number 580 * of valid registers in device V2. To be compatible with these 581 * devices, driver uses a fixed value. 582 */ 583 if (hdev->ae_dev->dev_version == HNAE3_DEVICE_VERSION_V2) { 584 *reg_num = HCLGE_MAC_STATS_MAX_NUM_V1; 585 return 0; 586 } 587 588 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_MAC_REG_NUM, true); 589 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 590 if (ret) { 591 dev_err(&hdev->pdev->dev, 592 "failed to query mac statistic reg number, ret = %d\n", 593 ret); 594 return ret; 595 } 596 597 *reg_num = le32_to_cpu(desc.data[0]); 598 if (*reg_num == 0) { 599 dev_err(&hdev->pdev->dev, 600 "mac statistic reg number is invalid!\n"); 601 return -ENODATA; 602 } 603 604 return 0; 605 } 606 607 int hclge_mac_update_stats(struct hclge_dev *hdev) 608 { 609 /* The firmware supports the new statistics acquisition method */ 610 if (hdev->ae_dev->dev_specs.mac_stats_num) 611 return hclge_mac_update_stats_complete(hdev); 612 else 613 return hclge_mac_update_stats_defective(hdev); 614 } 615 616 static int hclge_comm_get_count(struct hclge_dev *hdev, 617 const struct hclge_comm_stats_str strs[], 618 u32 size) 619 { 620 int count = 0; 621 u32 i; 622 623 for (i = 0; i < size; i++) 624 if (strs[i].stats_num <= hdev->ae_dev->dev_specs.mac_stats_num) 625 count++; 626 627 return count; 628 } 629 630 static u64 *hclge_comm_get_stats(struct hclge_dev *hdev, 631 const struct hclge_comm_stats_str strs[], 632 int size, u64 *data) 633 { 634 u64 *buf = data; 635 u32 i; 636 637 for (i = 0; i < size; i++) { 638 if (strs[i].stats_num > hdev->ae_dev->dev_specs.mac_stats_num) 639 continue; 640 641 *buf = HCLGE_STATS_READ(&hdev->mac_stats, strs[i].offset); 642 buf++; 643 } 644 645 return buf; 646 } 647 648 static u8 *hclge_comm_get_strings(struct hclge_dev *hdev, u32 stringset, 649 const struct hclge_comm_stats_str strs[], 650 int size, u8 *data) 651 { 652 char *buff = (char *)data; 653 u32 i; 654 655 if (stringset != ETH_SS_STATS) 656 return buff; 657 658 for (i = 0; i < size; i++) { 659 if (strs[i].stats_num > hdev->ae_dev->dev_specs.mac_stats_num) 660 continue; 661 662 snprintf(buff, ETH_GSTRING_LEN, "%s", strs[i].desc); 663 buff = buff + ETH_GSTRING_LEN; 664 } 665 666 return (u8 *)buff; 667 } 668 669 static void hclge_update_stats_for_all(struct hclge_dev *hdev) 670 { 671 struct hnae3_handle *handle; 672 int status; 673 674 handle = &hdev->vport[0].nic; 675 if (handle->client) { 676 status = hclge_comm_tqps_update_stats(handle, &hdev->hw.hw); 677 if (status) { 678 dev_err(&hdev->pdev->dev, 679 "Update TQPS stats fail, status = %d.\n", 680 status); 681 } 682 } 683 684 hclge_update_fec_stats(hdev); 685 686 status = hclge_mac_update_stats(hdev); 687 if (status) 688 dev_err(&hdev->pdev->dev, 689 "Update MAC stats fail, status = %d.\n", status); 690 } 691 692 static void hclge_update_stats(struct hnae3_handle *handle, 693 struct net_device_stats *net_stats) 694 { 695 struct hclge_vport *vport = hclge_get_vport(handle); 696 struct hclge_dev *hdev = vport->back; 697 int status; 698 699 if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state)) 700 return; 701 702 status = hclge_mac_update_stats(hdev); 703 if (status) 704 dev_err(&hdev->pdev->dev, 705 "Update MAC stats fail, status = %d.\n", 706 status); 707 708 status = hclge_comm_tqps_update_stats(handle, &hdev->hw.hw); 709 if (status) 710 dev_err(&hdev->pdev->dev, 711 "Update TQPS stats fail, status = %d.\n", 712 status); 713 714 clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state); 715 } 716 717 static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset) 718 { 719 #define HCLGE_LOOPBACK_TEST_FLAGS (HNAE3_SUPPORT_APP_LOOPBACK | \ 720 HNAE3_SUPPORT_PHY_LOOPBACK | \ 721 HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK | \ 722 HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK | \ 723 HNAE3_SUPPORT_EXTERNAL_LOOPBACK) 724 725 struct hclge_vport *vport = hclge_get_vport(handle); 726 struct hclge_dev *hdev = vport->back; 727 int count = 0; 728 729 /* Loopback test support rules: 730 * mac: only GE mode support 731 * serdes: all mac mode will support include GE/XGE/LGE/CGE 732 * phy: only support when phy device exist on board 733 */ 734 if (stringset == ETH_SS_TEST) { 735 /* clear loopback bit flags at first */ 736 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS)); 737 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2 || 738 hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M || 739 hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M || 740 hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) { 741 count += 1; 742 handle->flags |= HNAE3_SUPPORT_APP_LOOPBACK; 743 } 744 745 count += 1; 746 handle->flags |= HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK; 747 count += 1; 748 handle->flags |= HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK; 749 count += 1; 750 handle->flags |= HNAE3_SUPPORT_EXTERNAL_LOOPBACK; 751 752 if ((hdev->hw.mac.phydev && hdev->hw.mac.phydev->drv && 753 hdev->hw.mac.phydev->drv->set_loopback) || 754 hnae3_dev_phy_imp_supported(hdev)) { 755 count += 1; 756 handle->flags |= HNAE3_SUPPORT_PHY_LOOPBACK; 757 } 758 } else if (stringset == ETH_SS_STATS) { 759 count = hclge_comm_get_count(hdev, g_mac_stats_string, 760 ARRAY_SIZE(g_mac_stats_string)) + 761 hclge_comm_tqps_get_sset_count(handle); 762 } 763 764 return count; 765 } 766 767 static void hclge_get_strings(struct hnae3_handle *handle, u32 stringset, 768 u8 *data) 769 { 770 struct hclge_vport *vport = hclge_get_vport(handle); 771 struct hclge_dev *hdev = vport->back; 772 u8 *p = (char *)data; 773 int size; 774 775 if (stringset == ETH_SS_STATS) { 776 size = ARRAY_SIZE(g_mac_stats_string); 777 p = hclge_comm_get_strings(hdev, stringset, g_mac_stats_string, 778 size, p); 779 p = hclge_comm_tqps_get_strings(handle, p); 780 } else if (stringset == ETH_SS_TEST) { 781 if (handle->flags & HNAE3_SUPPORT_EXTERNAL_LOOPBACK) { 782 memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_EXTERNAL], 783 ETH_GSTRING_LEN); 784 p += ETH_GSTRING_LEN; 785 } 786 if (handle->flags & HNAE3_SUPPORT_APP_LOOPBACK) { 787 memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_APP], 788 ETH_GSTRING_LEN); 789 p += ETH_GSTRING_LEN; 790 } 791 if (handle->flags & HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK) { 792 memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_SERIAL_SERDES], 793 ETH_GSTRING_LEN); 794 p += ETH_GSTRING_LEN; 795 } 796 if (handle->flags & HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK) { 797 memcpy(p, 798 hns3_nic_test_strs[HNAE3_LOOP_PARALLEL_SERDES], 799 ETH_GSTRING_LEN); 800 p += ETH_GSTRING_LEN; 801 } 802 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) { 803 memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_PHY], 804 ETH_GSTRING_LEN); 805 p += ETH_GSTRING_LEN; 806 } 807 } 808 } 809 810 static void hclge_get_stats(struct hnae3_handle *handle, u64 *data) 811 { 812 struct hclge_vport *vport = hclge_get_vport(handle); 813 struct hclge_dev *hdev = vport->back; 814 u64 *p; 815 816 p = hclge_comm_get_stats(hdev, g_mac_stats_string, 817 ARRAY_SIZE(g_mac_stats_string), data); 818 p = hclge_comm_tqps_get_stats(handle, p); 819 } 820 821 static void hclge_get_mac_stat(struct hnae3_handle *handle, 822 struct hns3_mac_stats *mac_stats) 823 { 824 struct hclge_vport *vport = hclge_get_vport(handle); 825 struct hclge_dev *hdev = vport->back; 826 827 hclge_update_stats(handle, NULL); 828 829 mac_stats->tx_pause_cnt = hdev->mac_stats.mac_tx_mac_pause_num; 830 mac_stats->rx_pause_cnt = hdev->mac_stats.mac_rx_mac_pause_num; 831 } 832 833 static int hclge_parse_func_status(struct hclge_dev *hdev, 834 struct hclge_func_status_cmd *status) 835 { 836 #define HCLGE_MAC_ID_MASK 0xF 837 838 if (!(status->pf_state & HCLGE_PF_STATE_DONE)) 839 return -EINVAL; 840 841 /* Set the pf to main pf */ 842 if (status->pf_state & HCLGE_PF_STATE_MAIN) 843 hdev->flag |= HCLGE_FLAG_MAIN; 844 else 845 hdev->flag &= ~HCLGE_FLAG_MAIN; 846 847 hdev->hw.mac.mac_id = status->mac_id & HCLGE_MAC_ID_MASK; 848 return 0; 849 } 850 851 static int hclge_query_function_status(struct hclge_dev *hdev) 852 { 853 #define HCLGE_QUERY_MAX_CNT 5 854 855 struct hclge_func_status_cmd *req; 856 struct hclge_desc desc; 857 int timeout = 0; 858 int ret; 859 860 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true); 861 req = (struct hclge_func_status_cmd *)desc.data; 862 863 do { 864 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 865 if (ret) { 866 dev_err(&hdev->pdev->dev, 867 "query function status failed %d.\n", ret); 868 return ret; 869 } 870 871 /* Check pf reset is done */ 872 if (req->pf_state) 873 break; 874 usleep_range(1000, 2000); 875 } while (timeout++ < HCLGE_QUERY_MAX_CNT); 876 877 return hclge_parse_func_status(hdev, req); 878 } 879 880 static int hclge_query_pf_resource(struct hclge_dev *hdev) 881 { 882 struct hclge_pf_res_cmd *req; 883 struct hclge_desc desc; 884 int ret; 885 886 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true); 887 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 888 if (ret) { 889 dev_err(&hdev->pdev->dev, 890 "query pf resource failed %d.\n", ret); 891 return ret; 892 } 893 894 req = (struct hclge_pf_res_cmd *)desc.data; 895 hdev->num_tqps = le16_to_cpu(req->tqp_num) + 896 le16_to_cpu(req->ext_tqp_num); 897 hdev->pkt_buf_size = le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S; 898 899 if (req->tx_buf_size) 900 hdev->tx_buf_size = 901 le16_to_cpu(req->tx_buf_size) << HCLGE_BUF_UNIT_S; 902 else 903 hdev->tx_buf_size = HCLGE_DEFAULT_TX_BUF; 904 905 hdev->tx_buf_size = roundup(hdev->tx_buf_size, HCLGE_BUF_SIZE_UNIT); 906 907 if (req->dv_buf_size) 908 hdev->dv_buf_size = 909 le16_to_cpu(req->dv_buf_size) << HCLGE_BUF_UNIT_S; 910 else 911 hdev->dv_buf_size = HCLGE_DEFAULT_DV; 912 913 hdev->dv_buf_size = roundup(hdev->dv_buf_size, HCLGE_BUF_SIZE_UNIT); 914 915 hdev->num_nic_msi = le16_to_cpu(req->msixcap_localid_number_nic); 916 if (hdev->num_nic_msi < HNAE3_MIN_VECTOR_NUM) { 917 dev_err(&hdev->pdev->dev, 918 "only %u msi resources available, not enough for pf(min:2).\n", 919 hdev->num_nic_msi); 920 return -EINVAL; 921 } 922 923 if (hnae3_dev_roce_supported(hdev)) { 924 hdev->num_roce_msi = 925 le16_to_cpu(req->pf_intr_vector_number_roce); 926 927 /* PF should have NIC vectors and Roce vectors, 928 * NIC vectors are queued before Roce vectors. 929 */ 930 hdev->num_msi = hdev->num_nic_msi + hdev->num_roce_msi; 931 } else { 932 hdev->num_msi = hdev->num_nic_msi; 933 } 934 935 return 0; 936 } 937 938 static int hclge_parse_speed(u8 speed_cmd, u32 *speed) 939 { 940 switch (speed_cmd) { 941 case HCLGE_FW_MAC_SPEED_10M: 942 *speed = HCLGE_MAC_SPEED_10M; 943 break; 944 case HCLGE_FW_MAC_SPEED_100M: 945 *speed = HCLGE_MAC_SPEED_100M; 946 break; 947 case HCLGE_FW_MAC_SPEED_1G: 948 *speed = HCLGE_MAC_SPEED_1G; 949 break; 950 case HCLGE_FW_MAC_SPEED_10G: 951 *speed = HCLGE_MAC_SPEED_10G; 952 break; 953 case HCLGE_FW_MAC_SPEED_25G: 954 *speed = HCLGE_MAC_SPEED_25G; 955 break; 956 case HCLGE_FW_MAC_SPEED_40G: 957 *speed = HCLGE_MAC_SPEED_40G; 958 break; 959 case HCLGE_FW_MAC_SPEED_50G: 960 *speed = HCLGE_MAC_SPEED_50G; 961 break; 962 case HCLGE_FW_MAC_SPEED_100G: 963 *speed = HCLGE_MAC_SPEED_100G; 964 break; 965 case HCLGE_FW_MAC_SPEED_200G: 966 *speed = HCLGE_MAC_SPEED_200G; 967 break; 968 default: 969 return -EINVAL; 970 } 971 972 return 0; 973 } 974 975 static const struct hclge_speed_bit_map speed_bit_map[] = { 976 {HCLGE_MAC_SPEED_10M, HCLGE_SUPPORT_10M_BIT}, 977 {HCLGE_MAC_SPEED_100M, HCLGE_SUPPORT_100M_BIT}, 978 {HCLGE_MAC_SPEED_1G, HCLGE_SUPPORT_1G_BIT}, 979 {HCLGE_MAC_SPEED_10G, HCLGE_SUPPORT_10G_BIT}, 980 {HCLGE_MAC_SPEED_25G, HCLGE_SUPPORT_25G_BIT}, 981 {HCLGE_MAC_SPEED_40G, HCLGE_SUPPORT_40G_BIT}, 982 {HCLGE_MAC_SPEED_50G, HCLGE_SUPPORT_50G_BIT}, 983 {HCLGE_MAC_SPEED_100G, HCLGE_SUPPORT_100G_BIT}, 984 {HCLGE_MAC_SPEED_200G, HCLGE_SUPPORT_200G_BIT}, 985 }; 986 987 static int hclge_get_speed_bit(u32 speed, u32 *speed_bit) 988 { 989 u16 i; 990 991 for (i = 0; i < ARRAY_SIZE(speed_bit_map); i++) { 992 if (speed == speed_bit_map[i].speed) { 993 *speed_bit = speed_bit_map[i].speed_bit; 994 return 0; 995 } 996 } 997 998 return -EINVAL; 999 } 1000 1001 static int hclge_check_port_speed(struct hnae3_handle *handle, u32 speed) 1002 { 1003 struct hclge_vport *vport = hclge_get_vport(handle); 1004 struct hclge_dev *hdev = vport->back; 1005 u32 speed_ability = hdev->hw.mac.speed_ability; 1006 u32 speed_bit = 0; 1007 int ret; 1008 1009 ret = hclge_get_speed_bit(speed, &speed_bit); 1010 if (ret) 1011 return ret; 1012 1013 if (speed_bit & speed_ability) 1014 return 0; 1015 1016 return -EINVAL; 1017 } 1018 1019 static void hclge_update_fec_support(struct hclge_mac *mac) 1020 { 1021 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, mac->supported); 1022 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, mac->supported); 1023 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, mac->supported); 1024 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported); 1025 1026 if (mac->fec_ability & BIT(HNAE3_FEC_BASER)) 1027 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 1028 mac->supported); 1029 if (mac->fec_ability & BIT(HNAE3_FEC_RS)) 1030 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 1031 mac->supported); 1032 if (mac->fec_ability & BIT(HNAE3_FEC_LLRS)) 1033 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 1034 mac->supported); 1035 if (mac->fec_ability & BIT(HNAE3_FEC_NONE)) 1036 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 1037 mac->supported); 1038 } 1039 1040 static void hclge_convert_setting_sr(u16 speed_ability, 1041 unsigned long *link_mode) 1042 { 1043 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 1044 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, 1045 link_mode); 1046 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 1047 linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 1048 link_mode); 1049 if (speed_ability & HCLGE_SUPPORT_40G_BIT) 1050 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT, 1051 link_mode); 1052 if (speed_ability & HCLGE_SUPPORT_50G_BIT) 1053 linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT, 1054 link_mode); 1055 if (speed_ability & HCLGE_SUPPORT_100G_BIT) 1056 linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, 1057 link_mode); 1058 if (speed_ability & HCLGE_SUPPORT_200G_BIT) 1059 linkmode_set_bit(ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT, 1060 link_mode); 1061 } 1062 1063 static void hclge_convert_setting_lr(u16 speed_ability, 1064 unsigned long *link_mode) 1065 { 1066 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 1067 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, 1068 link_mode); 1069 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 1070 linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 1071 link_mode); 1072 if (speed_ability & HCLGE_SUPPORT_50G_BIT) 1073 linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT, 1074 link_mode); 1075 if (speed_ability & HCLGE_SUPPORT_40G_BIT) 1076 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT, 1077 link_mode); 1078 if (speed_ability & HCLGE_SUPPORT_100G_BIT) 1079 linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT, 1080 link_mode); 1081 if (speed_ability & HCLGE_SUPPORT_200G_BIT) 1082 linkmode_set_bit( 1083 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT, 1084 link_mode); 1085 } 1086 1087 static void hclge_convert_setting_cr(u16 speed_ability, 1088 unsigned long *link_mode) 1089 { 1090 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 1091 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseCR_Full_BIT, 1092 link_mode); 1093 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 1094 linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseCR_Full_BIT, 1095 link_mode); 1096 if (speed_ability & HCLGE_SUPPORT_40G_BIT) 1097 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, 1098 link_mode); 1099 if (speed_ability & HCLGE_SUPPORT_50G_BIT) 1100 linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT, 1101 link_mode); 1102 if (speed_ability & HCLGE_SUPPORT_100G_BIT) 1103 linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, 1104 link_mode); 1105 if (speed_ability & HCLGE_SUPPORT_200G_BIT) 1106 linkmode_set_bit(ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT, 1107 link_mode); 1108 } 1109 1110 static void hclge_convert_setting_kr(u16 speed_ability, 1111 unsigned long *link_mode) 1112 { 1113 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1114 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 1115 link_mode); 1116 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 1117 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 1118 link_mode); 1119 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 1120 linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseKR_Full_BIT, 1121 link_mode); 1122 if (speed_ability & HCLGE_SUPPORT_40G_BIT) 1123 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, 1124 link_mode); 1125 if (speed_ability & HCLGE_SUPPORT_50G_BIT) 1126 linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT, 1127 link_mode); 1128 if (speed_ability & HCLGE_SUPPORT_100G_BIT) 1129 linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT, 1130 link_mode); 1131 if (speed_ability & HCLGE_SUPPORT_200G_BIT) 1132 linkmode_set_bit(ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT, 1133 link_mode); 1134 } 1135 1136 static void hclge_convert_setting_fec(struct hclge_mac *mac) 1137 { 1138 /* If firmware has reported fec_ability, don't need to convert by speed */ 1139 if (mac->fec_ability) 1140 goto out; 1141 1142 switch (mac->speed) { 1143 case HCLGE_MAC_SPEED_10G: 1144 case HCLGE_MAC_SPEED_40G: 1145 mac->fec_ability = BIT(HNAE3_FEC_BASER) | BIT(HNAE3_FEC_AUTO) | 1146 BIT(HNAE3_FEC_NONE); 1147 break; 1148 case HCLGE_MAC_SPEED_25G: 1149 case HCLGE_MAC_SPEED_50G: 1150 mac->fec_ability = BIT(HNAE3_FEC_BASER) | BIT(HNAE3_FEC_RS) | 1151 BIT(HNAE3_FEC_AUTO) | BIT(HNAE3_FEC_NONE); 1152 break; 1153 case HCLGE_MAC_SPEED_100G: 1154 mac->fec_ability = BIT(HNAE3_FEC_RS) | BIT(HNAE3_FEC_AUTO) | 1155 BIT(HNAE3_FEC_NONE); 1156 break; 1157 case HCLGE_MAC_SPEED_200G: 1158 mac->fec_ability = BIT(HNAE3_FEC_RS) | BIT(HNAE3_FEC_AUTO) | 1159 BIT(HNAE3_FEC_LLRS); 1160 break; 1161 default: 1162 mac->fec_ability = 0; 1163 break; 1164 } 1165 1166 out: 1167 hclge_update_fec_support(mac); 1168 } 1169 1170 static void hclge_parse_fiber_link_mode(struct hclge_dev *hdev, 1171 u16 speed_ability) 1172 { 1173 struct hclge_mac *mac = &hdev->hw.mac; 1174 1175 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1176 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 1177 mac->supported); 1178 1179 hclge_convert_setting_sr(speed_ability, mac->supported); 1180 hclge_convert_setting_lr(speed_ability, mac->supported); 1181 hclge_convert_setting_cr(speed_ability, mac->supported); 1182 if (hnae3_dev_fec_supported(hdev)) 1183 hclge_convert_setting_fec(mac); 1184 1185 if (hnae3_dev_pause_supported(hdev)) 1186 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, mac->supported); 1187 1188 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, mac->supported); 1189 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported); 1190 } 1191 1192 static void hclge_parse_backplane_link_mode(struct hclge_dev *hdev, 1193 u16 speed_ability) 1194 { 1195 struct hclge_mac *mac = &hdev->hw.mac; 1196 1197 hclge_convert_setting_kr(speed_ability, mac->supported); 1198 if (hnae3_dev_fec_supported(hdev)) 1199 hclge_convert_setting_fec(mac); 1200 1201 if (hnae3_dev_pause_supported(hdev)) 1202 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, mac->supported); 1203 1204 linkmode_set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, mac->supported); 1205 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported); 1206 } 1207 1208 static void hclge_parse_copper_link_mode(struct hclge_dev *hdev, 1209 u16 speed_ability) 1210 { 1211 unsigned long *supported = hdev->hw.mac.supported; 1212 1213 /* default to support all speed for GE port */ 1214 if (!speed_ability) 1215 speed_ability = HCLGE_SUPPORT_GE; 1216 1217 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1218 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 1219 supported); 1220 1221 if (speed_ability & HCLGE_SUPPORT_100M_BIT) { 1222 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, 1223 supported); 1224 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, 1225 supported); 1226 } 1227 1228 if (speed_ability & HCLGE_SUPPORT_10M_BIT) { 1229 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, supported); 1230 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, supported); 1231 } 1232 1233 if (hnae3_dev_pause_supported(hdev)) { 1234 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported); 1235 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, supported); 1236 } 1237 1238 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, supported); 1239 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, supported); 1240 } 1241 1242 static void hclge_parse_link_mode(struct hclge_dev *hdev, u16 speed_ability) 1243 { 1244 u8 media_type = hdev->hw.mac.media_type; 1245 1246 if (media_type == HNAE3_MEDIA_TYPE_FIBER) 1247 hclge_parse_fiber_link_mode(hdev, speed_ability); 1248 else if (media_type == HNAE3_MEDIA_TYPE_COPPER) 1249 hclge_parse_copper_link_mode(hdev, speed_ability); 1250 else if (media_type == HNAE3_MEDIA_TYPE_BACKPLANE) 1251 hclge_parse_backplane_link_mode(hdev, speed_ability); 1252 } 1253 1254 static u32 hclge_get_max_speed(u16 speed_ability) 1255 { 1256 if (speed_ability & HCLGE_SUPPORT_200G_BIT) 1257 return HCLGE_MAC_SPEED_200G; 1258 1259 if (speed_ability & HCLGE_SUPPORT_100G_BIT) 1260 return HCLGE_MAC_SPEED_100G; 1261 1262 if (speed_ability & HCLGE_SUPPORT_50G_BIT) 1263 return HCLGE_MAC_SPEED_50G; 1264 1265 if (speed_ability & HCLGE_SUPPORT_40G_BIT) 1266 return HCLGE_MAC_SPEED_40G; 1267 1268 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 1269 return HCLGE_MAC_SPEED_25G; 1270 1271 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 1272 return HCLGE_MAC_SPEED_10G; 1273 1274 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1275 return HCLGE_MAC_SPEED_1G; 1276 1277 if (speed_ability & HCLGE_SUPPORT_100M_BIT) 1278 return HCLGE_MAC_SPEED_100M; 1279 1280 if (speed_ability & HCLGE_SUPPORT_10M_BIT) 1281 return HCLGE_MAC_SPEED_10M; 1282 1283 return HCLGE_MAC_SPEED_1G; 1284 } 1285 1286 static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc) 1287 { 1288 #define HCLGE_TX_SPARE_SIZE_UNIT 4096 1289 #define SPEED_ABILITY_EXT_SHIFT 8 1290 1291 struct hclge_cfg_param_cmd *req; 1292 u64 mac_addr_tmp_high; 1293 u16 speed_ability_ext; 1294 u64 mac_addr_tmp; 1295 unsigned int i; 1296 1297 req = (struct hclge_cfg_param_cmd *)desc[0].data; 1298 1299 /* get the configuration */ 1300 cfg->tc_num = hnae3_get_field(__le32_to_cpu(req->param[0]), 1301 HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S); 1302 cfg->tqp_desc_num = hnae3_get_field(__le32_to_cpu(req->param[0]), 1303 HCLGE_CFG_TQP_DESC_N_M, 1304 HCLGE_CFG_TQP_DESC_N_S); 1305 1306 cfg->phy_addr = hnae3_get_field(__le32_to_cpu(req->param[1]), 1307 HCLGE_CFG_PHY_ADDR_M, 1308 HCLGE_CFG_PHY_ADDR_S); 1309 cfg->media_type = hnae3_get_field(__le32_to_cpu(req->param[1]), 1310 HCLGE_CFG_MEDIA_TP_M, 1311 HCLGE_CFG_MEDIA_TP_S); 1312 cfg->rx_buf_len = hnae3_get_field(__le32_to_cpu(req->param[1]), 1313 HCLGE_CFG_RX_BUF_LEN_M, 1314 HCLGE_CFG_RX_BUF_LEN_S); 1315 /* get mac_address */ 1316 mac_addr_tmp = __le32_to_cpu(req->param[2]); 1317 mac_addr_tmp_high = hnae3_get_field(__le32_to_cpu(req->param[3]), 1318 HCLGE_CFG_MAC_ADDR_H_M, 1319 HCLGE_CFG_MAC_ADDR_H_S); 1320 1321 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1; 1322 1323 cfg->default_speed = hnae3_get_field(__le32_to_cpu(req->param[3]), 1324 HCLGE_CFG_DEFAULT_SPEED_M, 1325 HCLGE_CFG_DEFAULT_SPEED_S); 1326 cfg->vf_rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[3]), 1327 HCLGE_CFG_RSS_SIZE_M, 1328 HCLGE_CFG_RSS_SIZE_S); 1329 1330 for (i = 0; i < ETH_ALEN; i++) 1331 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff; 1332 1333 req = (struct hclge_cfg_param_cmd *)desc[1].data; 1334 cfg->numa_node_map = __le32_to_cpu(req->param[0]); 1335 1336 cfg->speed_ability = hnae3_get_field(__le32_to_cpu(req->param[1]), 1337 HCLGE_CFG_SPEED_ABILITY_M, 1338 HCLGE_CFG_SPEED_ABILITY_S); 1339 speed_ability_ext = hnae3_get_field(__le32_to_cpu(req->param[1]), 1340 HCLGE_CFG_SPEED_ABILITY_EXT_M, 1341 HCLGE_CFG_SPEED_ABILITY_EXT_S); 1342 cfg->speed_ability |= speed_ability_ext << SPEED_ABILITY_EXT_SHIFT; 1343 1344 cfg->vlan_fliter_cap = hnae3_get_field(__le32_to_cpu(req->param[1]), 1345 HCLGE_CFG_VLAN_FLTR_CAP_M, 1346 HCLGE_CFG_VLAN_FLTR_CAP_S); 1347 1348 cfg->umv_space = hnae3_get_field(__le32_to_cpu(req->param[1]), 1349 HCLGE_CFG_UMV_TBL_SPACE_M, 1350 HCLGE_CFG_UMV_TBL_SPACE_S); 1351 1352 cfg->pf_rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[2]), 1353 HCLGE_CFG_PF_RSS_SIZE_M, 1354 HCLGE_CFG_PF_RSS_SIZE_S); 1355 1356 /* HCLGE_CFG_PF_RSS_SIZE_M is the PF max rss size, which is a 1357 * power of 2, instead of reading out directly. This would 1358 * be more flexible for future changes and expansions. 1359 * When VF max rss size field is HCLGE_CFG_RSS_SIZE_S, 1360 * it does not make sense if PF's field is 0. In this case, PF and VF 1361 * has the same max rss size filed: HCLGE_CFG_RSS_SIZE_S. 1362 */ 1363 cfg->pf_rss_size_max = cfg->pf_rss_size_max ? 1364 1U << cfg->pf_rss_size_max : 1365 cfg->vf_rss_size_max; 1366 1367 /* The unit of the tx spare buffer size queried from configuration 1368 * file is HCLGE_TX_SPARE_SIZE_UNIT(4096) bytes, so a conversion is 1369 * needed here. 1370 */ 1371 cfg->tx_spare_buf_size = hnae3_get_field(__le32_to_cpu(req->param[2]), 1372 HCLGE_CFG_TX_SPARE_BUF_SIZE_M, 1373 HCLGE_CFG_TX_SPARE_BUF_SIZE_S); 1374 cfg->tx_spare_buf_size *= HCLGE_TX_SPARE_SIZE_UNIT; 1375 } 1376 1377 /* hclge_get_cfg: query the static parameter from flash 1378 * @hdev: pointer to struct hclge_dev 1379 * @hcfg: the config structure to be getted 1380 */ 1381 static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg) 1382 { 1383 struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM]; 1384 struct hclge_cfg_param_cmd *req; 1385 unsigned int i; 1386 int ret; 1387 1388 for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) { 1389 u32 offset = 0; 1390 1391 req = (struct hclge_cfg_param_cmd *)desc[i].data; 1392 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM, 1393 true); 1394 hnae3_set_field(offset, HCLGE_CFG_OFFSET_M, 1395 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES); 1396 /* Len should be united by 4 bytes when send to hardware */ 1397 hnae3_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S, 1398 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT); 1399 req->offset = cpu_to_le32(offset); 1400 } 1401 1402 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM); 1403 if (ret) { 1404 dev_err(&hdev->pdev->dev, "get config failed %d.\n", ret); 1405 return ret; 1406 } 1407 1408 hclge_parse_cfg(hcfg, desc); 1409 1410 return 0; 1411 } 1412 1413 static void hclge_set_default_dev_specs(struct hclge_dev *hdev) 1414 { 1415 #define HCLGE_MAX_NON_TSO_BD_NUM 8U 1416 1417 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1418 1419 ae_dev->dev_specs.max_non_tso_bd_num = HCLGE_MAX_NON_TSO_BD_NUM; 1420 ae_dev->dev_specs.rss_ind_tbl_size = HCLGE_RSS_IND_TBL_SIZE; 1421 ae_dev->dev_specs.rss_key_size = HCLGE_COMM_RSS_KEY_SIZE; 1422 ae_dev->dev_specs.max_tm_rate = HCLGE_ETHER_MAX_RATE; 1423 ae_dev->dev_specs.max_int_gl = HCLGE_DEF_MAX_INT_GL; 1424 ae_dev->dev_specs.max_frm_size = HCLGE_MAC_MAX_FRAME; 1425 ae_dev->dev_specs.max_qset_num = HCLGE_MAX_QSET_NUM; 1426 ae_dev->dev_specs.umv_size = HCLGE_DEFAULT_UMV_SPACE_PER_PF; 1427 } 1428 1429 static void hclge_parse_dev_specs(struct hclge_dev *hdev, 1430 struct hclge_desc *desc) 1431 { 1432 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1433 struct hclge_dev_specs_0_cmd *req0; 1434 struct hclge_dev_specs_1_cmd *req1; 1435 1436 req0 = (struct hclge_dev_specs_0_cmd *)desc[0].data; 1437 req1 = (struct hclge_dev_specs_1_cmd *)desc[1].data; 1438 1439 ae_dev->dev_specs.max_non_tso_bd_num = req0->max_non_tso_bd_num; 1440 ae_dev->dev_specs.rss_ind_tbl_size = 1441 le16_to_cpu(req0->rss_ind_tbl_size); 1442 ae_dev->dev_specs.int_ql_max = le16_to_cpu(req0->int_ql_max); 1443 ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size); 1444 ae_dev->dev_specs.max_tm_rate = le32_to_cpu(req0->max_tm_rate); 1445 ae_dev->dev_specs.max_qset_num = le16_to_cpu(req1->max_qset_num); 1446 ae_dev->dev_specs.max_int_gl = le16_to_cpu(req1->max_int_gl); 1447 ae_dev->dev_specs.max_frm_size = le16_to_cpu(req1->max_frm_size); 1448 ae_dev->dev_specs.umv_size = le16_to_cpu(req1->umv_size); 1449 ae_dev->dev_specs.mc_mac_size = le16_to_cpu(req1->mc_mac_size); 1450 } 1451 1452 static void hclge_check_dev_specs(struct hclge_dev *hdev) 1453 { 1454 struct hnae3_dev_specs *dev_specs = &hdev->ae_dev->dev_specs; 1455 1456 if (!dev_specs->max_non_tso_bd_num) 1457 dev_specs->max_non_tso_bd_num = HCLGE_MAX_NON_TSO_BD_NUM; 1458 if (!dev_specs->rss_ind_tbl_size) 1459 dev_specs->rss_ind_tbl_size = HCLGE_RSS_IND_TBL_SIZE; 1460 if (!dev_specs->rss_key_size) 1461 dev_specs->rss_key_size = HCLGE_COMM_RSS_KEY_SIZE; 1462 if (!dev_specs->max_tm_rate) 1463 dev_specs->max_tm_rate = HCLGE_ETHER_MAX_RATE; 1464 if (!dev_specs->max_qset_num) 1465 dev_specs->max_qset_num = HCLGE_MAX_QSET_NUM; 1466 if (!dev_specs->max_int_gl) 1467 dev_specs->max_int_gl = HCLGE_DEF_MAX_INT_GL; 1468 if (!dev_specs->max_frm_size) 1469 dev_specs->max_frm_size = HCLGE_MAC_MAX_FRAME; 1470 if (!dev_specs->umv_size) 1471 dev_specs->umv_size = HCLGE_DEFAULT_UMV_SPACE_PER_PF; 1472 } 1473 1474 static int hclge_query_mac_stats_num(struct hclge_dev *hdev) 1475 { 1476 u32 reg_num = 0; 1477 int ret; 1478 1479 ret = hclge_mac_query_reg_num(hdev, ®_num); 1480 if (ret && ret != -EOPNOTSUPP) 1481 return ret; 1482 1483 hdev->ae_dev->dev_specs.mac_stats_num = reg_num; 1484 return 0; 1485 } 1486 1487 static int hclge_query_dev_specs(struct hclge_dev *hdev) 1488 { 1489 struct hclge_desc desc[HCLGE_QUERY_DEV_SPECS_BD_NUM]; 1490 int ret; 1491 int i; 1492 1493 ret = hclge_query_mac_stats_num(hdev); 1494 if (ret) 1495 return ret; 1496 1497 /* set default specifications as devices lower than version V3 do not 1498 * support querying specifications from firmware. 1499 */ 1500 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) { 1501 hclge_set_default_dev_specs(hdev); 1502 return 0; 1503 } 1504 1505 for (i = 0; i < HCLGE_QUERY_DEV_SPECS_BD_NUM - 1; i++) { 1506 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS, 1507 true); 1508 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 1509 } 1510 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS, true); 1511 1512 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_QUERY_DEV_SPECS_BD_NUM); 1513 if (ret) 1514 return ret; 1515 1516 hclge_parse_dev_specs(hdev, desc); 1517 hclge_check_dev_specs(hdev); 1518 1519 return 0; 1520 } 1521 1522 static int hclge_get_cap(struct hclge_dev *hdev) 1523 { 1524 int ret; 1525 1526 ret = hclge_query_function_status(hdev); 1527 if (ret) { 1528 dev_err(&hdev->pdev->dev, 1529 "query function status error %d.\n", ret); 1530 return ret; 1531 } 1532 1533 /* get pf resource */ 1534 return hclge_query_pf_resource(hdev); 1535 } 1536 1537 static void hclge_init_kdump_kernel_config(struct hclge_dev *hdev) 1538 { 1539 #define HCLGE_MIN_TX_DESC 64 1540 #define HCLGE_MIN_RX_DESC 64 1541 1542 if (!is_kdump_kernel()) 1543 return; 1544 1545 dev_info(&hdev->pdev->dev, 1546 "Running kdump kernel. Using minimal resources\n"); 1547 1548 /* minimal queue pairs equals to the number of vports */ 1549 hdev->num_tqps = hdev->num_req_vfs + 1; 1550 hdev->num_tx_desc = HCLGE_MIN_TX_DESC; 1551 hdev->num_rx_desc = HCLGE_MIN_RX_DESC; 1552 } 1553 1554 static void hclge_init_tc_config(struct hclge_dev *hdev) 1555 { 1556 unsigned int i; 1557 1558 if (hdev->tc_max > HNAE3_MAX_TC || 1559 hdev->tc_max < 1) { 1560 dev_warn(&hdev->pdev->dev, "TC num = %u.\n", 1561 hdev->tc_max); 1562 hdev->tc_max = 1; 1563 } 1564 1565 /* Dev does not support DCB */ 1566 if (!hnae3_dev_dcb_supported(hdev)) { 1567 hdev->tc_max = 1; 1568 hdev->pfc_max = 0; 1569 } else { 1570 hdev->pfc_max = hdev->tc_max; 1571 } 1572 1573 hdev->tm_info.num_tc = 1; 1574 1575 /* Currently not support uncontiuous tc */ 1576 for (i = 0; i < hdev->tm_info.num_tc; i++) 1577 hnae3_set_bit(hdev->hw_tc_map, i, 1); 1578 1579 hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE; 1580 } 1581 1582 static int hclge_configure(struct hclge_dev *hdev) 1583 { 1584 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1585 struct hclge_cfg cfg; 1586 int ret; 1587 1588 ret = hclge_get_cfg(hdev, &cfg); 1589 if (ret) 1590 return ret; 1591 1592 hdev->base_tqp_pid = 0; 1593 hdev->vf_rss_size_max = cfg.vf_rss_size_max; 1594 hdev->pf_rss_size_max = cfg.pf_rss_size_max; 1595 hdev->rx_buf_len = cfg.rx_buf_len; 1596 ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr); 1597 hdev->hw.mac.media_type = cfg.media_type; 1598 hdev->hw.mac.phy_addr = cfg.phy_addr; 1599 hdev->num_tx_desc = cfg.tqp_desc_num; 1600 hdev->num_rx_desc = cfg.tqp_desc_num; 1601 hdev->tm_info.num_pg = 1; 1602 hdev->tc_max = cfg.tc_num; 1603 hdev->tm_info.hw_pfc_map = 0; 1604 if (cfg.umv_space) 1605 hdev->wanted_umv_size = cfg.umv_space; 1606 else 1607 hdev->wanted_umv_size = hdev->ae_dev->dev_specs.umv_size; 1608 hdev->tx_spare_buf_size = cfg.tx_spare_buf_size; 1609 hdev->gro_en = true; 1610 if (cfg.vlan_fliter_cap == HCLGE_VLAN_FLTR_CAN_MDF) 1611 set_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps); 1612 1613 if (hnae3_ae_dev_fd_supported(hdev->ae_dev)) { 1614 hdev->fd_en = true; 1615 hdev->fd_active_type = HCLGE_FD_RULE_NONE; 1616 } 1617 1618 ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed); 1619 if (ret) { 1620 dev_err(&hdev->pdev->dev, "failed to parse speed %u, ret = %d\n", 1621 cfg.default_speed, ret); 1622 return ret; 1623 } 1624 1625 hclge_parse_link_mode(hdev, cfg.speed_ability); 1626 1627 hdev->hw.mac.max_speed = hclge_get_max_speed(cfg.speed_ability); 1628 1629 hclge_init_tc_config(hdev); 1630 hclge_init_kdump_kernel_config(hdev); 1631 1632 return ret; 1633 } 1634 1635 static int hclge_config_tso(struct hclge_dev *hdev, u16 tso_mss_min, 1636 u16 tso_mss_max) 1637 { 1638 struct hclge_cfg_tso_status_cmd *req; 1639 struct hclge_desc desc; 1640 1641 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false); 1642 1643 req = (struct hclge_cfg_tso_status_cmd *)desc.data; 1644 req->tso_mss_min = cpu_to_le16(tso_mss_min); 1645 req->tso_mss_max = cpu_to_le16(tso_mss_max); 1646 1647 return hclge_cmd_send(&hdev->hw, &desc, 1); 1648 } 1649 1650 static int hclge_config_gro(struct hclge_dev *hdev) 1651 { 1652 struct hclge_cfg_gro_status_cmd *req; 1653 struct hclge_desc desc; 1654 int ret; 1655 1656 if (!hnae3_ae_dev_gro_supported(hdev->ae_dev)) 1657 return 0; 1658 1659 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GRO_GENERIC_CONFIG, false); 1660 req = (struct hclge_cfg_gro_status_cmd *)desc.data; 1661 1662 req->gro_en = hdev->gro_en ? 1 : 0; 1663 1664 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1665 if (ret) 1666 dev_err(&hdev->pdev->dev, 1667 "GRO hardware config cmd failed, ret = %d\n", ret); 1668 1669 return ret; 1670 } 1671 1672 static int hclge_alloc_tqps(struct hclge_dev *hdev) 1673 { 1674 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1675 struct hclge_comm_tqp *tqp; 1676 int i; 1677 1678 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 1679 sizeof(struct hclge_comm_tqp), GFP_KERNEL); 1680 if (!hdev->htqp) 1681 return -ENOMEM; 1682 1683 tqp = hdev->htqp; 1684 1685 for (i = 0; i < hdev->num_tqps; i++) { 1686 tqp->dev = &hdev->pdev->dev; 1687 tqp->index = i; 1688 1689 tqp->q.ae_algo = &ae_algo; 1690 tqp->q.buf_size = hdev->rx_buf_len; 1691 tqp->q.tx_desc_num = hdev->num_tx_desc; 1692 tqp->q.rx_desc_num = hdev->num_rx_desc; 1693 1694 /* need an extended offset to configure queues >= 1695 * HCLGE_TQP_MAX_SIZE_DEV_V2 1696 */ 1697 if (i < HCLGE_TQP_MAX_SIZE_DEV_V2) 1698 tqp->q.io_base = hdev->hw.hw.io_base + 1699 HCLGE_TQP_REG_OFFSET + 1700 i * HCLGE_TQP_REG_SIZE; 1701 else 1702 tqp->q.io_base = hdev->hw.hw.io_base + 1703 HCLGE_TQP_REG_OFFSET + 1704 HCLGE_TQP_EXT_REG_OFFSET + 1705 (i - HCLGE_TQP_MAX_SIZE_DEV_V2) * 1706 HCLGE_TQP_REG_SIZE; 1707 1708 /* when device supports tx push and has device memory, 1709 * the queue can execute push mode or doorbell mode on 1710 * device memory. 1711 */ 1712 if (test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, ae_dev->caps)) 1713 tqp->q.mem_base = hdev->hw.hw.mem_base + 1714 HCLGE_TQP_MEM_OFFSET(hdev, i); 1715 1716 tqp++; 1717 } 1718 1719 return 0; 1720 } 1721 1722 static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id, 1723 u16 tqp_pid, u16 tqp_vid, bool is_pf) 1724 { 1725 struct hclge_tqp_map_cmd *req; 1726 struct hclge_desc desc; 1727 int ret; 1728 1729 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false); 1730 1731 req = (struct hclge_tqp_map_cmd *)desc.data; 1732 req->tqp_id = cpu_to_le16(tqp_pid); 1733 req->tqp_vf = func_id; 1734 req->tqp_flag = 1U << HCLGE_TQP_MAP_EN_B; 1735 if (!is_pf) 1736 req->tqp_flag |= 1U << HCLGE_TQP_MAP_TYPE_B; 1737 req->tqp_vid = cpu_to_le16(tqp_vid); 1738 1739 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1740 if (ret) 1741 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n", ret); 1742 1743 return ret; 1744 } 1745 1746 static int hclge_assign_tqp(struct hclge_vport *vport, u16 num_tqps) 1747 { 1748 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 1749 struct hclge_dev *hdev = vport->back; 1750 int i, alloced; 1751 1752 for (i = 0, alloced = 0; i < hdev->num_tqps && 1753 alloced < num_tqps; i++) { 1754 if (!hdev->htqp[i].alloced) { 1755 hdev->htqp[i].q.handle = &vport->nic; 1756 hdev->htqp[i].q.tqp_index = alloced; 1757 hdev->htqp[i].q.tx_desc_num = kinfo->num_tx_desc; 1758 hdev->htqp[i].q.rx_desc_num = kinfo->num_rx_desc; 1759 kinfo->tqp[alloced] = &hdev->htqp[i].q; 1760 hdev->htqp[i].alloced = true; 1761 alloced++; 1762 } 1763 } 1764 vport->alloc_tqps = alloced; 1765 kinfo->rss_size = min_t(u16, hdev->pf_rss_size_max, 1766 vport->alloc_tqps / hdev->tm_info.num_tc); 1767 1768 /* ensure one to one mapping between irq and queue at default */ 1769 kinfo->rss_size = min_t(u16, kinfo->rss_size, 1770 (hdev->num_nic_msi - 1) / hdev->tm_info.num_tc); 1771 1772 return 0; 1773 } 1774 1775 static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps, 1776 u16 num_tx_desc, u16 num_rx_desc) 1777 1778 { 1779 struct hnae3_handle *nic = &vport->nic; 1780 struct hnae3_knic_private_info *kinfo = &nic->kinfo; 1781 struct hclge_dev *hdev = vport->back; 1782 int ret; 1783 1784 kinfo->num_tx_desc = num_tx_desc; 1785 kinfo->num_rx_desc = num_rx_desc; 1786 1787 kinfo->rx_buf_len = hdev->rx_buf_len; 1788 kinfo->tx_spare_buf_size = hdev->tx_spare_buf_size; 1789 1790 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, num_tqps, 1791 sizeof(struct hnae3_queue *), GFP_KERNEL); 1792 if (!kinfo->tqp) 1793 return -ENOMEM; 1794 1795 ret = hclge_assign_tqp(vport, num_tqps); 1796 if (ret) 1797 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret); 1798 1799 return ret; 1800 } 1801 1802 static int hclge_map_tqp_to_vport(struct hclge_dev *hdev, 1803 struct hclge_vport *vport) 1804 { 1805 struct hnae3_handle *nic = &vport->nic; 1806 struct hnae3_knic_private_info *kinfo; 1807 u16 i; 1808 1809 kinfo = &nic->kinfo; 1810 for (i = 0; i < vport->alloc_tqps; i++) { 1811 struct hclge_comm_tqp *q = 1812 container_of(kinfo->tqp[i], struct hclge_comm_tqp, q); 1813 bool is_pf; 1814 int ret; 1815 1816 is_pf = !(vport->vport_id); 1817 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index, 1818 i, is_pf); 1819 if (ret) 1820 return ret; 1821 } 1822 1823 return 0; 1824 } 1825 1826 static int hclge_map_tqp(struct hclge_dev *hdev) 1827 { 1828 struct hclge_vport *vport = hdev->vport; 1829 u16 i, num_vport; 1830 1831 num_vport = hdev->num_req_vfs + 1; 1832 for (i = 0; i < num_vport; i++) { 1833 int ret; 1834 1835 ret = hclge_map_tqp_to_vport(hdev, vport); 1836 if (ret) 1837 return ret; 1838 1839 vport++; 1840 } 1841 1842 return 0; 1843 } 1844 1845 static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps) 1846 { 1847 struct hnae3_handle *nic = &vport->nic; 1848 struct hclge_dev *hdev = vport->back; 1849 int ret; 1850 1851 nic->pdev = hdev->pdev; 1852 nic->ae_algo = &ae_algo; 1853 nic->numa_node_mask = hdev->numa_node_mask; 1854 nic->kinfo.io_base = hdev->hw.hw.io_base; 1855 1856 ret = hclge_knic_setup(vport, num_tqps, 1857 hdev->num_tx_desc, hdev->num_rx_desc); 1858 if (ret) 1859 dev_err(&hdev->pdev->dev, "knic setup failed %d\n", ret); 1860 1861 return ret; 1862 } 1863 1864 static int hclge_alloc_vport(struct hclge_dev *hdev) 1865 { 1866 struct pci_dev *pdev = hdev->pdev; 1867 struct hclge_vport *vport; 1868 u32 tqp_main_vport; 1869 u32 tqp_per_vport; 1870 int num_vport, i; 1871 int ret; 1872 1873 /* We need to alloc a vport for main NIC of PF */ 1874 num_vport = hdev->num_req_vfs + 1; 1875 1876 if (hdev->num_tqps < num_vport) { 1877 dev_err(&hdev->pdev->dev, "tqps(%u) is less than vports(%d)", 1878 hdev->num_tqps, num_vport); 1879 return -EINVAL; 1880 } 1881 1882 /* Alloc the same number of TQPs for every vport */ 1883 tqp_per_vport = hdev->num_tqps / num_vport; 1884 tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport; 1885 1886 vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport), 1887 GFP_KERNEL); 1888 if (!vport) 1889 return -ENOMEM; 1890 1891 hdev->vport = vport; 1892 hdev->num_alloc_vport = num_vport; 1893 1894 if (IS_ENABLED(CONFIG_PCI_IOV)) 1895 hdev->num_alloc_vfs = hdev->num_req_vfs; 1896 1897 for (i = 0; i < num_vport; i++) { 1898 vport->back = hdev; 1899 vport->vport_id = i; 1900 vport->vf_info.link_state = IFLA_VF_LINK_STATE_AUTO; 1901 vport->mps = HCLGE_MAC_DEFAULT_FRAME; 1902 vport->port_base_vlan_cfg.state = HNAE3_PORT_BASE_VLAN_DISABLE; 1903 vport->port_base_vlan_cfg.tbl_sta = true; 1904 vport->rxvlan_cfg.rx_vlan_offload_en = true; 1905 vport->req_vlan_fltr_en = true; 1906 INIT_LIST_HEAD(&vport->vlan_list); 1907 INIT_LIST_HEAD(&vport->uc_mac_list); 1908 INIT_LIST_HEAD(&vport->mc_mac_list); 1909 spin_lock_init(&vport->mac_list_lock); 1910 1911 if (i == 0) 1912 ret = hclge_vport_setup(vport, tqp_main_vport); 1913 else 1914 ret = hclge_vport_setup(vport, tqp_per_vport); 1915 if (ret) { 1916 dev_err(&pdev->dev, 1917 "vport setup failed for vport %d, %d\n", 1918 i, ret); 1919 return ret; 1920 } 1921 1922 vport++; 1923 } 1924 1925 return 0; 1926 } 1927 1928 static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev, 1929 struct hclge_pkt_buf_alloc *buf_alloc) 1930 { 1931 /* TX buffer size is unit by 128 byte */ 1932 #define HCLGE_BUF_SIZE_UNIT_SHIFT 7 1933 #define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15) 1934 struct hclge_tx_buff_alloc_cmd *req; 1935 struct hclge_desc desc; 1936 int ret; 1937 u8 i; 1938 1939 req = (struct hclge_tx_buff_alloc_cmd *)desc.data; 1940 1941 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0); 1942 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1943 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size; 1944 1945 req->tx_pkt_buff[i] = 1946 cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) | 1947 HCLGE_BUF_SIZE_UPDATE_EN_MSK); 1948 } 1949 1950 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1951 if (ret) 1952 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n", 1953 ret); 1954 1955 return ret; 1956 } 1957 1958 static int hclge_tx_buffer_alloc(struct hclge_dev *hdev, 1959 struct hclge_pkt_buf_alloc *buf_alloc) 1960 { 1961 int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc); 1962 1963 if (ret) 1964 dev_err(&hdev->pdev->dev, "tx buffer alloc failed %d\n", ret); 1965 1966 return ret; 1967 } 1968 1969 static u32 hclge_get_tc_num(struct hclge_dev *hdev) 1970 { 1971 unsigned int i; 1972 u32 cnt = 0; 1973 1974 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) 1975 if (hdev->hw_tc_map & BIT(i)) 1976 cnt++; 1977 return cnt; 1978 } 1979 1980 /* Get the number of pfc enabled TCs, which have private buffer */ 1981 static int hclge_get_pfc_priv_num(struct hclge_dev *hdev, 1982 struct hclge_pkt_buf_alloc *buf_alloc) 1983 { 1984 struct hclge_priv_buf *priv; 1985 unsigned int i; 1986 int cnt = 0; 1987 1988 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1989 priv = &buf_alloc->priv_buf[i]; 1990 if ((hdev->tm_info.hw_pfc_map & BIT(i)) && 1991 priv->enable) 1992 cnt++; 1993 } 1994 1995 return cnt; 1996 } 1997 1998 /* Get the number of pfc disabled TCs, which have private buffer */ 1999 static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev, 2000 struct hclge_pkt_buf_alloc *buf_alloc) 2001 { 2002 struct hclge_priv_buf *priv; 2003 unsigned int i; 2004 int cnt = 0; 2005 2006 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2007 priv = &buf_alloc->priv_buf[i]; 2008 if (hdev->hw_tc_map & BIT(i) && 2009 !(hdev->tm_info.hw_pfc_map & BIT(i)) && 2010 priv->enable) 2011 cnt++; 2012 } 2013 2014 return cnt; 2015 } 2016 2017 static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc) 2018 { 2019 struct hclge_priv_buf *priv; 2020 u32 rx_priv = 0; 2021 int i; 2022 2023 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2024 priv = &buf_alloc->priv_buf[i]; 2025 if (priv->enable) 2026 rx_priv += priv->buf_size; 2027 } 2028 return rx_priv; 2029 } 2030 2031 static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc) 2032 { 2033 u32 i, total_tx_size = 0; 2034 2035 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) 2036 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size; 2037 2038 return total_tx_size; 2039 } 2040 2041 static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev, 2042 struct hclge_pkt_buf_alloc *buf_alloc, 2043 u32 rx_all) 2044 { 2045 u32 shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd; 2046 u32 tc_num = hclge_get_tc_num(hdev); 2047 u32 shared_buf, aligned_mps; 2048 u32 rx_priv; 2049 int i; 2050 2051 aligned_mps = roundup(hdev->mps, HCLGE_BUF_SIZE_UNIT); 2052 2053 if (hnae3_dev_dcb_supported(hdev)) 2054 shared_buf_min = HCLGE_BUF_MUL_BY * aligned_mps + 2055 hdev->dv_buf_size; 2056 else 2057 shared_buf_min = aligned_mps + HCLGE_NON_DCB_ADDITIONAL_BUF 2058 + hdev->dv_buf_size; 2059 2060 shared_buf_tc = tc_num * aligned_mps + aligned_mps; 2061 shared_std = roundup(max_t(u32, shared_buf_min, shared_buf_tc), 2062 HCLGE_BUF_SIZE_UNIT); 2063 2064 rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc); 2065 if (rx_all < rx_priv + shared_std) 2066 return false; 2067 2068 shared_buf = rounddown(rx_all - rx_priv, HCLGE_BUF_SIZE_UNIT); 2069 buf_alloc->s_buf.buf_size = shared_buf; 2070 if (hnae3_dev_dcb_supported(hdev)) { 2071 buf_alloc->s_buf.self.high = shared_buf - hdev->dv_buf_size; 2072 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high 2073 - roundup(aligned_mps / HCLGE_BUF_DIV_BY, 2074 HCLGE_BUF_SIZE_UNIT); 2075 } else { 2076 buf_alloc->s_buf.self.high = aligned_mps + 2077 HCLGE_NON_DCB_ADDITIONAL_BUF; 2078 buf_alloc->s_buf.self.low = aligned_mps; 2079 } 2080 2081 if (hnae3_dev_dcb_supported(hdev)) { 2082 hi_thrd = shared_buf - hdev->dv_buf_size; 2083 2084 if (tc_num <= NEED_RESERVE_TC_NUM) 2085 hi_thrd = hi_thrd * BUF_RESERVE_PERCENT 2086 / BUF_MAX_PERCENT; 2087 2088 if (tc_num) 2089 hi_thrd = hi_thrd / tc_num; 2090 2091 hi_thrd = max_t(u32, hi_thrd, HCLGE_BUF_MUL_BY * aligned_mps); 2092 hi_thrd = rounddown(hi_thrd, HCLGE_BUF_SIZE_UNIT); 2093 lo_thrd = hi_thrd - aligned_mps / HCLGE_BUF_DIV_BY; 2094 } else { 2095 hi_thrd = aligned_mps + HCLGE_NON_DCB_ADDITIONAL_BUF; 2096 lo_thrd = aligned_mps; 2097 } 2098 2099 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2100 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd; 2101 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd; 2102 } 2103 2104 return true; 2105 } 2106 2107 static int hclge_tx_buffer_calc(struct hclge_dev *hdev, 2108 struct hclge_pkt_buf_alloc *buf_alloc) 2109 { 2110 u32 i, total_size; 2111 2112 total_size = hdev->pkt_buf_size; 2113 2114 /* alloc tx buffer for all enabled tc */ 2115 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2116 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2117 2118 if (hdev->hw_tc_map & BIT(i)) { 2119 if (total_size < hdev->tx_buf_size) 2120 return -ENOMEM; 2121 2122 priv->tx_buf_size = hdev->tx_buf_size; 2123 } else { 2124 priv->tx_buf_size = 0; 2125 } 2126 2127 total_size -= priv->tx_buf_size; 2128 } 2129 2130 return 0; 2131 } 2132 2133 static bool hclge_rx_buf_calc_all(struct hclge_dev *hdev, bool max, 2134 struct hclge_pkt_buf_alloc *buf_alloc) 2135 { 2136 u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2137 u32 aligned_mps = round_up(hdev->mps, HCLGE_BUF_SIZE_UNIT); 2138 unsigned int i; 2139 2140 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2141 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2142 2143 priv->enable = 0; 2144 priv->wl.low = 0; 2145 priv->wl.high = 0; 2146 priv->buf_size = 0; 2147 2148 if (!(hdev->hw_tc_map & BIT(i))) 2149 continue; 2150 2151 priv->enable = 1; 2152 2153 if (hdev->tm_info.hw_pfc_map & BIT(i)) { 2154 priv->wl.low = max ? aligned_mps : HCLGE_BUF_SIZE_UNIT; 2155 priv->wl.high = roundup(priv->wl.low + aligned_mps, 2156 HCLGE_BUF_SIZE_UNIT); 2157 } else { 2158 priv->wl.low = 0; 2159 priv->wl.high = max ? (aligned_mps * HCLGE_BUF_MUL_BY) : 2160 aligned_mps; 2161 } 2162 2163 priv->buf_size = priv->wl.high + hdev->dv_buf_size; 2164 } 2165 2166 return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all); 2167 } 2168 2169 static bool hclge_drop_nopfc_buf_till_fit(struct hclge_dev *hdev, 2170 struct hclge_pkt_buf_alloc *buf_alloc) 2171 { 2172 u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2173 int no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc); 2174 int i; 2175 2176 /* let the last to be cleared first */ 2177 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) { 2178 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2179 unsigned int mask = BIT((unsigned int)i); 2180 2181 if (hdev->hw_tc_map & mask && 2182 !(hdev->tm_info.hw_pfc_map & mask)) { 2183 /* Clear the no pfc TC private buffer */ 2184 priv->wl.low = 0; 2185 priv->wl.high = 0; 2186 priv->buf_size = 0; 2187 priv->enable = 0; 2188 no_pfc_priv_num--; 2189 } 2190 2191 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) || 2192 no_pfc_priv_num == 0) 2193 break; 2194 } 2195 2196 return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all); 2197 } 2198 2199 static bool hclge_drop_pfc_buf_till_fit(struct hclge_dev *hdev, 2200 struct hclge_pkt_buf_alloc *buf_alloc) 2201 { 2202 u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2203 int pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc); 2204 int i; 2205 2206 /* let the last to be cleared first */ 2207 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) { 2208 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2209 unsigned int mask = BIT((unsigned int)i); 2210 2211 if (hdev->hw_tc_map & mask && 2212 hdev->tm_info.hw_pfc_map & mask) { 2213 /* Reduce the number of pfc TC with private buffer */ 2214 priv->wl.low = 0; 2215 priv->enable = 0; 2216 priv->wl.high = 0; 2217 priv->buf_size = 0; 2218 pfc_priv_num--; 2219 } 2220 2221 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) || 2222 pfc_priv_num == 0) 2223 break; 2224 } 2225 2226 return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all); 2227 } 2228 2229 static int hclge_only_alloc_priv_buff(struct hclge_dev *hdev, 2230 struct hclge_pkt_buf_alloc *buf_alloc) 2231 { 2232 #define COMPENSATE_BUFFER 0x3C00 2233 #define COMPENSATE_HALF_MPS_NUM 5 2234 #define PRIV_WL_GAP 0x1800 2235 2236 u32 rx_priv = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2237 u32 tc_num = hclge_get_tc_num(hdev); 2238 u32 half_mps = hdev->mps >> 1; 2239 u32 min_rx_priv; 2240 unsigned int i; 2241 2242 if (tc_num) 2243 rx_priv = rx_priv / tc_num; 2244 2245 if (tc_num <= NEED_RESERVE_TC_NUM) 2246 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT; 2247 2248 min_rx_priv = hdev->dv_buf_size + COMPENSATE_BUFFER + 2249 COMPENSATE_HALF_MPS_NUM * half_mps; 2250 min_rx_priv = round_up(min_rx_priv, HCLGE_BUF_SIZE_UNIT); 2251 rx_priv = round_down(rx_priv, HCLGE_BUF_SIZE_UNIT); 2252 if (rx_priv < min_rx_priv) 2253 return false; 2254 2255 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2256 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2257 2258 priv->enable = 0; 2259 priv->wl.low = 0; 2260 priv->wl.high = 0; 2261 priv->buf_size = 0; 2262 2263 if (!(hdev->hw_tc_map & BIT(i))) 2264 continue; 2265 2266 priv->enable = 1; 2267 priv->buf_size = rx_priv; 2268 priv->wl.high = rx_priv - hdev->dv_buf_size; 2269 priv->wl.low = priv->wl.high - PRIV_WL_GAP; 2270 } 2271 2272 buf_alloc->s_buf.buf_size = 0; 2273 2274 return true; 2275 } 2276 2277 /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs 2278 * @hdev: pointer to struct hclge_dev 2279 * @buf_alloc: pointer to buffer calculation data 2280 * @return: 0: calculate successful, negative: fail 2281 */ 2282 static int hclge_rx_buffer_calc(struct hclge_dev *hdev, 2283 struct hclge_pkt_buf_alloc *buf_alloc) 2284 { 2285 /* When DCB is not supported, rx private buffer is not allocated. */ 2286 if (!hnae3_dev_dcb_supported(hdev)) { 2287 u32 rx_all = hdev->pkt_buf_size; 2288 2289 rx_all -= hclge_get_tx_buff_alloced(buf_alloc); 2290 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) 2291 return -ENOMEM; 2292 2293 return 0; 2294 } 2295 2296 if (hclge_only_alloc_priv_buff(hdev, buf_alloc)) 2297 return 0; 2298 2299 if (hclge_rx_buf_calc_all(hdev, true, buf_alloc)) 2300 return 0; 2301 2302 /* try to decrease the buffer size */ 2303 if (hclge_rx_buf_calc_all(hdev, false, buf_alloc)) 2304 return 0; 2305 2306 if (hclge_drop_nopfc_buf_till_fit(hdev, buf_alloc)) 2307 return 0; 2308 2309 if (hclge_drop_pfc_buf_till_fit(hdev, buf_alloc)) 2310 return 0; 2311 2312 return -ENOMEM; 2313 } 2314 2315 static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev, 2316 struct hclge_pkt_buf_alloc *buf_alloc) 2317 { 2318 struct hclge_rx_priv_buff_cmd *req; 2319 struct hclge_desc desc; 2320 int ret; 2321 int i; 2322 2323 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false); 2324 req = (struct hclge_rx_priv_buff_cmd *)desc.data; 2325 2326 /* Alloc private buffer TCs */ 2327 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2328 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2329 2330 req->buf_num[i] = 2331 cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S); 2332 req->buf_num[i] |= 2333 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B); 2334 } 2335 2336 req->shared_buf = 2337 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) | 2338 (1 << HCLGE_TC0_PRI_BUF_EN_B)); 2339 2340 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2341 if (ret) 2342 dev_err(&hdev->pdev->dev, 2343 "rx private buffer alloc cmd failed %d\n", ret); 2344 2345 return ret; 2346 } 2347 2348 static int hclge_rx_priv_wl_config(struct hclge_dev *hdev, 2349 struct hclge_pkt_buf_alloc *buf_alloc) 2350 { 2351 struct hclge_rx_priv_wl_buf *req; 2352 struct hclge_priv_buf *priv; 2353 struct hclge_desc desc[2]; 2354 int i, j; 2355 int ret; 2356 2357 for (i = 0; i < 2; i++) { 2358 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC, 2359 false); 2360 req = (struct hclge_rx_priv_wl_buf *)desc[i].data; 2361 2362 /* The first descriptor set the NEXT bit to 1 */ 2363 if (i == 0) 2364 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2365 else 2366 desc[i].flag &= ~cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2367 2368 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) { 2369 u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j; 2370 2371 priv = &buf_alloc->priv_buf[idx]; 2372 req->tc_wl[j].high = 2373 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S); 2374 req->tc_wl[j].high |= 2375 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2376 req->tc_wl[j].low = 2377 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S); 2378 req->tc_wl[j].low |= 2379 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2380 } 2381 } 2382 2383 /* Send 2 descriptor at one time */ 2384 ret = hclge_cmd_send(&hdev->hw, desc, 2); 2385 if (ret) 2386 dev_err(&hdev->pdev->dev, 2387 "rx private waterline config cmd failed %d\n", 2388 ret); 2389 return ret; 2390 } 2391 2392 static int hclge_common_thrd_config(struct hclge_dev *hdev, 2393 struct hclge_pkt_buf_alloc *buf_alloc) 2394 { 2395 struct hclge_shared_buf *s_buf = &buf_alloc->s_buf; 2396 struct hclge_rx_com_thrd *req; 2397 struct hclge_desc desc[2]; 2398 struct hclge_tc_thrd *tc; 2399 int i, j; 2400 int ret; 2401 2402 for (i = 0; i < 2; i++) { 2403 hclge_cmd_setup_basic_desc(&desc[i], 2404 HCLGE_OPC_RX_COM_THRD_ALLOC, false); 2405 req = (struct hclge_rx_com_thrd *)&desc[i].data; 2406 2407 /* The first descriptor set the NEXT bit to 1 */ 2408 if (i == 0) 2409 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2410 else 2411 desc[i].flag &= ~cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2412 2413 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) { 2414 tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j]; 2415 2416 req->com_thrd[j].high = 2417 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S); 2418 req->com_thrd[j].high |= 2419 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2420 req->com_thrd[j].low = 2421 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S); 2422 req->com_thrd[j].low |= 2423 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2424 } 2425 } 2426 2427 /* Send 2 descriptors at one time */ 2428 ret = hclge_cmd_send(&hdev->hw, desc, 2); 2429 if (ret) 2430 dev_err(&hdev->pdev->dev, 2431 "common threshold config cmd failed %d\n", ret); 2432 return ret; 2433 } 2434 2435 static int hclge_common_wl_config(struct hclge_dev *hdev, 2436 struct hclge_pkt_buf_alloc *buf_alloc) 2437 { 2438 struct hclge_shared_buf *buf = &buf_alloc->s_buf; 2439 struct hclge_rx_com_wl *req; 2440 struct hclge_desc desc; 2441 int ret; 2442 2443 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false); 2444 2445 req = (struct hclge_rx_com_wl *)desc.data; 2446 req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S); 2447 req->com_wl.high |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2448 2449 req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S); 2450 req->com_wl.low |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2451 2452 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2453 if (ret) 2454 dev_err(&hdev->pdev->dev, 2455 "common waterline config cmd failed %d\n", ret); 2456 2457 return ret; 2458 } 2459 2460 int hclge_buffer_alloc(struct hclge_dev *hdev) 2461 { 2462 struct hclge_pkt_buf_alloc *pkt_buf; 2463 int ret; 2464 2465 pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL); 2466 if (!pkt_buf) 2467 return -ENOMEM; 2468 2469 ret = hclge_tx_buffer_calc(hdev, pkt_buf); 2470 if (ret) { 2471 dev_err(&hdev->pdev->dev, 2472 "could not calc tx buffer size for all TCs %d\n", ret); 2473 goto out; 2474 } 2475 2476 ret = hclge_tx_buffer_alloc(hdev, pkt_buf); 2477 if (ret) { 2478 dev_err(&hdev->pdev->dev, 2479 "could not alloc tx buffers %d\n", ret); 2480 goto out; 2481 } 2482 2483 ret = hclge_rx_buffer_calc(hdev, pkt_buf); 2484 if (ret) { 2485 dev_err(&hdev->pdev->dev, 2486 "could not calc rx priv buffer size for all TCs %d\n", 2487 ret); 2488 goto out; 2489 } 2490 2491 ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf); 2492 if (ret) { 2493 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n", 2494 ret); 2495 goto out; 2496 } 2497 2498 if (hnae3_dev_dcb_supported(hdev)) { 2499 ret = hclge_rx_priv_wl_config(hdev, pkt_buf); 2500 if (ret) { 2501 dev_err(&hdev->pdev->dev, 2502 "could not configure rx private waterline %d\n", 2503 ret); 2504 goto out; 2505 } 2506 2507 ret = hclge_common_thrd_config(hdev, pkt_buf); 2508 if (ret) { 2509 dev_err(&hdev->pdev->dev, 2510 "could not configure common threshold %d\n", 2511 ret); 2512 goto out; 2513 } 2514 } 2515 2516 ret = hclge_common_wl_config(hdev, pkt_buf); 2517 if (ret) 2518 dev_err(&hdev->pdev->dev, 2519 "could not configure common waterline %d\n", ret); 2520 2521 out: 2522 kfree(pkt_buf); 2523 return ret; 2524 } 2525 2526 static int hclge_init_roce_base_info(struct hclge_vport *vport) 2527 { 2528 struct hnae3_handle *roce = &vport->roce; 2529 struct hnae3_handle *nic = &vport->nic; 2530 struct hclge_dev *hdev = vport->back; 2531 2532 roce->rinfo.num_vectors = vport->back->num_roce_msi; 2533 2534 if (hdev->num_msi < hdev->num_nic_msi + hdev->num_roce_msi) 2535 return -EINVAL; 2536 2537 roce->rinfo.base_vector = hdev->num_nic_msi; 2538 2539 roce->rinfo.netdev = nic->kinfo.netdev; 2540 roce->rinfo.roce_io_base = hdev->hw.hw.io_base; 2541 roce->rinfo.roce_mem_base = hdev->hw.hw.mem_base; 2542 2543 roce->pdev = nic->pdev; 2544 roce->ae_algo = nic->ae_algo; 2545 roce->numa_node_mask = nic->numa_node_mask; 2546 2547 return 0; 2548 } 2549 2550 static int hclge_init_msi(struct hclge_dev *hdev) 2551 { 2552 struct pci_dev *pdev = hdev->pdev; 2553 int vectors; 2554 int i; 2555 2556 vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM, 2557 hdev->num_msi, 2558 PCI_IRQ_MSI | PCI_IRQ_MSIX); 2559 if (vectors < 0) { 2560 dev_err(&pdev->dev, 2561 "failed(%d) to allocate MSI/MSI-X vectors\n", 2562 vectors); 2563 return vectors; 2564 } 2565 if (vectors < hdev->num_msi) 2566 dev_warn(&hdev->pdev->dev, 2567 "requested %u MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2568 hdev->num_msi, vectors); 2569 2570 hdev->num_msi = vectors; 2571 hdev->num_msi_left = vectors; 2572 2573 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2574 sizeof(u16), GFP_KERNEL); 2575 if (!hdev->vector_status) { 2576 pci_free_irq_vectors(pdev); 2577 return -ENOMEM; 2578 } 2579 2580 for (i = 0; i < hdev->num_msi; i++) 2581 hdev->vector_status[i] = HCLGE_INVALID_VPORT; 2582 2583 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2584 sizeof(int), GFP_KERNEL); 2585 if (!hdev->vector_irq) { 2586 pci_free_irq_vectors(pdev); 2587 return -ENOMEM; 2588 } 2589 2590 return 0; 2591 } 2592 2593 static u8 hclge_check_speed_dup(u8 duplex, int speed) 2594 { 2595 if (!(speed == HCLGE_MAC_SPEED_10M || speed == HCLGE_MAC_SPEED_100M)) 2596 duplex = HCLGE_MAC_FULL; 2597 2598 return duplex; 2599 } 2600 2601 static struct hclge_mac_speed_map hclge_mac_speed_map_to_fw[] = { 2602 {HCLGE_MAC_SPEED_10M, HCLGE_FW_MAC_SPEED_10M}, 2603 {HCLGE_MAC_SPEED_100M, HCLGE_FW_MAC_SPEED_100M}, 2604 {HCLGE_MAC_SPEED_1G, HCLGE_FW_MAC_SPEED_1G}, 2605 {HCLGE_MAC_SPEED_10G, HCLGE_FW_MAC_SPEED_10G}, 2606 {HCLGE_MAC_SPEED_25G, HCLGE_FW_MAC_SPEED_25G}, 2607 {HCLGE_MAC_SPEED_40G, HCLGE_FW_MAC_SPEED_40G}, 2608 {HCLGE_MAC_SPEED_50G, HCLGE_FW_MAC_SPEED_50G}, 2609 {HCLGE_MAC_SPEED_100G, HCLGE_FW_MAC_SPEED_100G}, 2610 {HCLGE_MAC_SPEED_200G, HCLGE_FW_MAC_SPEED_200G}, 2611 }; 2612 2613 static int hclge_convert_to_fw_speed(u32 speed_drv, u32 *speed_fw) 2614 { 2615 u16 i; 2616 2617 for (i = 0; i < ARRAY_SIZE(hclge_mac_speed_map_to_fw); i++) { 2618 if (hclge_mac_speed_map_to_fw[i].speed_drv == speed_drv) { 2619 *speed_fw = hclge_mac_speed_map_to_fw[i].speed_fw; 2620 return 0; 2621 } 2622 } 2623 2624 return -EINVAL; 2625 } 2626 2627 static int hclge_cfg_mac_speed_dup_hw(struct hclge_dev *hdev, int speed, 2628 u8 duplex, u8 lane_num) 2629 { 2630 struct hclge_config_mac_speed_dup_cmd *req; 2631 struct hclge_desc desc; 2632 u32 speed_fw; 2633 int ret; 2634 2635 req = (struct hclge_config_mac_speed_dup_cmd *)desc.data; 2636 2637 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false); 2638 2639 if (duplex) 2640 hnae3_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, 1); 2641 2642 ret = hclge_convert_to_fw_speed(speed, &speed_fw); 2643 if (ret) { 2644 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed); 2645 return ret; 2646 } 2647 2648 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, HCLGE_CFG_SPEED_S, 2649 speed_fw); 2650 hnae3_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B, 2651 1); 2652 req->lane_num = lane_num; 2653 2654 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2655 if (ret) { 2656 dev_err(&hdev->pdev->dev, 2657 "mac speed/duplex config cmd failed %d.\n", ret); 2658 return ret; 2659 } 2660 2661 return 0; 2662 } 2663 2664 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex, u8 lane_num) 2665 { 2666 struct hclge_mac *mac = &hdev->hw.mac; 2667 int ret; 2668 2669 duplex = hclge_check_speed_dup(duplex, speed); 2670 if (!mac->support_autoneg && mac->speed == speed && 2671 mac->duplex == duplex && (mac->lane_num == lane_num || lane_num == 0)) 2672 return 0; 2673 2674 ret = hclge_cfg_mac_speed_dup_hw(hdev, speed, duplex, lane_num); 2675 if (ret) 2676 return ret; 2677 2678 hdev->hw.mac.speed = speed; 2679 hdev->hw.mac.duplex = duplex; 2680 if (!lane_num) 2681 hdev->hw.mac.lane_num = lane_num; 2682 2683 return 0; 2684 } 2685 2686 static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed, 2687 u8 duplex, u8 lane_num) 2688 { 2689 struct hclge_vport *vport = hclge_get_vport(handle); 2690 struct hclge_dev *hdev = vport->back; 2691 2692 return hclge_cfg_mac_speed_dup(hdev, speed, duplex, lane_num); 2693 } 2694 2695 static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable) 2696 { 2697 struct hclge_config_auto_neg_cmd *req; 2698 struct hclge_desc desc; 2699 u32 flag = 0; 2700 int ret; 2701 2702 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false); 2703 2704 req = (struct hclge_config_auto_neg_cmd *)desc.data; 2705 if (enable) 2706 hnae3_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, 1U); 2707 req->cfg_an_cmd_flag = cpu_to_le32(flag); 2708 2709 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2710 if (ret) 2711 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n", 2712 ret); 2713 2714 return ret; 2715 } 2716 2717 static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable) 2718 { 2719 struct hclge_vport *vport = hclge_get_vport(handle); 2720 struct hclge_dev *hdev = vport->back; 2721 2722 if (!hdev->hw.mac.support_autoneg) { 2723 if (enable) { 2724 dev_err(&hdev->pdev->dev, 2725 "autoneg is not supported by current port\n"); 2726 return -EOPNOTSUPP; 2727 } else { 2728 return 0; 2729 } 2730 } 2731 2732 return hclge_set_autoneg_en(hdev, enable); 2733 } 2734 2735 static int hclge_get_autoneg(struct hnae3_handle *handle) 2736 { 2737 struct hclge_vport *vport = hclge_get_vport(handle); 2738 struct hclge_dev *hdev = vport->back; 2739 struct phy_device *phydev = hdev->hw.mac.phydev; 2740 2741 if (phydev) 2742 return phydev->autoneg; 2743 2744 return hdev->hw.mac.autoneg; 2745 } 2746 2747 static int hclge_restart_autoneg(struct hnae3_handle *handle) 2748 { 2749 struct hclge_vport *vport = hclge_get_vport(handle); 2750 struct hclge_dev *hdev = vport->back; 2751 int ret; 2752 2753 dev_dbg(&hdev->pdev->dev, "restart autoneg\n"); 2754 2755 ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 2756 if (ret) 2757 return ret; 2758 return hclge_notify_client(hdev, HNAE3_UP_CLIENT); 2759 } 2760 2761 static int hclge_halt_autoneg(struct hnae3_handle *handle, bool halt) 2762 { 2763 struct hclge_vport *vport = hclge_get_vport(handle); 2764 struct hclge_dev *hdev = vport->back; 2765 2766 if (hdev->hw.mac.support_autoneg && hdev->hw.mac.autoneg) 2767 return hclge_set_autoneg_en(hdev, !halt); 2768 2769 return 0; 2770 } 2771 2772 static void hclge_parse_fec_stats_lanes(struct hclge_dev *hdev, 2773 struct hclge_desc *desc, u32 desc_len) 2774 { 2775 u32 lane_size = HCLGE_FEC_STATS_MAX_LANES * 2; 2776 u32 desc_index = 0; 2777 u32 data_index = 0; 2778 u32 i; 2779 2780 for (i = 0; i < lane_size; i++) { 2781 if (data_index >= HCLGE_DESC_DATA_LEN) { 2782 desc_index++; 2783 data_index = 0; 2784 } 2785 2786 if (desc_index >= desc_len) 2787 return; 2788 2789 hdev->fec_stats.per_lanes[i] += 2790 le32_to_cpu(desc[desc_index].data[data_index]); 2791 data_index++; 2792 } 2793 } 2794 2795 static void hclge_parse_fec_stats(struct hclge_dev *hdev, 2796 struct hclge_desc *desc, u32 desc_len) 2797 { 2798 struct hclge_query_fec_stats_cmd *req; 2799 2800 req = (struct hclge_query_fec_stats_cmd *)desc[0].data; 2801 2802 hdev->fec_stats.base_r_lane_num = req->base_r_lane_num; 2803 hdev->fec_stats.rs_corr_blocks += 2804 le32_to_cpu(req->rs_fec_corr_blocks); 2805 hdev->fec_stats.rs_uncorr_blocks += 2806 le32_to_cpu(req->rs_fec_uncorr_blocks); 2807 hdev->fec_stats.rs_error_blocks += 2808 le32_to_cpu(req->rs_fec_error_blocks); 2809 hdev->fec_stats.base_r_corr_blocks += 2810 le32_to_cpu(req->base_r_fec_corr_blocks); 2811 hdev->fec_stats.base_r_uncorr_blocks += 2812 le32_to_cpu(req->base_r_fec_uncorr_blocks); 2813 2814 hclge_parse_fec_stats_lanes(hdev, &desc[1], desc_len - 1); 2815 } 2816 2817 static int hclge_update_fec_stats_hw(struct hclge_dev *hdev) 2818 { 2819 struct hclge_desc desc[HCLGE_FEC_STATS_CMD_NUM]; 2820 int ret; 2821 u32 i; 2822 2823 for (i = 0; i < HCLGE_FEC_STATS_CMD_NUM; i++) { 2824 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_FEC_STATS, 2825 true); 2826 if (i != (HCLGE_FEC_STATS_CMD_NUM - 1)) 2827 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2828 } 2829 2830 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_FEC_STATS_CMD_NUM); 2831 if (ret) 2832 return ret; 2833 2834 hclge_parse_fec_stats(hdev, desc, HCLGE_FEC_STATS_CMD_NUM); 2835 2836 return 0; 2837 } 2838 2839 static void hclge_update_fec_stats(struct hclge_dev *hdev) 2840 { 2841 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 2842 int ret; 2843 2844 if (!hnae3_ae_dev_fec_stats_supported(ae_dev) || 2845 test_and_set_bit(HCLGE_STATE_FEC_STATS_UPDATING, &hdev->state)) 2846 return; 2847 2848 ret = hclge_update_fec_stats_hw(hdev); 2849 if (ret) 2850 dev_err(&hdev->pdev->dev, 2851 "failed to update fec stats, ret = %d\n", ret); 2852 2853 clear_bit(HCLGE_STATE_FEC_STATS_UPDATING, &hdev->state); 2854 } 2855 2856 static void hclge_get_fec_stats_total(struct hclge_dev *hdev, 2857 struct ethtool_fec_stats *fec_stats) 2858 { 2859 fec_stats->corrected_blocks.total = hdev->fec_stats.rs_corr_blocks; 2860 fec_stats->uncorrectable_blocks.total = 2861 hdev->fec_stats.rs_uncorr_blocks; 2862 } 2863 2864 static void hclge_get_fec_stats_lanes(struct hclge_dev *hdev, 2865 struct ethtool_fec_stats *fec_stats) 2866 { 2867 u32 i; 2868 2869 if (hdev->fec_stats.base_r_lane_num == 0 || 2870 hdev->fec_stats.base_r_lane_num > HCLGE_FEC_STATS_MAX_LANES) { 2871 dev_err(&hdev->pdev->dev, 2872 "fec stats lane number(%llu) is invalid\n", 2873 hdev->fec_stats.base_r_lane_num); 2874 return; 2875 } 2876 2877 for (i = 0; i < hdev->fec_stats.base_r_lane_num; i++) { 2878 fec_stats->corrected_blocks.lanes[i] = 2879 hdev->fec_stats.base_r_corr_per_lanes[i]; 2880 fec_stats->uncorrectable_blocks.lanes[i] = 2881 hdev->fec_stats.base_r_uncorr_per_lanes[i]; 2882 } 2883 } 2884 2885 static void hclge_comm_get_fec_stats(struct hclge_dev *hdev, 2886 struct ethtool_fec_stats *fec_stats) 2887 { 2888 u32 fec_mode = hdev->hw.mac.fec_mode; 2889 2890 switch (fec_mode) { 2891 case BIT(HNAE3_FEC_RS): 2892 case BIT(HNAE3_FEC_LLRS): 2893 hclge_get_fec_stats_total(hdev, fec_stats); 2894 break; 2895 case BIT(HNAE3_FEC_BASER): 2896 hclge_get_fec_stats_lanes(hdev, fec_stats); 2897 break; 2898 default: 2899 dev_err(&hdev->pdev->dev, 2900 "fec stats is not supported by current fec mode(0x%x)\n", 2901 fec_mode); 2902 break; 2903 } 2904 } 2905 2906 static void hclge_get_fec_stats(struct hnae3_handle *handle, 2907 struct ethtool_fec_stats *fec_stats) 2908 { 2909 struct hclge_vport *vport = hclge_get_vport(handle); 2910 struct hclge_dev *hdev = vport->back; 2911 u32 fec_mode = hdev->hw.mac.fec_mode; 2912 2913 if (fec_mode == BIT(HNAE3_FEC_NONE) || 2914 fec_mode == BIT(HNAE3_FEC_AUTO) || 2915 fec_mode == BIT(HNAE3_FEC_USER_DEF)) 2916 return; 2917 2918 hclge_update_fec_stats(hdev); 2919 2920 hclge_comm_get_fec_stats(hdev, fec_stats); 2921 } 2922 2923 static int hclge_set_fec_hw(struct hclge_dev *hdev, u32 fec_mode) 2924 { 2925 struct hclge_config_fec_cmd *req; 2926 struct hclge_desc desc; 2927 int ret; 2928 2929 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_FEC_MODE, false); 2930 2931 req = (struct hclge_config_fec_cmd *)desc.data; 2932 if (fec_mode & BIT(HNAE3_FEC_AUTO)) 2933 hnae3_set_bit(req->fec_mode, HCLGE_MAC_CFG_FEC_AUTO_EN_B, 1); 2934 if (fec_mode & BIT(HNAE3_FEC_RS)) 2935 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M, 2936 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_RS); 2937 if (fec_mode & BIT(HNAE3_FEC_LLRS)) 2938 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M, 2939 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_LLRS); 2940 if (fec_mode & BIT(HNAE3_FEC_BASER)) 2941 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M, 2942 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_BASER); 2943 2944 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2945 if (ret) 2946 dev_err(&hdev->pdev->dev, "set fec mode failed %d.\n", ret); 2947 2948 return ret; 2949 } 2950 2951 static int hclge_set_fec(struct hnae3_handle *handle, u32 fec_mode) 2952 { 2953 struct hclge_vport *vport = hclge_get_vport(handle); 2954 struct hclge_dev *hdev = vport->back; 2955 struct hclge_mac *mac = &hdev->hw.mac; 2956 int ret; 2957 2958 if (fec_mode && !(mac->fec_ability & fec_mode)) { 2959 dev_err(&hdev->pdev->dev, "unsupported fec mode\n"); 2960 return -EINVAL; 2961 } 2962 2963 ret = hclge_set_fec_hw(hdev, fec_mode); 2964 if (ret) 2965 return ret; 2966 2967 mac->user_fec_mode = fec_mode | BIT(HNAE3_FEC_USER_DEF); 2968 return 0; 2969 } 2970 2971 static void hclge_get_fec(struct hnae3_handle *handle, u8 *fec_ability, 2972 u8 *fec_mode) 2973 { 2974 struct hclge_vport *vport = hclge_get_vport(handle); 2975 struct hclge_dev *hdev = vport->back; 2976 struct hclge_mac *mac = &hdev->hw.mac; 2977 2978 if (fec_ability) 2979 *fec_ability = mac->fec_ability; 2980 if (fec_mode) 2981 *fec_mode = mac->fec_mode; 2982 } 2983 2984 static int hclge_mac_init(struct hclge_dev *hdev) 2985 { 2986 struct hclge_mac *mac = &hdev->hw.mac; 2987 int ret; 2988 2989 hdev->support_sfp_query = true; 2990 hdev->hw.mac.duplex = HCLGE_MAC_FULL; 2991 ret = hclge_cfg_mac_speed_dup_hw(hdev, hdev->hw.mac.speed, 2992 hdev->hw.mac.duplex, hdev->hw.mac.lane_num); 2993 if (ret) 2994 return ret; 2995 2996 if (hdev->hw.mac.support_autoneg) { 2997 ret = hclge_set_autoneg_en(hdev, hdev->hw.mac.autoneg); 2998 if (ret) 2999 return ret; 3000 } 3001 3002 mac->link = 0; 3003 3004 if (mac->user_fec_mode & BIT(HNAE3_FEC_USER_DEF)) { 3005 ret = hclge_set_fec_hw(hdev, mac->user_fec_mode); 3006 if (ret) 3007 return ret; 3008 } 3009 3010 ret = hclge_set_mac_mtu(hdev, hdev->mps); 3011 if (ret) { 3012 dev_err(&hdev->pdev->dev, "set mtu failed ret=%d\n", ret); 3013 return ret; 3014 } 3015 3016 ret = hclge_set_default_loopback(hdev); 3017 if (ret) 3018 return ret; 3019 3020 ret = hclge_buffer_alloc(hdev); 3021 if (ret) 3022 dev_err(&hdev->pdev->dev, 3023 "allocate buffer fail, ret=%d\n", ret); 3024 3025 return ret; 3026 } 3027 3028 static void hclge_mbx_task_schedule(struct hclge_dev *hdev) 3029 { 3030 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 3031 !test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state)) { 3032 hdev->last_mbx_scheduled = jiffies; 3033 mod_delayed_work(hclge_wq, &hdev->service_task, 0); 3034 } 3035 } 3036 3037 static void hclge_reset_task_schedule(struct hclge_dev *hdev) 3038 { 3039 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 3040 test_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state) && 3041 !test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state)) { 3042 hdev->last_rst_scheduled = jiffies; 3043 mod_delayed_work(hclge_wq, &hdev->service_task, 0); 3044 } 3045 } 3046 3047 static void hclge_errhand_task_schedule(struct hclge_dev *hdev) 3048 { 3049 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 3050 !test_and_set_bit(HCLGE_STATE_ERR_SERVICE_SCHED, &hdev->state)) 3051 mod_delayed_work(hclge_wq, &hdev->service_task, 0); 3052 } 3053 3054 void hclge_task_schedule(struct hclge_dev *hdev, unsigned long delay_time) 3055 { 3056 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 3057 !test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) 3058 mod_delayed_work(hclge_wq, &hdev->service_task, delay_time); 3059 } 3060 3061 static int hclge_get_mac_link_status(struct hclge_dev *hdev, int *link_status) 3062 { 3063 struct hclge_link_status_cmd *req; 3064 struct hclge_desc desc; 3065 int ret; 3066 3067 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true); 3068 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3069 if (ret) { 3070 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n", 3071 ret); 3072 return ret; 3073 } 3074 3075 req = (struct hclge_link_status_cmd *)desc.data; 3076 *link_status = (req->status & HCLGE_LINK_STATUS_UP_M) > 0 ? 3077 HCLGE_LINK_STATUS_UP : HCLGE_LINK_STATUS_DOWN; 3078 3079 return 0; 3080 } 3081 3082 static int hclge_get_mac_phy_link(struct hclge_dev *hdev, int *link_status) 3083 { 3084 struct phy_device *phydev = hdev->hw.mac.phydev; 3085 3086 *link_status = HCLGE_LINK_STATUS_DOWN; 3087 3088 if (test_bit(HCLGE_STATE_DOWN, &hdev->state)) 3089 return 0; 3090 3091 if (phydev && (phydev->state != PHY_RUNNING || !phydev->link)) 3092 return 0; 3093 3094 return hclge_get_mac_link_status(hdev, link_status); 3095 } 3096 3097 static void hclge_push_link_status(struct hclge_dev *hdev) 3098 { 3099 struct hclge_vport *vport; 3100 int ret; 3101 u16 i; 3102 3103 for (i = 0; i < pci_num_vf(hdev->pdev); i++) { 3104 vport = &hdev->vport[i + HCLGE_VF_VPORT_START_NUM]; 3105 3106 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state) || 3107 vport->vf_info.link_state != IFLA_VF_LINK_STATE_AUTO) 3108 continue; 3109 3110 ret = hclge_push_vf_link_status(vport); 3111 if (ret) { 3112 dev_err(&hdev->pdev->dev, 3113 "failed to push link status to vf%u, ret = %d\n", 3114 i, ret); 3115 } 3116 } 3117 } 3118 3119 static void hclge_update_link_status(struct hclge_dev *hdev) 3120 { 3121 struct hnae3_handle *rhandle = &hdev->vport[0].roce; 3122 struct hnae3_handle *handle = &hdev->vport[0].nic; 3123 struct hnae3_client *rclient = hdev->roce_client; 3124 struct hnae3_client *client = hdev->nic_client; 3125 int state; 3126 int ret; 3127 3128 if (!client) 3129 return; 3130 3131 if (test_and_set_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state)) 3132 return; 3133 3134 ret = hclge_get_mac_phy_link(hdev, &state); 3135 if (ret) { 3136 clear_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state); 3137 return; 3138 } 3139 3140 if (state != hdev->hw.mac.link) { 3141 hdev->hw.mac.link = state; 3142 client->ops->link_status_change(handle, state); 3143 hclge_config_mac_tnl_int(hdev, state); 3144 if (rclient && rclient->ops->link_status_change) 3145 rclient->ops->link_status_change(rhandle, state); 3146 3147 hclge_push_link_status(hdev); 3148 } 3149 3150 clear_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state); 3151 } 3152 3153 static void hclge_update_speed_advertising(struct hclge_mac *mac) 3154 { 3155 u32 speed_ability; 3156 3157 if (hclge_get_speed_bit(mac->speed, &speed_ability)) 3158 return; 3159 3160 switch (mac->module_type) { 3161 case HNAE3_MODULE_TYPE_FIBRE_LR: 3162 hclge_convert_setting_lr(speed_ability, mac->advertising); 3163 break; 3164 case HNAE3_MODULE_TYPE_FIBRE_SR: 3165 case HNAE3_MODULE_TYPE_AOC: 3166 hclge_convert_setting_sr(speed_ability, mac->advertising); 3167 break; 3168 case HNAE3_MODULE_TYPE_CR: 3169 hclge_convert_setting_cr(speed_ability, mac->advertising); 3170 break; 3171 case HNAE3_MODULE_TYPE_KR: 3172 hclge_convert_setting_kr(speed_ability, mac->advertising); 3173 break; 3174 default: 3175 break; 3176 } 3177 } 3178 3179 static void hclge_update_fec_advertising(struct hclge_mac *mac) 3180 { 3181 if (mac->fec_mode & BIT(HNAE3_FEC_RS)) 3182 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 3183 mac->advertising); 3184 else if (mac->fec_mode & BIT(HNAE3_FEC_LLRS)) 3185 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 3186 mac->advertising); 3187 else if (mac->fec_mode & BIT(HNAE3_FEC_BASER)) 3188 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 3189 mac->advertising); 3190 else 3191 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 3192 mac->advertising); 3193 } 3194 3195 static void hclge_update_pause_advertising(struct hclge_dev *hdev) 3196 { 3197 struct hclge_mac *mac = &hdev->hw.mac; 3198 bool rx_en, tx_en; 3199 3200 switch (hdev->fc_mode_last_time) { 3201 case HCLGE_FC_RX_PAUSE: 3202 rx_en = true; 3203 tx_en = false; 3204 break; 3205 case HCLGE_FC_TX_PAUSE: 3206 rx_en = false; 3207 tx_en = true; 3208 break; 3209 case HCLGE_FC_FULL: 3210 rx_en = true; 3211 tx_en = true; 3212 break; 3213 default: 3214 rx_en = false; 3215 tx_en = false; 3216 break; 3217 } 3218 3219 linkmode_set_pause(mac->advertising, tx_en, rx_en); 3220 } 3221 3222 static void hclge_update_advertising(struct hclge_dev *hdev) 3223 { 3224 struct hclge_mac *mac = &hdev->hw.mac; 3225 3226 linkmode_zero(mac->advertising); 3227 hclge_update_speed_advertising(mac); 3228 hclge_update_fec_advertising(mac); 3229 hclge_update_pause_advertising(hdev); 3230 } 3231 3232 static void hclge_update_port_capability(struct hclge_dev *hdev, 3233 struct hclge_mac *mac) 3234 { 3235 if (hnae3_dev_fec_supported(hdev)) 3236 hclge_convert_setting_fec(mac); 3237 3238 /* firmware can not identify back plane type, the media type 3239 * read from configuration can help deal it 3240 */ 3241 if (mac->media_type == HNAE3_MEDIA_TYPE_BACKPLANE && 3242 mac->module_type == HNAE3_MODULE_TYPE_UNKNOWN) 3243 mac->module_type = HNAE3_MODULE_TYPE_KR; 3244 else if (mac->media_type == HNAE3_MEDIA_TYPE_COPPER) 3245 mac->module_type = HNAE3_MODULE_TYPE_TP; 3246 3247 if (mac->support_autoneg) { 3248 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, mac->supported); 3249 linkmode_copy(mac->advertising, mac->supported); 3250 } else { 3251 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 3252 mac->supported); 3253 hclge_update_advertising(hdev); 3254 } 3255 } 3256 3257 static int hclge_get_sfp_speed(struct hclge_dev *hdev, u32 *speed) 3258 { 3259 struct hclge_sfp_info_cmd *resp; 3260 struct hclge_desc desc; 3261 int ret; 3262 3263 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_INFO, true); 3264 resp = (struct hclge_sfp_info_cmd *)desc.data; 3265 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3266 if (ret == -EOPNOTSUPP) { 3267 dev_warn(&hdev->pdev->dev, 3268 "IMP do not support get SFP speed %d\n", ret); 3269 return ret; 3270 } else if (ret) { 3271 dev_err(&hdev->pdev->dev, "get sfp speed failed %d\n", ret); 3272 return ret; 3273 } 3274 3275 *speed = le32_to_cpu(resp->speed); 3276 3277 return 0; 3278 } 3279 3280 static int hclge_get_sfp_info(struct hclge_dev *hdev, struct hclge_mac *mac) 3281 { 3282 struct hclge_sfp_info_cmd *resp; 3283 struct hclge_desc desc; 3284 int ret; 3285 3286 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_INFO, true); 3287 resp = (struct hclge_sfp_info_cmd *)desc.data; 3288 3289 resp->query_type = QUERY_ACTIVE_SPEED; 3290 3291 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3292 if (ret == -EOPNOTSUPP) { 3293 dev_warn(&hdev->pdev->dev, 3294 "IMP does not support get SFP info %d\n", ret); 3295 return ret; 3296 } else if (ret) { 3297 dev_err(&hdev->pdev->dev, "get sfp info failed %d\n", ret); 3298 return ret; 3299 } 3300 3301 /* In some case, mac speed get from IMP may be 0, it shouldn't be 3302 * set to mac->speed. 3303 */ 3304 if (!le32_to_cpu(resp->speed)) 3305 return 0; 3306 3307 mac->speed = le32_to_cpu(resp->speed); 3308 /* if resp->speed_ability is 0, it means it's an old version 3309 * firmware, do not update these params 3310 */ 3311 if (resp->speed_ability) { 3312 mac->module_type = le32_to_cpu(resp->module_type); 3313 mac->speed_ability = le32_to_cpu(resp->speed_ability); 3314 mac->autoneg = resp->autoneg; 3315 mac->support_autoneg = resp->autoneg_ability; 3316 mac->speed_type = QUERY_ACTIVE_SPEED; 3317 mac->lane_num = resp->lane_num; 3318 if (!resp->active_fec) 3319 mac->fec_mode = 0; 3320 else 3321 mac->fec_mode = BIT(resp->active_fec); 3322 mac->fec_ability = resp->fec_ability; 3323 } else { 3324 mac->speed_type = QUERY_SFP_SPEED; 3325 } 3326 3327 return 0; 3328 } 3329 3330 static int hclge_get_phy_link_ksettings(struct hnae3_handle *handle, 3331 struct ethtool_link_ksettings *cmd) 3332 { 3333 struct hclge_desc desc[HCLGE_PHY_LINK_SETTING_BD_NUM]; 3334 struct hclge_vport *vport = hclge_get_vport(handle); 3335 struct hclge_phy_link_ksetting_0_cmd *req0; 3336 struct hclge_phy_link_ksetting_1_cmd *req1; 3337 u32 supported, advertising, lp_advertising; 3338 struct hclge_dev *hdev = vport->back; 3339 int ret; 3340 3341 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_PHY_LINK_KSETTING, 3342 true); 3343 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 3344 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_PHY_LINK_KSETTING, 3345 true); 3346 3347 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PHY_LINK_SETTING_BD_NUM); 3348 if (ret) { 3349 dev_err(&hdev->pdev->dev, 3350 "failed to get phy link ksetting, ret = %d.\n", ret); 3351 return ret; 3352 } 3353 3354 req0 = (struct hclge_phy_link_ksetting_0_cmd *)desc[0].data; 3355 cmd->base.autoneg = req0->autoneg; 3356 cmd->base.speed = le32_to_cpu(req0->speed); 3357 cmd->base.duplex = req0->duplex; 3358 cmd->base.port = req0->port; 3359 cmd->base.transceiver = req0->transceiver; 3360 cmd->base.phy_address = req0->phy_address; 3361 cmd->base.eth_tp_mdix = req0->eth_tp_mdix; 3362 cmd->base.eth_tp_mdix_ctrl = req0->eth_tp_mdix_ctrl; 3363 supported = le32_to_cpu(req0->supported); 3364 advertising = le32_to_cpu(req0->advertising); 3365 lp_advertising = le32_to_cpu(req0->lp_advertising); 3366 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 3367 supported); 3368 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, 3369 advertising); 3370 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.lp_advertising, 3371 lp_advertising); 3372 3373 req1 = (struct hclge_phy_link_ksetting_1_cmd *)desc[1].data; 3374 cmd->base.master_slave_cfg = req1->master_slave_cfg; 3375 cmd->base.master_slave_state = req1->master_slave_state; 3376 3377 return 0; 3378 } 3379 3380 static int 3381 hclge_set_phy_link_ksettings(struct hnae3_handle *handle, 3382 const struct ethtool_link_ksettings *cmd) 3383 { 3384 struct hclge_desc desc[HCLGE_PHY_LINK_SETTING_BD_NUM]; 3385 struct hclge_vport *vport = hclge_get_vport(handle); 3386 struct hclge_phy_link_ksetting_0_cmd *req0; 3387 struct hclge_phy_link_ksetting_1_cmd *req1; 3388 struct hclge_dev *hdev = vport->back; 3389 u32 advertising; 3390 int ret; 3391 3392 if (cmd->base.autoneg == AUTONEG_DISABLE && 3393 ((cmd->base.speed != SPEED_100 && cmd->base.speed != SPEED_10) || 3394 (cmd->base.duplex != DUPLEX_HALF && 3395 cmd->base.duplex != DUPLEX_FULL))) 3396 return -EINVAL; 3397 3398 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_PHY_LINK_KSETTING, 3399 false); 3400 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 3401 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_PHY_LINK_KSETTING, 3402 false); 3403 3404 req0 = (struct hclge_phy_link_ksetting_0_cmd *)desc[0].data; 3405 req0->autoneg = cmd->base.autoneg; 3406 req0->speed = cpu_to_le32(cmd->base.speed); 3407 req0->duplex = cmd->base.duplex; 3408 ethtool_convert_link_mode_to_legacy_u32(&advertising, 3409 cmd->link_modes.advertising); 3410 req0->advertising = cpu_to_le32(advertising); 3411 req0->eth_tp_mdix_ctrl = cmd->base.eth_tp_mdix_ctrl; 3412 3413 req1 = (struct hclge_phy_link_ksetting_1_cmd *)desc[1].data; 3414 req1->master_slave_cfg = cmd->base.master_slave_cfg; 3415 3416 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PHY_LINK_SETTING_BD_NUM); 3417 if (ret) { 3418 dev_err(&hdev->pdev->dev, 3419 "failed to set phy link ksettings, ret = %d.\n", ret); 3420 return ret; 3421 } 3422 3423 hdev->hw.mac.autoneg = cmd->base.autoneg; 3424 hdev->hw.mac.speed = cmd->base.speed; 3425 hdev->hw.mac.duplex = cmd->base.duplex; 3426 linkmode_copy(hdev->hw.mac.advertising, cmd->link_modes.advertising); 3427 3428 return 0; 3429 } 3430 3431 static int hclge_update_tp_port_info(struct hclge_dev *hdev) 3432 { 3433 struct ethtool_link_ksettings cmd; 3434 int ret; 3435 3436 if (!hnae3_dev_phy_imp_supported(hdev)) 3437 return 0; 3438 3439 ret = hclge_get_phy_link_ksettings(&hdev->vport->nic, &cmd); 3440 if (ret) 3441 return ret; 3442 3443 hdev->hw.mac.autoneg = cmd.base.autoneg; 3444 hdev->hw.mac.speed = cmd.base.speed; 3445 hdev->hw.mac.duplex = cmd.base.duplex; 3446 linkmode_copy(hdev->hw.mac.advertising, cmd.link_modes.advertising); 3447 3448 return 0; 3449 } 3450 3451 static int hclge_tp_port_init(struct hclge_dev *hdev) 3452 { 3453 struct ethtool_link_ksettings cmd; 3454 3455 if (!hnae3_dev_phy_imp_supported(hdev)) 3456 return 0; 3457 3458 cmd.base.autoneg = hdev->hw.mac.autoneg; 3459 cmd.base.speed = hdev->hw.mac.speed; 3460 cmd.base.duplex = hdev->hw.mac.duplex; 3461 linkmode_copy(cmd.link_modes.advertising, hdev->hw.mac.advertising); 3462 3463 return hclge_set_phy_link_ksettings(&hdev->vport->nic, &cmd); 3464 } 3465 3466 static int hclge_update_port_info(struct hclge_dev *hdev) 3467 { 3468 struct hclge_mac *mac = &hdev->hw.mac; 3469 int speed; 3470 int ret; 3471 3472 /* get the port info from SFP cmd if not copper port */ 3473 if (mac->media_type == HNAE3_MEDIA_TYPE_COPPER) 3474 return hclge_update_tp_port_info(hdev); 3475 3476 /* if IMP does not support get SFP/qSFP info, return directly */ 3477 if (!hdev->support_sfp_query) 3478 return 0; 3479 3480 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 3481 speed = mac->speed; 3482 ret = hclge_get_sfp_info(hdev, mac); 3483 } else { 3484 speed = HCLGE_MAC_SPEED_UNKNOWN; 3485 ret = hclge_get_sfp_speed(hdev, &speed); 3486 } 3487 3488 if (ret == -EOPNOTSUPP) { 3489 hdev->support_sfp_query = false; 3490 return ret; 3491 } else if (ret) { 3492 return ret; 3493 } 3494 3495 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 3496 if (mac->speed_type == QUERY_ACTIVE_SPEED) { 3497 hclge_update_port_capability(hdev, mac); 3498 if (mac->speed != speed) 3499 (void)hclge_tm_port_shaper_cfg(hdev); 3500 return 0; 3501 } 3502 return hclge_cfg_mac_speed_dup(hdev, mac->speed, 3503 HCLGE_MAC_FULL, mac->lane_num); 3504 } else { 3505 if (speed == HCLGE_MAC_SPEED_UNKNOWN) 3506 return 0; /* do nothing if no SFP */ 3507 3508 /* must config full duplex for SFP */ 3509 return hclge_cfg_mac_speed_dup(hdev, speed, HCLGE_MAC_FULL, 0); 3510 } 3511 } 3512 3513 static int hclge_get_status(struct hnae3_handle *handle) 3514 { 3515 struct hclge_vport *vport = hclge_get_vport(handle); 3516 struct hclge_dev *hdev = vport->back; 3517 3518 hclge_update_link_status(hdev); 3519 3520 return hdev->hw.mac.link; 3521 } 3522 3523 static struct hclge_vport *hclge_get_vf_vport(struct hclge_dev *hdev, int vf) 3524 { 3525 if (!pci_num_vf(hdev->pdev)) { 3526 dev_err(&hdev->pdev->dev, 3527 "SRIOV is disabled, can not get vport(%d) info.\n", vf); 3528 return NULL; 3529 } 3530 3531 if (vf < 0 || vf >= pci_num_vf(hdev->pdev)) { 3532 dev_err(&hdev->pdev->dev, 3533 "vf id(%d) is out of range(0 <= vfid < %d)\n", 3534 vf, pci_num_vf(hdev->pdev)); 3535 return NULL; 3536 } 3537 3538 /* VF start from 1 in vport */ 3539 vf += HCLGE_VF_VPORT_START_NUM; 3540 return &hdev->vport[vf]; 3541 } 3542 3543 static int hclge_get_vf_config(struct hnae3_handle *handle, int vf, 3544 struct ifla_vf_info *ivf) 3545 { 3546 struct hclge_vport *vport = hclge_get_vport(handle); 3547 struct hclge_dev *hdev = vport->back; 3548 3549 vport = hclge_get_vf_vport(hdev, vf); 3550 if (!vport) 3551 return -EINVAL; 3552 3553 ivf->vf = vf; 3554 ivf->linkstate = vport->vf_info.link_state; 3555 ivf->spoofchk = vport->vf_info.spoofchk; 3556 ivf->trusted = vport->vf_info.trusted; 3557 ivf->min_tx_rate = 0; 3558 ivf->max_tx_rate = vport->vf_info.max_tx_rate; 3559 ivf->vlan = vport->port_base_vlan_cfg.vlan_info.vlan_tag; 3560 ivf->vlan_proto = htons(vport->port_base_vlan_cfg.vlan_info.vlan_proto); 3561 ivf->qos = vport->port_base_vlan_cfg.vlan_info.qos; 3562 ether_addr_copy(ivf->mac, vport->vf_info.mac); 3563 3564 return 0; 3565 } 3566 3567 static int hclge_set_vf_link_state(struct hnae3_handle *handle, int vf, 3568 int link_state) 3569 { 3570 struct hclge_vport *vport = hclge_get_vport(handle); 3571 struct hclge_dev *hdev = vport->back; 3572 int link_state_old; 3573 int ret; 3574 3575 vport = hclge_get_vf_vport(hdev, vf); 3576 if (!vport) 3577 return -EINVAL; 3578 3579 link_state_old = vport->vf_info.link_state; 3580 vport->vf_info.link_state = link_state; 3581 3582 /* return success directly if the VF is unalive, VF will 3583 * query link state itself when it starts work. 3584 */ 3585 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) 3586 return 0; 3587 3588 ret = hclge_push_vf_link_status(vport); 3589 if (ret) { 3590 vport->vf_info.link_state = link_state_old; 3591 dev_err(&hdev->pdev->dev, 3592 "failed to push vf%d link status, ret = %d\n", vf, ret); 3593 } 3594 3595 return ret; 3596 } 3597 3598 static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval) 3599 { 3600 u32 cmdq_src_reg, msix_src_reg, hw_err_src_reg; 3601 3602 /* fetch the events from their corresponding regs */ 3603 cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG); 3604 msix_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS); 3605 hw_err_src_reg = hclge_read_dev(&hdev->hw, 3606 HCLGE_RAS_PF_OTHER_INT_STS_REG); 3607 3608 /* Assumption: If by any chance reset and mailbox events are reported 3609 * together then we will only process reset event in this go and will 3610 * defer the processing of the mailbox events. Since, we would have not 3611 * cleared RX CMDQ event this time we would receive again another 3612 * interrupt from H/W just for the mailbox. 3613 * 3614 * check for vector0 reset event sources 3615 */ 3616 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & msix_src_reg) { 3617 dev_info(&hdev->pdev->dev, "IMP reset interrupt\n"); 3618 set_bit(HNAE3_IMP_RESET, &hdev->reset_pending); 3619 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 3620 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B); 3621 hdev->rst_stats.imp_rst_cnt++; 3622 return HCLGE_VECTOR0_EVENT_RST; 3623 } 3624 3625 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & msix_src_reg) { 3626 dev_info(&hdev->pdev->dev, "global reset interrupt\n"); 3627 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 3628 set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending); 3629 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B); 3630 hdev->rst_stats.global_rst_cnt++; 3631 return HCLGE_VECTOR0_EVENT_RST; 3632 } 3633 3634 /* check for vector0 msix event and hardware error event source */ 3635 if (msix_src_reg & HCLGE_VECTOR0_REG_MSIX_MASK || 3636 hw_err_src_reg & HCLGE_RAS_REG_ERR_MASK) 3637 return HCLGE_VECTOR0_EVENT_ERR; 3638 3639 /* check for vector0 ptp event source */ 3640 if (BIT(HCLGE_VECTOR0_REG_PTP_INT_B) & msix_src_reg) { 3641 *clearval = msix_src_reg; 3642 return HCLGE_VECTOR0_EVENT_PTP; 3643 } 3644 3645 /* check for vector0 mailbox(=CMDQ RX) event source */ 3646 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) { 3647 cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B); 3648 *clearval = cmdq_src_reg; 3649 return HCLGE_VECTOR0_EVENT_MBX; 3650 } 3651 3652 /* print other vector0 event source */ 3653 dev_info(&hdev->pdev->dev, 3654 "INT status: CMDQ(%#x) HW errors(%#x) other(%#x)\n", 3655 cmdq_src_reg, hw_err_src_reg, msix_src_reg); 3656 3657 return HCLGE_VECTOR0_EVENT_OTHER; 3658 } 3659 3660 static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type, 3661 u32 regclr) 3662 { 3663 switch (event_type) { 3664 case HCLGE_VECTOR0_EVENT_PTP: 3665 case HCLGE_VECTOR0_EVENT_RST: 3666 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr); 3667 break; 3668 case HCLGE_VECTOR0_EVENT_MBX: 3669 hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr); 3670 break; 3671 default: 3672 break; 3673 } 3674 } 3675 3676 static void hclge_clear_all_event_cause(struct hclge_dev *hdev) 3677 { 3678 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_RST, 3679 BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) | 3680 BIT(HCLGE_VECTOR0_CORERESET_INT_B) | 3681 BIT(HCLGE_VECTOR0_IMPRESET_INT_B)); 3682 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_MBX, 0); 3683 } 3684 3685 static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable) 3686 { 3687 writel(enable ? 1 : 0, vector->addr); 3688 } 3689 3690 static irqreturn_t hclge_misc_irq_handle(int irq, void *data) 3691 { 3692 struct hclge_dev *hdev = data; 3693 unsigned long flags; 3694 u32 clearval = 0; 3695 u32 event_cause; 3696 3697 hclge_enable_vector(&hdev->misc_vector, false); 3698 event_cause = hclge_check_event_cause(hdev, &clearval); 3699 3700 /* vector 0 interrupt is shared with reset and mailbox source events. */ 3701 switch (event_cause) { 3702 case HCLGE_VECTOR0_EVENT_ERR: 3703 hclge_errhand_task_schedule(hdev); 3704 break; 3705 case HCLGE_VECTOR0_EVENT_RST: 3706 hclge_reset_task_schedule(hdev); 3707 break; 3708 case HCLGE_VECTOR0_EVENT_PTP: 3709 spin_lock_irqsave(&hdev->ptp->lock, flags); 3710 hclge_ptp_clean_tx_hwts(hdev); 3711 spin_unlock_irqrestore(&hdev->ptp->lock, flags); 3712 break; 3713 case HCLGE_VECTOR0_EVENT_MBX: 3714 /* If we are here then, 3715 * 1. Either we are not handling any mbx task and we are not 3716 * scheduled as well 3717 * OR 3718 * 2. We could be handling a mbx task but nothing more is 3719 * scheduled. 3720 * In both cases, we should schedule mbx task as there are more 3721 * mbx messages reported by this interrupt. 3722 */ 3723 hclge_mbx_task_schedule(hdev); 3724 break; 3725 default: 3726 dev_warn(&hdev->pdev->dev, 3727 "received unknown or unhandled event of vector0\n"); 3728 break; 3729 } 3730 3731 hclge_clear_event_cause(hdev, event_cause, clearval); 3732 3733 /* Enable interrupt if it is not caused by reset event or error event */ 3734 if (event_cause == HCLGE_VECTOR0_EVENT_PTP || 3735 event_cause == HCLGE_VECTOR0_EVENT_MBX || 3736 event_cause == HCLGE_VECTOR0_EVENT_OTHER) 3737 hclge_enable_vector(&hdev->misc_vector, true); 3738 3739 return IRQ_HANDLED; 3740 } 3741 3742 static void hclge_free_vector(struct hclge_dev *hdev, int vector_id) 3743 { 3744 if (hdev->vector_status[vector_id] == HCLGE_INVALID_VPORT) { 3745 dev_warn(&hdev->pdev->dev, 3746 "vector(vector_id %d) has been freed.\n", vector_id); 3747 return; 3748 } 3749 3750 hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT; 3751 hdev->num_msi_left += 1; 3752 hdev->num_msi_used -= 1; 3753 } 3754 3755 static void hclge_get_misc_vector(struct hclge_dev *hdev) 3756 { 3757 struct hclge_misc_vector *vector = &hdev->misc_vector; 3758 3759 vector->vector_irq = pci_irq_vector(hdev->pdev, 0); 3760 3761 vector->addr = hdev->hw.hw.io_base + HCLGE_MISC_VECTOR_REG_BASE; 3762 hdev->vector_status[0] = 0; 3763 3764 hdev->num_msi_left -= 1; 3765 hdev->num_msi_used += 1; 3766 } 3767 3768 static int hclge_misc_irq_init(struct hclge_dev *hdev) 3769 { 3770 int ret; 3771 3772 hclge_get_misc_vector(hdev); 3773 3774 /* this would be explicitly freed in the end */ 3775 snprintf(hdev->misc_vector.name, HNAE3_INT_NAME_LEN, "%s-misc-%s", 3776 HCLGE_NAME, pci_name(hdev->pdev)); 3777 ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle, 3778 0, hdev->misc_vector.name, hdev); 3779 if (ret) { 3780 hclge_free_vector(hdev, 0); 3781 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n", 3782 hdev->misc_vector.vector_irq); 3783 } 3784 3785 return ret; 3786 } 3787 3788 static void hclge_misc_irq_uninit(struct hclge_dev *hdev) 3789 { 3790 free_irq(hdev->misc_vector.vector_irq, hdev); 3791 hclge_free_vector(hdev, 0); 3792 } 3793 3794 int hclge_notify_client(struct hclge_dev *hdev, 3795 enum hnae3_reset_notify_type type) 3796 { 3797 struct hnae3_handle *handle = &hdev->vport[0].nic; 3798 struct hnae3_client *client = hdev->nic_client; 3799 int ret; 3800 3801 if (!test_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state) || !client) 3802 return 0; 3803 3804 if (!client->ops->reset_notify) 3805 return -EOPNOTSUPP; 3806 3807 ret = client->ops->reset_notify(handle, type); 3808 if (ret) 3809 dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 3810 type, ret); 3811 3812 return ret; 3813 } 3814 3815 static int hclge_notify_roce_client(struct hclge_dev *hdev, 3816 enum hnae3_reset_notify_type type) 3817 { 3818 struct hnae3_handle *handle = &hdev->vport[0].roce; 3819 struct hnae3_client *client = hdev->roce_client; 3820 int ret; 3821 3822 if (!test_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state) || !client) 3823 return 0; 3824 3825 if (!client->ops->reset_notify) 3826 return -EOPNOTSUPP; 3827 3828 ret = client->ops->reset_notify(handle, type); 3829 if (ret) 3830 dev_err(&hdev->pdev->dev, "notify roce client failed %d(%d)", 3831 type, ret); 3832 3833 return ret; 3834 } 3835 3836 static int hclge_reset_wait(struct hclge_dev *hdev) 3837 { 3838 #define HCLGE_RESET_WATI_MS 100 3839 #define HCLGE_RESET_WAIT_CNT 350 3840 3841 u32 val, reg, reg_bit; 3842 u32 cnt = 0; 3843 3844 switch (hdev->reset_type) { 3845 case HNAE3_IMP_RESET: 3846 reg = HCLGE_GLOBAL_RESET_REG; 3847 reg_bit = HCLGE_IMP_RESET_BIT; 3848 break; 3849 case HNAE3_GLOBAL_RESET: 3850 reg = HCLGE_GLOBAL_RESET_REG; 3851 reg_bit = HCLGE_GLOBAL_RESET_BIT; 3852 break; 3853 case HNAE3_FUNC_RESET: 3854 reg = HCLGE_FUN_RST_ING; 3855 reg_bit = HCLGE_FUN_RST_ING_B; 3856 break; 3857 default: 3858 dev_err(&hdev->pdev->dev, 3859 "Wait for unsupported reset type: %d\n", 3860 hdev->reset_type); 3861 return -EINVAL; 3862 } 3863 3864 val = hclge_read_dev(&hdev->hw, reg); 3865 while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) { 3866 msleep(HCLGE_RESET_WATI_MS); 3867 val = hclge_read_dev(&hdev->hw, reg); 3868 cnt++; 3869 } 3870 3871 if (cnt >= HCLGE_RESET_WAIT_CNT) { 3872 dev_warn(&hdev->pdev->dev, 3873 "Wait for reset timeout: %d\n", hdev->reset_type); 3874 return -EBUSY; 3875 } 3876 3877 return 0; 3878 } 3879 3880 static int hclge_set_vf_rst(struct hclge_dev *hdev, int func_id, bool reset) 3881 { 3882 struct hclge_vf_rst_cmd *req; 3883 struct hclge_desc desc; 3884 3885 req = (struct hclge_vf_rst_cmd *)desc.data; 3886 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GBL_RST_STATUS, false); 3887 req->dest_vfid = func_id; 3888 3889 if (reset) 3890 req->vf_rst = 0x1; 3891 3892 return hclge_cmd_send(&hdev->hw, &desc, 1); 3893 } 3894 3895 static int hclge_set_all_vf_rst(struct hclge_dev *hdev, bool reset) 3896 { 3897 int i; 3898 3899 for (i = HCLGE_VF_VPORT_START_NUM; i < hdev->num_alloc_vport; i++) { 3900 struct hclge_vport *vport = &hdev->vport[i]; 3901 int ret; 3902 3903 /* Send cmd to set/clear VF's FUNC_RST_ING */ 3904 ret = hclge_set_vf_rst(hdev, vport->vport_id, reset); 3905 if (ret) { 3906 dev_err(&hdev->pdev->dev, 3907 "set vf(%u) rst failed %d!\n", 3908 vport->vport_id - HCLGE_VF_VPORT_START_NUM, 3909 ret); 3910 return ret; 3911 } 3912 3913 if (!reset || 3914 !test_bit(HCLGE_VPORT_STATE_INITED, &vport->state)) 3915 continue; 3916 3917 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state) && 3918 hdev->reset_type == HNAE3_FUNC_RESET) { 3919 set_bit(HCLGE_VPORT_NEED_NOTIFY_RESET, 3920 &vport->need_notify); 3921 continue; 3922 } 3923 3924 /* Inform VF to process the reset. 3925 * hclge_inform_reset_assert_to_vf may fail if VF 3926 * driver is not loaded. 3927 */ 3928 ret = hclge_inform_reset_assert_to_vf(vport); 3929 if (ret) 3930 dev_warn(&hdev->pdev->dev, 3931 "inform reset to vf(%u) failed %d!\n", 3932 vport->vport_id - HCLGE_VF_VPORT_START_NUM, 3933 ret); 3934 } 3935 3936 return 0; 3937 } 3938 3939 static void hclge_mailbox_service_task(struct hclge_dev *hdev) 3940 { 3941 if (!test_and_clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state) || 3942 test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state) || 3943 test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state)) 3944 return; 3945 3946 if (time_is_before_jiffies(hdev->last_mbx_scheduled + 3947 HCLGE_MBX_SCHED_TIMEOUT)) 3948 dev_warn(&hdev->pdev->dev, 3949 "mbx service task is scheduled after %ums on cpu%u!\n", 3950 jiffies_to_msecs(jiffies - hdev->last_mbx_scheduled), 3951 smp_processor_id()); 3952 3953 hclge_mbx_handler(hdev); 3954 3955 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state); 3956 } 3957 3958 static void hclge_func_reset_sync_vf(struct hclge_dev *hdev) 3959 { 3960 struct hclge_pf_rst_sync_cmd *req; 3961 struct hclge_desc desc; 3962 int cnt = 0; 3963 int ret; 3964 3965 req = (struct hclge_pf_rst_sync_cmd *)desc.data; 3966 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_VF_RST_RDY, true); 3967 3968 do { 3969 /* vf need to down netdev by mbx during PF or FLR reset */ 3970 hclge_mailbox_service_task(hdev); 3971 3972 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3973 /* for compatible with old firmware, wait 3974 * 100 ms for VF to stop IO 3975 */ 3976 if (ret == -EOPNOTSUPP) { 3977 msleep(HCLGE_RESET_SYNC_TIME); 3978 return; 3979 } else if (ret) { 3980 dev_warn(&hdev->pdev->dev, "sync with VF fail %d!\n", 3981 ret); 3982 return; 3983 } else if (req->all_vf_ready) { 3984 return; 3985 } 3986 msleep(HCLGE_PF_RESET_SYNC_TIME); 3987 hclge_comm_cmd_reuse_desc(&desc, true); 3988 } while (cnt++ < HCLGE_PF_RESET_SYNC_CNT); 3989 3990 dev_warn(&hdev->pdev->dev, "sync with VF timeout!\n"); 3991 } 3992 3993 void hclge_report_hw_error(struct hclge_dev *hdev, 3994 enum hnae3_hw_error_type type) 3995 { 3996 struct hnae3_client *client = hdev->nic_client; 3997 3998 if (!client || !client->ops->process_hw_error || 3999 !test_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state)) 4000 return; 4001 4002 client->ops->process_hw_error(&hdev->vport[0].nic, type); 4003 } 4004 4005 static void hclge_handle_imp_error(struct hclge_dev *hdev) 4006 { 4007 u32 reg_val; 4008 4009 reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG); 4010 if (reg_val & BIT(HCLGE_VECTOR0_IMP_RD_POISON_B)) { 4011 hclge_report_hw_error(hdev, HNAE3_IMP_RD_POISON_ERROR); 4012 reg_val &= ~BIT(HCLGE_VECTOR0_IMP_RD_POISON_B); 4013 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, reg_val); 4014 } 4015 4016 if (reg_val & BIT(HCLGE_VECTOR0_IMP_CMDQ_ERR_B)) { 4017 hclge_report_hw_error(hdev, HNAE3_CMDQ_ECC_ERROR); 4018 reg_val &= ~BIT(HCLGE_VECTOR0_IMP_CMDQ_ERR_B); 4019 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, reg_val); 4020 } 4021 } 4022 4023 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id) 4024 { 4025 struct hclge_desc desc; 4026 struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data; 4027 int ret; 4028 4029 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false); 4030 hnae3_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1); 4031 req->fun_reset_vfid = func_id; 4032 4033 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4034 if (ret) 4035 dev_err(&hdev->pdev->dev, 4036 "send function reset cmd fail, status =%d\n", ret); 4037 4038 return ret; 4039 } 4040 4041 static void hclge_do_reset(struct hclge_dev *hdev) 4042 { 4043 struct hnae3_handle *handle = &hdev->vport[0].nic; 4044 struct pci_dev *pdev = hdev->pdev; 4045 u32 val; 4046 4047 if (hclge_get_hw_reset_stat(handle)) { 4048 dev_info(&pdev->dev, "hardware reset not finish\n"); 4049 dev_info(&pdev->dev, "func_rst_reg:0x%x, global_rst_reg:0x%x\n", 4050 hclge_read_dev(&hdev->hw, HCLGE_FUN_RST_ING), 4051 hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG)); 4052 return; 4053 } 4054 4055 switch (hdev->reset_type) { 4056 case HNAE3_IMP_RESET: 4057 dev_info(&pdev->dev, "IMP reset requested\n"); 4058 val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG); 4059 hnae3_set_bit(val, HCLGE_TRIGGER_IMP_RESET_B, 1); 4060 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, val); 4061 break; 4062 case HNAE3_GLOBAL_RESET: 4063 dev_info(&pdev->dev, "global reset requested\n"); 4064 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG); 4065 hnae3_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1); 4066 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val); 4067 break; 4068 case HNAE3_FUNC_RESET: 4069 dev_info(&pdev->dev, "PF reset requested\n"); 4070 /* schedule again to check later */ 4071 set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending); 4072 hclge_reset_task_schedule(hdev); 4073 break; 4074 default: 4075 dev_warn(&pdev->dev, 4076 "unsupported reset type: %d\n", hdev->reset_type); 4077 break; 4078 } 4079 } 4080 4081 static enum hnae3_reset_type hclge_get_reset_level(struct hnae3_ae_dev *ae_dev, 4082 unsigned long *addr) 4083 { 4084 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 4085 struct hclge_dev *hdev = ae_dev->priv; 4086 4087 /* return the highest priority reset level amongst all */ 4088 if (test_bit(HNAE3_IMP_RESET, addr)) { 4089 rst_level = HNAE3_IMP_RESET; 4090 clear_bit(HNAE3_IMP_RESET, addr); 4091 clear_bit(HNAE3_GLOBAL_RESET, addr); 4092 clear_bit(HNAE3_FUNC_RESET, addr); 4093 } else if (test_bit(HNAE3_GLOBAL_RESET, addr)) { 4094 rst_level = HNAE3_GLOBAL_RESET; 4095 clear_bit(HNAE3_GLOBAL_RESET, addr); 4096 clear_bit(HNAE3_FUNC_RESET, addr); 4097 } else if (test_bit(HNAE3_FUNC_RESET, addr)) { 4098 rst_level = HNAE3_FUNC_RESET; 4099 clear_bit(HNAE3_FUNC_RESET, addr); 4100 } else if (test_bit(HNAE3_FLR_RESET, addr)) { 4101 rst_level = HNAE3_FLR_RESET; 4102 clear_bit(HNAE3_FLR_RESET, addr); 4103 } 4104 4105 if (hdev->reset_type != HNAE3_NONE_RESET && 4106 rst_level < hdev->reset_type) 4107 return HNAE3_NONE_RESET; 4108 4109 return rst_level; 4110 } 4111 4112 static void hclge_clear_reset_cause(struct hclge_dev *hdev) 4113 { 4114 u32 clearval = 0; 4115 4116 switch (hdev->reset_type) { 4117 case HNAE3_IMP_RESET: 4118 clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B); 4119 break; 4120 case HNAE3_GLOBAL_RESET: 4121 clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B); 4122 break; 4123 default: 4124 break; 4125 } 4126 4127 if (!clearval) 4128 return; 4129 4130 /* For revision 0x20, the reset interrupt source 4131 * can only be cleared after hardware reset done 4132 */ 4133 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 4134 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, 4135 clearval); 4136 4137 hclge_enable_vector(&hdev->misc_vector, true); 4138 } 4139 4140 static void hclge_reset_handshake(struct hclge_dev *hdev, bool enable) 4141 { 4142 u32 reg_val; 4143 4144 reg_val = hclge_read_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG); 4145 if (enable) 4146 reg_val |= HCLGE_COMM_NIC_SW_RST_RDY; 4147 else 4148 reg_val &= ~HCLGE_COMM_NIC_SW_RST_RDY; 4149 4150 hclge_write_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG, reg_val); 4151 } 4152 4153 static int hclge_func_reset_notify_vf(struct hclge_dev *hdev) 4154 { 4155 int ret; 4156 4157 ret = hclge_set_all_vf_rst(hdev, true); 4158 if (ret) 4159 return ret; 4160 4161 hclge_func_reset_sync_vf(hdev); 4162 4163 return 0; 4164 } 4165 4166 static int hclge_reset_prepare_wait(struct hclge_dev *hdev) 4167 { 4168 u32 reg_val; 4169 int ret = 0; 4170 4171 switch (hdev->reset_type) { 4172 case HNAE3_FUNC_RESET: 4173 ret = hclge_func_reset_notify_vf(hdev); 4174 if (ret) 4175 return ret; 4176 4177 ret = hclge_func_reset_cmd(hdev, 0); 4178 if (ret) { 4179 dev_err(&hdev->pdev->dev, 4180 "asserting function reset fail %d!\n", ret); 4181 return ret; 4182 } 4183 4184 /* After performaning pf reset, it is not necessary to do the 4185 * mailbox handling or send any command to firmware, because 4186 * any mailbox handling or command to firmware is only valid 4187 * after hclge_comm_cmd_init is called. 4188 */ 4189 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 4190 hdev->rst_stats.pf_rst_cnt++; 4191 break; 4192 case HNAE3_FLR_RESET: 4193 ret = hclge_func_reset_notify_vf(hdev); 4194 if (ret) 4195 return ret; 4196 break; 4197 case HNAE3_IMP_RESET: 4198 hclge_handle_imp_error(hdev); 4199 reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG); 4200 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, 4201 BIT(HCLGE_VECTOR0_IMP_RESET_INT_B) | reg_val); 4202 break; 4203 default: 4204 break; 4205 } 4206 4207 /* inform hardware that preparatory work is done */ 4208 msleep(HCLGE_RESET_SYNC_TIME); 4209 hclge_reset_handshake(hdev, true); 4210 dev_info(&hdev->pdev->dev, "prepare wait ok\n"); 4211 4212 return ret; 4213 } 4214 4215 static void hclge_show_rst_info(struct hclge_dev *hdev) 4216 { 4217 char *buf; 4218 4219 buf = kzalloc(HCLGE_DBG_RESET_INFO_LEN, GFP_KERNEL); 4220 if (!buf) 4221 return; 4222 4223 hclge_dbg_dump_rst_info(hdev, buf, HCLGE_DBG_RESET_INFO_LEN); 4224 4225 dev_info(&hdev->pdev->dev, "dump reset info:\n%s", buf); 4226 4227 kfree(buf); 4228 } 4229 4230 static bool hclge_reset_err_handle(struct hclge_dev *hdev) 4231 { 4232 #define MAX_RESET_FAIL_CNT 5 4233 4234 if (hdev->reset_pending) { 4235 dev_info(&hdev->pdev->dev, "Reset pending %lu\n", 4236 hdev->reset_pending); 4237 return true; 4238 } else if (hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS) & 4239 HCLGE_RESET_INT_M) { 4240 dev_info(&hdev->pdev->dev, 4241 "reset failed because new reset interrupt\n"); 4242 hclge_clear_reset_cause(hdev); 4243 return false; 4244 } else if (hdev->rst_stats.reset_fail_cnt < MAX_RESET_FAIL_CNT) { 4245 hdev->rst_stats.reset_fail_cnt++; 4246 set_bit(hdev->reset_type, &hdev->reset_pending); 4247 dev_info(&hdev->pdev->dev, 4248 "re-schedule reset task(%u)\n", 4249 hdev->rst_stats.reset_fail_cnt); 4250 return true; 4251 } 4252 4253 hclge_clear_reset_cause(hdev); 4254 4255 /* recover the handshake status when reset fail */ 4256 hclge_reset_handshake(hdev, true); 4257 4258 dev_err(&hdev->pdev->dev, "Reset fail!\n"); 4259 4260 hclge_show_rst_info(hdev); 4261 4262 set_bit(HCLGE_STATE_RST_FAIL, &hdev->state); 4263 4264 return false; 4265 } 4266 4267 static void hclge_update_reset_level(struct hclge_dev *hdev) 4268 { 4269 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4270 enum hnae3_reset_type reset_level; 4271 4272 /* reset request will not be set during reset, so clear 4273 * pending reset request to avoid unnecessary reset 4274 * caused by the same reason. 4275 */ 4276 hclge_get_reset_level(ae_dev, &hdev->reset_request); 4277 4278 /* if default_reset_request has a higher level reset request, 4279 * it should be handled as soon as possible. since some errors 4280 * need this kind of reset to fix. 4281 */ 4282 reset_level = hclge_get_reset_level(ae_dev, 4283 &hdev->default_reset_request); 4284 if (reset_level != HNAE3_NONE_RESET) 4285 set_bit(reset_level, &hdev->reset_request); 4286 } 4287 4288 static int hclge_set_rst_done(struct hclge_dev *hdev) 4289 { 4290 struct hclge_pf_rst_done_cmd *req; 4291 struct hclge_desc desc; 4292 int ret; 4293 4294 req = (struct hclge_pf_rst_done_cmd *)desc.data; 4295 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PF_RST_DONE, false); 4296 req->pf_rst_done |= HCLGE_PF_RESET_DONE_BIT; 4297 4298 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4299 /* To be compatible with the old firmware, which does not support 4300 * command HCLGE_OPC_PF_RST_DONE, just print a warning and 4301 * return success 4302 */ 4303 if (ret == -EOPNOTSUPP) { 4304 dev_warn(&hdev->pdev->dev, 4305 "current firmware does not support command(0x%x)!\n", 4306 HCLGE_OPC_PF_RST_DONE); 4307 return 0; 4308 } else if (ret) { 4309 dev_err(&hdev->pdev->dev, "assert PF reset done fail %d!\n", 4310 ret); 4311 } 4312 4313 return ret; 4314 } 4315 4316 static int hclge_reset_prepare_up(struct hclge_dev *hdev) 4317 { 4318 int ret = 0; 4319 4320 switch (hdev->reset_type) { 4321 case HNAE3_FUNC_RESET: 4322 case HNAE3_FLR_RESET: 4323 ret = hclge_set_all_vf_rst(hdev, false); 4324 break; 4325 case HNAE3_GLOBAL_RESET: 4326 case HNAE3_IMP_RESET: 4327 ret = hclge_set_rst_done(hdev); 4328 break; 4329 default: 4330 break; 4331 } 4332 4333 /* clear up the handshake status after re-initialize done */ 4334 hclge_reset_handshake(hdev, false); 4335 4336 return ret; 4337 } 4338 4339 static int hclge_reset_stack(struct hclge_dev *hdev) 4340 { 4341 int ret; 4342 4343 ret = hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT); 4344 if (ret) 4345 return ret; 4346 4347 ret = hclge_reset_ae_dev(hdev->ae_dev); 4348 if (ret) 4349 return ret; 4350 4351 return hclge_notify_client(hdev, HNAE3_INIT_CLIENT); 4352 } 4353 4354 static int hclge_reset_prepare(struct hclge_dev *hdev) 4355 { 4356 int ret; 4357 4358 hdev->rst_stats.reset_cnt++; 4359 /* perform reset of the stack & ae device for a client */ 4360 ret = hclge_notify_roce_client(hdev, HNAE3_DOWN_CLIENT); 4361 if (ret) 4362 return ret; 4363 4364 rtnl_lock(); 4365 ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 4366 rtnl_unlock(); 4367 if (ret) 4368 return ret; 4369 4370 return hclge_reset_prepare_wait(hdev); 4371 } 4372 4373 static int hclge_reset_rebuild(struct hclge_dev *hdev) 4374 { 4375 int ret; 4376 4377 hdev->rst_stats.hw_reset_done_cnt++; 4378 4379 ret = hclge_notify_roce_client(hdev, HNAE3_UNINIT_CLIENT); 4380 if (ret) 4381 return ret; 4382 4383 rtnl_lock(); 4384 ret = hclge_reset_stack(hdev); 4385 rtnl_unlock(); 4386 if (ret) 4387 return ret; 4388 4389 hclge_clear_reset_cause(hdev); 4390 4391 ret = hclge_notify_roce_client(hdev, HNAE3_INIT_CLIENT); 4392 /* ignore RoCE notify error if it fails HCLGE_RESET_MAX_FAIL_CNT - 1 4393 * times 4394 */ 4395 if (ret && 4396 hdev->rst_stats.reset_fail_cnt < HCLGE_RESET_MAX_FAIL_CNT - 1) 4397 return ret; 4398 4399 ret = hclge_reset_prepare_up(hdev); 4400 if (ret) 4401 return ret; 4402 4403 rtnl_lock(); 4404 ret = hclge_notify_client(hdev, HNAE3_UP_CLIENT); 4405 rtnl_unlock(); 4406 if (ret) 4407 return ret; 4408 4409 ret = hclge_notify_roce_client(hdev, HNAE3_UP_CLIENT); 4410 if (ret) 4411 return ret; 4412 4413 hdev->last_reset_time = jiffies; 4414 hdev->rst_stats.reset_fail_cnt = 0; 4415 hdev->rst_stats.reset_done_cnt++; 4416 clear_bit(HCLGE_STATE_RST_FAIL, &hdev->state); 4417 4418 hclge_update_reset_level(hdev); 4419 4420 return 0; 4421 } 4422 4423 static void hclge_reset(struct hclge_dev *hdev) 4424 { 4425 if (hclge_reset_prepare(hdev)) 4426 goto err_reset; 4427 4428 if (hclge_reset_wait(hdev)) 4429 goto err_reset; 4430 4431 if (hclge_reset_rebuild(hdev)) 4432 goto err_reset; 4433 4434 return; 4435 4436 err_reset: 4437 if (hclge_reset_err_handle(hdev)) 4438 hclge_reset_task_schedule(hdev); 4439 } 4440 4441 static void hclge_reset_event(struct pci_dev *pdev, struct hnae3_handle *handle) 4442 { 4443 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 4444 struct hclge_dev *hdev = ae_dev->priv; 4445 4446 /* We might end up getting called broadly because of 2 below cases: 4447 * 1. Recoverable error was conveyed through APEI and only way to bring 4448 * normalcy is to reset. 4449 * 2. A new reset request from the stack due to timeout 4450 * 4451 * check if this is a new reset request and we are not here just because 4452 * last reset attempt did not succeed and watchdog hit us again. We will 4453 * know this if last reset request did not occur very recently (watchdog 4454 * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz) 4455 * In case of new request we reset the "reset level" to PF reset. 4456 * And if it is a repeat reset request of the most recent one then we 4457 * want to make sure we throttle the reset request. Therefore, we will 4458 * not allow it again before 3*HZ times. 4459 */ 4460 4461 if (time_before(jiffies, (hdev->last_reset_time + 4462 HCLGE_RESET_INTERVAL))) { 4463 mod_timer(&hdev->reset_timer, jiffies + HCLGE_RESET_INTERVAL); 4464 return; 4465 } 4466 4467 if (hdev->default_reset_request) { 4468 hdev->reset_level = 4469 hclge_get_reset_level(ae_dev, 4470 &hdev->default_reset_request); 4471 } else if (time_after(jiffies, (hdev->last_reset_time + 4 * 5 * HZ))) { 4472 hdev->reset_level = HNAE3_FUNC_RESET; 4473 } 4474 4475 dev_info(&hdev->pdev->dev, "received reset event, reset type is %d\n", 4476 hdev->reset_level); 4477 4478 /* request reset & schedule reset task */ 4479 set_bit(hdev->reset_level, &hdev->reset_request); 4480 hclge_reset_task_schedule(hdev); 4481 4482 if (hdev->reset_level < HNAE3_GLOBAL_RESET) 4483 hdev->reset_level++; 4484 } 4485 4486 static void hclge_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 4487 enum hnae3_reset_type rst_type) 4488 { 4489 struct hclge_dev *hdev = ae_dev->priv; 4490 4491 set_bit(rst_type, &hdev->default_reset_request); 4492 } 4493 4494 static void hclge_reset_timer(struct timer_list *t) 4495 { 4496 struct hclge_dev *hdev = from_timer(hdev, t, reset_timer); 4497 4498 /* if default_reset_request has no value, it means that this reset 4499 * request has already be handled, so just return here 4500 */ 4501 if (!hdev->default_reset_request) 4502 return; 4503 4504 dev_info(&hdev->pdev->dev, 4505 "triggering reset in reset timer\n"); 4506 hclge_reset_event(hdev->pdev, NULL); 4507 } 4508 4509 static void hclge_reset_subtask(struct hclge_dev *hdev) 4510 { 4511 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4512 4513 /* check if there is any ongoing reset in the hardware. This status can 4514 * be checked from reset_pending. If there is then, we need to wait for 4515 * hardware to complete reset. 4516 * a. If we are able to figure out in reasonable time that hardware 4517 * has fully resetted then, we can proceed with driver, client 4518 * reset. 4519 * b. else, we can come back later to check this status so re-sched 4520 * now. 4521 */ 4522 hdev->last_reset_time = jiffies; 4523 hdev->reset_type = hclge_get_reset_level(ae_dev, &hdev->reset_pending); 4524 if (hdev->reset_type != HNAE3_NONE_RESET) 4525 hclge_reset(hdev); 4526 4527 /* check if we got any *new* reset requests to be honored */ 4528 hdev->reset_type = hclge_get_reset_level(ae_dev, &hdev->reset_request); 4529 if (hdev->reset_type != HNAE3_NONE_RESET) 4530 hclge_do_reset(hdev); 4531 4532 hdev->reset_type = HNAE3_NONE_RESET; 4533 } 4534 4535 static void hclge_handle_err_reset_request(struct hclge_dev *hdev) 4536 { 4537 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4538 enum hnae3_reset_type reset_type; 4539 4540 if (ae_dev->hw_err_reset_req) { 4541 reset_type = hclge_get_reset_level(ae_dev, 4542 &ae_dev->hw_err_reset_req); 4543 hclge_set_def_reset_request(ae_dev, reset_type); 4544 } 4545 4546 if (hdev->default_reset_request && ae_dev->ops->reset_event) 4547 ae_dev->ops->reset_event(hdev->pdev, NULL); 4548 4549 /* enable interrupt after error handling complete */ 4550 hclge_enable_vector(&hdev->misc_vector, true); 4551 } 4552 4553 static void hclge_handle_err_recovery(struct hclge_dev *hdev) 4554 { 4555 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4556 4557 ae_dev->hw_err_reset_req = 0; 4558 4559 if (hclge_find_error_source(hdev)) { 4560 hclge_handle_error_info_log(ae_dev); 4561 hclge_handle_mac_tnl(hdev); 4562 } 4563 4564 hclge_handle_err_reset_request(hdev); 4565 } 4566 4567 static void hclge_misc_err_recovery(struct hclge_dev *hdev) 4568 { 4569 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4570 struct device *dev = &hdev->pdev->dev; 4571 u32 msix_sts_reg; 4572 4573 msix_sts_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS); 4574 if (msix_sts_reg & HCLGE_VECTOR0_REG_MSIX_MASK) { 4575 if (hclge_handle_hw_msix_error 4576 (hdev, &hdev->default_reset_request)) 4577 dev_info(dev, "received msix interrupt 0x%x\n", 4578 msix_sts_reg); 4579 } 4580 4581 hclge_handle_hw_ras_error(ae_dev); 4582 4583 hclge_handle_err_reset_request(hdev); 4584 } 4585 4586 static void hclge_errhand_service_task(struct hclge_dev *hdev) 4587 { 4588 if (!test_and_clear_bit(HCLGE_STATE_ERR_SERVICE_SCHED, &hdev->state)) 4589 return; 4590 4591 if (hnae3_dev_ras_imp_supported(hdev)) 4592 hclge_handle_err_recovery(hdev); 4593 else 4594 hclge_misc_err_recovery(hdev); 4595 } 4596 4597 static void hclge_reset_service_task(struct hclge_dev *hdev) 4598 { 4599 if (!test_and_clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state)) 4600 return; 4601 4602 if (time_is_before_jiffies(hdev->last_rst_scheduled + 4603 HCLGE_RESET_SCHED_TIMEOUT)) 4604 dev_warn(&hdev->pdev->dev, 4605 "reset service task is scheduled after %ums on cpu%u!\n", 4606 jiffies_to_msecs(jiffies - hdev->last_rst_scheduled), 4607 smp_processor_id()); 4608 4609 down(&hdev->reset_sem); 4610 set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 4611 4612 hclge_reset_subtask(hdev); 4613 4614 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 4615 up(&hdev->reset_sem); 4616 } 4617 4618 static void hclge_update_vport_alive(struct hclge_dev *hdev) 4619 { 4620 #define HCLGE_ALIVE_SECONDS_NORMAL 8 4621 4622 unsigned long alive_time = HCLGE_ALIVE_SECONDS_NORMAL * HZ; 4623 int i; 4624 4625 /* start from vport 1 for PF is always alive */ 4626 for (i = 1; i < hdev->num_alloc_vport; i++) { 4627 struct hclge_vport *vport = &hdev->vport[i]; 4628 4629 if (!test_bit(HCLGE_VPORT_STATE_INITED, &vport->state) || 4630 !test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) 4631 continue; 4632 if (time_after(jiffies, vport->last_active_jiffies + 4633 alive_time)) { 4634 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 4635 dev_warn(&hdev->pdev->dev, 4636 "VF %u heartbeat timeout\n", 4637 i - HCLGE_VF_VPORT_START_NUM); 4638 } 4639 } 4640 } 4641 4642 static void hclge_periodic_service_task(struct hclge_dev *hdev) 4643 { 4644 unsigned long delta = round_jiffies_relative(HZ); 4645 4646 if (test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) 4647 return; 4648 4649 /* Always handle the link updating to make sure link state is 4650 * updated when it is triggered by mbx. 4651 */ 4652 hclge_update_link_status(hdev); 4653 hclge_sync_mac_table(hdev); 4654 hclge_sync_promisc_mode(hdev); 4655 hclge_sync_fd_table(hdev); 4656 4657 if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) { 4658 delta = jiffies - hdev->last_serv_processed; 4659 4660 if (delta < round_jiffies_relative(HZ)) { 4661 delta = round_jiffies_relative(HZ) - delta; 4662 goto out; 4663 } 4664 } 4665 4666 hdev->serv_processed_cnt++; 4667 hclge_update_vport_alive(hdev); 4668 4669 if (test_bit(HCLGE_STATE_DOWN, &hdev->state)) { 4670 hdev->last_serv_processed = jiffies; 4671 goto out; 4672 } 4673 4674 if (!(hdev->serv_processed_cnt % HCLGE_STATS_TIMER_INTERVAL)) 4675 hclge_update_stats_for_all(hdev); 4676 4677 hclge_update_port_info(hdev); 4678 hclge_sync_vlan_filter(hdev); 4679 4680 if (!(hdev->serv_processed_cnt % HCLGE_ARFS_EXPIRE_INTERVAL)) 4681 hclge_rfs_filter_expire(hdev); 4682 4683 hdev->last_serv_processed = jiffies; 4684 4685 out: 4686 hclge_task_schedule(hdev, delta); 4687 } 4688 4689 static void hclge_ptp_service_task(struct hclge_dev *hdev) 4690 { 4691 unsigned long flags; 4692 4693 if (!test_bit(HCLGE_STATE_PTP_EN, &hdev->state) || 4694 !test_bit(HCLGE_STATE_PTP_TX_HANDLING, &hdev->state) || 4695 !time_is_before_jiffies(hdev->ptp->tx_start + HZ)) 4696 return; 4697 4698 /* to prevent concurrence with the irq handler */ 4699 spin_lock_irqsave(&hdev->ptp->lock, flags); 4700 4701 /* check HCLGE_STATE_PTP_TX_HANDLING here again, since the irq 4702 * handler may handle it just before spin_lock_irqsave(). 4703 */ 4704 if (test_bit(HCLGE_STATE_PTP_TX_HANDLING, &hdev->state)) 4705 hclge_ptp_clean_tx_hwts(hdev); 4706 4707 spin_unlock_irqrestore(&hdev->ptp->lock, flags); 4708 } 4709 4710 static void hclge_service_task(struct work_struct *work) 4711 { 4712 struct hclge_dev *hdev = 4713 container_of(work, struct hclge_dev, service_task.work); 4714 4715 hclge_errhand_service_task(hdev); 4716 hclge_reset_service_task(hdev); 4717 hclge_ptp_service_task(hdev); 4718 hclge_mailbox_service_task(hdev); 4719 hclge_periodic_service_task(hdev); 4720 4721 /* Handle error recovery, reset and mbx again in case periodical task 4722 * delays the handling by calling hclge_task_schedule() in 4723 * hclge_periodic_service_task(). 4724 */ 4725 hclge_errhand_service_task(hdev); 4726 hclge_reset_service_task(hdev); 4727 hclge_mailbox_service_task(hdev); 4728 } 4729 4730 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle) 4731 { 4732 /* VF handle has no client */ 4733 if (!handle->client) 4734 return container_of(handle, struct hclge_vport, nic); 4735 else if (handle->client->type == HNAE3_CLIENT_ROCE) 4736 return container_of(handle, struct hclge_vport, roce); 4737 else 4738 return container_of(handle, struct hclge_vport, nic); 4739 } 4740 4741 static void hclge_get_vector_info(struct hclge_dev *hdev, u16 idx, 4742 struct hnae3_vector_info *vector_info) 4743 { 4744 #define HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 64 4745 4746 vector_info->vector = pci_irq_vector(hdev->pdev, idx); 4747 4748 /* need an extend offset to config vector >= 64 */ 4749 if (idx - 1 < HCLGE_PF_MAX_VECTOR_NUM_DEV_V2) 4750 vector_info->io_addr = hdev->hw.hw.io_base + 4751 HCLGE_VECTOR_REG_BASE + 4752 (idx - 1) * HCLGE_VECTOR_REG_OFFSET; 4753 else 4754 vector_info->io_addr = hdev->hw.hw.io_base + 4755 HCLGE_VECTOR_EXT_REG_BASE + 4756 (idx - 1) / HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 * 4757 HCLGE_VECTOR_REG_OFFSET_H + 4758 (idx - 1) % HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 * 4759 HCLGE_VECTOR_REG_OFFSET; 4760 4761 hdev->vector_status[idx] = hdev->vport[0].vport_id; 4762 hdev->vector_irq[idx] = vector_info->vector; 4763 } 4764 4765 static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num, 4766 struct hnae3_vector_info *vector_info) 4767 { 4768 struct hclge_vport *vport = hclge_get_vport(handle); 4769 struct hnae3_vector_info *vector = vector_info; 4770 struct hclge_dev *hdev = vport->back; 4771 int alloc = 0; 4772 u16 i = 0; 4773 u16 j; 4774 4775 vector_num = min_t(u16, hdev->num_nic_msi - 1, vector_num); 4776 vector_num = min(hdev->num_msi_left, vector_num); 4777 4778 for (j = 0; j < vector_num; j++) { 4779 while (++i < hdev->num_nic_msi) { 4780 if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) { 4781 hclge_get_vector_info(hdev, i, vector); 4782 vector++; 4783 alloc++; 4784 4785 break; 4786 } 4787 } 4788 } 4789 hdev->num_msi_left -= alloc; 4790 hdev->num_msi_used += alloc; 4791 4792 return alloc; 4793 } 4794 4795 static int hclge_get_vector_index(struct hclge_dev *hdev, int vector) 4796 { 4797 int i; 4798 4799 for (i = 0; i < hdev->num_msi; i++) 4800 if (vector == hdev->vector_irq[i]) 4801 return i; 4802 4803 return -EINVAL; 4804 } 4805 4806 static int hclge_put_vector(struct hnae3_handle *handle, int vector) 4807 { 4808 struct hclge_vport *vport = hclge_get_vport(handle); 4809 struct hclge_dev *hdev = vport->back; 4810 int vector_id; 4811 4812 vector_id = hclge_get_vector_index(hdev, vector); 4813 if (vector_id < 0) { 4814 dev_err(&hdev->pdev->dev, 4815 "Get vector index fail. vector = %d\n", vector); 4816 return vector_id; 4817 } 4818 4819 hclge_free_vector(hdev, vector_id); 4820 4821 return 0; 4822 } 4823 4824 static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir, 4825 u8 *key, u8 *hfunc) 4826 { 4827 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 4828 struct hclge_vport *vport = hclge_get_vport(handle); 4829 struct hclge_comm_rss_cfg *rss_cfg = &vport->back->rss_cfg; 4830 4831 hclge_comm_get_rss_hash_info(rss_cfg, key, hfunc); 4832 4833 hclge_comm_get_rss_indir_tbl(rss_cfg, indir, 4834 ae_dev->dev_specs.rss_ind_tbl_size); 4835 4836 return 0; 4837 } 4838 4839 static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir, 4840 const u8 *key, const u8 hfunc) 4841 { 4842 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 4843 struct hclge_vport *vport = hclge_get_vport(handle); 4844 struct hclge_dev *hdev = vport->back; 4845 struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 4846 int ret, i; 4847 4848 ret = hclge_comm_set_rss_hash_key(rss_cfg, &hdev->hw.hw, key, hfunc); 4849 if (ret) { 4850 dev_err(&hdev->pdev->dev, "invalid hfunc type %u\n", hfunc); 4851 return ret; 4852 } 4853 4854 /* Update the shadow RSS table with user specified qids */ 4855 for (i = 0; i < ae_dev->dev_specs.rss_ind_tbl_size; i++) 4856 rss_cfg->rss_indirection_tbl[i] = indir[i]; 4857 4858 /* Update the hardware */ 4859 return hclge_comm_set_rss_indir_table(ae_dev, &hdev->hw.hw, 4860 rss_cfg->rss_indirection_tbl); 4861 } 4862 4863 static int hclge_set_rss_tuple(struct hnae3_handle *handle, 4864 struct ethtool_rxnfc *nfc) 4865 { 4866 struct hclge_vport *vport = hclge_get_vport(handle); 4867 struct hclge_dev *hdev = vport->back; 4868 int ret; 4869 4870 ret = hclge_comm_set_rss_tuple(hdev->ae_dev, &hdev->hw.hw, 4871 &hdev->rss_cfg, nfc); 4872 if (ret) { 4873 dev_err(&hdev->pdev->dev, 4874 "failed to set rss tuple, ret = %d.\n", ret); 4875 return ret; 4876 } 4877 4878 return 0; 4879 } 4880 4881 static int hclge_get_rss_tuple(struct hnae3_handle *handle, 4882 struct ethtool_rxnfc *nfc) 4883 { 4884 struct hclge_vport *vport = hclge_get_vport(handle); 4885 u8 tuple_sets; 4886 int ret; 4887 4888 nfc->data = 0; 4889 4890 ret = hclge_comm_get_rss_tuple(&vport->back->rss_cfg, nfc->flow_type, 4891 &tuple_sets); 4892 if (ret || !tuple_sets) 4893 return ret; 4894 4895 nfc->data = hclge_comm_convert_rss_tuple(tuple_sets); 4896 4897 return 0; 4898 } 4899 4900 static int hclge_get_tc_size(struct hnae3_handle *handle) 4901 { 4902 struct hclge_vport *vport = hclge_get_vport(handle); 4903 struct hclge_dev *hdev = vport->back; 4904 4905 return hdev->pf_rss_size_max; 4906 } 4907 4908 static int hclge_init_rss_tc_mode(struct hclge_dev *hdev) 4909 { 4910 struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 4911 struct hclge_vport *vport = hdev->vport; 4912 u16 tc_offset[HCLGE_MAX_TC_NUM] = {0}; 4913 u16 tc_valid[HCLGE_MAX_TC_NUM] = {0}; 4914 u16 tc_size[HCLGE_MAX_TC_NUM] = {0}; 4915 struct hnae3_tc_info *tc_info; 4916 u16 roundup_size; 4917 u16 rss_size; 4918 int i; 4919 4920 tc_info = &vport->nic.kinfo.tc_info; 4921 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 4922 rss_size = tc_info->tqp_count[i]; 4923 tc_valid[i] = 0; 4924 4925 if (!(hdev->hw_tc_map & BIT(i))) 4926 continue; 4927 4928 /* tc_size set to hardware is the log2 of roundup power of two 4929 * of rss_size, the acutal queue size is limited by indirection 4930 * table. 4931 */ 4932 if (rss_size > ae_dev->dev_specs.rss_ind_tbl_size || 4933 rss_size == 0) { 4934 dev_err(&hdev->pdev->dev, 4935 "Configure rss tc size failed, invalid TC_SIZE = %u\n", 4936 rss_size); 4937 return -EINVAL; 4938 } 4939 4940 roundup_size = roundup_pow_of_two(rss_size); 4941 roundup_size = ilog2(roundup_size); 4942 4943 tc_valid[i] = 1; 4944 tc_size[i] = roundup_size; 4945 tc_offset[i] = tc_info->tqp_offset[i]; 4946 } 4947 4948 return hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, tc_valid, 4949 tc_size); 4950 } 4951 4952 int hclge_rss_init_hw(struct hclge_dev *hdev) 4953 { 4954 u16 *rss_indir = hdev->rss_cfg.rss_indirection_tbl; 4955 u8 *key = hdev->rss_cfg.rss_hash_key; 4956 u8 hfunc = hdev->rss_cfg.rss_algo; 4957 int ret; 4958 4959 ret = hclge_comm_set_rss_indir_table(hdev->ae_dev, &hdev->hw.hw, 4960 rss_indir); 4961 if (ret) 4962 return ret; 4963 4964 ret = hclge_comm_set_rss_algo_key(&hdev->hw.hw, hfunc, key); 4965 if (ret) 4966 return ret; 4967 4968 ret = hclge_comm_set_rss_input_tuple(&hdev->vport[0].nic, 4969 &hdev->hw.hw, true, 4970 &hdev->rss_cfg); 4971 if (ret) 4972 return ret; 4973 4974 return hclge_init_rss_tc_mode(hdev); 4975 } 4976 4977 int hclge_bind_ring_with_vector(struct hclge_vport *vport, 4978 int vector_id, bool en, 4979 struct hnae3_ring_chain_node *ring_chain) 4980 { 4981 struct hclge_dev *hdev = vport->back; 4982 struct hnae3_ring_chain_node *node; 4983 struct hclge_desc desc; 4984 struct hclge_ctrl_vector_chain_cmd *req = 4985 (struct hclge_ctrl_vector_chain_cmd *)desc.data; 4986 enum hclge_comm_cmd_status status; 4987 enum hclge_opcode_type op; 4988 u16 tqp_type_and_id; 4989 int i; 4990 4991 op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR; 4992 hclge_cmd_setup_basic_desc(&desc, op, false); 4993 req->int_vector_id_l = hnae3_get_field(vector_id, 4994 HCLGE_VECTOR_ID_L_M, 4995 HCLGE_VECTOR_ID_L_S); 4996 req->int_vector_id_h = hnae3_get_field(vector_id, 4997 HCLGE_VECTOR_ID_H_M, 4998 HCLGE_VECTOR_ID_H_S); 4999 5000 i = 0; 5001 for (node = ring_chain; node; node = node->next) { 5002 tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]); 5003 hnae3_set_field(tqp_type_and_id, HCLGE_INT_TYPE_M, 5004 HCLGE_INT_TYPE_S, 5005 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B)); 5006 hnae3_set_field(tqp_type_and_id, HCLGE_TQP_ID_M, 5007 HCLGE_TQP_ID_S, node->tqp_index); 5008 hnae3_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M, 5009 HCLGE_INT_GL_IDX_S, 5010 hnae3_get_field(node->int_gl_idx, 5011 HNAE3_RING_GL_IDX_M, 5012 HNAE3_RING_GL_IDX_S)); 5013 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id); 5014 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) { 5015 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD; 5016 req->vfid = vport->vport_id; 5017 5018 status = hclge_cmd_send(&hdev->hw, &desc, 1); 5019 if (status) { 5020 dev_err(&hdev->pdev->dev, 5021 "Map TQP fail, status is %d.\n", 5022 status); 5023 return -EIO; 5024 } 5025 i = 0; 5026 5027 hclge_cmd_setup_basic_desc(&desc, 5028 op, 5029 false); 5030 req->int_vector_id_l = 5031 hnae3_get_field(vector_id, 5032 HCLGE_VECTOR_ID_L_M, 5033 HCLGE_VECTOR_ID_L_S); 5034 req->int_vector_id_h = 5035 hnae3_get_field(vector_id, 5036 HCLGE_VECTOR_ID_H_M, 5037 HCLGE_VECTOR_ID_H_S); 5038 } 5039 } 5040 5041 if (i > 0) { 5042 req->int_cause_num = i; 5043 req->vfid = vport->vport_id; 5044 status = hclge_cmd_send(&hdev->hw, &desc, 1); 5045 if (status) { 5046 dev_err(&hdev->pdev->dev, 5047 "Map TQP fail, status is %d.\n", status); 5048 return -EIO; 5049 } 5050 } 5051 5052 return 0; 5053 } 5054 5055 static int hclge_map_ring_to_vector(struct hnae3_handle *handle, int vector, 5056 struct hnae3_ring_chain_node *ring_chain) 5057 { 5058 struct hclge_vport *vport = hclge_get_vport(handle); 5059 struct hclge_dev *hdev = vport->back; 5060 int vector_id; 5061 5062 vector_id = hclge_get_vector_index(hdev, vector); 5063 if (vector_id < 0) { 5064 dev_err(&hdev->pdev->dev, 5065 "failed to get vector index. vector=%d\n", vector); 5066 return vector_id; 5067 } 5068 5069 return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain); 5070 } 5071 5072 static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle, int vector, 5073 struct hnae3_ring_chain_node *ring_chain) 5074 { 5075 struct hclge_vport *vport = hclge_get_vport(handle); 5076 struct hclge_dev *hdev = vport->back; 5077 int vector_id, ret; 5078 5079 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 5080 return 0; 5081 5082 vector_id = hclge_get_vector_index(hdev, vector); 5083 if (vector_id < 0) { 5084 dev_err(&handle->pdev->dev, 5085 "Get vector index fail. ret =%d\n", vector_id); 5086 return vector_id; 5087 } 5088 5089 ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain); 5090 if (ret) 5091 dev_err(&handle->pdev->dev, 5092 "Unmap ring from vector fail. vectorid=%d, ret =%d\n", 5093 vector_id, ret); 5094 5095 return ret; 5096 } 5097 5098 static int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev, u8 vf_id, 5099 bool en_uc, bool en_mc, bool en_bc) 5100 { 5101 struct hclge_vport *vport = &hdev->vport[vf_id]; 5102 struct hnae3_handle *handle = &vport->nic; 5103 struct hclge_promisc_cfg_cmd *req; 5104 struct hclge_desc desc; 5105 bool uc_tx_en = en_uc; 5106 u8 promisc_cfg = 0; 5107 int ret; 5108 5109 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false); 5110 5111 req = (struct hclge_promisc_cfg_cmd *)desc.data; 5112 req->vf_id = vf_id; 5113 5114 if (test_bit(HNAE3_PFLAG_LIMIT_PROMISC, &handle->priv_flags)) 5115 uc_tx_en = false; 5116 5117 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_UC_RX_EN, en_uc ? 1 : 0); 5118 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_MC_RX_EN, en_mc ? 1 : 0); 5119 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_BC_RX_EN, en_bc ? 1 : 0); 5120 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_UC_TX_EN, uc_tx_en ? 1 : 0); 5121 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_MC_TX_EN, en_mc ? 1 : 0); 5122 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_BC_TX_EN, en_bc ? 1 : 0); 5123 req->extend_promisc = promisc_cfg; 5124 5125 /* to be compatible with DEVICE_VERSION_V1/2 */ 5126 promisc_cfg = 0; 5127 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_UC, en_uc ? 1 : 0); 5128 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_MC, en_mc ? 1 : 0); 5129 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_BC, en_bc ? 1 : 0); 5130 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_TX_EN, 1); 5131 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_RX_EN, 1); 5132 req->promisc = promisc_cfg; 5133 5134 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5135 if (ret) 5136 dev_err(&hdev->pdev->dev, 5137 "failed to set vport %u promisc mode, ret = %d.\n", 5138 vf_id, ret); 5139 5140 return ret; 5141 } 5142 5143 int hclge_set_vport_promisc_mode(struct hclge_vport *vport, bool en_uc_pmc, 5144 bool en_mc_pmc, bool en_bc_pmc) 5145 { 5146 return hclge_cmd_set_promisc_mode(vport->back, vport->vport_id, 5147 en_uc_pmc, en_mc_pmc, en_bc_pmc); 5148 } 5149 5150 static int hclge_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc, 5151 bool en_mc_pmc) 5152 { 5153 struct hclge_vport *vport = hclge_get_vport(handle); 5154 struct hclge_dev *hdev = vport->back; 5155 bool en_bc_pmc = true; 5156 5157 /* For device whose version below V2, if broadcast promisc enabled, 5158 * vlan filter is always bypassed. So broadcast promisc should be 5159 * disabled until user enable promisc mode 5160 */ 5161 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 5162 en_bc_pmc = handle->netdev_flags & HNAE3_BPE ? true : false; 5163 5164 return hclge_set_vport_promisc_mode(vport, en_uc_pmc, en_mc_pmc, 5165 en_bc_pmc); 5166 } 5167 5168 static void hclge_request_update_promisc_mode(struct hnae3_handle *handle) 5169 { 5170 struct hclge_vport *vport = hclge_get_vport(handle); 5171 5172 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 5173 } 5174 5175 static void hclge_sync_fd_state(struct hclge_dev *hdev) 5176 { 5177 if (hlist_empty(&hdev->fd_rule_list)) 5178 hdev->fd_active_type = HCLGE_FD_RULE_NONE; 5179 } 5180 5181 static void hclge_fd_inc_rule_cnt(struct hclge_dev *hdev, u16 location) 5182 { 5183 if (!test_bit(location, hdev->fd_bmap)) { 5184 set_bit(location, hdev->fd_bmap); 5185 hdev->hclge_fd_rule_num++; 5186 } 5187 } 5188 5189 static void hclge_fd_dec_rule_cnt(struct hclge_dev *hdev, u16 location) 5190 { 5191 if (test_bit(location, hdev->fd_bmap)) { 5192 clear_bit(location, hdev->fd_bmap); 5193 hdev->hclge_fd_rule_num--; 5194 } 5195 } 5196 5197 static void hclge_fd_free_node(struct hclge_dev *hdev, 5198 struct hclge_fd_rule *rule) 5199 { 5200 hlist_del(&rule->rule_node); 5201 kfree(rule); 5202 hclge_sync_fd_state(hdev); 5203 } 5204 5205 static void hclge_update_fd_rule_node(struct hclge_dev *hdev, 5206 struct hclge_fd_rule *old_rule, 5207 struct hclge_fd_rule *new_rule, 5208 enum HCLGE_FD_NODE_STATE state) 5209 { 5210 switch (state) { 5211 case HCLGE_FD_TO_ADD: 5212 case HCLGE_FD_ACTIVE: 5213 /* 1) if the new state is TO_ADD, just replace the old rule 5214 * with the same location, no matter its state, because the 5215 * new rule will be configured to the hardware. 5216 * 2) if the new state is ACTIVE, it means the new rule 5217 * has been configured to the hardware, so just replace 5218 * the old rule node with the same location. 5219 * 3) for it doesn't add a new node to the list, so it's 5220 * unnecessary to update the rule number and fd_bmap. 5221 */ 5222 new_rule->rule_node.next = old_rule->rule_node.next; 5223 new_rule->rule_node.pprev = old_rule->rule_node.pprev; 5224 memcpy(old_rule, new_rule, sizeof(*old_rule)); 5225 kfree(new_rule); 5226 break; 5227 case HCLGE_FD_DELETED: 5228 hclge_fd_dec_rule_cnt(hdev, old_rule->location); 5229 hclge_fd_free_node(hdev, old_rule); 5230 break; 5231 case HCLGE_FD_TO_DEL: 5232 /* if new request is TO_DEL, and old rule is existent 5233 * 1) the state of old rule is TO_DEL, we need do nothing, 5234 * because we delete rule by location, other rule content 5235 * is unncessary. 5236 * 2) the state of old rule is ACTIVE, we need to change its 5237 * state to TO_DEL, so the rule will be deleted when periodic 5238 * task being scheduled. 5239 * 3) the state of old rule is TO_ADD, it means the rule hasn't 5240 * been added to hardware, so we just delete the rule node from 5241 * fd_rule_list directly. 5242 */ 5243 if (old_rule->state == HCLGE_FD_TO_ADD) { 5244 hclge_fd_dec_rule_cnt(hdev, old_rule->location); 5245 hclge_fd_free_node(hdev, old_rule); 5246 return; 5247 } 5248 old_rule->state = HCLGE_FD_TO_DEL; 5249 break; 5250 } 5251 } 5252 5253 static struct hclge_fd_rule *hclge_find_fd_rule(struct hlist_head *hlist, 5254 u16 location, 5255 struct hclge_fd_rule **parent) 5256 { 5257 struct hclge_fd_rule *rule; 5258 struct hlist_node *node; 5259 5260 hlist_for_each_entry_safe(rule, node, hlist, rule_node) { 5261 if (rule->location == location) 5262 return rule; 5263 else if (rule->location > location) 5264 return NULL; 5265 /* record the parent node, use to keep the nodes in fd_rule_list 5266 * in ascend order. 5267 */ 5268 *parent = rule; 5269 } 5270 5271 return NULL; 5272 } 5273 5274 /* insert fd rule node in ascend order according to rule->location */ 5275 static void hclge_fd_insert_rule_node(struct hlist_head *hlist, 5276 struct hclge_fd_rule *rule, 5277 struct hclge_fd_rule *parent) 5278 { 5279 INIT_HLIST_NODE(&rule->rule_node); 5280 5281 if (parent) 5282 hlist_add_behind(&rule->rule_node, &parent->rule_node); 5283 else 5284 hlist_add_head(&rule->rule_node, hlist); 5285 } 5286 5287 static int hclge_fd_set_user_def_cmd(struct hclge_dev *hdev, 5288 struct hclge_fd_user_def_cfg *cfg) 5289 { 5290 struct hclge_fd_user_def_cfg_cmd *req; 5291 struct hclge_desc desc; 5292 u16 data = 0; 5293 int ret; 5294 5295 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_USER_DEF_OP, false); 5296 5297 req = (struct hclge_fd_user_def_cfg_cmd *)desc.data; 5298 5299 hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[0].ref_cnt > 0); 5300 hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M, 5301 HCLGE_FD_USER_DEF_OFT_S, cfg[0].offset); 5302 req->ol2_cfg = cpu_to_le16(data); 5303 5304 data = 0; 5305 hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[1].ref_cnt > 0); 5306 hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M, 5307 HCLGE_FD_USER_DEF_OFT_S, cfg[1].offset); 5308 req->ol3_cfg = cpu_to_le16(data); 5309 5310 data = 0; 5311 hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[2].ref_cnt > 0); 5312 hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M, 5313 HCLGE_FD_USER_DEF_OFT_S, cfg[2].offset); 5314 req->ol4_cfg = cpu_to_le16(data); 5315 5316 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5317 if (ret) 5318 dev_err(&hdev->pdev->dev, 5319 "failed to set fd user def data, ret= %d\n", ret); 5320 return ret; 5321 } 5322 5323 static void hclge_sync_fd_user_def_cfg(struct hclge_dev *hdev, bool locked) 5324 { 5325 int ret; 5326 5327 if (!test_and_clear_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state)) 5328 return; 5329 5330 if (!locked) 5331 spin_lock_bh(&hdev->fd_rule_lock); 5332 5333 ret = hclge_fd_set_user_def_cmd(hdev, hdev->fd_cfg.user_def_cfg); 5334 if (ret) 5335 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 5336 5337 if (!locked) 5338 spin_unlock_bh(&hdev->fd_rule_lock); 5339 } 5340 5341 static int hclge_fd_check_user_def_refcnt(struct hclge_dev *hdev, 5342 struct hclge_fd_rule *rule) 5343 { 5344 struct hlist_head *hlist = &hdev->fd_rule_list; 5345 struct hclge_fd_rule *fd_rule, *parent = NULL; 5346 struct hclge_fd_user_def_info *info, *old_info; 5347 struct hclge_fd_user_def_cfg *cfg; 5348 5349 if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE || 5350 rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE) 5351 return 0; 5352 5353 /* for valid layer is start from 1, so need minus 1 to get the cfg */ 5354 cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1]; 5355 info = &rule->ep.user_def; 5356 5357 if (!cfg->ref_cnt || cfg->offset == info->offset) 5358 return 0; 5359 5360 if (cfg->ref_cnt > 1) 5361 goto error; 5362 5363 fd_rule = hclge_find_fd_rule(hlist, rule->location, &parent); 5364 if (fd_rule) { 5365 old_info = &fd_rule->ep.user_def; 5366 if (info->layer == old_info->layer) 5367 return 0; 5368 } 5369 5370 error: 5371 dev_err(&hdev->pdev->dev, 5372 "No available offset for layer%d fd rule, each layer only support one user def offset.\n", 5373 info->layer + 1); 5374 return -ENOSPC; 5375 } 5376 5377 static void hclge_fd_inc_user_def_refcnt(struct hclge_dev *hdev, 5378 struct hclge_fd_rule *rule) 5379 { 5380 struct hclge_fd_user_def_cfg *cfg; 5381 5382 if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE || 5383 rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE) 5384 return; 5385 5386 cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1]; 5387 if (!cfg->ref_cnt) { 5388 cfg->offset = rule->ep.user_def.offset; 5389 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 5390 } 5391 cfg->ref_cnt++; 5392 } 5393 5394 static void hclge_fd_dec_user_def_refcnt(struct hclge_dev *hdev, 5395 struct hclge_fd_rule *rule) 5396 { 5397 struct hclge_fd_user_def_cfg *cfg; 5398 5399 if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE || 5400 rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE) 5401 return; 5402 5403 cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1]; 5404 if (!cfg->ref_cnt) 5405 return; 5406 5407 cfg->ref_cnt--; 5408 if (!cfg->ref_cnt) { 5409 cfg->offset = 0; 5410 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 5411 } 5412 } 5413 5414 static void hclge_update_fd_list(struct hclge_dev *hdev, 5415 enum HCLGE_FD_NODE_STATE state, u16 location, 5416 struct hclge_fd_rule *new_rule) 5417 { 5418 struct hlist_head *hlist = &hdev->fd_rule_list; 5419 struct hclge_fd_rule *fd_rule, *parent = NULL; 5420 5421 fd_rule = hclge_find_fd_rule(hlist, location, &parent); 5422 if (fd_rule) { 5423 hclge_fd_dec_user_def_refcnt(hdev, fd_rule); 5424 if (state == HCLGE_FD_ACTIVE) 5425 hclge_fd_inc_user_def_refcnt(hdev, new_rule); 5426 hclge_sync_fd_user_def_cfg(hdev, true); 5427 5428 hclge_update_fd_rule_node(hdev, fd_rule, new_rule, state); 5429 return; 5430 } 5431 5432 /* it's unlikely to fail here, because we have checked the rule 5433 * exist before. 5434 */ 5435 if (unlikely(state == HCLGE_FD_TO_DEL || state == HCLGE_FD_DELETED)) { 5436 dev_warn(&hdev->pdev->dev, 5437 "failed to delete fd rule %u, it's inexistent\n", 5438 location); 5439 return; 5440 } 5441 5442 hclge_fd_inc_user_def_refcnt(hdev, new_rule); 5443 hclge_sync_fd_user_def_cfg(hdev, true); 5444 5445 hclge_fd_insert_rule_node(hlist, new_rule, parent); 5446 hclge_fd_inc_rule_cnt(hdev, new_rule->location); 5447 5448 if (state == HCLGE_FD_TO_ADD) { 5449 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 5450 hclge_task_schedule(hdev, 0); 5451 } 5452 } 5453 5454 static int hclge_get_fd_mode(struct hclge_dev *hdev, u8 *fd_mode) 5455 { 5456 struct hclge_get_fd_mode_cmd *req; 5457 struct hclge_desc desc; 5458 int ret; 5459 5460 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_MODE_CTRL, true); 5461 5462 req = (struct hclge_get_fd_mode_cmd *)desc.data; 5463 5464 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5465 if (ret) { 5466 dev_err(&hdev->pdev->dev, "get fd mode fail, ret=%d\n", ret); 5467 return ret; 5468 } 5469 5470 *fd_mode = req->mode; 5471 5472 return ret; 5473 } 5474 5475 static int hclge_get_fd_allocation(struct hclge_dev *hdev, 5476 u32 *stage1_entry_num, 5477 u32 *stage2_entry_num, 5478 u16 *stage1_counter_num, 5479 u16 *stage2_counter_num) 5480 { 5481 struct hclge_get_fd_allocation_cmd *req; 5482 struct hclge_desc desc; 5483 int ret; 5484 5485 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_GET_ALLOCATION, true); 5486 5487 req = (struct hclge_get_fd_allocation_cmd *)desc.data; 5488 5489 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5490 if (ret) { 5491 dev_err(&hdev->pdev->dev, "query fd allocation fail, ret=%d\n", 5492 ret); 5493 return ret; 5494 } 5495 5496 *stage1_entry_num = le32_to_cpu(req->stage1_entry_num); 5497 *stage2_entry_num = le32_to_cpu(req->stage2_entry_num); 5498 *stage1_counter_num = le16_to_cpu(req->stage1_counter_num); 5499 *stage2_counter_num = le16_to_cpu(req->stage2_counter_num); 5500 5501 return ret; 5502 } 5503 5504 static int hclge_set_fd_key_config(struct hclge_dev *hdev, 5505 enum HCLGE_FD_STAGE stage_num) 5506 { 5507 struct hclge_set_fd_key_config_cmd *req; 5508 struct hclge_fd_key_cfg *stage; 5509 struct hclge_desc desc; 5510 int ret; 5511 5512 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_KEY_CONFIG, false); 5513 5514 req = (struct hclge_set_fd_key_config_cmd *)desc.data; 5515 stage = &hdev->fd_cfg.key_cfg[stage_num]; 5516 req->stage = stage_num; 5517 req->key_select = stage->key_sel; 5518 req->inner_sipv6_word_en = stage->inner_sipv6_word_en; 5519 req->inner_dipv6_word_en = stage->inner_dipv6_word_en; 5520 req->outer_sipv6_word_en = stage->outer_sipv6_word_en; 5521 req->outer_dipv6_word_en = stage->outer_dipv6_word_en; 5522 req->tuple_mask = cpu_to_le32(~stage->tuple_active); 5523 req->meta_data_mask = cpu_to_le32(~stage->meta_data_active); 5524 5525 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5526 if (ret) 5527 dev_err(&hdev->pdev->dev, "set fd key fail, ret=%d\n", ret); 5528 5529 return ret; 5530 } 5531 5532 static void hclge_fd_disable_user_def(struct hclge_dev *hdev) 5533 { 5534 struct hclge_fd_user_def_cfg *cfg = hdev->fd_cfg.user_def_cfg; 5535 5536 spin_lock_bh(&hdev->fd_rule_lock); 5537 memset(cfg, 0, sizeof(hdev->fd_cfg.user_def_cfg)); 5538 spin_unlock_bh(&hdev->fd_rule_lock); 5539 5540 hclge_fd_set_user_def_cmd(hdev, cfg); 5541 } 5542 5543 static int hclge_init_fd_config(struct hclge_dev *hdev) 5544 { 5545 #define LOW_2_WORDS 0x03 5546 struct hclge_fd_key_cfg *key_cfg; 5547 int ret; 5548 5549 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 5550 return 0; 5551 5552 ret = hclge_get_fd_mode(hdev, &hdev->fd_cfg.fd_mode); 5553 if (ret) 5554 return ret; 5555 5556 switch (hdev->fd_cfg.fd_mode) { 5557 case HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1: 5558 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH; 5559 break; 5560 case HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1: 5561 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH / 2; 5562 break; 5563 default: 5564 dev_err(&hdev->pdev->dev, 5565 "Unsupported flow director mode %u\n", 5566 hdev->fd_cfg.fd_mode); 5567 return -EOPNOTSUPP; 5568 } 5569 5570 key_cfg = &hdev->fd_cfg.key_cfg[HCLGE_FD_STAGE_1]; 5571 key_cfg->key_sel = HCLGE_FD_KEY_BASE_ON_TUPLE; 5572 key_cfg->inner_sipv6_word_en = LOW_2_WORDS; 5573 key_cfg->inner_dipv6_word_en = LOW_2_WORDS; 5574 key_cfg->outer_sipv6_word_en = 0; 5575 key_cfg->outer_dipv6_word_en = 0; 5576 5577 key_cfg->tuple_active = BIT(INNER_VLAN_TAG_FST) | BIT(INNER_ETH_TYPE) | 5578 BIT(INNER_IP_PROTO) | BIT(INNER_IP_TOS) | 5579 BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) | 5580 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT); 5581 5582 /* If use max 400bit key, we can support tuples for ether type */ 5583 if (hdev->fd_cfg.fd_mode == HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) { 5584 key_cfg->tuple_active |= 5585 BIT(INNER_DST_MAC) | BIT(INNER_SRC_MAC); 5586 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) 5587 key_cfg->tuple_active |= HCLGE_FD_TUPLE_USER_DEF_TUPLES; 5588 } 5589 5590 /* roce_type is used to filter roce frames 5591 * dst_vport is used to specify the rule 5592 */ 5593 key_cfg->meta_data_active = BIT(ROCE_TYPE) | BIT(DST_VPORT); 5594 5595 ret = hclge_get_fd_allocation(hdev, 5596 &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1], 5597 &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_2], 5598 &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1], 5599 &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_2]); 5600 if (ret) 5601 return ret; 5602 5603 return hclge_set_fd_key_config(hdev, HCLGE_FD_STAGE_1); 5604 } 5605 5606 static int hclge_fd_tcam_config(struct hclge_dev *hdev, u8 stage, bool sel_x, 5607 int loc, u8 *key, bool is_add) 5608 { 5609 struct hclge_fd_tcam_config_1_cmd *req1; 5610 struct hclge_fd_tcam_config_2_cmd *req2; 5611 struct hclge_fd_tcam_config_3_cmd *req3; 5612 struct hclge_desc desc[3]; 5613 int ret; 5614 5615 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_FD_TCAM_OP, false); 5616 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 5617 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_FD_TCAM_OP, false); 5618 desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 5619 hclge_cmd_setup_basic_desc(&desc[2], HCLGE_OPC_FD_TCAM_OP, false); 5620 5621 req1 = (struct hclge_fd_tcam_config_1_cmd *)desc[0].data; 5622 req2 = (struct hclge_fd_tcam_config_2_cmd *)desc[1].data; 5623 req3 = (struct hclge_fd_tcam_config_3_cmd *)desc[2].data; 5624 5625 req1->stage = stage; 5626 req1->xy_sel = sel_x ? 1 : 0; 5627 hnae3_set_bit(req1->port_info, HCLGE_FD_EPORT_SW_EN_B, 0); 5628 req1->index = cpu_to_le32(loc); 5629 req1->entry_vld = sel_x ? is_add : 0; 5630 5631 if (key) { 5632 memcpy(req1->tcam_data, &key[0], sizeof(req1->tcam_data)); 5633 memcpy(req2->tcam_data, &key[sizeof(req1->tcam_data)], 5634 sizeof(req2->tcam_data)); 5635 memcpy(req3->tcam_data, &key[sizeof(req1->tcam_data) + 5636 sizeof(req2->tcam_data)], sizeof(req3->tcam_data)); 5637 } 5638 5639 ret = hclge_cmd_send(&hdev->hw, desc, 3); 5640 if (ret) 5641 dev_err(&hdev->pdev->dev, 5642 "config tcam key fail, ret=%d\n", 5643 ret); 5644 5645 return ret; 5646 } 5647 5648 static int hclge_fd_ad_config(struct hclge_dev *hdev, u8 stage, int loc, 5649 struct hclge_fd_ad_data *action) 5650 { 5651 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 5652 struct hclge_fd_ad_config_cmd *req; 5653 struct hclge_desc desc; 5654 u64 ad_data = 0; 5655 int ret; 5656 5657 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_AD_OP, false); 5658 5659 req = (struct hclge_fd_ad_config_cmd *)desc.data; 5660 req->index = cpu_to_le32(loc); 5661 req->stage = stage; 5662 5663 hnae3_set_bit(ad_data, HCLGE_FD_AD_WR_RULE_ID_B, 5664 action->write_rule_id_to_bd); 5665 hnae3_set_field(ad_data, HCLGE_FD_AD_RULE_ID_M, HCLGE_FD_AD_RULE_ID_S, 5666 action->rule_id); 5667 if (test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, ae_dev->caps)) { 5668 hnae3_set_bit(ad_data, HCLGE_FD_AD_TC_OVRD_B, 5669 action->override_tc); 5670 hnae3_set_field(ad_data, HCLGE_FD_AD_TC_SIZE_M, 5671 HCLGE_FD_AD_TC_SIZE_S, (u32)action->tc_size); 5672 } 5673 ad_data <<= 32; 5674 hnae3_set_bit(ad_data, HCLGE_FD_AD_DROP_B, action->drop_packet); 5675 hnae3_set_bit(ad_data, HCLGE_FD_AD_DIRECT_QID_B, 5676 action->forward_to_direct_queue); 5677 hnae3_set_field(ad_data, HCLGE_FD_AD_QID_M, HCLGE_FD_AD_QID_S, 5678 action->queue_id); 5679 hnae3_set_bit(ad_data, HCLGE_FD_AD_USE_COUNTER_B, action->use_counter); 5680 hnae3_set_field(ad_data, HCLGE_FD_AD_COUNTER_NUM_M, 5681 HCLGE_FD_AD_COUNTER_NUM_S, action->counter_id); 5682 hnae3_set_bit(ad_data, HCLGE_FD_AD_NXT_STEP_B, action->use_next_stage); 5683 hnae3_set_field(ad_data, HCLGE_FD_AD_NXT_KEY_M, HCLGE_FD_AD_NXT_KEY_S, 5684 action->counter_id); 5685 5686 req->ad_data = cpu_to_le64(ad_data); 5687 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5688 if (ret) 5689 dev_err(&hdev->pdev->dev, "fd ad config fail, ret=%d\n", ret); 5690 5691 return ret; 5692 } 5693 5694 static bool hclge_fd_convert_tuple(u32 tuple_bit, u8 *key_x, u8 *key_y, 5695 struct hclge_fd_rule *rule) 5696 { 5697 int offset, moffset, ip_offset; 5698 enum HCLGE_FD_KEY_OPT key_opt; 5699 u16 tmp_x_s, tmp_y_s; 5700 u32 tmp_x_l, tmp_y_l; 5701 u8 *p = (u8 *)rule; 5702 int i; 5703 5704 if (rule->unused_tuple & BIT(tuple_bit)) 5705 return true; 5706 5707 key_opt = tuple_key_info[tuple_bit].key_opt; 5708 offset = tuple_key_info[tuple_bit].offset; 5709 moffset = tuple_key_info[tuple_bit].moffset; 5710 5711 switch (key_opt) { 5712 case KEY_OPT_U8: 5713 calc_x(*key_x, p[offset], p[moffset]); 5714 calc_y(*key_y, p[offset], p[moffset]); 5715 5716 return true; 5717 case KEY_OPT_LE16: 5718 calc_x(tmp_x_s, *(u16 *)(&p[offset]), *(u16 *)(&p[moffset])); 5719 calc_y(tmp_y_s, *(u16 *)(&p[offset]), *(u16 *)(&p[moffset])); 5720 *(__le16 *)key_x = cpu_to_le16(tmp_x_s); 5721 *(__le16 *)key_y = cpu_to_le16(tmp_y_s); 5722 5723 return true; 5724 case KEY_OPT_LE32: 5725 calc_x(tmp_x_l, *(u32 *)(&p[offset]), *(u32 *)(&p[moffset])); 5726 calc_y(tmp_y_l, *(u32 *)(&p[offset]), *(u32 *)(&p[moffset])); 5727 *(__le32 *)key_x = cpu_to_le32(tmp_x_l); 5728 *(__le32 *)key_y = cpu_to_le32(tmp_y_l); 5729 5730 return true; 5731 case KEY_OPT_MAC: 5732 for (i = 0; i < ETH_ALEN; i++) { 5733 calc_x(key_x[ETH_ALEN - 1 - i], p[offset + i], 5734 p[moffset + i]); 5735 calc_y(key_y[ETH_ALEN - 1 - i], p[offset + i], 5736 p[moffset + i]); 5737 } 5738 5739 return true; 5740 case KEY_OPT_IP: 5741 ip_offset = IPV4_INDEX * sizeof(u32); 5742 calc_x(tmp_x_l, *(u32 *)(&p[offset + ip_offset]), 5743 *(u32 *)(&p[moffset + ip_offset])); 5744 calc_y(tmp_y_l, *(u32 *)(&p[offset + ip_offset]), 5745 *(u32 *)(&p[moffset + ip_offset])); 5746 *(__le32 *)key_x = cpu_to_le32(tmp_x_l); 5747 *(__le32 *)key_y = cpu_to_le32(tmp_y_l); 5748 5749 return true; 5750 default: 5751 return false; 5752 } 5753 } 5754 5755 static u32 hclge_get_port_number(enum HLCGE_PORT_TYPE port_type, u8 pf_id, 5756 u8 vf_id, u8 network_port_id) 5757 { 5758 u32 port_number = 0; 5759 5760 if (port_type == HOST_PORT) { 5761 hnae3_set_field(port_number, HCLGE_PF_ID_M, HCLGE_PF_ID_S, 5762 pf_id); 5763 hnae3_set_field(port_number, HCLGE_VF_ID_M, HCLGE_VF_ID_S, 5764 vf_id); 5765 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, HOST_PORT); 5766 } else { 5767 hnae3_set_field(port_number, HCLGE_NETWORK_PORT_ID_M, 5768 HCLGE_NETWORK_PORT_ID_S, network_port_id); 5769 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, NETWORK_PORT); 5770 } 5771 5772 return port_number; 5773 } 5774 5775 static void hclge_fd_convert_meta_data(struct hclge_fd_key_cfg *key_cfg, 5776 __le32 *key_x, __le32 *key_y, 5777 struct hclge_fd_rule *rule) 5778 { 5779 u32 tuple_bit, meta_data = 0, tmp_x, tmp_y, port_number; 5780 u8 cur_pos = 0, tuple_size, shift_bits; 5781 unsigned int i; 5782 5783 for (i = 0; i < MAX_META_DATA; i++) { 5784 tuple_size = meta_data_key_info[i].key_length; 5785 tuple_bit = key_cfg->meta_data_active & BIT(i); 5786 5787 switch (tuple_bit) { 5788 case BIT(ROCE_TYPE): 5789 hnae3_set_bit(meta_data, cur_pos, NIC_PACKET); 5790 cur_pos += tuple_size; 5791 break; 5792 case BIT(DST_VPORT): 5793 port_number = hclge_get_port_number(HOST_PORT, 0, 5794 rule->vf_id, 0); 5795 hnae3_set_field(meta_data, 5796 GENMASK(cur_pos + tuple_size, cur_pos), 5797 cur_pos, port_number); 5798 cur_pos += tuple_size; 5799 break; 5800 default: 5801 break; 5802 } 5803 } 5804 5805 calc_x(tmp_x, meta_data, 0xFFFFFFFF); 5806 calc_y(tmp_y, meta_data, 0xFFFFFFFF); 5807 shift_bits = sizeof(meta_data) * 8 - cur_pos; 5808 5809 *key_x = cpu_to_le32(tmp_x << shift_bits); 5810 *key_y = cpu_to_le32(tmp_y << shift_bits); 5811 } 5812 5813 /* A complete key is combined with meta data key and tuple key. 5814 * Meta data key is stored at the MSB region, and tuple key is stored at 5815 * the LSB region, unused bits will be filled 0. 5816 */ 5817 static int hclge_config_key(struct hclge_dev *hdev, u8 stage, 5818 struct hclge_fd_rule *rule) 5819 { 5820 struct hclge_fd_key_cfg *key_cfg = &hdev->fd_cfg.key_cfg[stage]; 5821 u8 key_x[MAX_KEY_BYTES], key_y[MAX_KEY_BYTES]; 5822 u8 *cur_key_x, *cur_key_y; 5823 u8 meta_data_region; 5824 u8 tuple_size; 5825 int ret; 5826 u32 i; 5827 5828 memset(key_x, 0, sizeof(key_x)); 5829 memset(key_y, 0, sizeof(key_y)); 5830 cur_key_x = key_x; 5831 cur_key_y = key_y; 5832 5833 for (i = 0; i < MAX_TUPLE; i++) { 5834 bool tuple_valid; 5835 5836 tuple_size = tuple_key_info[i].key_length / 8; 5837 if (!(key_cfg->tuple_active & BIT(i))) 5838 continue; 5839 5840 tuple_valid = hclge_fd_convert_tuple(i, cur_key_x, 5841 cur_key_y, rule); 5842 if (tuple_valid) { 5843 cur_key_x += tuple_size; 5844 cur_key_y += tuple_size; 5845 } 5846 } 5847 5848 meta_data_region = hdev->fd_cfg.max_key_length / 8 - 5849 MAX_META_DATA_LENGTH / 8; 5850 5851 hclge_fd_convert_meta_data(key_cfg, 5852 (__le32 *)(key_x + meta_data_region), 5853 (__le32 *)(key_y + meta_data_region), 5854 rule); 5855 5856 ret = hclge_fd_tcam_config(hdev, stage, false, rule->location, key_y, 5857 true); 5858 if (ret) { 5859 dev_err(&hdev->pdev->dev, 5860 "fd key_y config fail, loc=%u, ret=%d\n", 5861 rule->queue_id, ret); 5862 return ret; 5863 } 5864 5865 ret = hclge_fd_tcam_config(hdev, stage, true, rule->location, key_x, 5866 true); 5867 if (ret) 5868 dev_err(&hdev->pdev->dev, 5869 "fd key_x config fail, loc=%u, ret=%d\n", 5870 rule->queue_id, ret); 5871 return ret; 5872 } 5873 5874 static int hclge_config_action(struct hclge_dev *hdev, u8 stage, 5875 struct hclge_fd_rule *rule) 5876 { 5877 struct hclge_vport *vport = hdev->vport; 5878 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 5879 struct hclge_fd_ad_data ad_data; 5880 5881 memset(&ad_data, 0, sizeof(struct hclge_fd_ad_data)); 5882 ad_data.ad_id = rule->location; 5883 5884 if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) { 5885 ad_data.drop_packet = true; 5886 } else if (rule->action == HCLGE_FD_ACTION_SELECT_TC) { 5887 ad_data.override_tc = true; 5888 ad_data.queue_id = 5889 kinfo->tc_info.tqp_offset[rule->cls_flower.tc]; 5890 ad_data.tc_size = 5891 ilog2(kinfo->tc_info.tqp_count[rule->cls_flower.tc]); 5892 } else { 5893 ad_data.forward_to_direct_queue = true; 5894 ad_data.queue_id = rule->queue_id; 5895 } 5896 5897 if (hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1]) { 5898 ad_data.use_counter = true; 5899 ad_data.counter_id = rule->vf_id % 5900 hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1]; 5901 } else { 5902 ad_data.use_counter = false; 5903 ad_data.counter_id = 0; 5904 } 5905 5906 ad_data.use_next_stage = false; 5907 ad_data.next_input_key = 0; 5908 5909 ad_data.write_rule_id_to_bd = true; 5910 ad_data.rule_id = rule->location; 5911 5912 return hclge_fd_ad_config(hdev, stage, ad_data.ad_id, &ad_data); 5913 } 5914 5915 static int hclge_fd_check_tcpip4_tuple(struct ethtool_tcpip4_spec *spec, 5916 u32 *unused_tuple) 5917 { 5918 if (!spec || !unused_tuple) 5919 return -EINVAL; 5920 5921 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC); 5922 5923 if (!spec->ip4src) 5924 *unused_tuple |= BIT(INNER_SRC_IP); 5925 5926 if (!spec->ip4dst) 5927 *unused_tuple |= BIT(INNER_DST_IP); 5928 5929 if (!spec->psrc) 5930 *unused_tuple |= BIT(INNER_SRC_PORT); 5931 5932 if (!spec->pdst) 5933 *unused_tuple |= BIT(INNER_DST_PORT); 5934 5935 if (!spec->tos) 5936 *unused_tuple |= BIT(INNER_IP_TOS); 5937 5938 return 0; 5939 } 5940 5941 static int hclge_fd_check_ip4_tuple(struct ethtool_usrip4_spec *spec, 5942 u32 *unused_tuple) 5943 { 5944 if (!spec || !unused_tuple) 5945 return -EINVAL; 5946 5947 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) | 5948 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT); 5949 5950 if (!spec->ip4src) 5951 *unused_tuple |= BIT(INNER_SRC_IP); 5952 5953 if (!spec->ip4dst) 5954 *unused_tuple |= BIT(INNER_DST_IP); 5955 5956 if (!spec->tos) 5957 *unused_tuple |= BIT(INNER_IP_TOS); 5958 5959 if (!spec->proto) 5960 *unused_tuple |= BIT(INNER_IP_PROTO); 5961 5962 if (spec->l4_4_bytes) 5963 return -EOPNOTSUPP; 5964 5965 if (spec->ip_ver != ETH_RX_NFC_IP4) 5966 return -EOPNOTSUPP; 5967 5968 return 0; 5969 } 5970 5971 static int hclge_fd_check_tcpip6_tuple(struct ethtool_tcpip6_spec *spec, 5972 u32 *unused_tuple) 5973 { 5974 if (!spec || !unused_tuple) 5975 return -EINVAL; 5976 5977 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC); 5978 5979 /* check whether src/dst ip address used */ 5980 if (ipv6_addr_any((struct in6_addr *)spec->ip6src)) 5981 *unused_tuple |= BIT(INNER_SRC_IP); 5982 5983 if (ipv6_addr_any((struct in6_addr *)spec->ip6dst)) 5984 *unused_tuple |= BIT(INNER_DST_IP); 5985 5986 if (!spec->psrc) 5987 *unused_tuple |= BIT(INNER_SRC_PORT); 5988 5989 if (!spec->pdst) 5990 *unused_tuple |= BIT(INNER_DST_PORT); 5991 5992 if (!spec->tclass) 5993 *unused_tuple |= BIT(INNER_IP_TOS); 5994 5995 return 0; 5996 } 5997 5998 static int hclge_fd_check_ip6_tuple(struct ethtool_usrip6_spec *spec, 5999 u32 *unused_tuple) 6000 { 6001 if (!spec || !unused_tuple) 6002 return -EINVAL; 6003 6004 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) | 6005 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT); 6006 6007 /* check whether src/dst ip address used */ 6008 if (ipv6_addr_any((struct in6_addr *)spec->ip6src)) 6009 *unused_tuple |= BIT(INNER_SRC_IP); 6010 6011 if (ipv6_addr_any((struct in6_addr *)spec->ip6dst)) 6012 *unused_tuple |= BIT(INNER_DST_IP); 6013 6014 if (!spec->l4_proto) 6015 *unused_tuple |= BIT(INNER_IP_PROTO); 6016 6017 if (!spec->tclass) 6018 *unused_tuple |= BIT(INNER_IP_TOS); 6019 6020 if (spec->l4_4_bytes) 6021 return -EOPNOTSUPP; 6022 6023 return 0; 6024 } 6025 6026 static int hclge_fd_check_ether_tuple(struct ethhdr *spec, u32 *unused_tuple) 6027 { 6028 if (!spec || !unused_tuple) 6029 return -EINVAL; 6030 6031 *unused_tuple |= BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) | 6032 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT) | 6033 BIT(INNER_IP_TOS) | BIT(INNER_IP_PROTO); 6034 6035 if (is_zero_ether_addr(spec->h_source)) 6036 *unused_tuple |= BIT(INNER_SRC_MAC); 6037 6038 if (is_zero_ether_addr(spec->h_dest)) 6039 *unused_tuple |= BIT(INNER_DST_MAC); 6040 6041 if (!spec->h_proto) 6042 *unused_tuple |= BIT(INNER_ETH_TYPE); 6043 6044 return 0; 6045 } 6046 6047 static int hclge_fd_check_ext_tuple(struct hclge_dev *hdev, 6048 struct ethtool_rx_flow_spec *fs, 6049 u32 *unused_tuple) 6050 { 6051 if (fs->flow_type & FLOW_EXT) { 6052 if (fs->h_ext.vlan_etype) { 6053 dev_err(&hdev->pdev->dev, "vlan-etype is not supported!\n"); 6054 return -EOPNOTSUPP; 6055 } 6056 6057 if (!fs->h_ext.vlan_tci) 6058 *unused_tuple |= BIT(INNER_VLAN_TAG_FST); 6059 6060 if (fs->m_ext.vlan_tci && 6061 be16_to_cpu(fs->h_ext.vlan_tci) >= VLAN_N_VID) { 6062 dev_err(&hdev->pdev->dev, 6063 "failed to config vlan_tci, invalid vlan_tci: %u, max is %d.\n", 6064 ntohs(fs->h_ext.vlan_tci), VLAN_N_VID - 1); 6065 return -EINVAL; 6066 } 6067 } else { 6068 *unused_tuple |= BIT(INNER_VLAN_TAG_FST); 6069 } 6070 6071 if (fs->flow_type & FLOW_MAC_EXT) { 6072 if (hdev->fd_cfg.fd_mode != 6073 HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) { 6074 dev_err(&hdev->pdev->dev, 6075 "FLOW_MAC_EXT is not supported in current fd mode!\n"); 6076 return -EOPNOTSUPP; 6077 } 6078 6079 if (is_zero_ether_addr(fs->h_ext.h_dest)) 6080 *unused_tuple |= BIT(INNER_DST_MAC); 6081 else 6082 *unused_tuple &= ~BIT(INNER_DST_MAC); 6083 } 6084 6085 return 0; 6086 } 6087 6088 static int hclge_fd_get_user_def_layer(u32 flow_type, u32 *unused_tuple, 6089 struct hclge_fd_user_def_info *info) 6090 { 6091 switch (flow_type) { 6092 case ETHER_FLOW: 6093 info->layer = HCLGE_FD_USER_DEF_L2; 6094 *unused_tuple &= ~BIT(INNER_L2_RSV); 6095 break; 6096 case IP_USER_FLOW: 6097 case IPV6_USER_FLOW: 6098 info->layer = HCLGE_FD_USER_DEF_L3; 6099 *unused_tuple &= ~BIT(INNER_L3_RSV); 6100 break; 6101 case TCP_V4_FLOW: 6102 case UDP_V4_FLOW: 6103 case TCP_V6_FLOW: 6104 case UDP_V6_FLOW: 6105 info->layer = HCLGE_FD_USER_DEF_L4; 6106 *unused_tuple &= ~BIT(INNER_L4_RSV); 6107 break; 6108 default: 6109 return -EOPNOTSUPP; 6110 } 6111 6112 return 0; 6113 } 6114 6115 static bool hclge_fd_is_user_def_all_masked(struct ethtool_rx_flow_spec *fs) 6116 { 6117 return be32_to_cpu(fs->m_ext.data[1] | fs->m_ext.data[0]) == 0; 6118 } 6119 6120 static int hclge_fd_parse_user_def_field(struct hclge_dev *hdev, 6121 struct ethtool_rx_flow_spec *fs, 6122 u32 *unused_tuple, 6123 struct hclge_fd_user_def_info *info) 6124 { 6125 u32 tuple_active = hdev->fd_cfg.key_cfg[HCLGE_FD_STAGE_1].tuple_active; 6126 u32 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT); 6127 u16 data, offset, data_mask, offset_mask; 6128 int ret; 6129 6130 info->layer = HCLGE_FD_USER_DEF_NONE; 6131 *unused_tuple |= HCLGE_FD_TUPLE_USER_DEF_TUPLES; 6132 6133 if (!(fs->flow_type & FLOW_EXT) || hclge_fd_is_user_def_all_masked(fs)) 6134 return 0; 6135 6136 /* user-def data from ethtool is 64 bit value, the bit0~15 is used 6137 * for data, and bit32~47 is used for offset. 6138 */ 6139 data = be32_to_cpu(fs->h_ext.data[1]) & HCLGE_FD_USER_DEF_DATA; 6140 data_mask = be32_to_cpu(fs->m_ext.data[1]) & HCLGE_FD_USER_DEF_DATA; 6141 offset = be32_to_cpu(fs->h_ext.data[0]) & HCLGE_FD_USER_DEF_OFFSET; 6142 offset_mask = be32_to_cpu(fs->m_ext.data[0]) & HCLGE_FD_USER_DEF_OFFSET; 6143 6144 if (!(tuple_active & HCLGE_FD_TUPLE_USER_DEF_TUPLES)) { 6145 dev_err(&hdev->pdev->dev, "user-def bytes are not supported\n"); 6146 return -EOPNOTSUPP; 6147 } 6148 6149 if (offset > HCLGE_FD_MAX_USER_DEF_OFFSET) { 6150 dev_err(&hdev->pdev->dev, 6151 "user-def offset[%u] should be no more than %u\n", 6152 offset, HCLGE_FD_MAX_USER_DEF_OFFSET); 6153 return -EINVAL; 6154 } 6155 6156 if (offset_mask != HCLGE_FD_USER_DEF_OFFSET_UNMASK) { 6157 dev_err(&hdev->pdev->dev, "user-def offset can't be masked\n"); 6158 return -EINVAL; 6159 } 6160 6161 ret = hclge_fd_get_user_def_layer(flow_type, unused_tuple, info); 6162 if (ret) { 6163 dev_err(&hdev->pdev->dev, 6164 "unsupported flow type for user-def bytes, ret = %d\n", 6165 ret); 6166 return ret; 6167 } 6168 6169 info->data = data; 6170 info->data_mask = data_mask; 6171 info->offset = offset; 6172 6173 return 0; 6174 } 6175 6176 static int hclge_fd_check_spec(struct hclge_dev *hdev, 6177 struct ethtool_rx_flow_spec *fs, 6178 u32 *unused_tuple, 6179 struct hclge_fd_user_def_info *info) 6180 { 6181 u32 flow_type; 6182 int ret; 6183 6184 if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) { 6185 dev_err(&hdev->pdev->dev, 6186 "failed to config fd rules, invalid rule location: %u, max is %u\n.", 6187 fs->location, 6188 hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1] - 1); 6189 return -EINVAL; 6190 } 6191 6192 ret = hclge_fd_parse_user_def_field(hdev, fs, unused_tuple, info); 6193 if (ret) 6194 return ret; 6195 6196 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT); 6197 switch (flow_type) { 6198 case SCTP_V4_FLOW: 6199 case TCP_V4_FLOW: 6200 case UDP_V4_FLOW: 6201 ret = hclge_fd_check_tcpip4_tuple(&fs->h_u.tcp_ip4_spec, 6202 unused_tuple); 6203 break; 6204 case IP_USER_FLOW: 6205 ret = hclge_fd_check_ip4_tuple(&fs->h_u.usr_ip4_spec, 6206 unused_tuple); 6207 break; 6208 case SCTP_V6_FLOW: 6209 case TCP_V6_FLOW: 6210 case UDP_V6_FLOW: 6211 ret = hclge_fd_check_tcpip6_tuple(&fs->h_u.tcp_ip6_spec, 6212 unused_tuple); 6213 break; 6214 case IPV6_USER_FLOW: 6215 ret = hclge_fd_check_ip6_tuple(&fs->h_u.usr_ip6_spec, 6216 unused_tuple); 6217 break; 6218 case ETHER_FLOW: 6219 if (hdev->fd_cfg.fd_mode != 6220 HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) { 6221 dev_err(&hdev->pdev->dev, 6222 "ETHER_FLOW is not supported in current fd mode!\n"); 6223 return -EOPNOTSUPP; 6224 } 6225 6226 ret = hclge_fd_check_ether_tuple(&fs->h_u.ether_spec, 6227 unused_tuple); 6228 break; 6229 default: 6230 dev_err(&hdev->pdev->dev, 6231 "unsupported protocol type, protocol type = %#x\n", 6232 flow_type); 6233 return -EOPNOTSUPP; 6234 } 6235 6236 if (ret) { 6237 dev_err(&hdev->pdev->dev, 6238 "failed to check flow union tuple, ret = %d\n", 6239 ret); 6240 return ret; 6241 } 6242 6243 return hclge_fd_check_ext_tuple(hdev, fs, unused_tuple); 6244 } 6245 6246 static void hclge_fd_get_tcpip4_tuple(struct hclge_dev *hdev, 6247 struct ethtool_rx_flow_spec *fs, 6248 struct hclge_fd_rule *rule, u8 ip_proto) 6249 { 6250 rule->tuples.src_ip[IPV4_INDEX] = 6251 be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4src); 6252 rule->tuples_mask.src_ip[IPV4_INDEX] = 6253 be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4src); 6254 6255 rule->tuples.dst_ip[IPV4_INDEX] = 6256 be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4dst); 6257 rule->tuples_mask.dst_ip[IPV4_INDEX] = 6258 be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4dst); 6259 6260 rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.psrc); 6261 rule->tuples_mask.src_port = be16_to_cpu(fs->m_u.tcp_ip4_spec.psrc); 6262 6263 rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.pdst); 6264 rule->tuples_mask.dst_port = be16_to_cpu(fs->m_u.tcp_ip4_spec.pdst); 6265 6266 rule->tuples.ip_tos = fs->h_u.tcp_ip4_spec.tos; 6267 rule->tuples_mask.ip_tos = fs->m_u.tcp_ip4_spec.tos; 6268 6269 rule->tuples.ether_proto = ETH_P_IP; 6270 rule->tuples_mask.ether_proto = 0xFFFF; 6271 6272 rule->tuples.ip_proto = ip_proto; 6273 rule->tuples_mask.ip_proto = 0xFF; 6274 } 6275 6276 static void hclge_fd_get_ip4_tuple(struct hclge_dev *hdev, 6277 struct ethtool_rx_flow_spec *fs, 6278 struct hclge_fd_rule *rule) 6279 { 6280 rule->tuples.src_ip[IPV4_INDEX] = 6281 be32_to_cpu(fs->h_u.usr_ip4_spec.ip4src); 6282 rule->tuples_mask.src_ip[IPV4_INDEX] = 6283 be32_to_cpu(fs->m_u.usr_ip4_spec.ip4src); 6284 6285 rule->tuples.dst_ip[IPV4_INDEX] = 6286 be32_to_cpu(fs->h_u.usr_ip4_spec.ip4dst); 6287 rule->tuples_mask.dst_ip[IPV4_INDEX] = 6288 be32_to_cpu(fs->m_u.usr_ip4_spec.ip4dst); 6289 6290 rule->tuples.ip_tos = fs->h_u.usr_ip4_spec.tos; 6291 rule->tuples_mask.ip_tos = fs->m_u.usr_ip4_spec.tos; 6292 6293 rule->tuples.ip_proto = fs->h_u.usr_ip4_spec.proto; 6294 rule->tuples_mask.ip_proto = fs->m_u.usr_ip4_spec.proto; 6295 6296 rule->tuples.ether_proto = ETH_P_IP; 6297 rule->tuples_mask.ether_proto = 0xFFFF; 6298 } 6299 6300 static void hclge_fd_get_tcpip6_tuple(struct hclge_dev *hdev, 6301 struct ethtool_rx_flow_spec *fs, 6302 struct hclge_fd_rule *rule, u8 ip_proto) 6303 { 6304 be32_to_cpu_array(rule->tuples.src_ip, fs->h_u.tcp_ip6_spec.ip6src, 6305 IPV6_SIZE); 6306 be32_to_cpu_array(rule->tuples_mask.src_ip, fs->m_u.tcp_ip6_spec.ip6src, 6307 IPV6_SIZE); 6308 6309 be32_to_cpu_array(rule->tuples.dst_ip, fs->h_u.tcp_ip6_spec.ip6dst, 6310 IPV6_SIZE); 6311 be32_to_cpu_array(rule->tuples_mask.dst_ip, fs->m_u.tcp_ip6_spec.ip6dst, 6312 IPV6_SIZE); 6313 6314 rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.psrc); 6315 rule->tuples_mask.src_port = be16_to_cpu(fs->m_u.tcp_ip6_spec.psrc); 6316 6317 rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.pdst); 6318 rule->tuples_mask.dst_port = be16_to_cpu(fs->m_u.tcp_ip6_spec.pdst); 6319 6320 rule->tuples.ether_proto = ETH_P_IPV6; 6321 rule->tuples_mask.ether_proto = 0xFFFF; 6322 6323 rule->tuples.ip_tos = fs->h_u.tcp_ip6_spec.tclass; 6324 rule->tuples_mask.ip_tos = fs->m_u.tcp_ip6_spec.tclass; 6325 6326 rule->tuples.ip_proto = ip_proto; 6327 rule->tuples_mask.ip_proto = 0xFF; 6328 } 6329 6330 static void hclge_fd_get_ip6_tuple(struct hclge_dev *hdev, 6331 struct ethtool_rx_flow_spec *fs, 6332 struct hclge_fd_rule *rule) 6333 { 6334 be32_to_cpu_array(rule->tuples.src_ip, fs->h_u.usr_ip6_spec.ip6src, 6335 IPV6_SIZE); 6336 be32_to_cpu_array(rule->tuples_mask.src_ip, fs->m_u.usr_ip6_spec.ip6src, 6337 IPV6_SIZE); 6338 6339 be32_to_cpu_array(rule->tuples.dst_ip, fs->h_u.usr_ip6_spec.ip6dst, 6340 IPV6_SIZE); 6341 be32_to_cpu_array(rule->tuples_mask.dst_ip, fs->m_u.usr_ip6_spec.ip6dst, 6342 IPV6_SIZE); 6343 6344 rule->tuples.ip_proto = fs->h_u.usr_ip6_spec.l4_proto; 6345 rule->tuples_mask.ip_proto = fs->m_u.usr_ip6_spec.l4_proto; 6346 6347 rule->tuples.ip_tos = fs->h_u.tcp_ip6_spec.tclass; 6348 rule->tuples_mask.ip_tos = fs->m_u.tcp_ip6_spec.tclass; 6349 6350 rule->tuples.ether_proto = ETH_P_IPV6; 6351 rule->tuples_mask.ether_proto = 0xFFFF; 6352 } 6353 6354 static void hclge_fd_get_ether_tuple(struct hclge_dev *hdev, 6355 struct ethtool_rx_flow_spec *fs, 6356 struct hclge_fd_rule *rule) 6357 { 6358 ether_addr_copy(rule->tuples.src_mac, fs->h_u.ether_spec.h_source); 6359 ether_addr_copy(rule->tuples_mask.src_mac, fs->m_u.ether_spec.h_source); 6360 6361 ether_addr_copy(rule->tuples.dst_mac, fs->h_u.ether_spec.h_dest); 6362 ether_addr_copy(rule->tuples_mask.dst_mac, fs->m_u.ether_spec.h_dest); 6363 6364 rule->tuples.ether_proto = be16_to_cpu(fs->h_u.ether_spec.h_proto); 6365 rule->tuples_mask.ether_proto = be16_to_cpu(fs->m_u.ether_spec.h_proto); 6366 } 6367 6368 static void hclge_fd_get_user_def_tuple(struct hclge_fd_user_def_info *info, 6369 struct hclge_fd_rule *rule) 6370 { 6371 switch (info->layer) { 6372 case HCLGE_FD_USER_DEF_L2: 6373 rule->tuples.l2_user_def = info->data; 6374 rule->tuples_mask.l2_user_def = info->data_mask; 6375 break; 6376 case HCLGE_FD_USER_DEF_L3: 6377 rule->tuples.l3_user_def = info->data; 6378 rule->tuples_mask.l3_user_def = info->data_mask; 6379 break; 6380 case HCLGE_FD_USER_DEF_L4: 6381 rule->tuples.l4_user_def = (u32)info->data << 16; 6382 rule->tuples_mask.l4_user_def = (u32)info->data_mask << 16; 6383 break; 6384 default: 6385 break; 6386 } 6387 6388 rule->ep.user_def = *info; 6389 } 6390 6391 static int hclge_fd_get_tuple(struct hclge_dev *hdev, 6392 struct ethtool_rx_flow_spec *fs, 6393 struct hclge_fd_rule *rule, 6394 struct hclge_fd_user_def_info *info) 6395 { 6396 u32 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT); 6397 6398 switch (flow_type) { 6399 case SCTP_V4_FLOW: 6400 hclge_fd_get_tcpip4_tuple(hdev, fs, rule, IPPROTO_SCTP); 6401 break; 6402 case TCP_V4_FLOW: 6403 hclge_fd_get_tcpip4_tuple(hdev, fs, rule, IPPROTO_TCP); 6404 break; 6405 case UDP_V4_FLOW: 6406 hclge_fd_get_tcpip4_tuple(hdev, fs, rule, IPPROTO_UDP); 6407 break; 6408 case IP_USER_FLOW: 6409 hclge_fd_get_ip4_tuple(hdev, fs, rule); 6410 break; 6411 case SCTP_V6_FLOW: 6412 hclge_fd_get_tcpip6_tuple(hdev, fs, rule, IPPROTO_SCTP); 6413 break; 6414 case TCP_V6_FLOW: 6415 hclge_fd_get_tcpip6_tuple(hdev, fs, rule, IPPROTO_TCP); 6416 break; 6417 case UDP_V6_FLOW: 6418 hclge_fd_get_tcpip6_tuple(hdev, fs, rule, IPPROTO_UDP); 6419 break; 6420 case IPV6_USER_FLOW: 6421 hclge_fd_get_ip6_tuple(hdev, fs, rule); 6422 break; 6423 case ETHER_FLOW: 6424 hclge_fd_get_ether_tuple(hdev, fs, rule); 6425 break; 6426 default: 6427 return -EOPNOTSUPP; 6428 } 6429 6430 if (fs->flow_type & FLOW_EXT) { 6431 rule->tuples.vlan_tag1 = be16_to_cpu(fs->h_ext.vlan_tci); 6432 rule->tuples_mask.vlan_tag1 = be16_to_cpu(fs->m_ext.vlan_tci); 6433 hclge_fd_get_user_def_tuple(info, rule); 6434 } 6435 6436 if (fs->flow_type & FLOW_MAC_EXT) { 6437 ether_addr_copy(rule->tuples.dst_mac, fs->h_ext.h_dest); 6438 ether_addr_copy(rule->tuples_mask.dst_mac, fs->m_ext.h_dest); 6439 } 6440 6441 return 0; 6442 } 6443 6444 static int hclge_fd_config_rule(struct hclge_dev *hdev, 6445 struct hclge_fd_rule *rule) 6446 { 6447 int ret; 6448 6449 ret = hclge_config_action(hdev, HCLGE_FD_STAGE_1, rule); 6450 if (ret) 6451 return ret; 6452 6453 return hclge_config_key(hdev, HCLGE_FD_STAGE_1, rule); 6454 } 6455 6456 static int hclge_add_fd_entry_common(struct hclge_dev *hdev, 6457 struct hclge_fd_rule *rule) 6458 { 6459 int ret; 6460 6461 spin_lock_bh(&hdev->fd_rule_lock); 6462 6463 if (hdev->fd_active_type != rule->rule_type && 6464 (hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE || 6465 hdev->fd_active_type == HCLGE_FD_EP_ACTIVE)) { 6466 dev_err(&hdev->pdev->dev, 6467 "mode conflict(new type %d, active type %d), please delete existent rules first\n", 6468 rule->rule_type, hdev->fd_active_type); 6469 spin_unlock_bh(&hdev->fd_rule_lock); 6470 return -EINVAL; 6471 } 6472 6473 ret = hclge_fd_check_user_def_refcnt(hdev, rule); 6474 if (ret) 6475 goto out; 6476 6477 ret = hclge_clear_arfs_rules(hdev); 6478 if (ret) 6479 goto out; 6480 6481 ret = hclge_fd_config_rule(hdev, rule); 6482 if (ret) 6483 goto out; 6484 6485 rule->state = HCLGE_FD_ACTIVE; 6486 hdev->fd_active_type = rule->rule_type; 6487 hclge_update_fd_list(hdev, rule->state, rule->location, rule); 6488 6489 out: 6490 spin_unlock_bh(&hdev->fd_rule_lock); 6491 return ret; 6492 } 6493 6494 static bool hclge_is_cls_flower_active(struct hnae3_handle *handle) 6495 { 6496 struct hclge_vport *vport = hclge_get_vport(handle); 6497 struct hclge_dev *hdev = vport->back; 6498 6499 return hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE; 6500 } 6501 6502 static int hclge_fd_parse_ring_cookie(struct hclge_dev *hdev, u64 ring_cookie, 6503 u16 *vport_id, u8 *action, u16 *queue_id) 6504 { 6505 struct hclge_vport *vport = hdev->vport; 6506 6507 if (ring_cookie == RX_CLS_FLOW_DISC) { 6508 *action = HCLGE_FD_ACTION_DROP_PACKET; 6509 } else { 6510 u32 ring = ethtool_get_flow_spec_ring(ring_cookie); 6511 u8 vf = ethtool_get_flow_spec_ring_vf(ring_cookie); 6512 u16 tqps; 6513 6514 /* To keep consistent with user's configuration, minus 1 when 6515 * printing 'vf', because vf id from ethtool is added 1 for vf. 6516 */ 6517 if (vf > hdev->num_req_vfs) { 6518 dev_err(&hdev->pdev->dev, 6519 "Error: vf id (%u) should be less than %u\n", 6520 vf - 1U, hdev->num_req_vfs); 6521 return -EINVAL; 6522 } 6523 6524 *vport_id = vf ? hdev->vport[vf].vport_id : vport->vport_id; 6525 tqps = hdev->vport[vf].nic.kinfo.num_tqps; 6526 6527 if (ring >= tqps) { 6528 dev_err(&hdev->pdev->dev, 6529 "Error: queue id (%u) > max tqp num (%u)\n", 6530 ring, tqps - 1U); 6531 return -EINVAL; 6532 } 6533 6534 *action = HCLGE_FD_ACTION_SELECT_QUEUE; 6535 *queue_id = ring; 6536 } 6537 6538 return 0; 6539 } 6540 6541 static int hclge_add_fd_entry(struct hnae3_handle *handle, 6542 struct ethtool_rxnfc *cmd) 6543 { 6544 struct hclge_vport *vport = hclge_get_vport(handle); 6545 struct hclge_dev *hdev = vport->back; 6546 struct hclge_fd_user_def_info info; 6547 u16 dst_vport_id = 0, q_index = 0; 6548 struct ethtool_rx_flow_spec *fs; 6549 struct hclge_fd_rule *rule; 6550 u32 unused = 0; 6551 u8 action; 6552 int ret; 6553 6554 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) { 6555 dev_err(&hdev->pdev->dev, 6556 "flow table director is not supported\n"); 6557 return -EOPNOTSUPP; 6558 } 6559 6560 if (!hdev->fd_en) { 6561 dev_err(&hdev->pdev->dev, 6562 "please enable flow director first\n"); 6563 return -EOPNOTSUPP; 6564 } 6565 6566 fs = (struct ethtool_rx_flow_spec *)&cmd->fs; 6567 6568 ret = hclge_fd_check_spec(hdev, fs, &unused, &info); 6569 if (ret) 6570 return ret; 6571 6572 ret = hclge_fd_parse_ring_cookie(hdev, fs->ring_cookie, &dst_vport_id, 6573 &action, &q_index); 6574 if (ret) 6575 return ret; 6576 6577 rule = kzalloc(sizeof(*rule), GFP_KERNEL); 6578 if (!rule) 6579 return -ENOMEM; 6580 6581 ret = hclge_fd_get_tuple(hdev, fs, rule, &info); 6582 if (ret) { 6583 kfree(rule); 6584 return ret; 6585 } 6586 6587 rule->flow_type = fs->flow_type; 6588 rule->location = fs->location; 6589 rule->unused_tuple = unused; 6590 rule->vf_id = dst_vport_id; 6591 rule->queue_id = q_index; 6592 rule->action = action; 6593 rule->rule_type = HCLGE_FD_EP_ACTIVE; 6594 6595 ret = hclge_add_fd_entry_common(hdev, rule); 6596 if (ret) 6597 kfree(rule); 6598 6599 return ret; 6600 } 6601 6602 static int hclge_del_fd_entry(struct hnae3_handle *handle, 6603 struct ethtool_rxnfc *cmd) 6604 { 6605 struct hclge_vport *vport = hclge_get_vport(handle); 6606 struct hclge_dev *hdev = vport->back; 6607 struct ethtool_rx_flow_spec *fs; 6608 int ret; 6609 6610 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6611 return -EOPNOTSUPP; 6612 6613 fs = (struct ethtool_rx_flow_spec *)&cmd->fs; 6614 6615 if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) 6616 return -EINVAL; 6617 6618 spin_lock_bh(&hdev->fd_rule_lock); 6619 if (hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE || 6620 !test_bit(fs->location, hdev->fd_bmap)) { 6621 dev_err(&hdev->pdev->dev, 6622 "Delete fail, rule %u is inexistent\n", fs->location); 6623 spin_unlock_bh(&hdev->fd_rule_lock); 6624 return -ENOENT; 6625 } 6626 6627 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, fs->location, 6628 NULL, false); 6629 if (ret) 6630 goto out; 6631 6632 hclge_update_fd_list(hdev, HCLGE_FD_DELETED, fs->location, NULL); 6633 6634 out: 6635 spin_unlock_bh(&hdev->fd_rule_lock); 6636 return ret; 6637 } 6638 6639 static void hclge_clear_fd_rules_in_list(struct hclge_dev *hdev, 6640 bool clear_list) 6641 { 6642 struct hclge_fd_rule *rule; 6643 struct hlist_node *node; 6644 u16 location; 6645 6646 spin_lock_bh(&hdev->fd_rule_lock); 6647 6648 for_each_set_bit(location, hdev->fd_bmap, 6649 hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) 6650 hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, location, 6651 NULL, false); 6652 6653 if (clear_list) { 6654 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, 6655 rule_node) { 6656 hlist_del(&rule->rule_node); 6657 kfree(rule); 6658 } 6659 hdev->fd_active_type = HCLGE_FD_RULE_NONE; 6660 hdev->hclge_fd_rule_num = 0; 6661 bitmap_zero(hdev->fd_bmap, 6662 hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]); 6663 } 6664 6665 spin_unlock_bh(&hdev->fd_rule_lock); 6666 } 6667 6668 static void hclge_del_all_fd_entries(struct hclge_dev *hdev) 6669 { 6670 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6671 return; 6672 6673 hclge_clear_fd_rules_in_list(hdev, true); 6674 hclge_fd_disable_user_def(hdev); 6675 } 6676 6677 static int hclge_restore_fd_entries(struct hnae3_handle *handle) 6678 { 6679 struct hclge_vport *vport = hclge_get_vport(handle); 6680 struct hclge_dev *hdev = vport->back; 6681 struct hclge_fd_rule *rule; 6682 struct hlist_node *node; 6683 6684 /* Return ok here, because reset error handling will check this 6685 * return value. If error is returned here, the reset process will 6686 * fail. 6687 */ 6688 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6689 return 0; 6690 6691 /* if fd is disabled, should not restore it when reset */ 6692 if (!hdev->fd_en) 6693 return 0; 6694 6695 spin_lock_bh(&hdev->fd_rule_lock); 6696 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 6697 if (rule->state == HCLGE_FD_ACTIVE) 6698 rule->state = HCLGE_FD_TO_ADD; 6699 } 6700 spin_unlock_bh(&hdev->fd_rule_lock); 6701 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 6702 6703 return 0; 6704 } 6705 6706 static int hclge_get_fd_rule_cnt(struct hnae3_handle *handle, 6707 struct ethtool_rxnfc *cmd) 6708 { 6709 struct hclge_vport *vport = hclge_get_vport(handle); 6710 struct hclge_dev *hdev = vport->back; 6711 6712 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev) || hclge_is_cls_flower_active(handle)) 6713 return -EOPNOTSUPP; 6714 6715 cmd->rule_cnt = hdev->hclge_fd_rule_num; 6716 cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]; 6717 6718 return 0; 6719 } 6720 6721 static void hclge_fd_get_tcpip4_info(struct hclge_fd_rule *rule, 6722 struct ethtool_tcpip4_spec *spec, 6723 struct ethtool_tcpip4_spec *spec_mask) 6724 { 6725 spec->ip4src = cpu_to_be32(rule->tuples.src_ip[IPV4_INDEX]); 6726 spec_mask->ip4src = rule->unused_tuple & BIT(INNER_SRC_IP) ? 6727 0 : cpu_to_be32(rule->tuples_mask.src_ip[IPV4_INDEX]); 6728 6729 spec->ip4dst = cpu_to_be32(rule->tuples.dst_ip[IPV4_INDEX]); 6730 spec_mask->ip4dst = rule->unused_tuple & BIT(INNER_DST_IP) ? 6731 0 : cpu_to_be32(rule->tuples_mask.dst_ip[IPV4_INDEX]); 6732 6733 spec->psrc = cpu_to_be16(rule->tuples.src_port); 6734 spec_mask->psrc = rule->unused_tuple & BIT(INNER_SRC_PORT) ? 6735 0 : cpu_to_be16(rule->tuples_mask.src_port); 6736 6737 spec->pdst = cpu_to_be16(rule->tuples.dst_port); 6738 spec_mask->pdst = rule->unused_tuple & BIT(INNER_DST_PORT) ? 6739 0 : cpu_to_be16(rule->tuples_mask.dst_port); 6740 6741 spec->tos = rule->tuples.ip_tos; 6742 spec_mask->tos = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6743 0 : rule->tuples_mask.ip_tos; 6744 } 6745 6746 static void hclge_fd_get_ip4_info(struct hclge_fd_rule *rule, 6747 struct ethtool_usrip4_spec *spec, 6748 struct ethtool_usrip4_spec *spec_mask) 6749 { 6750 spec->ip4src = cpu_to_be32(rule->tuples.src_ip[IPV4_INDEX]); 6751 spec_mask->ip4src = rule->unused_tuple & BIT(INNER_SRC_IP) ? 6752 0 : cpu_to_be32(rule->tuples_mask.src_ip[IPV4_INDEX]); 6753 6754 spec->ip4dst = cpu_to_be32(rule->tuples.dst_ip[IPV4_INDEX]); 6755 spec_mask->ip4dst = rule->unused_tuple & BIT(INNER_DST_IP) ? 6756 0 : cpu_to_be32(rule->tuples_mask.dst_ip[IPV4_INDEX]); 6757 6758 spec->tos = rule->tuples.ip_tos; 6759 spec_mask->tos = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6760 0 : rule->tuples_mask.ip_tos; 6761 6762 spec->proto = rule->tuples.ip_proto; 6763 spec_mask->proto = rule->unused_tuple & BIT(INNER_IP_PROTO) ? 6764 0 : rule->tuples_mask.ip_proto; 6765 6766 spec->ip_ver = ETH_RX_NFC_IP4; 6767 } 6768 6769 static void hclge_fd_get_tcpip6_info(struct hclge_fd_rule *rule, 6770 struct ethtool_tcpip6_spec *spec, 6771 struct ethtool_tcpip6_spec *spec_mask) 6772 { 6773 cpu_to_be32_array(spec->ip6src, 6774 rule->tuples.src_ip, IPV6_SIZE); 6775 cpu_to_be32_array(spec->ip6dst, 6776 rule->tuples.dst_ip, IPV6_SIZE); 6777 if (rule->unused_tuple & BIT(INNER_SRC_IP)) 6778 memset(spec_mask->ip6src, 0, sizeof(spec_mask->ip6src)); 6779 else 6780 cpu_to_be32_array(spec_mask->ip6src, rule->tuples_mask.src_ip, 6781 IPV6_SIZE); 6782 6783 if (rule->unused_tuple & BIT(INNER_DST_IP)) 6784 memset(spec_mask->ip6dst, 0, sizeof(spec_mask->ip6dst)); 6785 else 6786 cpu_to_be32_array(spec_mask->ip6dst, rule->tuples_mask.dst_ip, 6787 IPV6_SIZE); 6788 6789 spec->tclass = rule->tuples.ip_tos; 6790 spec_mask->tclass = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6791 0 : rule->tuples_mask.ip_tos; 6792 6793 spec->psrc = cpu_to_be16(rule->tuples.src_port); 6794 spec_mask->psrc = rule->unused_tuple & BIT(INNER_SRC_PORT) ? 6795 0 : cpu_to_be16(rule->tuples_mask.src_port); 6796 6797 spec->pdst = cpu_to_be16(rule->tuples.dst_port); 6798 spec_mask->pdst = rule->unused_tuple & BIT(INNER_DST_PORT) ? 6799 0 : cpu_to_be16(rule->tuples_mask.dst_port); 6800 } 6801 6802 static void hclge_fd_get_ip6_info(struct hclge_fd_rule *rule, 6803 struct ethtool_usrip6_spec *spec, 6804 struct ethtool_usrip6_spec *spec_mask) 6805 { 6806 cpu_to_be32_array(spec->ip6src, rule->tuples.src_ip, IPV6_SIZE); 6807 cpu_to_be32_array(spec->ip6dst, rule->tuples.dst_ip, IPV6_SIZE); 6808 if (rule->unused_tuple & BIT(INNER_SRC_IP)) 6809 memset(spec_mask->ip6src, 0, sizeof(spec_mask->ip6src)); 6810 else 6811 cpu_to_be32_array(spec_mask->ip6src, 6812 rule->tuples_mask.src_ip, IPV6_SIZE); 6813 6814 if (rule->unused_tuple & BIT(INNER_DST_IP)) 6815 memset(spec_mask->ip6dst, 0, sizeof(spec_mask->ip6dst)); 6816 else 6817 cpu_to_be32_array(spec_mask->ip6dst, 6818 rule->tuples_mask.dst_ip, IPV6_SIZE); 6819 6820 spec->tclass = rule->tuples.ip_tos; 6821 spec_mask->tclass = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6822 0 : rule->tuples_mask.ip_tos; 6823 6824 spec->l4_proto = rule->tuples.ip_proto; 6825 spec_mask->l4_proto = rule->unused_tuple & BIT(INNER_IP_PROTO) ? 6826 0 : rule->tuples_mask.ip_proto; 6827 } 6828 6829 static void hclge_fd_get_ether_info(struct hclge_fd_rule *rule, 6830 struct ethhdr *spec, 6831 struct ethhdr *spec_mask) 6832 { 6833 ether_addr_copy(spec->h_source, rule->tuples.src_mac); 6834 ether_addr_copy(spec->h_dest, rule->tuples.dst_mac); 6835 6836 if (rule->unused_tuple & BIT(INNER_SRC_MAC)) 6837 eth_zero_addr(spec_mask->h_source); 6838 else 6839 ether_addr_copy(spec_mask->h_source, rule->tuples_mask.src_mac); 6840 6841 if (rule->unused_tuple & BIT(INNER_DST_MAC)) 6842 eth_zero_addr(spec_mask->h_dest); 6843 else 6844 ether_addr_copy(spec_mask->h_dest, rule->tuples_mask.dst_mac); 6845 6846 spec->h_proto = cpu_to_be16(rule->tuples.ether_proto); 6847 spec_mask->h_proto = rule->unused_tuple & BIT(INNER_ETH_TYPE) ? 6848 0 : cpu_to_be16(rule->tuples_mask.ether_proto); 6849 } 6850 6851 static void hclge_fd_get_user_def_info(struct ethtool_rx_flow_spec *fs, 6852 struct hclge_fd_rule *rule) 6853 { 6854 if ((rule->unused_tuple & HCLGE_FD_TUPLE_USER_DEF_TUPLES) == 6855 HCLGE_FD_TUPLE_USER_DEF_TUPLES) { 6856 fs->h_ext.data[0] = 0; 6857 fs->h_ext.data[1] = 0; 6858 fs->m_ext.data[0] = 0; 6859 fs->m_ext.data[1] = 0; 6860 } else { 6861 fs->h_ext.data[0] = cpu_to_be32(rule->ep.user_def.offset); 6862 fs->h_ext.data[1] = cpu_to_be32(rule->ep.user_def.data); 6863 fs->m_ext.data[0] = 6864 cpu_to_be32(HCLGE_FD_USER_DEF_OFFSET_UNMASK); 6865 fs->m_ext.data[1] = cpu_to_be32(rule->ep.user_def.data_mask); 6866 } 6867 } 6868 6869 static void hclge_fd_get_ext_info(struct ethtool_rx_flow_spec *fs, 6870 struct hclge_fd_rule *rule) 6871 { 6872 if (fs->flow_type & FLOW_EXT) { 6873 fs->h_ext.vlan_tci = cpu_to_be16(rule->tuples.vlan_tag1); 6874 fs->m_ext.vlan_tci = 6875 rule->unused_tuple & BIT(INNER_VLAN_TAG_FST) ? 6876 0 : cpu_to_be16(rule->tuples_mask.vlan_tag1); 6877 6878 hclge_fd_get_user_def_info(fs, rule); 6879 } 6880 6881 if (fs->flow_type & FLOW_MAC_EXT) { 6882 ether_addr_copy(fs->h_ext.h_dest, rule->tuples.dst_mac); 6883 if (rule->unused_tuple & BIT(INNER_DST_MAC)) 6884 eth_zero_addr(fs->m_u.ether_spec.h_dest); 6885 else 6886 ether_addr_copy(fs->m_u.ether_spec.h_dest, 6887 rule->tuples_mask.dst_mac); 6888 } 6889 } 6890 6891 static struct hclge_fd_rule *hclge_get_fd_rule(struct hclge_dev *hdev, 6892 u16 location) 6893 { 6894 struct hclge_fd_rule *rule = NULL; 6895 struct hlist_node *node2; 6896 6897 hlist_for_each_entry_safe(rule, node2, &hdev->fd_rule_list, rule_node) { 6898 if (rule->location == location) 6899 return rule; 6900 else if (rule->location > location) 6901 return NULL; 6902 } 6903 6904 return NULL; 6905 } 6906 6907 static void hclge_fd_get_ring_cookie(struct ethtool_rx_flow_spec *fs, 6908 struct hclge_fd_rule *rule) 6909 { 6910 if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) { 6911 fs->ring_cookie = RX_CLS_FLOW_DISC; 6912 } else { 6913 u64 vf_id; 6914 6915 fs->ring_cookie = rule->queue_id; 6916 vf_id = rule->vf_id; 6917 vf_id <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF; 6918 fs->ring_cookie |= vf_id; 6919 } 6920 } 6921 6922 static int hclge_get_fd_rule_info(struct hnae3_handle *handle, 6923 struct ethtool_rxnfc *cmd) 6924 { 6925 struct hclge_vport *vport = hclge_get_vport(handle); 6926 struct hclge_fd_rule *rule = NULL; 6927 struct hclge_dev *hdev = vport->back; 6928 struct ethtool_rx_flow_spec *fs; 6929 6930 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6931 return -EOPNOTSUPP; 6932 6933 fs = (struct ethtool_rx_flow_spec *)&cmd->fs; 6934 6935 spin_lock_bh(&hdev->fd_rule_lock); 6936 6937 rule = hclge_get_fd_rule(hdev, fs->location); 6938 if (!rule) { 6939 spin_unlock_bh(&hdev->fd_rule_lock); 6940 return -ENOENT; 6941 } 6942 6943 fs->flow_type = rule->flow_type; 6944 switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) { 6945 case SCTP_V4_FLOW: 6946 case TCP_V4_FLOW: 6947 case UDP_V4_FLOW: 6948 hclge_fd_get_tcpip4_info(rule, &fs->h_u.tcp_ip4_spec, 6949 &fs->m_u.tcp_ip4_spec); 6950 break; 6951 case IP_USER_FLOW: 6952 hclge_fd_get_ip4_info(rule, &fs->h_u.usr_ip4_spec, 6953 &fs->m_u.usr_ip4_spec); 6954 break; 6955 case SCTP_V6_FLOW: 6956 case TCP_V6_FLOW: 6957 case UDP_V6_FLOW: 6958 hclge_fd_get_tcpip6_info(rule, &fs->h_u.tcp_ip6_spec, 6959 &fs->m_u.tcp_ip6_spec); 6960 break; 6961 case IPV6_USER_FLOW: 6962 hclge_fd_get_ip6_info(rule, &fs->h_u.usr_ip6_spec, 6963 &fs->m_u.usr_ip6_spec); 6964 break; 6965 /* The flow type of fd rule has been checked before adding in to rule 6966 * list. As other flow types have been handled, it must be ETHER_FLOW 6967 * for the default case 6968 */ 6969 default: 6970 hclge_fd_get_ether_info(rule, &fs->h_u.ether_spec, 6971 &fs->m_u.ether_spec); 6972 break; 6973 } 6974 6975 hclge_fd_get_ext_info(fs, rule); 6976 6977 hclge_fd_get_ring_cookie(fs, rule); 6978 6979 spin_unlock_bh(&hdev->fd_rule_lock); 6980 6981 return 0; 6982 } 6983 6984 static int hclge_get_all_rules(struct hnae3_handle *handle, 6985 struct ethtool_rxnfc *cmd, u32 *rule_locs) 6986 { 6987 struct hclge_vport *vport = hclge_get_vport(handle); 6988 struct hclge_dev *hdev = vport->back; 6989 struct hclge_fd_rule *rule; 6990 struct hlist_node *node2; 6991 int cnt = 0; 6992 6993 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6994 return -EOPNOTSUPP; 6995 6996 cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]; 6997 6998 spin_lock_bh(&hdev->fd_rule_lock); 6999 hlist_for_each_entry_safe(rule, node2, 7000 &hdev->fd_rule_list, rule_node) { 7001 if (cnt == cmd->rule_cnt) { 7002 spin_unlock_bh(&hdev->fd_rule_lock); 7003 return -EMSGSIZE; 7004 } 7005 7006 if (rule->state == HCLGE_FD_TO_DEL) 7007 continue; 7008 7009 rule_locs[cnt] = rule->location; 7010 cnt++; 7011 } 7012 7013 spin_unlock_bh(&hdev->fd_rule_lock); 7014 7015 cmd->rule_cnt = cnt; 7016 7017 return 0; 7018 } 7019 7020 static void hclge_fd_get_flow_tuples(const struct flow_keys *fkeys, 7021 struct hclge_fd_rule_tuples *tuples) 7022 { 7023 #define flow_ip6_src fkeys->addrs.v6addrs.src.in6_u.u6_addr32 7024 #define flow_ip6_dst fkeys->addrs.v6addrs.dst.in6_u.u6_addr32 7025 7026 tuples->ether_proto = be16_to_cpu(fkeys->basic.n_proto); 7027 tuples->ip_proto = fkeys->basic.ip_proto; 7028 tuples->dst_port = be16_to_cpu(fkeys->ports.dst); 7029 7030 if (fkeys->basic.n_proto == htons(ETH_P_IP)) { 7031 tuples->src_ip[3] = be32_to_cpu(fkeys->addrs.v4addrs.src); 7032 tuples->dst_ip[3] = be32_to_cpu(fkeys->addrs.v4addrs.dst); 7033 } else { 7034 int i; 7035 7036 for (i = 0; i < IPV6_SIZE; i++) { 7037 tuples->src_ip[i] = be32_to_cpu(flow_ip6_src[i]); 7038 tuples->dst_ip[i] = be32_to_cpu(flow_ip6_dst[i]); 7039 } 7040 } 7041 } 7042 7043 /* traverse all rules, check whether an existed rule has the same tuples */ 7044 static struct hclge_fd_rule * 7045 hclge_fd_search_flow_keys(struct hclge_dev *hdev, 7046 const struct hclge_fd_rule_tuples *tuples) 7047 { 7048 struct hclge_fd_rule *rule = NULL; 7049 struct hlist_node *node; 7050 7051 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 7052 if (!memcmp(tuples, &rule->tuples, sizeof(*tuples))) 7053 return rule; 7054 } 7055 7056 return NULL; 7057 } 7058 7059 static void hclge_fd_build_arfs_rule(const struct hclge_fd_rule_tuples *tuples, 7060 struct hclge_fd_rule *rule) 7061 { 7062 rule->unused_tuple = BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) | 7063 BIT(INNER_VLAN_TAG_FST) | BIT(INNER_IP_TOS) | 7064 BIT(INNER_SRC_PORT); 7065 rule->action = 0; 7066 rule->vf_id = 0; 7067 rule->rule_type = HCLGE_FD_ARFS_ACTIVE; 7068 rule->state = HCLGE_FD_TO_ADD; 7069 if (tuples->ether_proto == ETH_P_IP) { 7070 if (tuples->ip_proto == IPPROTO_TCP) 7071 rule->flow_type = TCP_V4_FLOW; 7072 else 7073 rule->flow_type = UDP_V4_FLOW; 7074 } else { 7075 if (tuples->ip_proto == IPPROTO_TCP) 7076 rule->flow_type = TCP_V6_FLOW; 7077 else 7078 rule->flow_type = UDP_V6_FLOW; 7079 } 7080 memcpy(&rule->tuples, tuples, sizeof(rule->tuples)); 7081 memset(&rule->tuples_mask, 0xFF, sizeof(rule->tuples_mask)); 7082 } 7083 7084 static int hclge_add_fd_entry_by_arfs(struct hnae3_handle *handle, u16 queue_id, 7085 u16 flow_id, struct flow_keys *fkeys) 7086 { 7087 struct hclge_vport *vport = hclge_get_vport(handle); 7088 struct hclge_fd_rule_tuples new_tuples = {}; 7089 struct hclge_dev *hdev = vport->back; 7090 struct hclge_fd_rule *rule; 7091 u16 bit_id; 7092 7093 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 7094 return -EOPNOTSUPP; 7095 7096 /* when there is already fd rule existed add by user, 7097 * arfs should not work 7098 */ 7099 spin_lock_bh(&hdev->fd_rule_lock); 7100 if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE && 7101 hdev->fd_active_type != HCLGE_FD_RULE_NONE) { 7102 spin_unlock_bh(&hdev->fd_rule_lock); 7103 return -EOPNOTSUPP; 7104 } 7105 7106 hclge_fd_get_flow_tuples(fkeys, &new_tuples); 7107 7108 /* check is there flow director filter existed for this flow, 7109 * if not, create a new filter for it; 7110 * if filter exist with different queue id, modify the filter; 7111 * if filter exist with same queue id, do nothing 7112 */ 7113 rule = hclge_fd_search_flow_keys(hdev, &new_tuples); 7114 if (!rule) { 7115 bit_id = find_first_zero_bit(hdev->fd_bmap, MAX_FD_FILTER_NUM); 7116 if (bit_id >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) { 7117 spin_unlock_bh(&hdev->fd_rule_lock); 7118 return -ENOSPC; 7119 } 7120 7121 rule = kzalloc(sizeof(*rule), GFP_ATOMIC); 7122 if (!rule) { 7123 spin_unlock_bh(&hdev->fd_rule_lock); 7124 return -ENOMEM; 7125 } 7126 7127 rule->location = bit_id; 7128 rule->arfs.flow_id = flow_id; 7129 rule->queue_id = queue_id; 7130 hclge_fd_build_arfs_rule(&new_tuples, rule); 7131 hclge_update_fd_list(hdev, rule->state, rule->location, rule); 7132 hdev->fd_active_type = HCLGE_FD_ARFS_ACTIVE; 7133 } else if (rule->queue_id != queue_id) { 7134 rule->queue_id = queue_id; 7135 rule->state = HCLGE_FD_TO_ADD; 7136 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 7137 hclge_task_schedule(hdev, 0); 7138 } 7139 spin_unlock_bh(&hdev->fd_rule_lock); 7140 return rule->location; 7141 } 7142 7143 static void hclge_rfs_filter_expire(struct hclge_dev *hdev) 7144 { 7145 #ifdef CONFIG_RFS_ACCEL 7146 struct hnae3_handle *handle = &hdev->vport[0].nic; 7147 struct hclge_fd_rule *rule; 7148 struct hlist_node *node; 7149 7150 spin_lock_bh(&hdev->fd_rule_lock); 7151 if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE) { 7152 spin_unlock_bh(&hdev->fd_rule_lock); 7153 return; 7154 } 7155 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 7156 if (rule->state != HCLGE_FD_ACTIVE) 7157 continue; 7158 if (rps_may_expire_flow(handle->netdev, rule->queue_id, 7159 rule->arfs.flow_id, rule->location)) { 7160 rule->state = HCLGE_FD_TO_DEL; 7161 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 7162 } 7163 } 7164 spin_unlock_bh(&hdev->fd_rule_lock); 7165 #endif 7166 } 7167 7168 /* make sure being called after lock up with fd_rule_lock */ 7169 static int hclge_clear_arfs_rules(struct hclge_dev *hdev) 7170 { 7171 #ifdef CONFIG_RFS_ACCEL 7172 struct hclge_fd_rule *rule; 7173 struct hlist_node *node; 7174 int ret; 7175 7176 if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE) 7177 return 0; 7178 7179 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 7180 switch (rule->state) { 7181 case HCLGE_FD_TO_DEL: 7182 case HCLGE_FD_ACTIVE: 7183 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, 7184 rule->location, NULL, false); 7185 if (ret) 7186 return ret; 7187 fallthrough; 7188 case HCLGE_FD_TO_ADD: 7189 hclge_fd_dec_rule_cnt(hdev, rule->location); 7190 hlist_del(&rule->rule_node); 7191 kfree(rule); 7192 break; 7193 default: 7194 break; 7195 } 7196 } 7197 hclge_sync_fd_state(hdev); 7198 7199 #endif 7200 return 0; 7201 } 7202 7203 static void hclge_get_cls_key_basic(const struct flow_rule *flow, 7204 struct hclge_fd_rule *rule) 7205 { 7206 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_BASIC)) { 7207 struct flow_match_basic match; 7208 u16 ethtype_key, ethtype_mask; 7209 7210 flow_rule_match_basic(flow, &match); 7211 ethtype_key = ntohs(match.key->n_proto); 7212 ethtype_mask = ntohs(match.mask->n_proto); 7213 7214 if (ethtype_key == ETH_P_ALL) { 7215 ethtype_key = 0; 7216 ethtype_mask = 0; 7217 } 7218 rule->tuples.ether_proto = ethtype_key; 7219 rule->tuples_mask.ether_proto = ethtype_mask; 7220 rule->tuples.ip_proto = match.key->ip_proto; 7221 rule->tuples_mask.ip_proto = match.mask->ip_proto; 7222 } else { 7223 rule->unused_tuple |= BIT(INNER_IP_PROTO); 7224 rule->unused_tuple |= BIT(INNER_ETH_TYPE); 7225 } 7226 } 7227 7228 static void hclge_get_cls_key_mac(const struct flow_rule *flow, 7229 struct hclge_fd_rule *rule) 7230 { 7231 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { 7232 struct flow_match_eth_addrs match; 7233 7234 flow_rule_match_eth_addrs(flow, &match); 7235 ether_addr_copy(rule->tuples.dst_mac, match.key->dst); 7236 ether_addr_copy(rule->tuples_mask.dst_mac, match.mask->dst); 7237 ether_addr_copy(rule->tuples.src_mac, match.key->src); 7238 ether_addr_copy(rule->tuples_mask.src_mac, match.mask->src); 7239 } else { 7240 rule->unused_tuple |= BIT(INNER_DST_MAC); 7241 rule->unused_tuple |= BIT(INNER_SRC_MAC); 7242 } 7243 } 7244 7245 static void hclge_get_cls_key_vlan(const struct flow_rule *flow, 7246 struct hclge_fd_rule *rule) 7247 { 7248 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_VLAN)) { 7249 struct flow_match_vlan match; 7250 7251 flow_rule_match_vlan(flow, &match); 7252 rule->tuples.vlan_tag1 = match.key->vlan_id | 7253 (match.key->vlan_priority << VLAN_PRIO_SHIFT); 7254 rule->tuples_mask.vlan_tag1 = match.mask->vlan_id | 7255 (match.mask->vlan_priority << VLAN_PRIO_SHIFT); 7256 } else { 7257 rule->unused_tuple |= BIT(INNER_VLAN_TAG_FST); 7258 } 7259 } 7260 7261 static void hclge_get_cls_key_ip(const struct flow_rule *flow, 7262 struct hclge_fd_rule *rule) 7263 { 7264 u16 addr_type = 0; 7265 7266 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_CONTROL)) { 7267 struct flow_match_control match; 7268 7269 flow_rule_match_control(flow, &match); 7270 addr_type = match.key->addr_type; 7271 } 7272 7273 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) { 7274 struct flow_match_ipv4_addrs match; 7275 7276 flow_rule_match_ipv4_addrs(flow, &match); 7277 rule->tuples.src_ip[IPV4_INDEX] = be32_to_cpu(match.key->src); 7278 rule->tuples_mask.src_ip[IPV4_INDEX] = 7279 be32_to_cpu(match.mask->src); 7280 rule->tuples.dst_ip[IPV4_INDEX] = be32_to_cpu(match.key->dst); 7281 rule->tuples_mask.dst_ip[IPV4_INDEX] = 7282 be32_to_cpu(match.mask->dst); 7283 } else if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) { 7284 struct flow_match_ipv6_addrs match; 7285 7286 flow_rule_match_ipv6_addrs(flow, &match); 7287 be32_to_cpu_array(rule->tuples.src_ip, match.key->src.s6_addr32, 7288 IPV6_SIZE); 7289 be32_to_cpu_array(rule->tuples_mask.src_ip, 7290 match.mask->src.s6_addr32, IPV6_SIZE); 7291 be32_to_cpu_array(rule->tuples.dst_ip, match.key->dst.s6_addr32, 7292 IPV6_SIZE); 7293 be32_to_cpu_array(rule->tuples_mask.dst_ip, 7294 match.mask->dst.s6_addr32, IPV6_SIZE); 7295 } else { 7296 rule->unused_tuple |= BIT(INNER_SRC_IP); 7297 rule->unused_tuple |= BIT(INNER_DST_IP); 7298 } 7299 } 7300 7301 static void hclge_get_cls_key_port(const struct flow_rule *flow, 7302 struct hclge_fd_rule *rule) 7303 { 7304 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_PORTS)) { 7305 struct flow_match_ports match; 7306 7307 flow_rule_match_ports(flow, &match); 7308 7309 rule->tuples.src_port = be16_to_cpu(match.key->src); 7310 rule->tuples_mask.src_port = be16_to_cpu(match.mask->src); 7311 rule->tuples.dst_port = be16_to_cpu(match.key->dst); 7312 rule->tuples_mask.dst_port = be16_to_cpu(match.mask->dst); 7313 } else { 7314 rule->unused_tuple |= BIT(INNER_SRC_PORT); 7315 rule->unused_tuple |= BIT(INNER_DST_PORT); 7316 } 7317 } 7318 7319 static int hclge_parse_cls_flower(struct hclge_dev *hdev, 7320 struct flow_cls_offload *cls_flower, 7321 struct hclge_fd_rule *rule) 7322 { 7323 struct flow_rule *flow = flow_cls_offload_flow_rule(cls_flower); 7324 struct flow_dissector *dissector = flow->match.dissector; 7325 7326 if (dissector->used_keys & 7327 ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) | 7328 BIT(FLOW_DISSECTOR_KEY_BASIC) | 7329 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) | 7330 BIT(FLOW_DISSECTOR_KEY_VLAN) | 7331 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) | 7332 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) | 7333 BIT(FLOW_DISSECTOR_KEY_PORTS))) { 7334 dev_err(&hdev->pdev->dev, "unsupported key set: %#x\n", 7335 dissector->used_keys); 7336 return -EOPNOTSUPP; 7337 } 7338 7339 hclge_get_cls_key_basic(flow, rule); 7340 hclge_get_cls_key_mac(flow, rule); 7341 hclge_get_cls_key_vlan(flow, rule); 7342 hclge_get_cls_key_ip(flow, rule); 7343 hclge_get_cls_key_port(flow, rule); 7344 7345 return 0; 7346 } 7347 7348 static int hclge_check_cls_flower(struct hclge_dev *hdev, 7349 struct flow_cls_offload *cls_flower, int tc) 7350 { 7351 u32 prio = cls_flower->common.prio; 7352 7353 if (tc < 0 || tc > hdev->tc_max) { 7354 dev_err(&hdev->pdev->dev, "invalid traffic class\n"); 7355 return -EINVAL; 7356 } 7357 7358 if (prio == 0 || 7359 prio > hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) { 7360 dev_err(&hdev->pdev->dev, 7361 "prio %u should be in range[1, %u]\n", 7362 prio, hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]); 7363 return -EINVAL; 7364 } 7365 7366 if (test_bit(prio - 1, hdev->fd_bmap)) { 7367 dev_err(&hdev->pdev->dev, "prio %u is already used\n", prio); 7368 return -EINVAL; 7369 } 7370 return 0; 7371 } 7372 7373 static int hclge_add_cls_flower(struct hnae3_handle *handle, 7374 struct flow_cls_offload *cls_flower, 7375 int tc) 7376 { 7377 struct hclge_vport *vport = hclge_get_vport(handle); 7378 struct hclge_dev *hdev = vport->back; 7379 struct hclge_fd_rule *rule; 7380 int ret; 7381 7382 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) { 7383 dev_err(&hdev->pdev->dev, 7384 "cls flower is not supported\n"); 7385 return -EOPNOTSUPP; 7386 } 7387 7388 ret = hclge_check_cls_flower(hdev, cls_flower, tc); 7389 if (ret) { 7390 dev_err(&hdev->pdev->dev, 7391 "failed to check cls flower params, ret = %d\n", ret); 7392 return ret; 7393 } 7394 7395 rule = kzalloc(sizeof(*rule), GFP_KERNEL); 7396 if (!rule) 7397 return -ENOMEM; 7398 7399 ret = hclge_parse_cls_flower(hdev, cls_flower, rule); 7400 if (ret) { 7401 kfree(rule); 7402 return ret; 7403 } 7404 7405 rule->action = HCLGE_FD_ACTION_SELECT_TC; 7406 rule->cls_flower.tc = tc; 7407 rule->location = cls_flower->common.prio - 1; 7408 rule->vf_id = 0; 7409 rule->cls_flower.cookie = cls_flower->cookie; 7410 rule->rule_type = HCLGE_FD_TC_FLOWER_ACTIVE; 7411 7412 ret = hclge_add_fd_entry_common(hdev, rule); 7413 if (ret) 7414 kfree(rule); 7415 7416 return ret; 7417 } 7418 7419 static struct hclge_fd_rule *hclge_find_cls_flower(struct hclge_dev *hdev, 7420 unsigned long cookie) 7421 { 7422 struct hclge_fd_rule *rule; 7423 struct hlist_node *node; 7424 7425 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 7426 if (rule->cls_flower.cookie == cookie) 7427 return rule; 7428 } 7429 7430 return NULL; 7431 } 7432 7433 static int hclge_del_cls_flower(struct hnae3_handle *handle, 7434 struct flow_cls_offload *cls_flower) 7435 { 7436 struct hclge_vport *vport = hclge_get_vport(handle); 7437 struct hclge_dev *hdev = vport->back; 7438 struct hclge_fd_rule *rule; 7439 int ret; 7440 7441 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 7442 return -EOPNOTSUPP; 7443 7444 spin_lock_bh(&hdev->fd_rule_lock); 7445 7446 rule = hclge_find_cls_flower(hdev, cls_flower->cookie); 7447 if (!rule) { 7448 spin_unlock_bh(&hdev->fd_rule_lock); 7449 return -EINVAL; 7450 } 7451 7452 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, rule->location, 7453 NULL, false); 7454 if (ret) { 7455 spin_unlock_bh(&hdev->fd_rule_lock); 7456 return ret; 7457 } 7458 7459 hclge_update_fd_list(hdev, HCLGE_FD_DELETED, rule->location, NULL); 7460 spin_unlock_bh(&hdev->fd_rule_lock); 7461 7462 return 0; 7463 } 7464 7465 static void hclge_sync_fd_list(struct hclge_dev *hdev, struct hlist_head *hlist) 7466 { 7467 struct hclge_fd_rule *rule; 7468 struct hlist_node *node; 7469 int ret = 0; 7470 7471 if (!test_and_clear_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state)) 7472 return; 7473 7474 spin_lock_bh(&hdev->fd_rule_lock); 7475 7476 hlist_for_each_entry_safe(rule, node, hlist, rule_node) { 7477 switch (rule->state) { 7478 case HCLGE_FD_TO_ADD: 7479 ret = hclge_fd_config_rule(hdev, rule); 7480 if (ret) 7481 goto out; 7482 rule->state = HCLGE_FD_ACTIVE; 7483 break; 7484 case HCLGE_FD_TO_DEL: 7485 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, 7486 rule->location, NULL, false); 7487 if (ret) 7488 goto out; 7489 hclge_fd_dec_rule_cnt(hdev, rule->location); 7490 hclge_fd_free_node(hdev, rule); 7491 break; 7492 default: 7493 break; 7494 } 7495 } 7496 7497 out: 7498 if (ret) 7499 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 7500 7501 spin_unlock_bh(&hdev->fd_rule_lock); 7502 } 7503 7504 static void hclge_sync_fd_table(struct hclge_dev *hdev) 7505 { 7506 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 7507 return; 7508 7509 if (test_and_clear_bit(HCLGE_STATE_FD_CLEAR_ALL, &hdev->state)) { 7510 bool clear_list = hdev->fd_active_type == HCLGE_FD_ARFS_ACTIVE; 7511 7512 hclge_clear_fd_rules_in_list(hdev, clear_list); 7513 } 7514 7515 hclge_sync_fd_user_def_cfg(hdev, false); 7516 7517 hclge_sync_fd_list(hdev, &hdev->fd_rule_list); 7518 } 7519 7520 static bool hclge_get_hw_reset_stat(struct hnae3_handle *handle) 7521 { 7522 struct hclge_vport *vport = hclge_get_vport(handle); 7523 struct hclge_dev *hdev = vport->back; 7524 7525 return hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG) || 7526 hclge_read_dev(&hdev->hw, HCLGE_FUN_RST_ING); 7527 } 7528 7529 static bool hclge_get_cmdq_stat(struct hnae3_handle *handle) 7530 { 7531 struct hclge_vport *vport = hclge_get_vport(handle); 7532 struct hclge_dev *hdev = vport->back; 7533 7534 return test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 7535 } 7536 7537 static bool hclge_ae_dev_resetting(struct hnae3_handle *handle) 7538 { 7539 struct hclge_vport *vport = hclge_get_vport(handle); 7540 struct hclge_dev *hdev = vport->back; 7541 7542 return test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 7543 } 7544 7545 static unsigned long hclge_ae_dev_reset_cnt(struct hnae3_handle *handle) 7546 { 7547 struct hclge_vport *vport = hclge_get_vport(handle); 7548 struct hclge_dev *hdev = vport->back; 7549 7550 return hdev->rst_stats.hw_reset_done_cnt; 7551 } 7552 7553 static void hclge_enable_fd(struct hnae3_handle *handle, bool enable) 7554 { 7555 struct hclge_vport *vport = hclge_get_vport(handle); 7556 struct hclge_dev *hdev = vport->back; 7557 7558 hdev->fd_en = enable; 7559 7560 if (!enable) 7561 set_bit(HCLGE_STATE_FD_CLEAR_ALL, &hdev->state); 7562 else 7563 hclge_restore_fd_entries(handle); 7564 7565 hclge_task_schedule(hdev, 0); 7566 } 7567 7568 static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable) 7569 { 7570 struct hclge_desc desc; 7571 struct hclge_config_mac_mode_cmd *req = 7572 (struct hclge_config_mac_mode_cmd *)desc.data; 7573 u32 loop_en = 0; 7574 int ret; 7575 7576 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false); 7577 7578 if (enable) { 7579 hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, 1U); 7580 hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, 1U); 7581 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, 1U); 7582 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, 1U); 7583 hnae3_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, 1U); 7584 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, 1U); 7585 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, 1U); 7586 hnae3_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, 1U); 7587 hnae3_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, 1U); 7588 hnae3_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, 1U); 7589 } 7590 7591 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en); 7592 7593 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7594 if (ret) 7595 dev_err(&hdev->pdev->dev, 7596 "mac enable fail, ret =%d.\n", ret); 7597 } 7598 7599 static int hclge_config_switch_param(struct hclge_dev *hdev, int vfid, 7600 u8 switch_param, u8 param_mask) 7601 { 7602 struct hclge_mac_vlan_switch_cmd *req; 7603 struct hclge_desc desc; 7604 u32 func_id; 7605 int ret; 7606 7607 func_id = hclge_get_port_number(HOST_PORT, 0, vfid, 0); 7608 req = (struct hclge_mac_vlan_switch_cmd *)desc.data; 7609 7610 /* read current config parameter */ 7611 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_SWITCH_PARAM, 7612 true); 7613 req->roce_sel = HCLGE_MAC_VLAN_NIC_SEL; 7614 req->func_id = cpu_to_le32(func_id); 7615 7616 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7617 if (ret) { 7618 dev_err(&hdev->pdev->dev, 7619 "read mac vlan switch parameter fail, ret = %d\n", ret); 7620 return ret; 7621 } 7622 7623 /* modify and write new config parameter */ 7624 hclge_comm_cmd_reuse_desc(&desc, false); 7625 req->switch_param = (req->switch_param & param_mask) | switch_param; 7626 req->param_mask = param_mask; 7627 7628 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7629 if (ret) 7630 dev_err(&hdev->pdev->dev, 7631 "set mac vlan switch parameter fail, ret = %d\n", ret); 7632 return ret; 7633 } 7634 7635 static void hclge_phy_link_status_wait(struct hclge_dev *hdev, 7636 int link_ret) 7637 { 7638 #define HCLGE_PHY_LINK_STATUS_NUM 200 7639 7640 struct phy_device *phydev = hdev->hw.mac.phydev; 7641 int i = 0; 7642 int ret; 7643 7644 do { 7645 ret = phy_read_status(phydev); 7646 if (ret) { 7647 dev_err(&hdev->pdev->dev, 7648 "phy update link status fail, ret = %d\n", ret); 7649 return; 7650 } 7651 7652 if (phydev->link == link_ret) 7653 break; 7654 7655 msleep(HCLGE_LINK_STATUS_MS); 7656 } while (++i < HCLGE_PHY_LINK_STATUS_NUM); 7657 } 7658 7659 static int hclge_mac_link_status_wait(struct hclge_dev *hdev, int link_ret) 7660 { 7661 #define HCLGE_MAC_LINK_STATUS_NUM 100 7662 7663 int link_status; 7664 int i = 0; 7665 int ret; 7666 7667 do { 7668 ret = hclge_get_mac_link_status(hdev, &link_status); 7669 if (ret) 7670 return ret; 7671 if (link_status == link_ret) 7672 return 0; 7673 7674 msleep(HCLGE_LINK_STATUS_MS); 7675 } while (++i < HCLGE_MAC_LINK_STATUS_NUM); 7676 return -EBUSY; 7677 } 7678 7679 static int hclge_mac_phy_link_status_wait(struct hclge_dev *hdev, bool en, 7680 bool is_phy) 7681 { 7682 int link_ret; 7683 7684 link_ret = en ? HCLGE_LINK_STATUS_UP : HCLGE_LINK_STATUS_DOWN; 7685 7686 if (is_phy) 7687 hclge_phy_link_status_wait(hdev, link_ret); 7688 7689 return hclge_mac_link_status_wait(hdev, link_ret); 7690 } 7691 7692 static int hclge_set_app_loopback(struct hclge_dev *hdev, bool en) 7693 { 7694 struct hclge_config_mac_mode_cmd *req; 7695 struct hclge_desc desc; 7696 u32 loop_en; 7697 int ret; 7698 7699 req = (struct hclge_config_mac_mode_cmd *)&desc.data[0]; 7700 /* 1 Read out the MAC mode config at first */ 7701 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true); 7702 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7703 if (ret) { 7704 dev_err(&hdev->pdev->dev, 7705 "mac loopback get fail, ret =%d.\n", ret); 7706 return ret; 7707 } 7708 7709 /* 2 Then setup the loopback flag */ 7710 loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en); 7711 hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, en ? 1 : 0); 7712 7713 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en); 7714 7715 /* 3 Config mac work mode with loopback flag 7716 * and its original configure parameters 7717 */ 7718 hclge_comm_cmd_reuse_desc(&desc, false); 7719 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7720 if (ret) 7721 dev_err(&hdev->pdev->dev, 7722 "mac loopback set fail, ret =%d.\n", ret); 7723 return ret; 7724 } 7725 7726 static int hclge_cfg_common_loopback_cmd_send(struct hclge_dev *hdev, bool en, 7727 enum hnae3_loop loop_mode) 7728 { 7729 struct hclge_common_lb_cmd *req; 7730 struct hclge_desc desc; 7731 u8 loop_mode_b; 7732 int ret; 7733 7734 req = (struct hclge_common_lb_cmd *)desc.data; 7735 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_COMMON_LOOPBACK, false); 7736 7737 switch (loop_mode) { 7738 case HNAE3_LOOP_SERIAL_SERDES: 7739 loop_mode_b = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B; 7740 break; 7741 case HNAE3_LOOP_PARALLEL_SERDES: 7742 loop_mode_b = HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B; 7743 break; 7744 case HNAE3_LOOP_PHY: 7745 loop_mode_b = HCLGE_CMD_GE_PHY_INNER_LOOP_B; 7746 break; 7747 default: 7748 dev_err(&hdev->pdev->dev, 7749 "unsupported loopback mode %d\n", loop_mode); 7750 return -ENOTSUPP; 7751 } 7752 7753 req->mask = loop_mode_b; 7754 if (en) 7755 req->enable = loop_mode_b; 7756 7757 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7758 if (ret) 7759 dev_err(&hdev->pdev->dev, 7760 "failed to send loopback cmd, loop_mode = %d, ret = %d\n", 7761 loop_mode, ret); 7762 7763 return ret; 7764 } 7765 7766 static int hclge_cfg_common_loopback_wait(struct hclge_dev *hdev) 7767 { 7768 #define HCLGE_COMMON_LB_RETRY_MS 10 7769 #define HCLGE_COMMON_LB_RETRY_NUM 100 7770 7771 struct hclge_common_lb_cmd *req; 7772 struct hclge_desc desc; 7773 u32 i = 0; 7774 int ret; 7775 7776 req = (struct hclge_common_lb_cmd *)desc.data; 7777 7778 do { 7779 msleep(HCLGE_COMMON_LB_RETRY_MS); 7780 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_COMMON_LOOPBACK, 7781 true); 7782 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7783 if (ret) { 7784 dev_err(&hdev->pdev->dev, 7785 "failed to get loopback done status, ret = %d\n", 7786 ret); 7787 return ret; 7788 } 7789 } while (++i < HCLGE_COMMON_LB_RETRY_NUM && 7790 !(req->result & HCLGE_CMD_COMMON_LB_DONE_B)); 7791 7792 if (!(req->result & HCLGE_CMD_COMMON_LB_DONE_B)) { 7793 dev_err(&hdev->pdev->dev, "wait loopback timeout\n"); 7794 return -EBUSY; 7795 } else if (!(req->result & HCLGE_CMD_COMMON_LB_SUCCESS_B)) { 7796 dev_err(&hdev->pdev->dev, "failed to do loopback test\n"); 7797 return -EIO; 7798 } 7799 7800 return 0; 7801 } 7802 7803 static int hclge_cfg_common_loopback(struct hclge_dev *hdev, bool en, 7804 enum hnae3_loop loop_mode) 7805 { 7806 int ret; 7807 7808 ret = hclge_cfg_common_loopback_cmd_send(hdev, en, loop_mode); 7809 if (ret) 7810 return ret; 7811 7812 return hclge_cfg_common_loopback_wait(hdev); 7813 } 7814 7815 static int hclge_set_common_loopback(struct hclge_dev *hdev, bool en, 7816 enum hnae3_loop loop_mode) 7817 { 7818 int ret; 7819 7820 ret = hclge_cfg_common_loopback(hdev, en, loop_mode); 7821 if (ret) 7822 return ret; 7823 7824 hclge_cfg_mac_mode(hdev, en); 7825 7826 ret = hclge_mac_phy_link_status_wait(hdev, en, false); 7827 if (ret) 7828 dev_err(&hdev->pdev->dev, 7829 "serdes loopback config mac mode timeout\n"); 7830 7831 return ret; 7832 } 7833 7834 static int hclge_enable_phy_loopback(struct hclge_dev *hdev, 7835 struct phy_device *phydev) 7836 { 7837 int ret; 7838 7839 if (!phydev->suspended) { 7840 ret = phy_suspend(phydev); 7841 if (ret) 7842 return ret; 7843 } 7844 7845 ret = phy_resume(phydev); 7846 if (ret) 7847 return ret; 7848 7849 return phy_loopback(phydev, true); 7850 } 7851 7852 static int hclge_disable_phy_loopback(struct hclge_dev *hdev, 7853 struct phy_device *phydev) 7854 { 7855 int ret; 7856 7857 ret = phy_loopback(phydev, false); 7858 if (ret) 7859 return ret; 7860 7861 return phy_suspend(phydev); 7862 } 7863 7864 static int hclge_set_phy_loopback(struct hclge_dev *hdev, bool en) 7865 { 7866 struct phy_device *phydev = hdev->hw.mac.phydev; 7867 int ret; 7868 7869 if (!phydev) { 7870 if (hnae3_dev_phy_imp_supported(hdev)) 7871 return hclge_set_common_loopback(hdev, en, 7872 HNAE3_LOOP_PHY); 7873 return -ENOTSUPP; 7874 } 7875 7876 if (en) 7877 ret = hclge_enable_phy_loopback(hdev, phydev); 7878 else 7879 ret = hclge_disable_phy_loopback(hdev, phydev); 7880 if (ret) { 7881 dev_err(&hdev->pdev->dev, 7882 "set phy loopback fail, ret = %d\n", ret); 7883 return ret; 7884 } 7885 7886 hclge_cfg_mac_mode(hdev, en); 7887 7888 ret = hclge_mac_phy_link_status_wait(hdev, en, true); 7889 if (ret) 7890 dev_err(&hdev->pdev->dev, 7891 "phy loopback config mac mode timeout\n"); 7892 7893 return ret; 7894 } 7895 7896 static int hclge_tqp_enable_cmd_send(struct hclge_dev *hdev, u16 tqp_id, 7897 u16 stream_id, bool enable) 7898 { 7899 struct hclge_desc desc; 7900 struct hclge_cfg_com_tqp_queue_cmd *req = 7901 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data; 7902 7903 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false); 7904 req->tqp_id = cpu_to_le16(tqp_id); 7905 req->stream_id = cpu_to_le16(stream_id); 7906 if (enable) 7907 req->enable |= 1U << HCLGE_TQP_ENABLE_B; 7908 7909 return hclge_cmd_send(&hdev->hw, &desc, 1); 7910 } 7911 7912 static int hclge_tqp_enable(struct hnae3_handle *handle, bool enable) 7913 { 7914 struct hclge_vport *vport = hclge_get_vport(handle); 7915 struct hclge_dev *hdev = vport->back; 7916 int ret; 7917 u16 i; 7918 7919 for (i = 0; i < handle->kinfo.num_tqps; i++) { 7920 ret = hclge_tqp_enable_cmd_send(hdev, i, 0, enable); 7921 if (ret) 7922 return ret; 7923 } 7924 return 0; 7925 } 7926 7927 static int hclge_set_loopback(struct hnae3_handle *handle, 7928 enum hnae3_loop loop_mode, bool en) 7929 { 7930 struct hclge_vport *vport = hclge_get_vport(handle); 7931 struct hclge_dev *hdev = vport->back; 7932 int ret = 0; 7933 7934 /* Loopback can be enabled in three places: SSU, MAC, and serdes. By 7935 * default, SSU loopback is enabled, so if the SMAC and the DMAC are 7936 * the same, the packets are looped back in the SSU. If SSU loopback 7937 * is disabled, packets can reach MAC even if SMAC is the same as DMAC. 7938 */ 7939 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 7940 u8 switch_param = en ? 0 : BIT(HCLGE_SWITCH_ALW_LPBK_B); 7941 7942 ret = hclge_config_switch_param(hdev, PF_VPORT_ID, switch_param, 7943 HCLGE_SWITCH_ALW_LPBK_MASK); 7944 if (ret) 7945 return ret; 7946 } 7947 7948 switch (loop_mode) { 7949 case HNAE3_LOOP_APP: 7950 ret = hclge_set_app_loopback(hdev, en); 7951 break; 7952 case HNAE3_LOOP_SERIAL_SERDES: 7953 case HNAE3_LOOP_PARALLEL_SERDES: 7954 ret = hclge_set_common_loopback(hdev, en, loop_mode); 7955 break; 7956 case HNAE3_LOOP_PHY: 7957 ret = hclge_set_phy_loopback(hdev, en); 7958 break; 7959 case HNAE3_LOOP_EXTERNAL: 7960 break; 7961 default: 7962 ret = -ENOTSUPP; 7963 dev_err(&hdev->pdev->dev, 7964 "loop_mode %d is not supported\n", loop_mode); 7965 break; 7966 } 7967 7968 if (ret) 7969 return ret; 7970 7971 ret = hclge_tqp_enable(handle, en); 7972 if (ret) 7973 dev_err(&hdev->pdev->dev, "failed to %s tqp in loopback, ret = %d\n", 7974 en ? "enable" : "disable", ret); 7975 7976 return ret; 7977 } 7978 7979 static int hclge_set_default_loopback(struct hclge_dev *hdev) 7980 { 7981 int ret; 7982 7983 ret = hclge_set_app_loopback(hdev, false); 7984 if (ret) 7985 return ret; 7986 7987 ret = hclge_cfg_common_loopback(hdev, false, HNAE3_LOOP_SERIAL_SERDES); 7988 if (ret) 7989 return ret; 7990 7991 return hclge_cfg_common_loopback(hdev, false, 7992 HNAE3_LOOP_PARALLEL_SERDES); 7993 } 7994 7995 static void hclge_flush_link_update(struct hclge_dev *hdev) 7996 { 7997 #define HCLGE_FLUSH_LINK_TIMEOUT 100000 7998 7999 unsigned long last = hdev->serv_processed_cnt; 8000 int i = 0; 8001 8002 while (test_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state) && 8003 i++ < HCLGE_FLUSH_LINK_TIMEOUT && 8004 last == hdev->serv_processed_cnt) 8005 usleep_range(1, 1); 8006 } 8007 8008 static void hclge_set_timer_task(struct hnae3_handle *handle, bool enable) 8009 { 8010 struct hclge_vport *vport = hclge_get_vport(handle); 8011 struct hclge_dev *hdev = vport->back; 8012 8013 if (enable) { 8014 hclge_task_schedule(hdev, 0); 8015 } else { 8016 /* Set the DOWN flag here to disable link updating */ 8017 set_bit(HCLGE_STATE_DOWN, &hdev->state); 8018 8019 /* flush memory to make sure DOWN is seen by service task */ 8020 smp_mb__before_atomic(); 8021 hclge_flush_link_update(hdev); 8022 } 8023 } 8024 8025 static int hclge_ae_start(struct hnae3_handle *handle) 8026 { 8027 struct hclge_vport *vport = hclge_get_vport(handle); 8028 struct hclge_dev *hdev = vport->back; 8029 8030 /* mac enable */ 8031 hclge_cfg_mac_mode(hdev, true); 8032 clear_bit(HCLGE_STATE_DOWN, &hdev->state); 8033 hdev->hw.mac.link = 0; 8034 8035 /* reset tqp stats */ 8036 hclge_comm_reset_tqp_stats(handle); 8037 8038 hclge_mac_start_phy(hdev); 8039 8040 return 0; 8041 } 8042 8043 static void hclge_ae_stop(struct hnae3_handle *handle) 8044 { 8045 struct hclge_vport *vport = hclge_get_vport(handle); 8046 struct hclge_dev *hdev = vport->back; 8047 8048 set_bit(HCLGE_STATE_DOWN, &hdev->state); 8049 spin_lock_bh(&hdev->fd_rule_lock); 8050 hclge_clear_arfs_rules(hdev); 8051 spin_unlock_bh(&hdev->fd_rule_lock); 8052 8053 /* If it is not PF reset or FLR, the firmware will disable the MAC, 8054 * so it only need to stop phy here. 8055 */ 8056 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) && 8057 hdev->reset_type != HNAE3_FUNC_RESET && 8058 hdev->reset_type != HNAE3_FLR_RESET) { 8059 hclge_mac_stop_phy(hdev); 8060 hclge_update_link_status(hdev); 8061 return; 8062 } 8063 8064 hclge_reset_tqp(handle); 8065 8066 hclge_config_mac_tnl_int(hdev, false); 8067 8068 /* Mac disable */ 8069 hclge_cfg_mac_mode(hdev, false); 8070 8071 hclge_mac_stop_phy(hdev); 8072 8073 /* reset tqp stats */ 8074 hclge_comm_reset_tqp_stats(handle); 8075 hclge_update_link_status(hdev); 8076 } 8077 8078 int hclge_vport_start(struct hclge_vport *vport) 8079 { 8080 struct hclge_dev *hdev = vport->back; 8081 8082 set_bit(HCLGE_VPORT_STATE_INITED, &vport->state); 8083 set_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 8084 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 8085 vport->last_active_jiffies = jiffies; 8086 vport->need_notify = 0; 8087 8088 if (test_bit(vport->vport_id, hdev->vport_config_block)) { 8089 if (vport->vport_id) { 8090 hclge_restore_mac_table_common(vport); 8091 hclge_restore_vport_vlan_table(vport); 8092 } else { 8093 hclge_restore_hw_table(hdev); 8094 } 8095 } 8096 8097 clear_bit(vport->vport_id, hdev->vport_config_block); 8098 8099 return 0; 8100 } 8101 8102 void hclge_vport_stop(struct hclge_vport *vport) 8103 { 8104 clear_bit(HCLGE_VPORT_STATE_INITED, &vport->state); 8105 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 8106 vport->need_notify = 0; 8107 } 8108 8109 static int hclge_client_start(struct hnae3_handle *handle) 8110 { 8111 struct hclge_vport *vport = hclge_get_vport(handle); 8112 8113 return hclge_vport_start(vport); 8114 } 8115 8116 static void hclge_client_stop(struct hnae3_handle *handle) 8117 { 8118 struct hclge_vport *vport = hclge_get_vport(handle); 8119 8120 hclge_vport_stop(vport); 8121 } 8122 8123 static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport, 8124 u16 cmdq_resp, u8 resp_code, 8125 enum hclge_mac_vlan_tbl_opcode op) 8126 { 8127 struct hclge_dev *hdev = vport->back; 8128 8129 if (cmdq_resp) { 8130 dev_err(&hdev->pdev->dev, 8131 "cmdq execute failed for get_mac_vlan_cmd_status,status=%u.\n", 8132 cmdq_resp); 8133 return -EIO; 8134 } 8135 8136 if (op == HCLGE_MAC_VLAN_ADD) { 8137 if (!resp_code || resp_code == 1) 8138 return 0; 8139 else if (resp_code == HCLGE_ADD_UC_OVERFLOW || 8140 resp_code == HCLGE_ADD_MC_OVERFLOW) 8141 return -ENOSPC; 8142 8143 dev_err(&hdev->pdev->dev, 8144 "add mac addr failed for undefined, code=%u.\n", 8145 resp_code); 8146 return -EIO; 8147 } else if (op == HCLGE_MAC_VLAN_REMOVE) { 8148 if (!resp_code) { 8149 return 0; 8150 } else if (resp_code == 1) { 8151 dev_dbg(&hdev->pdev->dev, 8152 "remove mac addr failed for miss.\n"); 8153 return -ENOENT; 8154 } 8155 8156 dev_err(&hdev->pdev->dev, 8157 "remove mac addr failed for undefined, code=%u.\n", 8158 resp_code); 8159 return -EIO; 8160 } else if (op == HCLGE_MAC_VLAN_LKUP) { 8161 if (!resp_code) { 8162 return 0; 8163 } else if (resp_code == 1) { 8164 dev_dbg(&hdev->pdev->dev, 8165 "lookup mac addr failed for miss.\n"); 8166 return -ENOENT; 8167 } 8168 8169 dev_err(&hdev->pdev->dev, 8170 "lookup mac addr failed for undefined, code=%u.\n", 8171 resp_code); 8172 return -EIO; 8173 } 8174 8175 dev_err(&hdev->pdev->dev, 8176 "unknown opcode for get_mac_vlan_cmd_status, opcode=%d.\n", op); 8177 8178 return -EINVAL; 8179 } 8180 8181 static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr) 8182 { 8183 #define HCLGE_VF_NUM_IN_FIRST_DESC 192 8184 8185 unsigned int word_num; 8186 unsigned int bit_num; 8187 8188 if (vfid > 255 || vfid < 0) 8189 return -EIO; 8190 8191 if (vfid >= 0 && vfid < HCLGE_VF_NUM_IN_FIRST_DESC) { 8192 word_num = vfid / 32; 8193 bit_num = vfid % 32; 8194 if (clr) 8195 desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num)); 8196 else 8197 desc[1].data[word_num] |= cpu_to_le32(1 << bit_num); 8198 } else { 8199 word_num = (vfid - HCLGE_VF_NUM_IN_FIRST_DESC) / 32; 8200 bit_num = vfid % 32; 8201 if (clr) 8202 desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num)); 8203 else 8204 desc[2].data[word_num] |= cpu_to_le32(1 << bit_num); 8205 } 8206 8207 return 0; 8208 } 8209 8210 static bool hclge_is_all_function_id_zero(struct hclge_desc *desc) 8211 { 8212 #define HCLGE_DESC_NUMBER 3 8213 #define HCLGE_FUNC_NUMBER_PER_DESC 6 8214 int i, j; 8215 8216 for (i = 1; i < HCLGE_DESC_NUMBER; i++) 8217 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++) 8218 if (desc[i].data[j]) 8219 return false; 8220 8221 return true; 8222 } 8223 8224 static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req, 8225 const u8 *addr, bool is_mc) 8226 { 8227 const unsigned char *mac_addr = addr; 8228 u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) | 8229 (mac_addr[0]) | (mac_addr[1] << 8); 8230 u32 low_val = mac_addr[4] | (mac_addr[5] << 8); 8231 8232 hnae3_set_bit(new_req->flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 8233 if (is_mc) { 8234 hnae3_set_bit(new_req->entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1); 8235 hnae3_set_bit(new_req->mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 8236 } 8237 8238 new_req->mac_addr_hi32 = cpu_to_le32(high_val); 8239 new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff); 8240 } 8241 8242 static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport, 8243 struct hclge_mac_vlan_tbl_entry_cmd *req) 8244 { 8245 struct hclge_dev *hdev = vport->back; 8246 struct hclge_desc desc; 8247 u8 resp_code; 8248 u16 retval; 8249 int ret; 8250 8251 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false); 8252 8253 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8254 8255 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 8256 if (ret) { 8257 dev_err(&hdev->pdev->dev, 8258 "del mac addr failed for cmd_send, ret =%d.\n", 8259 ret); 8260 return ret; 8261 } 8262 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 8263 retval = le16_to_cpu(desc.retval); 8264 8265 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code, 8266 HCLGE_MAC_VLAN_REMOVE); 8267 } 8268 8269 static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport, 8270 struct hclge_mac_vlan_tbl_entry_cmd *req, 8271 struct hclge_desc *desc, 8272 bool is_mc) 8273 { 8274 struct hclge_dev *hdev = vport->back; 8275 u8 resp_code; 8276 u16 retval; 8277 int ret; 8278 8279 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true); 8280 if (is_mc) { 8281 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8282 memcpy(desc[0].data, 8283 req, 8284 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8285 hclge_cmd_setup_basic_desc(&desc[1], 8286 HCLGE_OPC_MAC_VLAN_ADD, 8287 true); 8288 desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8289 hclge_cmd_setup_basic_desc(&desc[2], 8290 HCLGE_OPC_MAC_VLAN_ADD, 8291 true); 8292 ret = hclge_cmd_send(&hdev->hw, desc, 3); 8293 } else { 8294 memcpy(desc[0].data, 8295 req, 8296 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8297 ret = hclge_cmd_send(&hdev->hw, desc, 1); 8298 } 8299 if (ret) { 8300 dev_err(&hdev->pdev->dev, 8301 "lookup mac addr failed for cmd_send, ret =%d.\n", 8302 ret); 8303 return ret; 8304 } 8305 resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff; 8306 retval = le16_to_cpu(desc[0].retval); 8307 8308 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code, 8309 HCLGE_MAC_VLAN_LKUP); 8310 } 8311 8312 static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport, 8313 struct hclge_mac_vlan_tbl_entry_cmd *req, 8314 struct hclge_desc *mc_desc) 8315 { 8316 struct hclge_dev *hdev = vport->back; 8317 int cfg_status; 8318 u8 resp_code; 8319 u16 retval; 8320 int ret; 8321 8322 if (!mc_desc) { 8323 struct hclge_desc desc; 8324 8325 hclge_cmd_setup_basic_desc(&desc, 8326 HCLGE_OPC_MAC_VLAN_ADD, 8327 false); 8328 memcpy(desc.data, req, 8329 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8330 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 8331 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 8332 retval = le16_to_cpu(desc.retval); 8333 8334 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval, 8335 resp_code, 8336 HCLGE_MAC_VLAN_ADD); 8337 } else { 8338 hclge_comm_cmd_reuse_desc(&mc_desc[0], false); 8339 mc_desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8340 hclge_comm_cmd_reuse_desc(&mc_desc[1], false); 8341 mc_desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8342 hclge_comm_cmd_reuse_desc(&mc_desc[2], false); 8343 mc_desc[2].flag &= cpu_to_le16(~HCLGE_COMM_CMD_FLAG_NEXT); 8344 memcpy(mc_desc[0].data, req, 8345 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8346 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3); 8347 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff; 8348 retval = le16_to_cpu(mc_desc[0].retval); 8349 8350 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval, 8351 resp_code, 8352 HCLGE_MAC_VLAN_ADD); 8353 } 8354 8355 if (ret) { 8356 dev_err(&hdev->pdev->dev, 8357 "add mac addr failed for cmd_send, ret =%d.\n", 8358 ret); 8359 return ret; 8360 } 8361 8362 return cfg_status; 8363 } 8364 8365 static int hclge_set_umv_space(struct hclge_dev *hdev, u16 space_size, 8366 u16 *allocated_size) 8367 { 8368 struct hclge_umv_spc_alc_cmd *req; 8369 struct hclge_desc desc; 8370 int ret; 8371 8372 req = (struct hclge_umv_spc_alc_cmd *)desc.data; 8373 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_ALLOCATE, false); 8374 8375 req->space_size = cpu_to_le32(space_size); 8376 8377 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 8378 if (ret) { 8379 dev_err(&hdev->pdev->dev, "failed to set umv space, ret = %d\n", 8380 ret); 8381 return ret; 8382 } 8383 8384 *allocated_size = le32_to_cpu(desc.data[1]); 8385 8386 return 0; 8387 } 8388 8389 static int hclge_init_umv_space(struct hclge_dev *hdev) 8390 { 8391 u16 allocated_size = 0; 8392 int ret; 8393 8394 ret = hclge_set_umv_space(hdev, hdev->wanted_umv_size, &allocated_size); 8395 if (ret) 8396 return ret; 8397 8398 if (allocated_size < hdev->wanted_umv_size) 8399 dev_warn(&hdev->pdev->dev, 8400 "failed to alloc umv space, want %u, get %u\n", 8401 hdev->wanted_umv_size, allocated_size); 8402 8403 hdev->max_umv_size = allocated_size; 8404 hdev->priv_umv_size = hdev->max_umv_size / (hdev->num_alloc_vport + 1); 8405 hdev->share_umv_size = hdev->priv_umv_size + 8406 hdev->max_umv_size % (hdev->num_alloc_vport + 1); 8407 8408 if (hdev->ae_dev->dev_specs.mc_mac_size) 8409 set_bit(HNAE3_DEV_SUPPORT_MC_MAC_MNG_B, hdev->ae_dev->caps); 8410 8411 return 0; 8412 } 8413 8414 static void hclge_reset_umv_space(struct hclge_dev *hdev) 8415 { 8416 struct hclge_vport *vport; 8417 int i; 8418 8419 for (i = 0; i < hdev->num_alloc_vport; i++) { 8420 vport = &hdev->vport[i]; 8421 vport->used_umv_num = 0; 8422 } 8423 8424 mutex_lock(&hdev->vport_lock); 8425 hdev->share_umv_size = hdev->priv_umv_size + 8426 hdev->max_umv_size % (hdev->num_alloc_vport + 1); 8427 mutex_unlock(&hdev->vport_lock); 8428 8429 hdev->used_mc_mac_num = 0; 8430 } 8431 8432 static bool hclge_is_umv_space_full(struct hclge_vport *vport, bool need_lock) 8433 { 8434 struct hclge_dev *hdev = vport->back; 8435 bool is_full; 8436 8437 if (need_lock) 8438 mutex_lock(&hdev->vport_lock); 8439 8440 is_full = (vport->used_umv_num >= hdev->priv_umv_size && 8441 hdev->share_umv_size == 0); 8442 8443 if (need_lock) 8444 mutex_unlock(&hdev->vport_lock); 8445 8446 return is_full; 8447 } 8448 8449 static void hclge_update_umv_space(struct hclge_vport *vport, bool is_free) 8450 { 8451 struct hclge_dev *hdev = vport->back; 8452 8453 if (is_free) { 8454 if (vport->used_umv_num > hdev->priv_umv_size) 8455 hdev->share_umv_size++; 8456 8457 if (vport->used_umv_num > 0) 8458 vport->used_umv_num--; 8459 } else { 8460 if (vport->used_umv_num >= hdev->priv_umv_size && 8461 hdev->share_umv_size > 0) 8462 hdev->share_umv_size--; 8463 vport->used_umv_num++; 8464 } 8465 } 8466 8467 static struct hclge_mac_node *hclge_find_mac_node(struct list_head *list, 8468 const u8 *mac_addr) 8469 { 8470 struct hclge_mac_node *mac_node, *tmp; 8471 8472 list_for_each_entry_safe(mac_node, tmp, list, node) 8473 if (ether_addr_equal(mac_addr, mac_node->mac_addr)) 8474 return mac_node; 8475 8476 return NULL; 8477 } 8478 8479 static void hclge_update_mac_node(struct hclge_mac_node *mac_node, 8480 enum HCLGE_MAC_NODE_STATE state) 8481 { 8482 switch (state) { 8483 /* from set_rx_mode or tmp_add_list */ 8484 case HCLGE_MAC_TO_ADD: 8485 if (mac_node->state == HCLGE_MAC_TO_DEL) 8486 mac_node->state = HCLGE_MAC_ACTIVE; 8487 break; 8488 /* only from set_rx_mode */ 8489 case HCLGE_MAC_TO_DEL: 8490 if (mac_node->state == HCLGE_MAC_TO_ADD) { 8491 list_del(&mac_node->node); 8492 kfree(mac_node); 8493 } else { 8494 mac_node->state = HCLGE_MAC_TO_DEL; 8495 } 8496 break; 8497 /* only from tmp_add_list, the mac_node->state won't be 8498 * ACTIVE. 8499 */ 8500 case HCLGE_MAC_ACTIVE: 8501 if (mac_node->state == HCLGE_MAC_TO_ADD) 8502 mac_node->state = HCLGE_MAC_ACTIVE; 8503 8504 break; 8505 } 8506 } 8507 8508 int hclge_update_mac_list(struct hclge_vport *vport, 8509 enum HCLGE_MAC_NODE_STATE state, 8510 enum HCLGE_MAC_ADDR_TYPE mac_type, 8511 const unsigned char *addr) 8512 { 8513 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8514 struct hclge_dev *hdev = vport->back; 8515 struct hclge_mac_node *mac_node; 8516 struct list_head *list; 8517 8518 list = (mac_type == HCLGE_MAC_ADDR_UC) ? 8519 &vport->uc_mac_list : &vport->mc_mac_list; 8520 8521 spin_lock_bh(&vport->mac_list_lock); 8522 8523 /* if the mac addr is already in the mac list, no need to add a new 8524 * one into it, just check the mac addr state, convert it to a new 8525 * state, or just remove it, or do nothing. 8526 */ 8527 mac_node = hclge_find_mac_node(list, addr); 8528 if (mac_node) { 8529 hclge_update_mac_node(mac_node, state); 8530 spin_unlock_bh(&vport->mac_list_lock); 8531 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 8532 return 0; 8533 } 8534 8535 /* if this address is never added, unnecessary to delete */ 8536 if (state == HCLGE_MAC_TO_DEL) { 8537 spin_unlock_bh(&vport->mac_list_lock); 8538 hnae3_format_mac_addr(format_mac_addr, addr); 8539 dev_err(&hdev->pdev->dev, 8540 "failed to delete address %s from mac list\n", 8541 format_mac_addr); 8542 return -ENOENT; 8543 } 8544 8545 mac_node = kzalloc(sizeof(*mac_node), GFP_ATOMIC); 8546 if (!mac_node) { 8547 spin_unlock_bh(&vport->mac_list_lock); 8548 return -ENOMEM; 8549 } 8550 8551 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 8552 8553 mac_node->state = state; 8554 ether_addr_copy(mac_node->mac_addr, addr); 8555 list_add_tail(&mac_node->node, list); 8556 8557 spin_unlock_bh(&vport->mac_list_lock); 8558 8559 return 0; 8560 } 8561 8562 static int hclge_add_uc_addr(struct hnae3_handle *handle, 8563 const unsigned char *addr) 8564 { 8565 struct hclge_vport *vport = hclge_get_vport(handle); 8566 8567 return hclge_update_mac_list(vport, HCLGE_MAC_TO_ADD, HCLGE_MAC_ADDR_UC, 8568 addr); 8569 } 8570 8571 int hclge_add_uc_addr_common(struct hclge_vport *vport, 8572 const unsigned char *addr) 8573 { 8574 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8575 struct hclge_dev *hdev = vport->back; 8576 struct hclge_mac_vlan_tbl_entry_cmd req; 8577 struct hclge_desc desc; 8578 u16 egress_port = 0; 8579 int ret; 8580 8581 /* mac addr check */ 8582 if (is_zero_ether_addr(addr) || 8583 is_broadcast_ether_addr(addr) || 8584 is_multicast_ether_addr(addr)) { 8585 hnae3_format_mac_addr(format_mac_addr, addr); 8586 dev_err(&hdev->pdev->dev, 8587 "Set_uc mac err! invalid mac:%s. is_zero:%d,is_br=%d,is_mul=%d\n", 8588 format_mac_addr, is_zero_ether_addr(addr), 8589 is_broadcast_ether_addr(addr), 8590 is_multicast_ether_addr(addr)); 8591 return -EINVAL; 8592 } 8593 8594 memset(&req, 0, sizeof(req)); 8595 8596 hnae3_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M, 8597 HCLGE_MAC_EPORT_VFID_S, vport->vport_id); 8598 8599 req.egress_port = cpu_to_le16(egress_port); 8600 8601 hclge_prepare_mac_addr(&req, addr, false); 8602 8603 /* Lookup the mac address in the mac_vlan table, and add 8604 * it if the entry is inexistent. Repeated unicast entry 8605 * is not allowed in the mac vlan table. 8606 */ 8607 ret = hclge_lookup_mac_vlan_tbl(vport, &req, &desc, false); 8608 if (ret == -ENOENT) { 8609 mutex_lock(&hdev->vport_lock); 8610 if (!hclge_is_umv_space_full(vport, false)) { 8611 ret = hclge_add_mac_vlan_tbl(vport, &req, NULL); 8612 if (!ret) 8613 hclge_update_umv_space(vport, false); 8614 mutex_unlock(&hdev->vport_lock); 8615 return ret; 8616 } 8617 mutex_unlock(&hdev->vport_lock); 8618 8619 if (!(vport->overflow_promisc_flags & HNAE3_OVERFLOW_UPE)) 8620 dev_err(&hdev->pdev->dev, "UC MAC table full(%u)\n", 8621 hdev->priv_umv_size); 8622 8623 return -ENOSPC; 8624 } 8625 8626 /* check if we just hit the duplicate */ 8627 if (!ret) 8628 return -EEXIST; 8629 8630 return ret; 8631 } 8632 8633 static int hclge_rm_uc_addr(struct hnae3_handle *handle, 8634 const unsigned char *addr) 8635 { 8636 struct hclge_vport *vport = hclge_get_vport(handle); 8637 8638 return hclge_update_mac_list(vport, HCLGE_MAC_TO_DEL, HCLGE_MAC_ADDR_UC, 8639 addr); 8640 } 8641 8642 int hclge_rm_uc_addr_common(struct hclge_vport *vport, 8643 const unsigned char *addr) 8644 { 8645 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8646 struct hclge_dev *hdev = vport->back; 8647 struct hclge_mac_vlan_tbl_entry_cmd req; 8648 int ret; 8649 8650 /* mac addr check */ 8651 if (is_zero_ether_addr(addr) || 8652 is_broadcast_ether_addr(addr) || 8653 is_multicast_ether_addr(addr)) { 8654 hnae3_format_mac_addr(format_mac_addr, addr); 8655 dev_dbg(&hdev->pdev->dev, "Remove mac err! invalid mac:%s.\n", 8656 format_mac_addr); 8657 return -EINVAL; 8658 } 8659 8660 memset(&req, 0, sizeof(req)); 8661 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0); 8662 hclge_prepare_mac_addr(&req, addr, false); 8663 ret = hclge_remove_mac_vlan_tbl(vport, &req); 8664 if (!ret || ret == -ENOENT) { 8665 mutex_lock(&hdev->vport_lock); 8666 hclge_update_umv_space(vport, true); 8667 mutex_unlock(&hdev->vport_lock); 8668 return 0; 8669 } 8670 8671 return ret; 8672 } 8673 8674 static int hclge_add_mc_addr(struct hnae3_handle *handle, 8675 const unsigned char *addr) 8676 { 8677 struct hclge_vport *vport = hclge_get_vport(handle); 8678 8679 return hclge_update_mac_list(vport, HCLGE_MAC_TO_ADD, HCLGE_MAC_ADDR_MC, 8680 addr); 8681 } 8682 8683 int hclge_add_mc_addr_common(struct hclge_vport *vport, 8684 const unsigned char *addr) 8685 { 8686 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8687 struct hclge_dev *hdev = vport->back; 8688 struct hclge_mac_vlan_tbl_entry_cmd req; 8689 struct hclge_desc desc[3]; 8690 bool is_new_addr = false; 8691 int status; 8692 8693 /* mac addr check */ 8694 if (!is_multicast_ether_addr(addr)) { 8695 hnae3_format_mac_addr(format_mac_addr, addr); 8696 dev_err(&hdev->pdev->dev, 8697 "Add mc mac err! invalid mac:%s.\n", 8698 format_mac_addr); 8699 return -EINVAL; 8700 } 8701 memset(&req, 0, sizeof(req)); 8702 hclge_prepare_mac_addr(&req, addr, true); 8703 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true); 8704 if (status) { 8705 if (hnae3_ae_dev_mc_mac_mng_supported(hdev->ae_dev) && 8706 hdev->used_mc_mac_num >= 8707 hdev->ae_dev->dev_specs.mc_mac_size) 8708 goto err_no_space; 8709 8710 is_new_addr = true; 8711 8712 /* This mac addr do not exist, add new entry for it */ 8713 memset(desc[0].data, 0, sizeof(desc[0].data)); 8714 memset(desc[1].data, 0, sizeof(desc[0].data)); 8715 memset(desc[2].data, 0, sizeof(desc[0].data)); 8716 } 8717 status = hclge_update_desc_vfid(desc, vport->vport_id, false); 8718 if (status) 8719 return status; 8720 status = hclge_add_mac_vlan_tbl(vport, &req, desc); 8721 if (status == -ENOSPC) 8722 goto err_no_space; 8723 else if (!status && is_new_addr) 8724 hdev->used_mc_mac_num++; 8725 8726 return status; 8727 8728 err_no_space: 8729 /* if already overflow, not to print each time */ 8730 if (!(vport->overflow_promisc_flags & HNAE3_OVERFLOW_MPE)) { 8731 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_MPE; 8732 dev_err(&hdev->pdev->dev, "mc mac vlan table is full\n"); 8733 } 8734 8735 return -ENOSPC; 8736 } 8737 8738 static int hclge_rm_mc_addr(struct hnae3_handle *handle, 8739 const unsigned char *addr) 8740 { 8741 struct hclge_vport *vport = hclge_get_vport(handle); 8742 8743 return hclge_update_mac_list(vport, HCLGE_MAC_TO_DEL, HCLGE_MAC_ADDR_MC, 8744 addr); 8745 } 8746 8747 int hclge_rm_mc_addr_common(struct hclge_vport *vport, 8748 const unsigned char *addr) 8749 { 8750 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8751 struct hclge_dev *hdev = vport->back; 8752 struct hclge_mac_vlan_tbl_entry_cmd req; 8753 enum hclge_comm_cmd_status status; 8754 struct hclge_desc desc[3]; 8755 8756 /* mac addr check */ 8757 if (!is_multicast_ether_addr(addr)) { 8758 hnae3_format_mac_addr(format_mac_addr, addr); 8759 dev_dbg(&hdev->pdev->dev, 8760 "Remove mc mac err! invalid mac:%s.\n", 8761 format_mac_addr); 8762 return -EINVAL; 8763 } 8764 8765 memset(&req, 0, sizeof(req)); 8766 hclge_prepare_mac_addr(&req, addr, true); 8767 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true); 8768 if (!status) { 8769 /* This mac addr exist, remove this handle's VFID for it */ 8770 status = hclge_update_desc_vfid(desc, vport->vport_id, true); 8771 if (status) 8772 return status; 8773 8774 if (hclge_is_all_function_id_zero(desc)) { 8775 /* All the vfid is zero, so need to delete this entry */ 8776 status = hclge_remove_mac_vlan_tbl(vport, &req); 8777 if (!status) 8778 hdev->used_mc_mac_num--; 8779 } else { 8780 /* Not all the vfid is zero, update the vfid */ 8781 status = hclge_add_mac_vlan_tbl(vport, &req, desc); 8782 } 8783 } else if (status == -ENOENT) { 8784 status = 0; 8785 } 8786 8787 return status; 8788 } 8789 8790 static void hclge_sync_vport_mac_list(struct hclge_vport *vport, 8791 struct list_head *list, 8792 enum HCLGE_MAC_ADDR_TYPE mac_type) 8793 { 8794 int (*sync)(struct hclge_vport *vport, const unsigned char *addr); 8795 struct hclge_mac_node *mac_node, *tmp; 8796 int ret; 8797 8798 if (mac_type == HCLGE_MAC_ADDR_UC) 8799 sync = hclge_add_uc_addr_common; 8800 else 8801 sync = hclge_add_mc_addr_common; 8802 8803 list_for_each_entry_safe(mac_node, tmp, list, node) { 8804 ret = sync(vport, mac_node->mac_addr); 8805 if (!ret) { 8806 mac_node->state = HCLGE_MAC_ACTIVE; 8807 } else { 8808 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, 8809 &vport->state); 8810 8811 /* If one unicast mac address is existing in hardware, 8812 * we need to try whether other unicast mac addresses 8813 * are new addresses that can be added. 8814 * Multicast mac address can be reusable, even though 8815 * there is no space to add new multicast mac address, 8816 * we should check whether other mac addresses are 8817 * existing in hardware for reuse. 8818 */ 8819 if ((mac_type == HCLGE_MAC_ADDR_UC && ret != -EEXIST) || 8820 (mac_type == HCLGE_MAC_ADDR_MC && ret != -ENOSPC)) 8821 break; 8822 } 8823 } 8824 } 8825 8826 static void hclge_unsync_vport_mac_list(struct hclge_vport *vport, 8827 struct list_head *list, 8828 enum HCLGE_MAC_ADDR_TYPE mac_type) 8829 { 8830 int (*unsync)(struct hclge_vport *vport, const unsigned char *addr); 8831 struct hclge_mac_node *mac_node, *tmp; 8832 int ret; 8833 8834 if (mac_type == HCLGE_MAC_ADDR_UC) 8835 unsync = hclge_rm_uc_addr_common; 8836 else 8837 unsync = hclge_rm_mc_addr_common; 8838 8839 list_for_each_entry_safe(mac_node, tmp, list, node) { 8840 ret = unsync(vport, mac_node->mac_addr); 8841 if (!ret || ret == -ENOENT) { 8842 list_del(&mac_node->node); 8843 kfree(mac_node); 8844 } else { 8845 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, 8846 &vport->state); 8847 break; 8848 } 8849 } 8850 } 8851 8852 static bool hclge_sync_from_add_list(struct list_head *add_list, 8853 struct list_head *mac_list) 8854 { 8855 struct hclge_mac_node *mac_node, *tmp, *new_node; 8856 bool all_added = true; 8857 8858 list_for_each_entry_safe(mac_node, tmp, add_list, node) { 8859 if (mac_node->state == HCLGE_MAC_TO_ADD) 8860 all_added = false; 8861 8862 /* if the mac address from tmp_add_list is not in the 8863 * uc/mc_mac_list, it means have received a TO_DEL request 8864 * during the time window of adding the mac address into mac 8865 * table. if mac_node state is ACTIVE, then change it to TO_DEL, 8866 * then it will be removed at next time. else it must be TO_ADD, 8867 * this address hasn't been added into mac table, 8868 * so just remove the mac node. 8869 */ 8870 new_node = hclge_find_mac_node(mac_list, mac_node->mac_addr); 8871 if (new_node) { 8872 hclge_update_mac_node(new_node, mac_node->state); 8873 list_del(&mac_node->node); 8874 kfree(mac_node); 8875 } else if (mac_node->state == HCLGE_MAC_ACTIVE) { 8876 mac_node->state = HCLGE_MAC_TO_DEL; 8877 list_move_tail(&mac_node->node, mac_list); 8878 } else { 8879 list_del(&mac_node->node); 8880 kfree(mac_node); 8881 } 8882 } 8883 8884 return all_added; 8885 } 8886 8887 static void hclge_sync_from_del_list(struct list_head *del_list, 8888 struct list_head *mac_list) 8889 { 8890 struct hclge_mac_node *mac_node, *tmp, *new_node; 8891 8892 list_for_each_entry_safe(mac_node, tmp, del_list, node) { 8893 new_node = hclge_find_mac_node(mac_list, mac_node->mac_addr); 8894 if (new_node) { 8895 /* If the mac addr exists in the mac list, it means 8896 * received a new TO_ADD request during the time window 8897 * of configuring the mac address. For the mac node 8898 * state is TO_ADD, and the address is already in the 8899 * in the hardware(due to delete fail), so we just need 8900 * to change the mac node state to ACTIVE. 8901 */ 8902 new_node->state = HCLGE_MAC_ACTIVE; 8903 list_del(&mac_node->node); 8904 kfree(mac_node); 8905 } else { 8906 list_move_tail(&mac_node->node, mac_list); 8907 } 8908 } 8909 } 8910 8911 static void hclge_update_overflow_flags(struct hclge_vport *vport, 8912 enum HCLGE_MAC_ADDR_TYPE mac_type, 8913 bool is_all_added) 8914 { 8915 if (mac_type == HCLGE_MAC_ADDR_UC) { 8916 if (is_all_added) 8917 vport->overflow_promisc_flags &= ~HNAE3_OVERFLOW_UPE; 8918 else 8919 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_UPE; 8920 } else { 8921 if (is_all_added) 8922 vport->overflow_promisc_flags &= ~HNAE3_OVERFLOW_MPE; 8923 else 8924 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_MPE; 8925 } 8926 } 8927 8928 static void hclge_sync_vport_mac_table(struct hclge_vport *vport, 8929 enum HCLGE_MAC_ADDR_TYPE mac_type) 8930 { 8931 struct hclge_mac_node *mac_node, *tmp, *new_node; 8932 struct list_head tmp_add_list, tmp_del_list; 8933 struct list_head *list; 8934 bool all_added; 8935 8936 INIT_LIST_HEAD(&tmp_add_list); 8937 INIT_LIST_HEAD(&tmp_del_list); 8938 8939 /* move the mac addr to the tmp_add_list and tmp_del_list, then 8940 * we can add/delete these mac addr outside the spin lock 8941 */ 8942 list = (mac_type == HCLGE_MAC_ADDR_UC) ? 8943 &vport->uc_mac_list : &vport->mc_mac_list; 8944 8945 spin_lock_bh(&vport->mac_list_lock); 8946 8947 list_for_each_entry_safe(mac_node, tmp, list, node) { 8948 switch (mac_node->state) { 8949 case HCLGE_MAC_TO_DEL: 8950 list_move_tail(&mac_node->node, &tmp_del_list); 8951 break; 8952 case HCLGE_MAC_TO_ADD: 8953 new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC); 8954 if (!new_node) 8955 goto stop_traverse; 8956 ether_addr_copy(new_node->mac_addr, mac_node->mac_addr); 8957 new_node->state = mac_node->state; 8958 list_add_tail(&new_node->node, &tmp_add_list); 8959 break; 8960 default: 8961 break; 8962 } 8963 } 8964 8965 stop_traverse: 8966 spin_unlock_bh(&vport->mac_list_lock); 8967 8968 /* delete first, in order to get max mac table space for adding */ 8969 hclge_unsync_vport_mac_list(vport, &tmp_del_list, mac_type); 8970 hclge_sync_vport_mac_list(vport, &tmp_add_list, mac_type); 8971 8972 /* if some mac addresses were added/deleted fail, move back to the 8973 * mac_list, and retry at next time. 8974 */ 8975 spin_lock_bh(&vport->mac_list_lock); 8976 8977 hclge_sync_from_del_list(&tmp_del_list, list); 8978 all_added = hclge_sync_from_add_list(&tmp_add_list, list); 8979 8980 spin_unlock_bh(&vport->mac_list_lock); 8981 8982 hclge_update_overflow_flags(vport, mac_type, all_added); 8983 } 8984 8985 static bool hclge_need_sync_mac_table(struct hclge_vport *vport) 8986 { 8987 struct hclge_dev *hdev = vport->back; 8988 8989 if (test_bit(vport->vport_id, hdev->vport_config_block)) 8990 return false; 8991 8992 if (test_and_clear_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state)) 8993 return true; 8994 8995 return false; 8996 } 8997 8998 static void hclge_sync_mac_table(struct hclge_dev *hdev) 8999 { 9000 int i; 9001 9002 for (i = 0; i < hdev->num_alloc_vport; i++) { 9003 struct hclge_vport *vport = &hdev->vport[i]; 9004 9005 if (!hclge_need_sync_mac_table(vport)) 9006 continue; 9007 9008 hclge_sync_vport_mac_table(vport, HCLGE_MAC_ADDR_UC); 9009 hclge_sync_vport_mac_table(vport, HCLGE_MAC_ADDR_MC); 9010 } 9011 } 9012 9013 static void hclge_build_del_list(struct list_head *list, 9014 bool is_del_list, 9015 struct list_head *tmp_del_list) 9016 { 9017 struct hclge_mac_node *mac_cfg, *tmp; 9018 9019 list_for_each_entry_safe(mac_cfg, tmp, list, node) { 9020 switch (mac_cfg->state) { 9021 case HCLGE_MAC_TO_DEL: 9022 case HCLGE_MAC_ACTIVE: 9023 list_move_tail(&mac_cfg->node, tmp_del_list); 9024 break; 9025 case HCLGE_MAC_TO_ADD: 9026 if (is_del_list) { 9027 list_del(&mac_cfg->node); 9028 kfree(mac_cfg); 9029 } 9030 break; 9031 } 9032 } 9033 } 9034 9035 static void hclge_unsync_del_list(struct hclge_vport *vport, 9036 int (*unsync)(struct hclge_vport *vport, 9037 const unsigned char *addr), 9038 bool is_del_list, 9039 struct list_head *tmp_del_list) 9040 { 9041 struct hclge_mac_node *mac_cfg, *tmp; 9042 int ret; 9043 9044 list_for_each_entry_safe(mac_cfg, tmp, tmp_del_list, node) { 9045 ret = unsync(vport, mac_cfg->mac_addr); 9046 if (!ret || ret == -ENOENT) { 9047 /* clear all mac addr from hardware, but remain these 9048 * mac addr in the mac list, and restore them after 9049 * vf reset finished. 9050 */ 9051 if (!is_del_list && 9052 mac_cfg->state == HCLGE_MAC_ACTIVE) { 9053 mac_cfg->state = HCLGE_MAC_TO_ADD; 9054 } else { 9055 list_del(&mac_cfg->node); 9056 kfree(mac_cfg); 9057 } 9058 } else if (is_del_list) { 9059 mac_cfg->state = HCLGE_MAC_TO_DEL; 9060 } 9061 } 9062 } 9063 9064 void hclge_rm_vport_all_mac_table(struct hclge_vport *vport, bool is_del_list, 9065 enum HCLGE_MAC_ADDR_TYPE mac_type) 9066 { 9067 int (*unsync)(struct hclge_vport *vport, const unsigned char *addr); 9068 struct hclge_dev *hdev = vport->back; 9069 struct list_head tmp_del_list, *list; 9070 9071 if (mac_type == HCLGE_MAC_ADDR_UC) { 9072 list = &vport->uc_mac_list; 9073 unsync = hclge_rm_uc_addr_common; 9074 } else { 9075 list = &vport->mc_mac_list; 9076 unsync = hclge_rm_mc_addr_common; 9077 } 9078 9079 INIT_LIST_HEAD(&tmp_del_list); 9080 9081 if (!is_del_list) 9082 set_bit(vport->vport_id, hdev->vport_config_block); 9083 9084 spin_lock_bh(&vport->mac_list_lock); 9085 9086 hclge_build_del_list(list, is_del_list, &tmp_del_list); 9087 9088 spin_unlock_bh(&vport->mac_list_lock); 9089 9090 hclge_unsync_del_list(vport, unsync, is_del_list, &tmp_del_list); 9091 9092 spin_lock_bh(&vport->mac_list_lock); 9093 9094 hclge_sync_from_del_list(&tmp_del_list, list); 9095 9096 spin_unlock_bh(&vport->mac_list_lock); 9097 } 9098 9099 /* remove all mac address when uninitailize */ 9100 static void hclge_uninit_vport_mac_list(struct hclge_vport *vport, 9101 enum HCLGE_MAC_ADDR_TYPE mac_type) 9102 { 9103 struct hclge_mac_node *mac_node, *tmp; 9104 struct hclge_dev *hdev = vport->back; 9105 struct list_head tmp_del_list, *list; 9106 9107 INIT_LIST_HEAD(&tmp_del_list); 9108 9109 list = (mac_type == HCLGE_MAC_ADDR_UC) ? 9110 &vport->uc_mac_list : &vport->mc_mac_list; 9111 9112 spin_lock_bh(&vport->mac_list_lock); 9113 9114 list_for_each_entry_safe(mac_node, tmp, list, node) { 9115 switch (mac_node->state) { 9116 case HCLGE_MAC_TO_DEL: 9117 case HCLGE_MAC_ACTIVE: 9118 list_move_tail(&mac_node->node, &tmp_del_list); 9119 break; 9120 case HCLGE_MAC_TO_ADD: 9121 list_del(&mac_node->node); 9122 kfree(mac_node); 9123 break; 9124 } 9125 } 9126 9127 spin_unlock_bh(&vport->mac_list_lock); 9128 9129 hclge_unsync_vport_mac_list(vport, &tmp_del_list, mac_type); 9130 9131 if (!list_empty(&tmp_del_list)) 9132 dev_warn(&hdev->pdev->dev, 9133 "uninit %s mac list for vport %u not completely.\n", 9134 mac_type == HCLGE_MAC_ADDR_UC ? "uc" : "mc", 9135 vport->vport_id); 9136 9137 list_for_each_entry_safe(mac_node, tmp, &tmp_del_list, node) { 9138 list_del(&mac_node->node); 9139 kfree(mac_node); 9140 } 9141 } 9142 9143 static void hclge_uninit_mac_table(struct hclge_dev *hdev) 9144 { 9145 struct hclge_vport *vport; 9146 int i; 9147 9148 for (i = 0; i < hdev->num_alloc_vport; i++) { 9149 vport = &hdev->vport[i]; 9150 hclge_uninit_vport_mac_list(vport, HCLGE_MAC_ADDR_UC); 9151 hclge_uninit_vport_mac_list(vport, HCLGE_MAC_ADDR_MC); 9152 } 9153 } 9154 9155 static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev *hdev, 9156 u16 cmdq_resp, u8 resp_code) 9157 { 9158 #define HCLGE_ETHERTYPE_SUCCESS_ADD 0 9159 #define HCLGE_ETHERTYPE_ALREADY_ADD 1 9160 #define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW 2 9161 #define HCLGE_ETHERTYPE_KEY_CONFLICT 3 9162 9163 int return_status; 9164 9165 if (cmdq_resp) { 9166 dev_err(&hdev->pdev->dev, 9167 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n", 9168 cmdq_resp); 9169 return -EIO; 9170 } 9171 9172 switch (resp_code) { 9173 case HCLGE_ETHERTYPE_SUCCESS_ADD: 9174 case HCLGE_ETHERTYPE_ALREADY_ADD: 9175 return_status = 0; 9176 break; 9177 case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW: 9178 dev_err(&hdev->pdev->dev, 9179 "add mac ethertype failed for manager table overflow.\n"); 9180 return_status = -EIO; 9181 break; 9182 case HCLGE_ETHERTYPE_KEY_CONFLICT: 9183 dev_err(&hdev->pdev->dev, 9184 "add mac ethertype failed for key conflict.\n"); 9185 return_status = -EIO; 9186 break; 9187 default: 9188 dev_err(&hdev->pdev->dev, 9189 "add mac ethertype failed for undefined, code=%u.\n", 9190 resp_code); 9191 return_status = -EIO; 9192 } 9193 9194 return return_status; 9195 } 9196 9197 static int hclge_set_vf_mac(struct hnae3_handle *handle, int vf, 9198 u8 *mac_addr) 9199 { 9200 struct hclge_vport *vport = hclge_get_vport(handle); 9201 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 9202 struct hclge_dev *hdev = vport->back; 9203 9204 vport = hclge_get_vf_vport(hdev, vf); 9205 if (!vport) 9206 return -EINVAL; 9207 9208 hnae3_format_mac_addr(format_mac_addr, mac_addr); 9209 if (ether_addr_equal(mac_addr, vport->vf_info.mac)) { 9210 dev_info(&hdev->pdev->dev, 9211 "Specified MAC(=%s) is same as before, no change committed!\n", 9212 format_mac_addr); 9213 return 0; 9214 } 9215 9216 ether_addr_copy(vport->vf_info.mac, mac_addr); 9217 9218 /* there is a timewindow for PF to know VF unalive, it may 9219 * cause send mailbox fail, but it doesn't matter, VF will 9220 * query it when reinit. 9221 */ 9222 if (test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) { 9223 dev_info(&hdev->pdev->dev, 9224 "MAC of VF %d has been set to %s, and it will be reinitialized!\n", 9225 vf, format_mac_addr); 9226 (void)hclge_inform_reset_assert_to_vf(vport); 9227 return 0; 9228 } 9229 9230 dev_info(&hdev->pdev->dev, 9231 "MAC of VF %d has been set to %s, will be active after VF reset\n", 9232 vf, format_mac_addr); 9233 return 0; 9234 } 9235 9236 static int hclge_add_mgr_tbl(struct hclge_dev *hdev, 9237 const struct hclge_mac_mgr_tbl_entry_cmd *req) 9238 { 9239 struct hclge_desc desc; 9240 u8 resp_code; 9241 u16 retval; 9242 int ret; 9243 9244 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_ETHTYPE_ADD, false); 9245 memcpy(desc.data, req, sizeof(struct hclge_mac_mgr_tbl_entry_cmd)); 9246 9247 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9248 if (ret) { 9249 dev_err(&hdev->pdev->dev, 9250 "add mac ethertype failed for cmd_send, ret =%d.\n", 9251 ret); 9252 return ret; 9253 } 9254 9255 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 9256 retval = le16_to_cpu(desc.retval); 9257 9258 return hclge_get_mac_ethertype_cmd_status(hdev, retval, resp_code); 9259 } 9260 9261 static int init_mgr_tbl(struct hclge_dev *hdev) 9262 { 9263 int ret; 9264 int i; 9265 9266 for (i = 0; i < ARRAY_SIZE(hclge_mgr_table); i++) { 9267 ret = hclge_add_mgr_tbl(hdev, &hclge_mgr_table[i]); 9268 if (ret) { 9269 dev_err(&hdev->pdev->dev, 9270 "add mac ethertype failed, ret =%d.\n", 9271 ret); 9272 return ret; 9273 } 9274 } 9275 9276 return 0; 9277 } 9278 9279 static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p) 9280 { 9281 struct hclge_vport *vport = hclge_get_vport(handle); 9282 struct hclge_dev *hdev = vport->back; 9283 9284 ether_addr_copy(p, hdev->hw.mac.mac_addr); 9285 } 9286 9287 int hclge_update_mac_node_for_dev_addr(struct hclge_vport *vport, 9288 const u8 *old_addr, const u8 *new_addr) 9289 { 9290 struct list_head *list = &vport->uc_mac_list; 9291 struct hclge_mac_node *old_node, *new_node; 9292 9293 new_node = hclge_find_mac_node(list, new_addr); 9294 if (!new_node) { 9295 new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC); 9296 if (!new_node) 9297 return -ENOMEM; 9298 9299 new_node->state = HCLGE_MAC_TO_ADD; 9300 ether_addr_copy(new_node->mac_addr, new_addr); 9301 list_add(&new_node->node, list); 9302 } else { 9303 if (new_node->state == HCLGE_MAC_TO_DEL) 9304 new_node->state = HCLGE_MAC_ACTIVE; 9305 9306 /* make sure the new addr is in the list head, avoid dev 9307 * addr may be not re-added into mac table for the umv space 9308 * limitation after global/imp reset which will clear mac 9309 * table by hardware. 9310 */ 9311 list_move(&new_node->node, list); 9312 } 9313 9314 if (old_addr && !ether_addr_equal(old_addr, new_addr)) { 9315 old_node = hclge_find_mac_node(list, old_addr); 9316 if (old_node) { 9317 if (old_node->state == HCLGE_MAC_TO_ADD) { 9318 list_del(&old_node->node); 9319 kfree(old_node); 9320 } else { 9321 old_node->state = HCLGE_MAC_TO_DEL; 9322 } 9323 } 9324 } 9325 9326 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 9327 9328 return 0; 9329 } 9330 9331 static int hclge_set_mac_addr(struct hnae3_handle *handle, const void *p, 9332 bool is_first) 9333 { 9334 const unsigned char *new_addr = (const unsigned char *)p; 9335 struct hclge_vport *vport = hclge_get_vport(handle); 9336 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 9337 struct hclge_dev *hdev = vport->back; 9338 unsigned char *old_addr = NULL; 9339 int ret; 9340 9341 /* mac addr check */ 9342 if (is_zero_ether_addr(new_addr) || 9343 is_broadcast_ether_addr(new_addr) || 9344 is_multicast_ether_addr(new_addr)) { 9345 hnae3_format_mac_addr(format_mac_addr, new_addr); 9346 dev_err(&hdev->pdev->dev, 9347 "change uc mac err! invalid mac: %s.\n", 9348 format_mac_addr); 9349 return -EINVAL; 9350 } 9351 9352 ret = hclge_pause_addr_cfg(hdev, new_addr); 9353 if (ret) { 9354 dev_err(&hdev->pdev->dev, 9355 "failed to configure mac pause address, ret = %d\n", 9356 ret); 9357 return ret; 9358 } 9359 9360 if (!is_first) 9361 old_addr = hdev->hw.mac.mac_addr; 9362 9363 spin_lock_bh(&vport->mac_list_lock); 9364 ret = hclge_update_mac_node_for_dev_addr(vport, old_addr, new_addr); 9365 if (ret) { 9366 hnae3_format_mac_addr(format_mac_addr, new_addr); 9367 dev_err(&hdev->pdev->dev, 9368 "failed to change the mac addr:%s, ret = %d\n", 9369 format_mac_addr, ret); 9370 spin_unlock_bh(&vport->mac_list_lock); 9371 9372 if (!is_first) 9373 hclge_pause_addr_cfg(hdev, old_addr); 9374 9375 return ret; 9376 } 9377 /* we must update dev addr with spin lock protect, preventing dev addr 9378 * being removed by set_rx_mode path. 9379 */ 9380 ether_addr_copy(hdev->hw.mac.mac_addr, new_addr); 9381 spin_unlock_bh(&vport->mac_list_lock); 9382 9383 hclge_task_schedule(hdev, 0); 9384 9385 return 0; 9386 } 9387 9388 static int hclge_mii_ioctl(struct hclge_dev *hdev, struct ifreq *ifr, int cmd) 9389 { 9390 struct mii_ioctl_data *data = if_mii(ifr); 9391 9392 if (!hnae3_dev_phy_imp_supported(hdev)) 9393 return -EOPNOTSUPP; 9394 9395 switch (cmd) { 9396 case SIOCGMIIPHY: 9397 data->phy_id = hdev->hw.mac.phy_addr; 9398 /* this command reads phy id and register at the same time */ 9399 fallthrough; 9400 case SIOCGMIIREG: 9401 data->val_out = hclge_read_phy_reg(hdev, data->reg_num); 9402 return 0; 9403 9404 case SIOCSMIIREG: 9405 return hclge_write_phy_reg(hdev, data->reg_num, data->val_in); 9406 default: 9407 return -EOPNOTSUPP; 9408 } 9409 } 9410 9411 static int hclge_do_ioctl(struct hnae3_handle *handle, struct ifreq *ifr, 9412 int cmd) 9413 { 9414 struct hclge_vport *vport = hclge_get_vport(handle); 9415 struct hclge_dev *hdev = vport->back; 9416 9417 switch (cmd) { 9418 case SIOCGHWTSTAMP: 9419 return hclge_ptp_get_cfg(hdev, ifr); 9420 case SIOCSHWTSTAMP: 9421 return hclge_ptp_set_cfg(hdev, ifr); 9422 default: 9423 if (!hdev->hw.mac.phydev) 9424 return hclge_mii_ioctl(hdev, ifr, cmd); 9425 } 9426 9427 return phy_mii_ioctl(hdev->hw.mac.phydev, ifr, cmd); 9428 } 9429 9430 static int hclge_set_port_vlan_filter_bypass(struct hclge_dev *hdev, u8 vf_id, 9431 bool bypass_en) 9432 { 9433 struct hclge_port_vlan_filter_bypass_cmd *req; 9434 struct hclge_desc desc; 9435 int ret; 9436 9437 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PORT_VLAN_BYPASS, false); 9438 req = (struct hclge_port_vlan_filter_bypass_cmd *)desc.data; 9439 req->vf_id = vf_id; 9440 hnae3_set_bit(req->bypass_state, HCLGE_INGRESS_BYPASS_B, 9441 bypass_en ? 1 : 0); 9442 9443 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9444 if (ret) 9445 dev_err(&hdev->pdev->dev, 9446 "failed to set vport%u port vlan filter bypass state, ret = %d.\n", 9447 vf_id, ret); 9448 9449 return ret; 9450 } 9451 9452 static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type, 9453 u8 fe_type, bool filter_en, u8 vf_id) 9454 { 9455 struct hclge_vlan_filter_ctrl_cmd *req; 9456 struct hclge_desc desc; 9457 int ret; 9458 9459 /* read current vlan filter parameter */ 9460 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, true); 9461 req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data; 9462 req->vlan_type = vlan_type; 9463 req->vf_id = vf_id; 9464 9465 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9466 if (ret) { 9467 dev_err(&hdev->pdev->dev, "failed to get vport%u vlan filter config, ret = %d.\n", 9468 vf_id, ret); 9469 return ret; 9470 } 9471 9472 /* modify and write new config parameter */ 9473 hclge_comm_cmd_reuse_desc(&desc, false); 9474 req->vlan_fe = filter_en ? 9475 (req->vlan_fe | fe_type) : (req->vlan_fe & ~fe_type); 9476 9477 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9478 if (ret) 9479 dev_err(&hdev->pdev->dev, "failed to set vport%u vlan filter, ret = %d.\n", 9480 vf_id, ret); 9481 9482 return ret; 9483 } 9484 9485 static int hclge_set_vport_vlan_filter(struct hclge_vport *vport, bool enable) 9486 { 9487 struct hclge_dev *hdev = vport->back; 9488 struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 9489 int ret; 9490 9491 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 9492 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 9493 HCLGE_FILTER_FE_EGRESS_V1_B, 9494 enable, vport->vport_id); 9495 9496 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 9497 HCLGE_FILTER_FE_EGRESS, enable, 9498 vport->vport_id); 9499 if (ret) 9500 return ret; 9501 9502 if (test_bit(HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, ae_dev->caps)) { 9503 ret = hclge_set_port_vlan_filter_bypass(hdev, vport->vport_id, 9504 !enable); 9505 } else if (!vport->vport_id) { 9506 if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps)) 9507 enable = false; 9508 9509 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, 9510 HCLGE_FILTER_FE_INGRESS, 9511 enable, 0); 9512 } 9513 9514 return ret; 9515 } 9516 9517 static bool hclge_need_enable_vport_vlan_filter(struct hclge_vport *vport) 9518 { 9519 struct hnae3_handle *handle = &vport->nic; 9520 struct hclge_vport_vlan_cfg *vlan, *tmp; 9521 struct hclge_dev *hdev = vport->back; 9522 9523 if (vport->vport_id) { 9524 if (vport->port_base_vlan_cfg.state != 9525 HNAE3_PORT_BASE_VLAN_DISABLE) 9526 return true; 9527 9528 if (vport->vf_info.trusted && vport->vf_info.request_uc_en) 9529 return false; 9530 } else if (handle->netdev_flags & HNAE3_USER_UPE) { 9531 return false; 9532 } 9533 9534 if (!vport->req_vlan_fltr_en) 9535 return false; 9536 9537 /* compatible with former device, always enable vlan filter */ 9538 if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, hdev->ae_dev->caps)) 9539 return true; 9540 9541 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) 9542 if (vlan->vlan_id != 0) 9543 return true; 9544 9545 return false; 9546 } 9547 9548 int hclge_enable_vport_vlan_filter(struct hclge_vport *vport, bool request_en) 9549 { 9550 struct hclge_dev *hdev = vport->back; 9551 bool need_en; 9552 int ret; 9553 9554 mutex_lock(&hdev->vport_lock); 9555 9556 vport->req_vlan_fltr_en = request_en; 9557 9558 need_en = hclge_need_enable_vport_vlan_filter(vport); 9559 if (need_en == vport->cur_vlan_fltr_en) { 9560 mutex_unlock(&hdev->vport_lock); 9561 return 0; 9562 } 9563 9564 ret = hclge_set_vport_vlan_filter(vport, need_en); 9565 if (ret) { 9566 mutex_unlock(&hdev->vport_lock); 9567 return ret; 9568 } 9569 9570 vport->cur_vlan_fltr_en = need_en; 9571 9572 mutex_unlock(&hdev->vport_lock); 9573 9574 return 0; 9575 } 9576 9577 static int hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable) 9578 { 9579 struct hclge_vport *vport = hclge_get_vport(handle); 9580 9581 return hclge_enable_vport_vlan_filter(vport, enable); 9582 } 9583 9584 static int hclge_set_vf_vlan_filter_cmd(struct hclge_dev *hdev, u16 vfid, 9585 bool is_kill, u16 vlan, 9586 struct hclge_desc *desc) 9587 { 9588 struct hclge_vlan_filter_vf_cfg_cmd *req0; 9589 struct hclge_vlan_filter_vf_cfg_cmd *req1; 9590 u8 vf_byte_val; 9591 u8 vf_byte_off; 9592 int ret; 9593 9594 hclge_cmd_setup_basic_desc(&desc[0], 9595 HCLGE_OPC_VLAN_FILTER_VF_CFG, false); 9596 hclge_cmd_setup_basic_desc(&desc[1], 9597 HCLGE_OPC_VLAN_FILTER_VF_CFG, false); 9598 9599 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 9600 9601 vf_byte_off = vfid / 8; 9602 vf_byte_val = 1 << (vfid % 8); 9603 9604 req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data; 9605 req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data; 9606 9607 req0->vlan_id = cpu_to_le16(vlan); 9608 req0->vlan_cfg = is_kill; 9609 9610 if (vf_byte_off < HCLGE_MAX_VF_BYTES) 9611 req0->vf_bitmap[vf_byte_off] = vf_byte_val; 9612 else 9613 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val; 9614 9615 ret = hclge_cmd_send(&hdev->hw, desc, 2); 9616 if (ret) { 9617 dev_err(&hdev->pdev->dev, 9618 "Send vf vlan command fail, ret =%d.\n", 9619 ret); 9620 return ret; 9621 } 9622 9623 return 0; 9624 } 9625 9626 static int hclge_check_vf_vlan_cmd_status(struct hclge_dev *hdev, u16 vfid, 9627 bool is_kill, struct hclge_desc *desc) 9628 { 9629 struct hclge_vlan_filter_vf_cfg_cmd *req; 9630 9631 req = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data; 9632 9633 if (!is_kill) { 9634 #define HCLGE_VF_VLAN_NO_ENTRY 2 9635 if (!req->resp_code || req->resp_code == 1) 9636 return 0; 9637 9638 if (req->resp_code == HCLGE_VF_VLAN_NO_ENTRY) { 9639 set_bit(vfid, hdev->vf_vlan_full); 9640 dev_warn(&hdev->pdev->dev, 9641 "vf vlan table is full, vf vlan filter is disabled\n"); 9642 return 0; 9643 } 9644 9645 dev_err(&hdev->pdev->dev, 9646 "Add vf vlan filter fail, ret =%u.\n", 9647 req->resp_code); 9648 } else { 9649 #define HCLGE_VF_VLAN_DEL_NO_FOUND 1 9650 if (!req->resp_code) 9651 return 0; 9652 9653 /* vf vlan filter is disabled when vf vlan table is full, 9654 * then new vlan id will not be added into vf vlan table. 9655 * Just return 0 without warning, avoid massive verbose 9656 * print logs when unload. 9657 */ 9658 if (req->resp_code == HCLGE_VF_VLAN_DEL_NO_FOUND) 9659 return 0; 9660 9661 dev_err(&hdev->pdev->dev, 9662 "Kill vf vlan filter fail, ret =%u.\n", 9663 req->resp_code); 9664 } 9665 9666 return -EIO; 9667 } 9668 9669 static int hclge_set_vf_vlan_common(struct hclge_dev *hdev, u16 vfid, 9670 bool is_kill, u16 vlan) 9671 { 9672 struct hclge_vport *vport = &hdev->vport[vfid]; 9673 struct hclge_desc desc[2]; 9674 int ret; 9675 9676 /* if vf vlan table is full, firmware will close vf vlan filter, it 9677 * is unable and unnecessary to add new vlan id to vf vlan filter. 9678 * If spoof check is enable, and vf vlan is full, it shouldn't add 9679 * new vlan, because tx packets with these vlan id will be dropped. 9680 */ 9681 if (test_bit(vfid, hdev->vf_vlan_full) && !is_kill) { 9682 if (vport->vf_info.spoofchk && vlan) { 9683 dev_err(&hdev->pdev->dev, 9684 "Can't add vlan due to spoof check is on and vf vlan table is full\n"); 9685 return -EPERM; 9686 } 9687 return 0; 9688 } 9689 9690 ret = hclge_set_vf_vlan_filter_cmd(hdev, vfid, is_kill, vlan, desc); 9691 if (ret) 9692 return ret; 9693 9694 return hclge_check_vf_vlan_cmd_status(hdev, vfid, is_kill, desc); 9695 } 9696 9697 static int hclge_set_port_vlan_filter(struct hclge_dev *hdev, __be16 proto, 9698 u16 vlan_id, bool is_kill) 9699 { 9700 struct hclge_vlan_filter_pf_cfg_cmd *req; 9701 struct hclge_desc desc; 9702 u8 vlan_offset_byte_val; 9703 u8 vlan_offset_byte; 9704 u8 vlan_offset_160; 9705 int ret; 9706 9707 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false); 9708 9709 vlan_offset_160 = vlan_id / HCLGE_VLAN_ID_OFFSET_STEP; 9710 vlan_offset_byte = (vlan_id % HCLGE_VLAN_ID_OFFSET_STEP) / 9711 HCLGE_VLAN_BYTE_SIZE; 9712 vlan_offset_byte_val = 1 << (vlan_id % HCLGE_VLAN_BYTE_SIZE); 9713 9714 req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data; 9715 req->vlan_offset = vlan_offset_160; 9716 req->vlan_cfg = is_kill; 9717 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val; 9718 9719 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9720 if (ret) 9721 dev_err(&hdev->pdev->dev, 9722 "port vlan command, send fail, ret =%d.\n", ret); 9723 return ret; 9724 } 9725 9726 static bool hclge_need_update_port_vlan(struct hclge_dev *hdev, u16 vport_id, 9727 u16 vlan_id, bool is_kill) 9728 { 9729 /* vlan 0 may be added twice when 8021q module is enabled */ 9730 if (!is_kill && !vlan_id && 9731 test_bit(vport_id, hdev->vlan_table[vlan_id])) 9732 return false; 9733 9734 if (!is_kill && test_and_set_bit(vport_id, hdev->vlan_table[vlan_id])) { 9735 dev_warn(&hdev->pdev->dev, 9736 "Add port vlan failed, vport %u is already in vlan %u\n", 9737 vport_id, vlan_id); 9738 return false; 9739 } 9740 9741 if (is_kill && 9742 !test_and_clear_bit(vport_id, hdev->vlan_table[vlan_id])) { 9743 dev_warn(&hdev->pdev->dev, 9744 "Delete port vlan failed, vport %u is not in vlan %u\n", 9745 vport_id, vlan_id); 9746 return false; 9747 } 9748 9749 return true; 9750 } 9751 9752 static int hclge_set_vlan_filter_hw(struct hclge_dev *hdev, __be16 proto, 9753 u16 vport_id, u16 vlan_id, 9754 bool is_kill) 9755 { 9756 u16 vport_idx, vport_num = 0; 9757 int ret; 9758 9759 if (is_kill && !vlan_id) 9760 return 0; 9761 9762 if (vlan_id >= VLAN_N_VID) 9763 return -EINVAL; 9764 9765 ret = hclge_set_vf_vlan_common(hdev, vport_id, is_kill, vlan_id); 9766 if (ret) { 9767 dev_err(&hdev->pdev->dev, 9768 "Set %u vport vlan filter config fail, ret =%d.\n", 9769 vport_id, ret); 9770 return ret; 9771 } 9772 9773 if (!hclge_need_update_port_vlan(hdev, vport_id, vlan_id, is_kill)) 9774 return 0; 9775 9776 for_each_set_bit(vport_idx, hdev->vlan_table[vlan_id], HCLGE_VPORT_NUM) 9777 vport_num++; 9778 9779 if ((is_kill && vport_num == 0) || (!is_kill && vport_num == 1)) 9780 ret = hclge_set_port_vlan_filter(hdev, proto, vlan_id, 9781 is_kill); 9782 9783 return ret; 9784 } 9785 9786 static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport) 9787 { 9788 struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg; 9789 struct hclge_vport_vtag_tx_cfg_cmd *req; 9790 struct hclge_dev *hdev = vport->back; 9791 struct hclge_desc desc; 9792 u16 bmap_index; 9793 int status; 9794 9795 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false); 9796 9797 req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data; 9798 req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1); 9799 req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2); 9800 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG1_B, 9801 vcfg->accept_tag1 ? 1 : 0); 9802 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG1_B, 9803 vcfg->accept_untag1 ? 1 : 0); 9804 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG2_B, 9805 vcfg->accept_tag2 ? 1 : 0); 9806 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG2_B, 9807 vcfg->accept_untag2 ? 1 : 0); 9808 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B, 9809 vcfg->insert_tag1_en ? 1 : 0); 9810 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B, 9811 vcfg->insert_tag2_en ? 1 : 0); 9812 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_TAG_SHIFT_MODE_EN_B, 9813 vcfg->tag_shift_mode_en ? 1 : 0); 9814 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0); 9815 9816 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD; 9817 bmap_index = vport->vport_id % HCLGE_VF_NUM_PER_CMD / 9818 HCLGE_VF_NUM_PER_BYTE; 9819 req->vf_bitmap[bmap_index] = 9820 1U << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE); 9821 9822 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9823 if (status) 9824 dev_err(&hdev->pdev->dev, 9825 "Send port txvlan cfg command fail, ret =%d\n", 9826 status); 9827 9828 return status; 9829 } 9830 9831 static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport) 9832 { 9833 struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg; 9834 struct hclge_vport_vtag_rx_cfg_cmd *req; 9835 struct hclge_dev *hdev = vport->back; 9836 struct hclge_desc desc; 9837 u16 bmap_index; 9838 int status; 9839 9840 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false); 9841 9842 req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data; 9843 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B, 9844 vcfg->strip_tag1_en ? 1 : 0); 9845 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B, 9846 vcfg->strip_tag2_en ? 1 : 0); 9847 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B, 9848 vcfg->vlan1_vlan_prionly ? 1 : 0); 9849 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B, 9850 vcfg->vlan2_vlan_prionly ? 1 : 0); 9851 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_DISCARD_TAG1_EN_B, 9852 vcfg->strip_tag1_discard_en ? 1 : 0); 9853 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_DISCARD_TAG2_EN_B, 9854 vcfg->strip_tag2_discard_en ? 1 : 0); 9855 9856 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD; 9857 bmap_index = vport->vport_id % HCLGE_VF_NUM_PER_CMD / 9858 HCLGE_VF_NUM_PER_BYTE; 9859 req->vf_bitmap[bmap_index] = 9860 1U << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE); 9861 9862 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9863 if (status) 9864 dev_err(&hdev->pdev->dev, 9865 "Send port rxvlan cfg command fail, ret =%d\n", 9866 status); 9867 9868 return status; 9869 } 9870 9871 static int hclge_vlan_offload_cfg(struct hclge_vport *vport, 9872 u16 port_base_vlan_state, 9873 u16 vlan_tag, u8 qos) 9874 { 9875 int ret; 9876 9877 if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) { 9878 vport->txvlan_cfg.accept_tag1 = true; 9879 vport->txvlan_cfg.insert_tag1_en = false; 9880 vport->txvlan_cfg.default_tag1 = 0; 9881 } else { 9882 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(vport->nic.pdev); 9883 9884 vport->txvlan_cfg.accept_tag1 = 9885 ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3; 9886 vport->txvlan_cfg.insert_tag1_en = true; 9887 vport->txvlan_cfg.default_tag1 = (qos << VLAN_PRIO_SHIFT) | 9888 vlan_tag; 9889 } 9890 9891 vport->txvlan_cfg.accept_untag1 = true; 9892 9893 /* accept_tag2 and accept_untag2 are not supported on 9894 * pdev revision(0x20), new revision support them, 9895 * this two fields can not be configured by user. 9896 */ 9897 vport->txvlan_cfg.accept_tag2 = true; 9898 vport->txvlan_cfg.accept_untag2 = true; 9899 vport->txvlan_cfg.insert_tag2_en = false; 9900 vport->txvlan_cfg.default_tag2 = 0; 9901 vport->txvlan_cfg.tag_shift_mode_en = true; 9902 9903 if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) { 9904 vport->rxvlan_cfg.strip_tag1_en = false; 9905 vport->rxvlan_cfg.strip_tag2_en = 9906 vport->rxvlan_cfg.rx_vlan_offload_en; 9907 vport->rxvlan_cfg.strip_tag2_discard_en = false; 9908 } else { 9909 vport->rxvlan_cfg.strip_tag1_en = 9910 vport->rxvlan_cfg.rx_vlan_offload_en; 9911 vport->rxvlan_cfg.strip_tag2_en = true; 9912 vport->rxvlan_cfg.strip_tag2_discard_en = true; 9913 } 9914 9915 vport->rxvlan_cfg.strip_tag1_discard_en = false; 9916 vport->rxvlan_cfg.vlan1_vlan_prionly = false; 9917 vport->rxvlan_cfg.vlan2_vlan_prionly = false; 9918 9919 ret = hclge_set_vlan_tx_offload_cfg(vport); 9920 if (ret) 9921 return ret; 9922 9923 return hclge_set_vlan_rx_offload_cfg(vport); 9924 } 9925 9926 static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev) 9927 { 9928 struct hclge_rx_vlan_type_cfg_cmd *rx_req; 9929 struct hclge_tx_vlan_type_cfg_cmd *tx_req; 9930 struct hclge_desc desc; 9931 int status; 9932 9933 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false); 9934 rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data; 9935 rx_req->ot_fst_vlan_type = 9936 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type); 9937 rx_req->ot_sec_vlan_type = 9938 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type); 9939 rx_req->in_fst_vlan_type = 9940 cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type); 9941 rx_req->in_sec_vlan_type = 9942 cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type); 9943 9944 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9945 if (status) { 9946 dev_err(&hdev->pdev->dev, 9947 "Send rxvlan protocol type command fail, ret =%d\n", 9948 status); 9949 return status; 9950 } 9951 9952 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false); 9953 9954 tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)desc.data; 9955 tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type); 9956 tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type); 9957 9958 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9959 if (status) 9960 dev_err(&hdev->pdev->dev, 9961 "Send txvlan protocol type command fail, ret =%d\n", 9962 status); 9963 9964 return status; 9965 } 9966 9967 static int hclge_init_vlan_filter(struct hclge_dev *hdev) 9968 { 9969 struct hclge_vport *vport; 9970 int ret; 9971 int i; 9972 9973 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 9974 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 9975 HCLGE_FILTER_FE_EGRESS_V1_B, 9976 true, 0); 9977 9978 /* for revision 0x21, vf vlan filter is per function */ 9979 for (i = 0; i < hdev->num_alloc_vport; i++) { 9980 vport = &hdev->vport[i]; 9981 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 9982 HCLGE_FILTER_FE_EGRESS, true, 9983 vport->vport_id); 9984 if (ret) 9985 return ret; 9986 vport->cur_vlan_fltr_en = true; 9987 } 9988 9989 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, 9990 HCLGE_FILTER_FE_INGRESS, true, 0); 9991 } 9992 9993 static int hclge_init_vlan_type(struct hclge_dev *hdev) 9994 { 9995 hdev->vlan_type_cfg.rx_in_fst_vlan_type = ETH_P_8021Q; 9996 hdev->vlan_type_cfg.rx_in_sec_vlan_type = ETH_P_8021Q; 9997 hdev->vlan_type_cfg.rx_ot_fst_vlan_type = ETH_P_8021Q; 9998 hdev->vlan_type_cfg.rx_ot_sec_vlan_type = ETH_P_8021Q; 9999 hdev->vlan_type_cfg.tx_ot_vlan_type = ETH_P_8021Q; 10000 hdev->vlan_type_cfg.tx_in_vlan_type = ETH_P_8021Q; 10001 10002 return hclge_set_vlan_protocol_type(hdev); 10003 } 10004 10005 static int hclge_init_vport_vlan_offload(struct hclge_dev *hdev) 10006 { 10007 struct hclge_port_base_vlan_config *cfg; 10008 struct hclge_vport *vport; 10009 int ret; 10010 int i; 10011 10012 for (i = 0; i < hdev->num_alloc_vport; i++) { 10013 vport = &hdev->vport[i]; 10014 cfg = &vport->port_base_vlan_cfg; 10015 10016 ret = hclge_vlan_offload_cfg(vport, cfg->state, 10017 cfg->vlan_info.vlan_tag, 10018 cfg->vlan_info.qos); 10019 if (ret) 10020 return ret; 10021 } 10022 return 0; 10023 } 10024 10025 static int hclge_init_vlan_config(struct hclge_dev *hdev) 10026 { 10027 struct hnae3_handle *handle = &hdev->vport[0].nic; 10028 int ret; 10029 10030 ret = hclge_init_vlan_filter(hdev); 10031 if (ret) 10032 return ret; 10033 10034 ret = hclge_init_vlan_type(hdev); 10035 if (ret) 10036 return ret; 10037 10038 ret = hclge_init_vport_vlan_offload(hdev); 10039 if (ret) 10040 return ret; 10041 10042 return hclge_set_vlan_filter(handle, htons(ETH_P_8021Q), 0, false); 10043 } 10044 10045 static void hclge_add_vport_vlan_table(struct hclge_vport *vport, u16 vlan_id, 10046 bool writen_to_tbl) 10047 { 10048 struct hclge_vport_vlan_cfg *vlan, *tmp; 10049 struct hclge_dev *hdev = vport->back; 10050 10051 mutex_lock(&hdev->vport_lock); 10052 10053 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10054 if (vlan->vlan_id == vlan_id) { 10055 mutex_unlock(&hdev->vport_lock); 10056 return; 10057 } 10058 } 10059 10060 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL); 10061 if (!vlan) { 10062 mutex_unlock(&hdev->vport_lock); 10063 return; 10064 } 10065 10066 vlan->hd_tbl_status = writen_to_tbl; 10067 vlan->vlan_id = vlan_id; 10068 10069 list_add_tail(&vlan->node, &vport->vlan_list); 10070 mutex_unlock(&hdev->vport_lock); 10071 } 10072 10073 static int hclge_add_vport_all_vlan_table(struct hclge_vport *vport) 10074 { 10075 struct hclge_vport_vlan_cfg *vlan, *tmp; 10076 struct hclge_dev *hdev = vport->back; 10077 int ret; 10078 10079 mutex_lock(&hdev->vport_lock); 10080 10081 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10082 if (!vlan->hd_tbl_status) { 10083 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10084 vport->vport_id, 10085 vlan->vlan_id, false); 10086 if (ret) { 10087 dev_err(&hdev->pdev->dev, 10088 "restore vport vlan list failed, ret=%d\n", 10089 ret); 10090 10091 mutex_unlock(&hdev->vport_lock); 10092 return ret; 10093 } 10094 } 10095 vlan->hd_tbl_status = true; 10096 } 10097 10098 mutex_unlock(&hdev->vport_lock); 10099 10100 return 0; 10101 } 10102 10103 static void hclge_rm_vport_vlan_table(struct hclge_vport *vport, u16 vlan_id, 10104 bool is_write_tbl) 10105 { 10106 struct hclge_vport_vlan_cfg *vlan, *tmp; 10107 struct hclge_dev *hdev = vport->back; 10108 10109 mutex_lock(&hdev->vport_lock); 10110 10111 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10112 if (vlan->vlan_id == vlan_id) { 10113 if (is_write_tbl && vlan->hd_tbl_status) 10114 hclge_set_vlan_filter_hw(hdev, 10115 htons(ETH_P_8021Q), 10116 vport->vport_id, 10117 vlan_id, 10118 true); 10119 10120 list_del(&vlan->node); 10121 kfree(vlan); 10122 break; 10123 } 10124 } 10125 10126 mutex_unlock(&hdev->vport_lock); 10127 } 10128 10129 void hclge_rm_vport_all_vlan_table(struct hclge_vport *vport, bool is_del_list) 10130 { 10131 struct hclge_vport_vlan_cfg *vlan, *tmp; 10132 struct hclge_dev *hdev = vport->back; 10133 10134 mutex_lock(&hdev->vport_lock); 10135 10136 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10137 if (vlan->hd_tbl_status) 10138 hclge_set_vlan_filter_hw(hdev, 10139 htons(ETH_P_8021Q), 10140 vport->vport_id, 10141 vlan->vlan_id, 10142 true); 10143 10144 vlan->hd_tbl_status = false; 10145 if (is_del_list) { 10146 list_del(&vlan->node); 10147 kfree(vlan); 10148 } 10149 } 10150 clear_bit(vport->vport_id, hdev->vf_vlan_full); 10151 mutex_unlock(&hdev->vport_lock); 10152 } 10153 10154 void hclge_uninit_vport_vlan_table(struct hclge_dev *hdev) 10155 { 10156 struct hclge_vport_vlan_cfg *vlan, *tmp; 10157 struct hclge_vport *vport; 10158 int i; 10159 10160 mutex_lock(&hdev->vport_lock); 10161 10162 for (i = 0; i < hdev->num_alloc_vport; i++) { 10163 vport = &hdev->vport[i]; 10164 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10165 list_del(&vlan->node); 10166 kfree(vlan); 10167 } 10168 } 10169 10170 mutex_unlock(&hdev->vport_lock); 10171 } 10172 10173 void hclge_restore_vport_port_base_vlan_config(struct hclge_dev *hdev) 10174 { 10175 struct hclge_vlan_info *vlan_info; 10176 struct hclge_vport *vport; 10177 u16 vlan_proto; 10178 u16 vlan_id; 10179 u16 state; 10180 int vf_id; 10181 int ret; 10182 10183 /* PF should restore all vfs port base vlan */ 10184 for (vf_id = 0; vf_id < hdev->num_alloc_vfs; vf_id++) { 10185 vport = &hdev->vport[vf_id + HCLGE_VF_VPORT_START_NUM]; 10186 vlan_info = vport->port_base_vlan_cfg.tbl_sta ? 10187 &vport->port_base_vlan_cfg.vlan_info : 10188 &vport->port_base_vlan_cfg.old_vlan_info; 10189 10190 vlan_id = vlan_info->vlan_tag; 10191 vlan_proto = vlan_info->vlan_proto; 10192 state = vport->port_base_vlan_cfg.state; 10193 10194 if (state != HNAE3_PORT_BASE_VLAN_DISABLE) { 10195 clear_bit(vport->vport_id, hdev->vlan_table[vlan_id]); 10196 ret = hclge_set_vlan_filter_hw(hdev, htons(vlan_proto), 10197 vport->vport_id, 10198 vlan_id, false); 10199 vport->port_base_vlan_cfg.tbl_sta = ret == 0; 10200 } 10201 } 10202 } 10203 10204 void hclge_restore_vport_vlan_table(struct hclge_vport *vport) 10205 { 10206 struct hclge_vport_vlan_cfg *vlan, *tmp; 10207 struct hclge_dev *hdev = vport->back; 10208 int ret; 10209 10210 mutex_lock(&hdev->vport_lock); 10211 10212 if (vport->port_base_vlan_cfg.state == HNAE3_PORT_BASE_VLAN_DISABLE) { 10213 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10214 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10215 vport->vport_id, 10216 vlan->vlan_id, false); 10217 if (ret) 10218 break; 10219 vlan->hd_tbl_status = true; 10220 } 10221 } 10222 10223 mutex_unlock(&hdev->vport_lock); 10224 } 10225 10226 /* For global reset and imp reset, hardware will clear the mac table, 10227 * so we change the mac address state from ACTIVE to TO_ADD, then they 10228 * can be restored in the service task after reset complete. Furtherly, 10229 * the mac addresses with state TO_DEL or DEL_FAIL are unnecessary to 10230 * be restored after reset, so just remove these mac nodes from mac_list. 10231 */ 10232 static void hclge_mac_node_convert_for_reset(struct list_head *list) 10233 { 10234 struct hclge_mac_node *mac_node, *tmp; 10235 10236 list_for_each_entry_safe(mac_node, tmp, list, node) { 10237 if (mac_node->state == HCLGE_MAC_ACTIVE) { 10238 mac_node->state = HCLGE_MAC_TO_ADD; 10239 } else if (mac_node->state == HCLGE_MAC_TO_DEL) { 10240 list_del(&mac_node->node); 10241 kfree(mac_node); 10242 } 10243 } 10244 } 10245 10246 void hclge_restore_mac_table_common(struct hclge_vport *vport) 10247 { 10248 spin_lock_bh(&vport->mac_list_lock); 10249 10250 hclge_mac_node_convert_for_reset(&vport->uc_mac_list); 10251 hclge_mac_node_convert_for_reset(&vport->mc_mac_list); 10252 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 10253 10254 spin_unlock_bh(&vport->mac_list_lock); 10255 } 10256 10257 static void hclge_restore_hw_table(struct hclge_dev *hdev) 10258 { 10259 struct hclge_vport *vport = &hdev->vport[0]; 10260 struct hnae3_handle *handle = &vport->nic; 10261 10262 hclge_restore_mac_table_common(vport); 10263 hclge_restore_vport_port_base_vlan_config(hdev); 10264 hclge_restore_vport_vlan_table(vport); 10265 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 10266 hclge_restore_fd_entries(handle); 10267 } 10268 10269 int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 10270 { 10271 struct hclge_vport *vport = hclge_get_vport(handle); 10272 10273 if (vport->port_base_vlan_cfg.state == HNAE3_PORT_BASE_VLAN_DISABLE) { 10274 vport->rxvlan_cfg.strip_tag1_en = false; 10275 vport->rxvlan_cfg.strip_tag2_en = enable; 10276 vport->rxvlan_cfg.strip_tag2_discard_en = false; 10277 } else { 10278 vport->rxvlan_cfg.strip_tag1_en = enable; 10279 vport->rxvlan_cfg.strip_tag2_en = true; 10280 vport->rxvlan_cfg.strip_tag2_discard_en = true; 10281 } 10282 10283 vport->rxvlan_cfg.strip_tag1_discard_en = false; 10284 vport->rxvlan_cfg.vlan1_vlan_prionly = false; 10285 vport->rxvlan_cfg.vlan2_vlan_prionly = false; 10286 vport->rxvlan_cfg.rx_vlan_offload_en = enable; 10287 10288 return hclge_set_vlan_rx_offload_cfg(vport); 10289 } 10290 10291 static void hclge_set_vport_vlan_fltr_change(struct hclge_vport *vport) 10292 { 10293 struct hclge_dev *hdev = vport->back; 10294 10295 if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, hdev->ae_dev->caps)) 10296 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, &vport->state); 10297 } 10298 10299 static int hclge_update_vlan_filter_entries(struct hclge_vport *vport, 10300 u16 port_base_vlan_state, 10301 struct hclge_vlan_info *new_info, 10302 struct hclge_vlan_info *old_info) 10303 { 10304 struct hclge_dev *hdev = vport->back; 10305 int ret; 10306 10307 if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_ENABLE) { 10308 hclge_rm_vport_all_vlan_table(vport, false); 10309 /* force clear VLAN 0 */ 10310 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, true, 0); 10311 if (ret) 10312 return ret; 10313 return hclge_set_vlan_filter_hw(hdev, 10314 htons(new_info->vlan_proto), 10315 vport->vport_id, 10316 new_info->vlan_tag, 10317 false); 10318 } 10319 10320 vport->port_base_vlan_cfg.tbl_sta = false; 10321 10322 /* force add VLAN 0 */ 10323 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, false, 0); 10324 if (ret) 10325 return ret; 10326 10327 ret = hclge_set_vlan_filter_hw(hdev, htons(old_info->vlan_proto), 10328 vport->vport_id, old_info->vlan_tag, 10329 true); 10330 if (ret) 10331 return ret; 10332 10333 return hclge_add_vport_all_vlan_table(vport); 10334 } 10335 10336 static bool hclge_need_update_vlan_filter(const struct hclge_vlan_info *new_cfg, 10337 const struct hclge_vlan_info *old_cfg) 10338 { 10339 if (new_cfg->vlan_tag != old_cfg->vlan_tag) 10340 return true; 10341 10342 if (new_cfg->vlan_tag == 0 && (new_cfg->qos == 0 || old_cfg->qos == 0)) 10343 return true; 10344 10345 return false; 10346 } 10347 10348 static int hclge_modify_port_base_vlan_tag(struct hclge_vport *vport, 10349 struct hclge_vlan_info *new_info, 10350 struct hclge_vlan_info *old_info) 10351 { 10352 struct hclge_dev *hdev = vport->back; 10353 int ret; 10354 10355 /* add new VLAN tag */ 10356 ret = hclge_set_vlan_filter_hw(hdev, htons(new_info->vlan_proto), 10357 vport->vport_id, new_info->vlan_tag, 10358 false); 10359 if (ret) 10360 return ret; 10361 10362 vport->port_base_vlan_cfg.tbl_sta = false; 10363 /* remove old VLAN tag */ 10364 if (old_info->vlan_tag == 0) 10365 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, 10366 true, 0); 10367 else 10368 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10369 vport->vport_id, 10370 old_info->vlan_tag, true); 10371 if (ret) 10372 dev_err(&hdev->pdev->dev, 10373 "failed to clear vport%u port base vlan %u, ret = %d.\n", 10374 vport->vport_id, old_info->vlan_tag, ret); 10375 10376 return ret; 10377 } 10378 10379 int hclge_update_port_base_vlan_cfg(struct hclge_vport *vport, u16 state, 10380 struct hclge_vlan_info *vlan_info) 10381 { 10382 struct hnae3_handle *nic = &vport->nic; 10383 struct hclge_vlan_info *old_vlan_info; 10384 int ret; 10385 10386 old_vlan_info = &vport->port_base_vlan_cfg.vlan_info; 10387 10388 ret = hclge_vlan_offload_cfg(vport, state, vlan_info->vlan_tag, 10389 vlan_info->qos); 10390 if (ret) 10391 return ret; 10392 10393 if (!hclge_need_update_vlan_filter(vlan_info, old_vlan_info)) 10394 goto out; 10395 10396 if (state == HNAE3_PORT_BASE_VLAN_MODIFY) 10397 ret = hclge_modify_port_base_vlan_tag(vport, vlan_info, 10398 old_vlan_info); 10399 else 10400 ret = hclge_update_vlan_filter_entries(vport, state, vlan_info, 10401 old_vlan_info); 10402 if (ret) 10403 return ret; 10404 10405 out: 10406 vport->port_base_vlan_cfg.state = state; 10407 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 10408 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_DISABLE; 10409 else 10410 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 10411 10412 vport->port_base_vlan_cfg.old_vlan_info = *old_vlan_info; 10413 vport->port_base_vlan_cfg.vlan_info = *vlan_info; 10414 vport->port_base_vlan_cfg.tbl_sta = true; 10415 hclge_set_vport_vlan_fltr_change(vport); 10416 10417 return 0; 10418 } 10419 10420 static u16 hclge_get_port_base_vlan_state(struct hclge_vport *vport, 10421 enum hnae3_port_base_vlan_state state, 10422 u16 vlan, u8 qos) 10423 { 10424 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) { 10425 if (!vlan && !qos) 10426 return HNAE3_PORT_BASE_VLAN_NOCHANGE; 10427 10428 return HNAE3_PORT_BASE_VLAN_ENABLE; 10429 } 10430 10431 if (!vlan && !qos) 10432 return HNAE3_PORT_BASE_VLAN_DISABLE; 10433 10434 if (vport->port_base_vlan_cfg.vlan_info.vlan_tag == vlan && 10435 vport->port_base_vlan_cfg.vlan_info.qos == qos) 10436 return HNAE3_PORT_BASE_VLAN_NOCHANGE; 10437 10438 return HNAE3_PORT_BASE_VLAN_MODIFY; 10439 } 10440 10441 static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid, 10442 u16 vlan, u8 qos, __be16 proto) 10443 { 10444 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 10445 struct hclge_vport *vport = hclge_get_vport(handle); 10446 struct hclge_dev *hdev = vport->back; 10447 struct hclge_vlan_info vlan_info; 10448 u16 state; 10449 int ret; 10450 10451 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 10452 return -EOPNOTSUPP; 10453 10454 vport = hclge_get_vf_vport(hdev, vfid); 10455 if (!vport) 10456 return -EINVAL; 10457 10458 /* qos is a 3 bits value, so can not be bigger than 7 */ 10459 if (vlan > VLAN_N_VID - 1 || qos > 7) 10460 return -EINVAL; 10461 if (proto != htons(ETH_P_8021Q)) 10462 return -EPROTONOSUPPORT; 10463 10464 state = hclge_get_port_base_vlan_state(vport, 10465 vport->port_base_vlan_cfg.state, 10466 vlan, qos); 10467 if (state == HNAE3_PORT_BASE_VLAN_NOCHANGE) 10468 return 0; 10469 10470 vlan_info.vlan_tag = vlan; 10471 vlan_info.qos = qos; 10472 vlan_info.vlan_proto = ntohs(proto); 10473 10474 ret = hclge_update_port_base_vlan_cfg(vport, state, &vlan_info); 10475 if (ret) { 10476 dev_err(&hdev->pdev->dev, 10477 "failed to update port base vlan for vf %d, ret = %d\n", 10478 vfid, ret); 10479 return ret; 10480 } 10481 10482 /* there is a timewindow for PF to know VF unalive, it may 10483 * cause send mailbox fail, but it doesn't matter, VF will 10484 * query it when reinit. 10485 * for DEVICE_VERSION_V3, vf doesn't need to know about the port based 10486 * VLAN state. 10487 */ 10488 if (ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) { 10489 if (test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) 10490 (void)hclge_push_vf_port_base_vlan_info(&hdev->vport[0], 10491 vport->vport_id, 10492 state, 10493 &vlan_info); 10494 else 10495 set_bit(HCLGE_VPORT_NEED_NOTIFY_VF_VLAN, 10496 &vport->need_notify); 10497 } 10498 return 0; 10499 } 10500 10501 static void hclge_clear_vf_vlan(struct hclge_dev *hdev) 10502 { 10503 struct hclge_vlan_info *vlan_info; 10504 struct hclge_vport *vport; 10505 int ret; 10506 int vf; 10507 10508 /* clear port base vlan for all vf */ 10509 for (vf = HCLGE_VF_VPORT_START_NUM; vf < hdev->num_alloc_vport; vf++) { 10510 vport = &hdev->vport[vf]; 10511 vlan_info = &vport->port_base_vlan_cfg.vlan_info; 10512 10513 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10514 vport->vport_id, 10515 vlan_info->vlan_tag, true); 10516 if (ret) 10517 dev_err(&hdev->pdev->dev, 10518 "failed to clear vf vlan for vf%d, ret = %d\n", 10519 vf - HCLGE_VF_VPORT_START_NUM, ret); 10520 } 10521 } 10522 10523 int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto, 10524 u16 vlan_id, bool is_kill) 10525 { 10526 struct hclge_vport *vport = hclge_get_vport(handle); 10527 struct hclge_dev *hdev = vport->back; 10528 bool writen_to_tbl = false; 10529 int ret = 0; 10530 10531 /* When device is resetting or reset failed, firmware is unable to 10532 * handle mailbox. Just record the vlan id, and remove it after 10533 * reset finished. 10534 */ 10535 if ((test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 10536 test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) && is_kill) { 10537 set_bit(vlan_id, vport->vlan_del_fail_bmap); 10538 return -EBUSY; 10539 } 10540 10541 /* when port base vlan enabled, we use port base vlan as the vlan 10542 * filter entry. In this case, we don't update vlan filter table 10543 * when user add new vlan or remove exist vlan, just update the vport 10544 * vlan list. The vlan id in vlan list will be writen in vlan filter 10545 * table until port base vlan disabled 10546 */ 10547 if (handle->port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) { 10548 ret = hclge_set_vlan_filter_hw(hdev, proto, vport->vport_id, 10549 vlan_id, is_kill); 10550 writen_to_tbl = true; 10551 } 10552 10553 if (!ret) { 10554 if (!is_kill) 10555 hclge_add_vport_vlan_table(vport, vlan_id, 10556 writen_to_tbl); 10557 else if (is_kill && vlan_id != 0) 10558 hclge_rm_vport_vlan_table(vport, vlan_id, false); 10559 } else if (is_kill) { 10560 /* when remove hw vlan filter failed, record the vlan id, 10561 * and try to remove it from hw later, to be consistence 10562 * with stack 10563 */ 10564 set_bit(vlan_id, vport->vlan_del_fail_bmap); 10565 } 10566 10567 hclge_set_vport_vlan_fltr_change(vport); 10568 10569 return ret; 10570 } 10571 10572 static void hclge_sync_vlan_fltr_state(struct hclge_dev *hdev) 10573 { 10574 struct hclge_vport *vport; 10575 int ret; 10576 u16 i; 10577 10578 for (i = 0; i < hdev->num_alloc_vport; i++) { 10579 vport = &hdev->vport[i]; 10580 if (!test_and_clear_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 10581 &vport->state)) 10582 continue; 10583 10584 ret = hclge_enable_vport_vlan_filter(vport, 10585 vport->req_vlan_fltr_en); 10586 if (ret) { 10587 dev_err(&hdev->pdev->dev, 10588 "failed to sync vlan filter state for vport%u, ret = %d\n", 10589 vport->vport_id, ret); 10590 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 10591 &vport->state); 10592 return; 10593 } 10594 } 10595 } 10596 10597 static void hclge_sync_vlan_filter(struct hclge_dev *hdev) 10598 { 10599 #define HCLGE_MAX_SYNC_COUNT 60 10600 10601 int i, ret, sync_cnt = 0; 10602 u16 vlan_id; 10603 10604 /* start from vport 1 for PF is always alive */ 10605 for (i = 0; i < hdev->num_alloc_vport; i++) { 10606 struct hclge_vport *vport = &hdev->vport[i]; 10607 10608 vlan_id = find_first_bit(vport->vlan_del_fail_bmap, 10609 VLAN_N_VID); 10610 while (vlan_id != VLAN_N_VID) { 10611 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10612 vport->vport_id, vlan_id, 10613 true); 10614 if (ret && ret != -EINVAL) 10615 return; 10616 10617 clear_bit(vlan_id, vport->vlan_del_fail_bmap); 10618 hclge_rm_vport_vlan_table(vport, vlan_id, false); 10619 hclge_set_vport_vlan_fltr_change(vport); 10620 10621 sync_cnt++; 10622 if (sync_cnt >= HCLGE_MAX_SYNC_COUNT) 10623 return; 10624 10625 vlan_id = find_first_bit(vport->vlan_del_fail_bmap, 10626 VLAN_N_VID); 10627 } 10628 } 10629 10630 hclge_sync_vlan_fltr_state(hdev); 10631 } 10632 10633 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mps) 10634 { 10635 struct hclge_config_max_frm_size_cmd *req; 10636 struct hclge_desc desc; 10637 10638 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false); 10639 10640 req = (struct hclge_config_max_frm_size_cmd *)desc.data; 10641 req->max_frm_size = cpu_to_le16(new_mps); 10642 req->min_frm_size = HCLGE_MAC_MIN_FRAME; 10643 10644 return hclge_cmd_send(&hdev->hw, &desc, 1); 10645 } 10646 10647 static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu) 10648 { 10649 struct hclge_vport *vport = hclge_get_vport(handle); 10650 10651 return hclge_set_vport_mtu(vport, new_mtu); 10652 } 10653 10654 int hclge_set_vport_mtu(struct hclge_vport *vport, int new_mtu) 10655 { 10656 struct hclge_dev *hdev = vport->back; 10657 int i, max_frm_size, ret; 10658 10659 /* HW supprt 2 layer vlan */ 10660 max_frm_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN; 10661 if (max_frm_size < HCLGE_MAC_MIN_FRAME || 10662 max_frm_size > hdev->ae_dev->dev_specs.max_frm_size) 10663 return -EINVAL; 10664 10665 max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME); 10666 mutex_lock(&hdev->vport_lock); 10667 /* VF's mps must fit within hdev->mps */ 10668 if (vport->vport_id && max_frm_size > hdev->mps) { 10669 mutex_unlock(&hdev->vport_lock); 10670 return -EINVAL; 10671 } else if (vport->vport_id) { 10672 vport->mps = max_frm_size; 10673 mutex_unlock(&hdev->vport_lock); 10674 return 0; 10675 } 10676 10677 /* PF's mps must be greater then VF's mps */ 10678 for (i = 1; i < hdev->num_alloc_vport; i++) 10679 if (max_frm_size < hdev->vport[i].mps) { 10680 dev_err(&hdev->pdev->dev, 10681 "failed to set pf mtu for less than vport %d, mps = %u.\n", 10682 i, hdev->vport[i].mps); 10683 mutex_unlock(&hdev->vport_lock); 10684 return -EINVAL; 10685 } 10686 10687 hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 10688 10689 ret = hclge_set_mac_mtu(hdev, max_frm_size); 10690 if (ret) { 10691 dev_err(&hdev->pdev->dev, 10692 "Change mtu fail, ret =%d\n", ret); 10693 goto out; 10694 } 10695 10696 hdev->mps = max_frm_size; 10697 vport->mps = max_frm_size; 10698 10699 ret = hclge_buffer_alloc(hdev); 10700 if (ret) 10701 dev_err(&hdev->pdev->dev, 10702 "Allocate buffer fail, ret =%d\n", ret); 10703 10704 out: 10705 hclge_notify_client(hdev, HNAE3_UP_CLIENT); 10706 mutex_unlock(&hdev->vport_lock); 10707 return ret; 10708 } 10709 10710 static int hclge_reset_tqp_cmd_send(struct hclge_dev *hdev, u16 queue_id, 10711 bool enable) 10712 { 10713 struct hclge_reset_tqp_queue_cmd *req; 10714 struct hclge_desc desc; 10715 int ret; 10716 10717 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false); 10718 10719 req = (struct hclge_reset_tqp_queue_cmd *)desc.data; 10720 req->tqp_id = cpu_to_le16(queue_id); 10721 if (enable) 10722 hnae3_set_bit(req->reset_req, HCLGE_TQP_RESET_B, 1U); 10723 10724 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 10725 if (ret) { 10726 dev_err(&hdev->pdev->dev, 10727 "Send tqp reset cmd error, status =%d\n", ret); 10728 return ret; 10729 } 10730 10731 return 0; 10732 } 10733 10734 static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id, 10735 u8 *reset_status) 10736 { 10737 struct hclge_reset_tqp_queue_cmd *req; 10738 struct hclge_desc desc; 10739 int ret; 10740 10741 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true); 10742 10743 req = (struct hclge_reset_tqp_queue_cmd *)desc.data; 10744 req->tqp_id = cpu_to_le16(queue_id); 10745 10746 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 10747 if (ret) { 10748 dev_err(&hdev->pdev->dev, 10749 "Get reset status error, status =%d\n", ret); 10750 return ret; 10751 } 10752 10753 *reset_status = hnae3_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B); 10754 10755 return 0; 10756 } 10757 10758 u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, u16 queue_id) 10759 { 10760 struct hclge_comm_tqp *tqp; 10761 struct hnae3_queue *queue; 10762 10763 queue = handle->kinfo.tqp[queue_id]; 10764 tqp = container_of(queue, struct hclge_comm_tqp, q); 10765 10766 return tqp->index; 10767 } 10768 10769 static int hclge_reset_tqp_cmd(struct hnae3_handle *handle) 10770 { 10771 struct hclge_vport *vport = hclge_get_vport(handle); 10772 struct hclge_dev *hdev = vport->back; 10773 u16 reset_try_times = 0; 10774 u8 reset_status; 10775 u16 queue_gid; 10776 int ret; 10777 u16 i; 10778 10779 for (i = 0; i < handle->kinfo.num_tqps; i++) { 10780 queue_gid = hclge_covert_handle_qid_global(handle, i); 10781 ret = hclge_reset_tqp_cmd_send(hdev, queue_gid, true); 10782 if (ret) { 10783 dev_err(&hdev->pdev->dev, 10784 "failed to send reset tqp cmd, ret = %d\n", 10785 ret); 10786 return ret; 10787 } 10788 10789 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) { 10790 ret = hclge_get_reset_status(hdev, queue_gid, 10791 &reset_status); 10792 if (ret) 10793 return ret; 10794 10795 if (reset_status) 10796 break; 10797 10798 /* Wait for tqp hw reset */ 10799 usleep_range(1000, 1200); 10800 } 10801 10802 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) { 10803 dev_err(&hdev->pdev->dev, 10804 "wait for tqp hw reset timeout\n"); 10805 return -ETIME; 10806 } 10807 10808 ret = hclge_reset_tqp_cmd_send(hdev, queue_gid, false); 10809 if (ret) { 10810 dev_err(&hdev->pdev->dev, 10811 "failed to deassert soft reset, ret = %d\n", 10812 ret); 10813 return ret; 10814 } 10815 reset_try_times = 0; 10816 } 10817 return 0; 10818 } 10819 10820 static int hclge_reset_rcb(struct hnae3_handle *handle) 10821 { 10822 #define HCLGE_RESET_RCB_NOT_SUPPORT 0U 10823 #define HCLGE_RESET_RCB_SUCCESS 1U 10824 10825 struct hclge_vport *vport = hclge_get_vport(handle); 10826 struct hclge_dev *hdev = vport->back; 10827 struct hclge_reset_cmd *req; 10828 struct hclge_desc desc; 10829 u8 return_status; 10830 u16 queue_gid; 10831 int ret; 10832 10833 queue_gid = hclge_covert_handle_qid_global(handle, 0); 10834 10835 req = (struct hclge_reset_cmd *)desc.data; 10836 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false); 10837 hnae3_set_bit(req->fun_reset_rcb, HCLGE_CFG_RESET_RCB_B, 1); 10838 req->fun_reset_rcb_vqid_start = cpu_to_le16(queue_gid); 10839 req->fun_reset_rcb_vqid_num = cpu_to_le16(handle->kinfo.num_tqps); 10840 10841 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 10842 if (ret) { 10843 dev_err(&hdev->pdev->dev, 10844 "failed to send rcb reset cmd, ret = %d\n", ret); 10845 return ret; 10846 } 10847 10848 return_status = req->fun_reset_rcb_return_status; 10849 if (return_status == HCLGE_RESET_RCB_SUCCESS) 10850 return 0; 10851 10852 if (return_status != HCLGE_RESET_RCB_NOT_SUPPORT) { 10853 dev_err(&hdev->pdev->dev, "failed to reset rcb, ret = %u\n", 10854 return_status); 10855 return -EIO; 10856 } 10857 10858 /* if reset rcb cmd is unsupported, we need to send reset tqp cmd 10859 * again to reset all tqps 10860 */ 10861 return hclge_reset_tqp_cmd(handle); 10862 } 10863 10864 int hclge_reset_tqp(struct hnae3_handle *handle) 10865 { 10866 struct hclge_vport *vport = hclge_get_vport(handle); 10867 struct hclge_dev *hdev = vport->back; 10868 int ret; 10869 10870 /* only need to disable PF's tqp */ 10871 if (!vport->vport_id) { 10872 ret = hclge_tqp_enable(handle, false); 10873 if (ret) { 10874 dev_err(&hdev->pdev->dev, 10875 "failed to disable tqp, ret = %d\n", ret); 10876 return ret; 10877 } 10878 } 10879 10880 return hclge_reset_rcb(handle); 10881 } 10882 10883 static u32 hclge_get_fw_version(struct hnae3_handle *handle) 10884 { 10885 struct hclge_vport *vport = hclge_get_vport(handle); 10886 struct hclge_dev *hdev = vport->back; 10887 10888 return hdev->fw_version; 10889 } 10890 10891 static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en) 10892 { 10893 struct phy_device *phydev = hdev->hw.mac.phydev; 10894 10895 if (!phydev) 10896 return; 10897 10898 phy_set_asym_pause(phydev, rx_en, tx_en); 10899 } 10900 10901 static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en) 10902 { 10903 int ret; 10904 10905 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) 10906 return 0; 10907 10908 ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en); 10909 if (ret) 10910 dev_err(&hdev->pdev->dev, 10911 "configure pauseparam error, ret = %d.\n", ret); 10912 10913 return ret; 10914 } 10915 10916 int hclge_cfg_flowctrl(struct hclge_dev *hdev) 10917 { 10918 struct phy_device *phydev = hdev->hw.mac.phydev; 10919 u16 remote_advertising = 0; 10920 u16 local_advertising; 10921 u32 rx_pause, tx_pause; 10922 u8 flowctl; 10923 10924 if (!phydev->link || !phydev->autoneg) 10925 return 0; 10926 10927 local_advertising = linkmode_adv_to_lcl_adv_t(phydev->advertising); 10928 10929 if (phydev->pause) 10930 remote_advertising = LPA_PAUSE_CAP; 10931 10932 if (phydev->asym_pause) 10933 remote_advertising |= LPA_PAUSE_ASYM; 10934 10935 flowctl = mii_resolve_flowctrl_fdx(local_advertising, 10936 remote_advertising); 10937 tx_pause = flowctl & FLOW_CTRL_TX; 10938 rx_pause = flowctl & FLOW_CTRL_RX; 10939 10940 if (phydev->duplex == HCLGE_MAC_HALF) { 10941 tx_pause = 0; 10942 rx_pause = 0; 10943 } 10944 10945 return hclge_cfg_pauseparam(hdev, rx_pause, tx_pause); 10946 } 10947 10948 static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg, 10949 u32 *rx_en, u32 *tx_en) 10950 { 10951 struct hclge_vport *vport = hclge_get_vport(handle); 10952 struct hclge_dev *hdev = vport->back; 10953 u8 media_type = hdev->hw.mac.media_type; 10954 10955 *auto_neg = (media_type == HNAE3_MEDIA_TYPE_COPPER) ? 10956 hclge_get_autoneg(handle) : 0; 10957 10958 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) { 10959 *rx_en = 0; 10960 *tx_en = 0; 10961 return; 10962 } 10963 10964 if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) { 10965 *rx_en = 1; 10966 *tx_en = 0; 10967 } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) { 10968 *tx_en = 1; 10969 *rx_en = 0; 10970 } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) { 10971 *rx_en = 1; 10972 *tx_en = 1; 10973 } else { 10974 *rx_en = 0; 10975 *tx_en = 0; 10976 } 10977 } 10978 10979 static void hclge_record_user_pauseparam(struct hclge_dev *hdev, 10980 u32 rx_en, u32 tx_en) 10981 { 10982 if (rx_en && tx_en) 10983 hdev->fc_mode_last_time = HCLGE_FC_FULL; 10984 else if (rx_en && !tx_en) 10985 hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE; 10986 else if (!rx_en && tx_en) 10987 hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE; 10988 else 10989 hdev->fc_mode_last_time = HCLGE_FC_NONE; 10990 10991 hdev->tm_info.fc_mode = hdev->fc_mode_last_time; 10992 } 10993 10994 static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg, 10995 u32 rx_en, u32 tx_en) 10996 { 10997 struct hclge_vport *vport = hclge_get_vport(handle); 10998 struct hclge_dev *hdev = vport->back; 10999 struct phy_device *phydev = hdev->hw.mac.phydev; 11000 u32 fc_autoneg; 11001 11002 if (phydev || hnae3_dev_phy_imp_supported(hdev)) { 11003 fc_autoneg = hclge_get_autoneg(handle); 11004 if (auto_neg != fc_autoneg) { 11005 dev_info(&hdev->pdev->dev, 11006 "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n"); 11007 return -EOPNOTSUPP; 11008 } 11009 } 11010 11011 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) { 11012 dev_info(&hdev->pdev->dev, 11013 "Priority flow control enabled. Cannot set link flow control.\n"); 11014 return -EOPNOTSUPP; 11015 } 11016 11017 hclge_set_flowctrl_adv(hdev, rx_en, tx_en); 11018 11019 hclge_record_user_pauseparam(hdev, rx_en, tx_en); 11020 11021 if (!auto_neg || hnae3_dev_phy_imp_supported(hdev)) 11022 return hclge_cfg_pauseparam(hdev, rx_en, tx_en); 11023 11024 if (phydev) 11025 return phy_start_aneg(phydev); 11026 11027 return -EOPNOTSUPP; 11028 } 11029 11030 static void hclge_get_ksettings_an_result(struct hnae3_handle *handle, 11031 u8 *auto_neg, u32 *speed, u8 *duplex, u32 *lane_num) 11032 { 11033 struct hclge_vport *vport = hclge_get_vport(handle); 11034 struct hclge_dev *hdev = vport->back; 11035 11036 if (speed) 11037 *speed = hdev->hw.mac.speed; 11038 if (duplex) 11039 *duplex = hdev->hw.mac.duplex; 11040 if (auto_neg) 11041 *auto_neg = hdev->hw.mac.autoneg; 11042 if (lane_num) 11043 *lane_num = hdev->hw.mac.lane_num; 11044 } 11045 11046 static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type, 11047 u8 *module_type) 11048 { 11049 struct hclge_vport *vport = hclge_get_vport(handle); 11050 struct hclge_dev *hdev = vport->back; 11051 11052 /* When nic is down, the service task is not running, doesn't update 11053 * the port information per second. Query the port information before 11054 * return the media type, ensure getting the correct media information. 11055 */ 11056 hclge_update_port_info(hdev); 11057 11058 if (media_type) 11059 *media_type = hdev->hw.mac.media_type; 11060 11061 if (module_type) 11062 *module_type = hdev->hw.mac.module_type; 11063 } 11064 11065 static void hclge_get_mdix_mode(struct hnae3_handle *handle, 11066 u8 *tp_mdix_ctrl, u8 *tp_mdix) 11067 { 11068 struct hclge_vport *vport = hclge_get_vport(handle); 11069 struct hclge_dev *hdev = vport->back; 11070 struct phy_device *phydev = hdev->hw.mac.phydev; 11071 int mdix_ctrl, mdix, is_resolved; 11072 unsigned int retval; 11073 11074 if (!phydev) { 11075 *tp_mdix_ctrl = ETH_TP_MDI_INVALID; 11076 *tp_mdix = ETH_TP_MDI_INVALID; 11077 return; 11078 } 11079 11080 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX); 11081 11082 retval = phy_read(phydev, HCLGE_PHY_CSC_REG); 11083 mdix_ctrl = hnae3_get_field(retval, HCLGE_PHY_MDIX_CTRL_M, 11084 HCLGE_PHY_MDIX_CTRL_S); 11085 11086 retval = phy_read(phydev, HCLGE_PHY_CSS_REG); 11087 mdix = hnae3_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B); 11088 is_resolved = hnae3_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B); 11089 11090 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER); 11091 11092 switch (mdix_ctrl) { 11093 case 0x0: 11094 *tp_mdix_ctrl = ETH_TP_MDI; 11095 break; 11096 case 0x1: 11097 *tp_mdix_ctrl = ETH_TP_MDI_X; 11098 break; 11099 case 0x3: 11100 *tp_mdix_ctrl = ETH_TP_MDI_AUTO; 11101 break; 11102 default: 11103 *tp_mdix_ctrl = ETH_TP_MDI_INVALID; 11104 break; 11105 } 11106 11107 if (!is_resolved) 11108 *tp_mdix = ETH_TP_MDI_INVALID; 11109 else if (mdix) 11110 *tp_mdix = ETH_TP_MDI_X; 11111 else 11112 *tp_mdix = ETH_TP_MDI; 11113 } 11114 11115 static void hclge_info_show(struct hclge_dev *hdev) 11116 { 11117 struct device *dev = &hdev->pdev->dev; 11118 11119 dev_info(dev, "PF info begin:\n"); 11120 11121 dev_info(dev, "Task queue pairs numbers: %u\n", hdev->num_tqps); 11122 dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc); 11123 dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc); 11124 dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport); 11125 dev_info(dev, "Numbers of VF for this PF: %u\n", hdev->num_req_vfs); 11126 dev_info(dev, "HW tc map: 0x%x\n", hdev->hw_tc_map); 11127 dev_info(dev, "Total buffer size for TX/RX: %u\n", hdev->pkt_buf_size); 11128 dev_info(dev, "TX buffer size for each TC: %u\n", hdev->tx_buf_size); 11129 dev_info(dev, "DV buffer size for each TC: %u\n", hdev->dv_buf_size); 11130 dev_info(dev, "This is %s PF\n", 11131 hdev->flag & HCLGE_FLAG_MAIN ? "main" : "not main"); 11132 dev_info(dev, "DCB %s\n", 11133 hdev->flag & HCLGE_FLAG_DCB_ENABLE ? "enable" : "disable"); 11134 dev_info(dev, "MQPRIO %s\n", 11135 hdev->flag & HCLGE_FLAG_MQPRIO_ENABLE ? "enable" : "disable"); 11136 dev_info(dev, "Default tx spare buffer size: %u\n", 11137 hdev->tx_spare_buf_size); 11138 11139 dev_info(dev, "PF info end.\n"); 11140 } 11141 11142 static int hclge_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, 11143 struct hclge_vport *vport) 11144 { 11145 struct hnae3_client *client = vport->nic.client; 11146 struct hclge_dev *hdev = ae_dev->priv; 11147 int rst_cnt = hdev->rst_stats.reset_cnt; 11148 int ret; 11149 11150 ret = client->ops->init_instance(&vport->nic); 11151 if (ret) 11152 return ret; 11153 11154 set_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); 11155 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 11156 rst_cnt != hdev->rst_stats.reset_cnt) { 11157 ret = -EBUSY; 11158 goto init_nic_err; 11159 } 11160 11161 /* Enable nic hw error interrupts */ 11162 ret = hclge_config_nic_hw_error(hdev, true); 11163 if (ret) { 11164 dev_err(&ae_dev->pdev->dev, 11165 "fail(%d) to enable hw error interrupts\n", ret); 11166 goto init_nic_err; 11167 } 11168 11169 hnae3_set_client_init_flag(client, ae_dev, 1); 11170 11171 if (netif_msg_drv(&hdev->vport->nic)) 11172 hclge_info_show(hdev); 11173 11174 return ret; 11175 11176 init_nic_err: 11177 clear_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); 11178 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 11179 msleep(HCLGE_WAIT_RESET_DONE); 11180 11181 client->ops->uninit_instance(&vport->nic, 0); 11182 11183 return ret; 11184 } 11185 11186 static int hclge_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, 11187 struct hclge_vport *vport) 11188 { 11189 struct hclge_dev *hdev = ae_dev->priv; 11190 struct hnae3_client *client; 11191 int rst_cnt; 11192 int ret; 11193 11194 if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || 11195 !hdev->nic_client) 11196 return 0; 11197 11198 client = hdev->roce_client; 11199 ret = hclge_init_roce_base_info(vport); 11200 if (ret) 11201 return ret; 11202 11203 rst_cnt = hdev->rst_stats.reset_cnt; 11204 ret = client->ops->init_instance(&vport->roce); 11205 if (ret) 11206 return ret; 11207 11208 set_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state); 11209 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 11210 rst_cnt != hdev->rst_stats.reset_cnt) { 11211 ret = -EBUSY; 11212 goto init_roce_err; 11213 } 11214 11215 /* Enable roce ras interrupts */ 11216 ret = hclge_config_rocee_ras_interrupt(hdev, true); 11217 if (ret) { 11218 dev_err(&ae_dev->pdev->dev, 11219 "fail(%d) to enable roce ras interrupts\n", ret); 11220 goto init_roce_err; 11221 } 11222 11223 hnae3_set_client_init_flag(client, ae_dev, 1); 11224 11225 return 0; 11226 11227 init_roce_err: 11228 clear_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state); 11229 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 11230 msleep(HCLGE_WAIT_RESET_DONE); 11231 11232 hdev->roce_client->ops->uninit_instance(&vport->roce, 0); 11233 11234 return ret; 11235 } 11236 11237 static int hclge_init_client_instance(struct hnae3_client *client, 11238 struct hnae3_ae_dev *ae_dev) 11239 { 11240 struct hclge_dev *hdev = ae_dev->priv; 11241 struct hclge_vport *vport = &hdev->vport[0]; 11242 int ret; 11243 11244 switch (client->type) { 11245 case HNAE3_CLIENT_KNIC: 11246 hdev->nic_client = client; 11247 vport->nic.client = client; 11248 ret = hclge_init_nic_client_instance(ae_dev, vport); 11249 if (ret) 11250 goto clear_nic; 11251 11252 ret = hclge_init_roce_client_instance(ae_dev, vport); 11253 if (ret) 11254 goto clear_roce; 11255 11256 break; 11257 case HNAE3_CLIENT_ROCE: 11258 if (hnae3_dev_roce_supported(hdev)) { 11259 hdev->roce_client = client; 11260 vport->roce.client = client; 11261 } 11262 11263 ret = hclge_init_roce_client_instance(ae_dev, vport); 11264 if (ret) 11265 goto clear_roce; 11266 11267 break; 11268 default: 11269 return -EINVAL; 11270 } 11271 11272 return 0; 11273 11274 clear_nic: 11275 hdev->nic_client = NULL; 11276 vport->nic.client = NULL; 11277 return ret; 11278 clear_roce: 11279 hdev->roce_client = NULL; 11280 vport->roce.client = NULL; 11281 return ret; 11282 } 11283 11284 static void hclge_uninit_client_instance(struct hnae3_client *client, 11285 struct hnae3_ae_dev *ae_dev) 11286 { 11287 struct hclge_dev *hdev = ae_dev->priv; 11288 struct hclge_vport *vport = &hdev->vport[0]; 11289 11290 if (hdev->roce_client) { 11291 clear_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state); 11292 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 11293 msleep(HCLGE_WAIT_RESET_DONE); 11294 11295 hdev->roce_client->ops->uninit_instance(&vport->roce, 0); 11296 hdev->roce_client = NULL; 11297 vport->roce.client = NULL; 11298 } 11299 if (client->type == HNAE3_CLIENT_ROCE) 11300 return; 11301 if (hdev->nic_client && client->ops->uninit_instance) { 11302 clear_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); 11303 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 11304 msleep(HCLGE_WAIT_RESET_DONE); 11305 11306 client->ops->uninit_instance(&vport->nic, 0); 11307 hdev->nic_client = NULL; 11308 vport->nic.client = NULL; 11309 } 11310 } 11311 11312 static int hclge_dev_mem_map(struct hclge_dev *hdev) 11313 { 11314 struct pci_dev *pdev = hdev->pdev; 11315 struct hclge_hw *hw = &hdev->hw; 11316 11317 /* for device does not have device memory, return directly */ 11318 if (!(pci_select_bars(pdev, IORESOURCE_MEM) & BIT(HCLGE_MEM_BAR))) 11319 return 0; 11320 11321 hw->hw.mem_base = 11322 devm_ioremap_wc(&pdev->dev, 11323 pci_resource_start(pdev, HCLGE_MEM_BAR), 11324 pci_resource_len(pdev, HCLGE_MEM_BAR)); 11325 if (!hw->hw.mem_base) { 11326 dev_err(&pdev->dev, "failed to map device memory\n"); 11327 return -EFAULT; 11328 } 11329 11330 return 0; 11331 } 11332 11333 static int hclge_pci_init(struct hclge_dev *hdev) 11334 { 11335 struct pci_dev *pdev = hdev->pdev; 11336 struct hclge_hw *hw; 11337 int ret; 11338 11339 ret = pci_enable_device(pdev); 11340 if (ret) { 11341 dev_err(&pdev->dev, "failed to enable PCI device\n"); 11342 return ret; 11343 } 11344 11345 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 11346 if (ret) { 11347 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 11348 if (ret) { 11349 dev_err(&pdev->dev, 11350 "can't set consistent PCI DMA"); 11351 goto err_disable_device; 11352 } 11353 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n"); 11354 } 11355 11356 ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME); 11357 if (ret) { 11358 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 11359 goto err_disable_device; 11360 } 11361 11362 pci_set_master(pdev); 11363 hw = &hdev->hw; 11364 hw->hw.io_base = pcim_iomap(pdev, 2, 0); 11365 if (!hw->hw.io_base) { 11366 dev_err(&pdev->dev, "Can't map configuration register space\n"); 11367 ret = -ENOMEM; 11368 goto err_clr_master; 11369 } 11370 11371 ret = hclge_dev_mem_map(hdev); 11372 if (ret) 11373 goto err_unmap_io_base; 11374 11375 hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev); 11376 11377 return 0; 11378 11379 err_unmap_io_base: 11380 pcim_iounmap(pdev, hdev->hw.hw.io_base); 11381 err_clr_master: 11382 pci_clear_master(pdev); 11383 pci_release_regions(pdev); 11384 err_disable_device: 11385 pci_disable_device(pdev); 11386 11387 return ret; 11388 } 11389 11390 static void hclge_pci_uninit(struct hclge_dev *hdev) 11391 { 11392 struct pci_dev *pdev = hdev->pdev; 11393 11394 if (hdev->hw.hw.mem_base) 11395 devm_iounmap(&pdev->dev, hdev->hw.hw.mem_base); 11396 11397 pcim_iounmap(pdev, hdev->hw.hw.io_base); 11398 pci_free_irq_vectors(pdev); 11399 pci_clear_master(pdev); 11400 pci_release_mem_regions(pdev); 11401 pci_disable_device(pdev); 11402 } 11403 11404 static void hclge_state_init(struct hclge_dev *hdev) 11405 { 11406 set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state); 11407 set_bit(HCLGE_STATE_DOWN, &hdev->state); 11408 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state); 11409 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 11410 clear_bit(HCLGE_STATE_RST_FAIL, &hdev->state); 11411 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state); 11412 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state); 11413 } 11414 11415 static void hclge_state_uninit(struct hclge_dev *hdev) 11416 { 11417 set_bit(HCLGE_STATE_DOWN, &hdev->state); 11418 set_bit(HCLGE_STATE_REMOVING, &hdev->state); 11419 11420 if (hdev->reset_timer.function) 11421 del_timer_sync(&hdev->reset_timer); 11422 if (hdev->service_task.work.func) 11423 cancel_delayed_work_sync(&hdev->service_task); 11424 } 11425 11426 static void hclge_reset_prepare_general(struct hnae3_ae_dev *ae_dev, 11427 enum hnae3_reset_type rst_type) 11428 { 11429 #define HCLGE_RESET_RETRY_WAIT_MS 500 11430 #define HCLGE_RESET_RETRY_CNT 5 11431 11432 struct hclge_dev *hdev = ae_dev->priv; 11433 int retry_cnt = 0; 11434 int ret; 11435 11436 while (retry_cnt++ < HCLGE_RESET_RETRY_CNT) { 11437 down(&hdev->reset_sem); 11438 set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 11439 hdev->reset_type = rst_type; 11440 ret = hclge_reset_prepare(hdev); 11441 if (!ret && !hdev->reset_pending) 11442 break; 11443 11444 dev_err(&hdev->pdev->dev, 11445 "failed to prepare to reset, ret=%d, reset_pending:0x%lx, retry_cnt:%d\n", 11446 ret, hdev->reset_pending, retry_cnt); 11447 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 11448 up(&hdev->reset_sem); 11449 msleep(HCLGE_RESET_RETRY_WAIT_MS); 11450 } 11451 11452 /* disable misc vector before reset done */ 11453 hclge_enable_vector(&hdev->misc_vector, false); 11454 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 11455 11456 if (hdev->reset_type == HNAE3_FLR_RESET) 11457 hdev->rst_stats.flr_rst_cnt++; 11458 } 11459 11460 static void hclge_reset_done(struct hnae3_ae_dev *ae_dev) 11461 { 11462 struct hclge_dev *hdev = ae_dev->priv; 11463 int ret; 11464 11465 hclge_enable_vector(&hdev->misc_vector, true); 11466 11467 ret = hclge_reset_rebuild(hdev); 11468 if (ret) 11469 dev_err(&hdev->pdev->dev, "fail to rebuild, ret=%d\n", ret); 11470 11471 hdev->reset_type = HNAE3_NONE_RESET; 11472 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 11473 up(&hdev->reset_sem); 11474 } 11475 11476 static void hclge_clear_resetting_state(struct hclge_dev *hdev) 11477 { 11478 u16 i; 11479 11480 for (i = 0; i < hdev->num_alloc_vport; i++) { 11481 struct hclge_vport *vport = &hdev->vport[i]; 11482 int ret; 11483 11484 /* Send cmd to clear vport's FUNC_RST_ING */ 11485 ret = hclge_set_vf_rst(hdev, vport->vport_id, false); 11486 if (ret) 11487 dev_warn(&hdev->pdev->dev, 11488 "clear vport(%u) rst failed %d!\n", 11489 vport->vport_id, ret); 11490 } 11491 } 11492 11493 static int hclge_clear_hw_resource(struct hclge_dev *hdev) 11494 { 11495 struct hclge_desc desc; 11496 int ret; 11497 11498 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CLEAR_HW_RESOURCE, false); 11499 11500 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 11501 /* This new command is only supported by new firmware, it will 11502 * fail with older firmware. Error value -EOPNOSUPP can only be 11503 * returned by older firmware running this command, to keep code 11504 * backward compatible we will override this value and return 11505 * success. 11506 */ 11507 if (ret && ret != -EOPNOTSUPP) { 11508 dev_err(&hdev->pdev->dev, 11509 "failed to clear hw resource, ret = %d\n", ret); 11510 return ret; 11511 } 11512 return 0; 11513 } 11514 11515 static void hclge_init_rxd_adv_layout(struct hclge_dev *hdev) 11516 { 11517 if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 11518 hclge_write_dev(&hdev->hw, HCLGE_RXD_ADV_LAYOUT_EN_REG, 1); 11519 } 11520 11521 static void hclge_uninit_rxd_adv_layout(struct hclge_dev *hdev) 11522 { 11523 if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 11524 hclge_write_dev(&hdev->hw, HCLGE_RXD_ADV_LAYOUT_EN_REG, 0); 11525 } 11526 11527 static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev) 11528 { 11529 struct pci_dev *pdev = ae_dev->pdev; 11530 struct hclge_dev *hdev; 11531 int ret; 11532 11533 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 11534 if (!hdev) 11535 return -ENOMEM; 11536 11537 hdev->pdev = pdev; 11538 hdev->ae_dev = ae_dev; 11539 hdev->reset_type = HNAE3_NONE_RESET; 11540 hdev->reset_level = HNAE3_FUNC_RESET; 11541 ae_dev->priv = hdev; 11542 11543 /* HW supprt 2 layer vlan */ 11544 hdev->mps = ETH_FRAME_LEN + ETH_FCS_LEN + 2 * VLAN_HLEN; 11545 11546 mutex_init(&hdev->vport_lock); 11547 spin_lock_init(&hdev->fd_rule_lock); 11548 sema_init(&hdev->reset_sem, 1); 11549 11550 ret = hclge_pci_init(hdev); 11551 if (ret) 11552 goto out; 11553 11554 ret = hclge_devlink_init(hdev); 11555 if (ret) 11556 goto err_pci_uninit; 11557 11558 /* Firmware command queue initialize */ 11559 ret = hclge_comm_cmd_queue_init(hdev->pdev, &hdev->hw.hw); 11560 if (ret) 11561 goto err_devlink_uninit; 11562 11563 /* Firmware command initialize */ 11564 ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, &hdev->fw_version, 11565 true, hdev->reset_pending); 11566 if (ret) 11567 goto err_cmd_uninit; 11568 11569 ret = hclge_clear_hw_resource(hdev); 11570 if (ret) 11571 goto err_cmd_uninit; 11572 11573 ret = hclge_get_cap(hdev); 11574 if (ret) 11575 goto err_cmd_uninit; 11576 11577 ret = hclge_query_dev_specs(hdev); 11578 if (ret) { 11579 dev_err(&pdev->dev, "failed to query dev specifications, ret = %d.\n", 11580 ret); 11581 goto err_cmd_uninit; 11582 } 11583 11584 ret = hclge_configure(hdev); 11585 if (ret) { 11586 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret); 11587 goto err_cmd_uninit; 11588 } 11589 11590 ret = hclge_init_msi(hdev); 11591 if (ret) { 11592 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret); 11593 goto err_cmd_uninit; 11594 } 11595 11596 ret = hclge_misc_irq_init(hdev); 11597 if (ret) 11598 goto err_msi_uninit; 11599 11600 ret = hclge_alloc_tqps(hdev); 11601 if (ret) { 11602 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret); 11603 goto err_msi_irq_uninit; 11604 } 11605 11606 ret = hclge_alloc_vport(hdev); 11607 if (ret) 11608 goto err_msi_irq_uninit; 11609 11610 ret = hclge_map_tqp(hdev); 11611 if (ret) 11612 goto err_msi_irq_uninit; 11613 11614 if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER) { 11615 if (hnae3_dev_phy_imp_supported(hdev)) 11616 ret = hclge_update_tp_port_info(hdev); 11617 else 11618 ret = hclge_mac_mdio_config(hdev); 11619 11620 if (ret) 11621 goto err_msi_irq_uninit; 11622 } 11623 11624 ret = hclge_init_umv_space(hdev); 11625 if (ret) 11626 goto err_mdiobus_unreg; 11627 11628 ret = hclge_mac_init(hdev); 11629 if (ret) { 11630 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret); 11631 goto err_mdiobus_unreg; 11632 } 11633 11634 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX); 11635 if (ret) { 11636 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret); 11637 goto err_mdiobus_unreg; 11638 } 11639 11640 ret = hclge_config_gro(hdev); 11641 if (ret) 11642 goto err_mdiobus_unreg; 11643 11644 ret = hclge_init_vlan_config(hdev); 11645 if (ret) { 11646 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret); 11647 goto err_mdiobus_unreg; 11648 } 11649 11650 ret = hclge_tm_schd_init(hdev); 11651 if (ret) { 11652 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret); 11653 goto err_mdiobus_unreg; 11654 } 11655 11656 ret = hclge_comm_rss_init_cfg(&hdev->vport->nic, hdev->ae_dev, 11657 &hdev->rss_cfg); 11658 if (ret) { 11659 dev_err(&pdev->dev, "failed to init rss cfg, ret = %d\n", ret); 11660 goto err_mdiobus_unreg; 11661 } 11662 11663 ret = hclge_rss_init_hw(hdev); 11664 if (ret) { 11665 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret); 11666 goto err_mdiobus_unreg; 11667 } 11668 11669 ret = init_mgr_tbl(hdev); 11670 if (ret) { 11671 dev_err(&pdev->dev, "manager table init fail, ret =%d\n", ret); 11672 goto err_mdiobus_unreg; 11673 } 11674 11675 ret = hclge_init_fd_config(hdev); 11676 if (ret) { 11677 dev_err(&pdev->dev, 11678 "fd table init fail, ret=%d\n", ret); 11679 goto err_mdiobus_unreg; 11680 } 11681 11682 ret = hclge_ptp_init(hdev); 11683 if (ret) 11684 goto err_mdiobus_unreg; 11685 11686 ret = hclge_update_port_info(hdev); 11687 if (ret) 11688 goto err_mdiobus_unreg; 11689 11690 INIT_KFIFO(hdev->mac_tnl_log); 11691 11692 hclge_dcb_ops_set(hdev); 11693 11694 timer_setup(&hdev->reset_timer, hclge_reset_timer, 0); 11695 INIT_DELAYED_WORK(&hdev->service_task, hclge_service_task); 11696 11697 hclge_clear_all_event_cause(hdev); 11698 hclge_clear_resetting_state(hdev); 11699 11700 /* Log and clear the hw errors those already occurred */ 11701 if (hnae3_dev_ras_imp_supported(hdev)) 11702 hclge_handle_occurred_error(hdev); 11703 else 11704 hclge_handle_all_hns_hw_errors(ae_dev); 11705 11706 /* request delayed reset for the error recovery because an immediate 11707 * global reset on a PF affecting pending initialization of other PFs 11708 */ 11709 if (ae_dev->hw_err_reset_req) { 11710 enum hnae3_reset_type reset_level; 11711 11712 reset_level = hclge_get_reset_level(ae_dev, 11713 &ae_dev->hw_err_reset_req); 11714 hclge_set_def_reset_request(ae_dev, reset_level); 11715 mod_timer(&hdev->reset_timer, jiffies + HCLGE_RESET_INTERVAL); 11716 } 11717 11718 hclge_init_rxd_adv_layout(hdev); 11719 11720 /* Enable MISC vector(vector0) */ 11721 hclge_enable_vector(&hdev->misc_vector, true); 11722 11723 hclge_state_init(hdev); 11724 hdev->last_reset_time = jiffies; 11725 11726 dev_info(&hdev->pdev->dev, "%s driver initialization finished.\n", 11727 HCLGE_DRIVER_NAME); 11728 11729 hclge_task_schedule(hdev, round_jiffies_relative(HZ)); 11730 11731 return 0; 11732 11733 err_mdiobus_unreg: 11734 if (hdev->hw.mac.phydev) 11735 mdiobus_unregister(hdev->hw.mac.mdio_bus); 11736 err_msi_irq_uninit: 11737 hclge_misc_irq_uninit(hdev); 11738 err_msi_uninit: 11739 pci_free_irq_vectors(pdev); 11740 err_cmd_uninit: 11741 hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw); 11742 err_devlink_uninit: 11743 hclge_devlink_uninit(hdev); 11744 err_pci_uninit: 11745 pcim_iounmap(pdev, hdev->hw.hw.io_base); 11746 pci_clear_master(pdev); 11747 pci_release_regions(pdev); 11748 pci_disable_device(pdev); 11749 out: 11750 mutex_destroy(&hdev->vport_lock); 11751 return ret; 11752 } 11753 11754 static void hclge_stats_clear(struct hclge_dev *hdev) 11755 { 11756 memset(&hdev->mac_stats, 0, sizeof(hdev->mac_stats)); 11757 memset(&hdev->fec_stats, 0, sizeof(hdev->fec_stats)); 11758 } 11759 11760 static int hclge_set_mac_spoofchk(struct hclge_dev *hdev, int vf, bool enable) 11761 { 11762 return hclge_config_switch_param(hdev, vf, enable, 11763 HCLGE_SWITCH_ANTI_SPOOF_MASK); 11764 } 11765 11766 static int hclge_set_vlan_spoofchk(struct hclge_dev *hdev, int vf, bool enable) 11767 { 11768 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 11769 HCLGE_FILTER_FE_NIC_INGRESS_B, 11770 enable, vf); 11771 } 11772 11773 static int hclge_set_vf_spoofchk_hw(struct hclge_dev *hdev, int vf, bool enable) 11774 { 11775 int ret; 11776 11777 ret = hclge_set_mac_spoofchk(hdev, vf, enable); 11778 if (ret) { 11779 dev_err(&hdev->pdev->dev, 11780 "Set vf %d mac spoof check %s failed, ret=%d\n", 11781 vf, enable ? "on" : "off", ret); 11782 return ret; 11783 } 11784 11785 ret = hclge_set_vlan_spoofchk(hdev, vf, enable); 11786 if (ret) 11787 dev_err(&hdev->pdev->dev, 11788 "Set vf %d vlan spoof check %s failed, ret=%d\n", 11789 vf, enable ? "on" : "off", ret); 11790 11791 return ret; 11792 } 11793 11794 static int hclge_set_vf_spoofchk(struct hnae3_handle *handle, int vf, 11795 bool enable) 11796 { 11797 struct hclge_vport *vport = hclge_get_vport(handle); 11798 struct hclge_dev *hdev = vport->back; 11799 u32 new_spoofchk = enable ? 1 : 0; 11800 int ret; 11801 11802 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 11803 return -EOPNOTSUPP; 11804 11805 vport = hclge_get_vf_vport(hdev, vf); 11806 if (!vport) 11807 return -EINVAL; 11808 11809 if (vport->vf_info.spoofchk == new_spoofchk) 11810 return 0; 11811 11812 if (enable && test_bit(vport->vport_id, hdev->vf_vlan_full)) 11813 dev_warn(&hdev->pdev->dev, 11814 "vf %d vlan table is full, enable spoof check may cause its packet send fail\n", 11815 vf); 11816 else if (enable && hclge_is_umv_space_full(vport, true)) 11817 dev_warn(&hdev->pdev->dev, 11818 "vf %d mac table is full, enable spoof check may cause its packet send fail\n", 11819 vf); 11820 11821 ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, enable); 11822 if (ret) 11823 return ret; 11824 11825 vport->vf_info.spoofchk = new_spoofchk; 11826 return 0; 11827 } 11828 11829 static int hclge_reset_vport_spoofchk(struct hclge_dev *hdev) 11830 { 11831 struct hclge_vport *vport = hdev->vport; 11832 int ret; 11833 int i; 11834 11835 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 11836 return 0; 11837 11838 /* resume the vf spoof check state after reset */ 11839 for (i = 0; i < hdev->num_alloc_vport; i++) { 11840 ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, 11841 vport->vf_info.spoofchk); 11842 if (ret) 11843 return ret; 11844 11845 vport++; 11846 } 11847 11848 return 0; 11849 } 11850 11851 static int hclge_set_vf_trust(struct hnae3_handle *handle, int vf, bool enable) 11852 { 11853 struct hclge_vport *vport = hclge_get_vport(handle); 11854 struct hclge_dev *hdev = vport->back; 11855 u32 new_trusted = enable ? 1 : 0; 11856 11857 vport = hclge_get_vf_vport(hdev, vf); 11858 if (!vport) 11859 return -EINVAL; 11860 11861 if (vport->vf_info.trusted == new_trusted) 11862 return 0; 11863 11864 vport->vf_info.trusted = new_trusted; 11865 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 11866 hclge_task_schedule(hdev, 0); 11867 11868 return 0; 11869 } 11870 11871 static void hclge_reset_vf_rate(struct hclge_dev *hdev) 11872 { 11873 int ret; 11874 int vf; 11875 11876 /* reset vf rate to default value */ 11877 for (vf = HCLGE_VF_VPORT_START_NUM; vf < hdev->num_alloc_vport; vf++) { 11878 struct hclge_vport *vport = &hdev->vport[vf]; 11879 11880 vport->vf_info.max_tx_rate = 0; 11881 ret = hclge_tm_qs_shaper_cfg(vport, vport->vf_info.max_tx_rate); 11882 if (ret) 11883 dev_err(&hdev->pdev->dev, 11884 "vf%d failed to reset to default, ret=%d\n", 11885 vf - HCLGE_VF_VPORT_START_NUM, ret); 11886 } 11887 } 11888 11889 static int hclge_vf_rate_param_check(struct hclge_dev *hdev, 11890 int min_tx_rate, int max_tx_rate) 11891 { 11892 if (min_tx_rate != 0 || 11893 max_tx_rate < 0 || max_tx_rate > hdev->hw.mac.max_speed) { 11894 dev_err(&hdev->pdev->dev, 11895 "min_tx_rate:%d [0], max_tx_rate:%d [0, %u]\n", 11896 min_tx_rate, max_tx_rate, hdev->hw.mac.max_speed); 11897 return -EINVAL; 11898 } 11899 11900 return 0; 11901 } 11902 11903 static int hclge_set_vf_rate(struct hnae3_handle *handle, int vf, 11904 int min_tx_rate, int max_tx_rate, bool force) 11905 { 11906 struct hclge_vport *vport = hclge_get_vport(handle); 11907 struct hclge_dev *hdev = vport->back; 11908 int ret; 11909 11910 ret = hclge_vf_rate_param_check(hdev, min_tx_rate, max_tx_rate); 11911 if (ret) 11912 return ret; 11913 11914 vport = hclge_get_vf_vport(hdev, vf); 11915 if (!vport) 11916 return -EINVAL; 11917 11918 if (!force && max_tx_rate == vport->vf_info.max_tx_rate) 11919 return 0; 11920 11921 ret = hclge_tm_qs_shaper_cfg(vport, max_tx_rate); 11922 if (ret) 11923 return ret; 11924 11925 vport->vf_info.max_tx_rate = max_tx_rate; 11926 11927 return 0; 11928 } 11929 11930 static int hclge_resume_vf_rate(struct hclge_dev *hdev) 11931 { 11932 struct hnae3_handle *handle = &hdev->vport->nic; 11933 struct hclge_vport *vport; 11934 int ret; 11935 int vf; 11936 11937 /* resume the vf max_tx_rate after reset */ 11938 for (vf = 0; vf < pci_num_vf(hdev->pdev); vf++) { 11939 vport = hclge_get_vf_vport(hdev, vf); 11940 if (!vport) 11941 return -EINVAL; 11942 11943 /* zero means max rate, after reset, firmware already set it to 11944 * max rate, so just continue. 11945 */ 11946 if (!vport->vf_info.max_tx_rate) 11947 continue; 11948 11949 ret = hclge_set_vf_rate(handle, vf, 0, 11950 vport->vf_info.max_tx_rate, true); 11951 if (ret) { 11952 dev_err(&hdev->pdev->dev, 11953 "vf%d failed to resume tx_rate:%u, ret=%d\n", 11954 vf, vport->vf_info.max_tx_rate, ret); 11955 return ret; 11956 } 11957 } 11958 11959 return 0; 11960 } 11961 11962 static void hclge_reset_vport_state(struct hclge_dev *hdev) 11963 { 11964 struct hclge_vport *vport = hdev->vport; 11965 int i; 11966 11967 for (i = 0; i < hdev->num_alloc_vport; i++) { 11968 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 11969 vport++; 11970 } 11971 } 11972 11973 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev) 11974 { 11975 struct hclge_dev *hdev = ae_dev->priv; 11976 struct pci_dev *pdev = ae_dev->pdev; 11977 int ret; 11978 11979 set_bit(HCLGE_STATE_DOWN, &hdev->state); 11980 11981 hclge_stats_clear(hdev); 11982 /* NOTE: pf reset needn't to clear or restore pf and vf table entry. 11983 * so here should not clean table in memory. 11984 */ 11985 if (hdev->reset_type == HNAE3_IMP_RESET || 11986 hdev->reset_type == HNAE3_GLOBAL_RESET) { 11987 memset(hdev->vlan_table, 0, sizeof(hdev->vlan_table)); 11988 memset(hdev->vf_vlan_full, 0, sizeof(hdev->vf_vlan_full)); 11989 bitmap_set(hdev->vport_config_block, 0, hdev->num_alloc_vport); 11990 hclge_reset_umv_space(hdev); 11991 } 11992 11993 ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, &hdev->fw_version, 11994 true, hdev->reset_pending); 11995 if (ret) { 11996 dev_err(&pdev->dev, "Cmd queue init failed\n"); 11997 return ret; 11998 } 11999 12000 ret = hclge_map_tqp(hdev); 12001 if (ret) { 12002 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret); 12003 return ret; 12004 } 12005 12006 ret = hclge_mac_init(hdev); 12007 if (ret) { 12008 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret); 12009 return ret; 12010 } 12011 12012 ret = hclge_tp_port_init(hdev); 12013 if (ret) { 12014 dev_err(&pdev->dev, "failed to init tp port, ret = %d\n", 12015 ret); 12016 return ret; 12017 } 12018 12019 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX); 12020 if (ret) { 12021 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret); 12022 return ret; 12023 } 12024 12025 ret = hclge_config_gro(hdev); 12026 if (ret) 12027 return ret; 12028 12029 ret = hclge_init_vlan_config(hdev); 12030 if (ret) { 12031 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret); 12032 return ret; 12033 } 12034 12035 ret = hclge_tm_init_hw(hdev, true); 12036 if (ret) { 12037 dev_err(&pdev->dev, "tm init hw fail, ret =%d\n", ret); 12038 return ret; 12039 } 12040 12041 ret = hclge_rss_init_hw(hdev); 12042 if (ret) { 12043 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret); 12044 return ret; 12045 } 12046 12047 ret = init_mgr_tbl(hdev); 12048 if (ret) { 12049 dev_err(&pdev->dev, 12050 "failed to reinit manager table, ret = %d\n", ret); 12051 return ret; 12052 } 12053 12054 ret = hclge_init_fd_config(hdev); 12055 if (ret) { 12056 dev_err(&pdev->dev, "fd table init fail, ret=%d\n", ret); 12057 return ret; 12058 } 12059 12060 ret = hclge_ptp_init(hdev); 12061 if (ret) 12062 return ret; 12063 12064 /* Log and clear the hw errors those already occurred */ 12065 if (hnae3_dev_ras_imp_supported(hdev)) 12066 hclge_handle_occurred_error(hdev); 12067 else 12068 hclge_handle_all_hns_hw_errors(ae_dev); 12069 12070 /* Re-enable the hw error interrupts because 12071 * the interrupts get disabled on global reset. 12072 */ 12073 ret = hclge_config_nic_hw_error(hdev, true); 12074 if (ret) { 12075 dev_err(&pdev->dev, 12076 "fail(%d) to re-enable NIC hw error interrupts\n", 12077 ret); 12078 return ret; 12079 } 12080 12081 if (hdev->roce_client) { 12082 ret = hclge_config_rocee_ras_interrupt(hdev, true); 12083 if (ret) { 12084 dev_err(&pdev->dev, 12085 "fail(%d) to re-enable roce ras interrupts\n", 12086 ret); 12087 return ret; 12088 } 12089 } 12090 12091 hclge_reset_vport_state(hdev); 12092 ret = hclge_reset_vport_spoofchk(hdev); 12093 if (ret) 12094 return ret; 12095 12096 ret = hclge_resume_vf_rate(hdev); 12097 if (ret) 12098 return ret; 12099 12100 hclge_init_rxd_adv_layout(hdev); 12101 12102 dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n", 12103 HCLGE_DRIVER_NAME); 12104 12105 return 0; 12106 } 12107 12108 static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 12109 { 12110 struct hclge_dev *hdev = ae_dev->priv; 12111 struct hclge_mac *mac = &hdev->hw.mac; 12112 12113 hclge_reset_vf_rate(hdev); 12114 hclge_clear_vf_vlan(hdev); 12115 hclge_state_uninit(hdev); 12116 hclge_ptp_uninit(hdev); 12117 hclge_uninit_rxd_adv_layout(hdev); 12118 hclge_uninit_mac_table(hdev); 12119 hclge_del_all_fd_entries(hdev); 12120 12121 if (mac->phydev) 12122 mdiobus_unregister(mac->mdio_bus); 12123 12124 /* Disable MISC vector(vector0) */ 12125 hclge_enable_vector(&hdev->misc_vector, false); 12126 synchronize_irq(hdev->misc_vector.vector_irq); 12127 12128 /* Disable all hw interrupts */ 12129 hclge_config_mac_tnl_int(hdev, false); 12130 hclge_config_nic_hw_error(hdev, false); 12131 hclge_config_rocee_ras_interrupt(hdev, false); 12132 12133 hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw); 12134 hclge_misc_irq_uninit(hdev); 12135 hclge_devlink_uninit(hdev); 12136 hclge_pci_uninit(hdev); 12137 hclge_uninit_vport_vlan_table(hdev); 12138 mutex_destroy(&hdev->vport_lock); 12139 ae_dev->priv = NULL; 12140 } 12141 12142 static u32 hclge_get_max_channels(struct hnae3_handle *handle) 12143 { 12144 struct hclge_vport *vport = hclge_get_vport(handle); 12145 struct hclge_dev *hdev = vport->back; 12146 12147 return min_t(u32, hdev->pf_rss_size_max, vport->alloc_tqps); 12148 } 12149 12150 static void hclge_get_channels(struct hnae3_handle *handle, 12151 struct ethtool_channels *ch) 12152 { 12153 ch->max_combined = hclge_get_max_channels(handle); 12154 ch->other_count = 1; 12155 ch->max_other = 1; 12156 ch->combined_count = handle->kinfo.rss_size; 12157 } 12158 12159 static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle, 12160 u16 *alloc_tqps, u16 *max_rss_size) 12161 { 12162 struct hclge_vport *vport = hclge_get_vport(handle); 12163 struct hclge_dev *hdev = vport->back; 12164 12165 *alloc_tqps = vport->alloc_tqps; 12166 *max_rss_size = hdev->pf_rss_size_max; 12167 } 12168 12169 static int hclge_set_rss_tc_mode_cfg(struct hnae3_handle *handle) 12170 { 12171 struct hclge_vport *vport = hclge_get_vport(handle); 12172 u16 tc_offset[HCLGE_MAX_TC_NUM] = {0}; 12173 struct hclge_dev *hdev = vport->back; 12174 u16 tc_size[HCLGE_MAX_TC_NUM] = {0}; 12175 u16 tc_valid[HCLGE_MAX_TC_NUM]; 12176 u16 roundup_size; 12177 unsigned int i; 12178 12179 roundup_size = roundup_pow_of_two(vport->nic.kinfo.rss_size); 12180 roundup_size = ilog2(roundup_size); 12181 /* Set the RSS TC mode according to the new RSS size */ 12182 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 12183 tc_valid[i] = 0; 12184 12185 if (!(hdev->hw_tc_map & BIT(i))) 12186 continue; 12187 12188 tc_valid[i] = 1; 12189 tc_size[i] = roundup_size; 12190 tc_offset[i] = vport->nic.kinfo.rss_size * i; 12191 } 12192 12193 return hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, tc_valid, 12194 tc_size); 12195 } 12196 12197 static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num, 12198 bool rxfh_configured) 12199 { 12200 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 12201 struct hclge_vport *vport = hclge_get_vport(handle); 12202 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 12203 struct hclge_dev *hdev = vport->back; 12204 u16 cur_rss_size = kinfo->rss_size; 12205 u16 cur_tqps = kinfo->num_tqps; 12206 u32 *rss_indir; 12207 unsigned int i; 12208 int ret; 12209 12210 kinfo->req_rss_size = new_tqps_num; 12211 12212 ret = hclge_tm_vport_map_update(hdev); 12213 if (ret) { 12214 dev_err(&hdev->pdev->dev, "tm vport map fail, ret =%d\n", ret); 12215 return ret; 12216 } 12217 12218 ret = hclge_set_rss_tc_mode_cfg(handle); 12219 if (ret) 12220 return ret; 12221 12222 /* RSS indirection table has been configured by user */ 12223 if (rxfh_configured) 12224 goto out; 12225 12226 /* Reinitializes the rss indirect table according to the new RSS size */ 12227 rss_indir = kcalloc(ae_dev->dev_specs.rss_ind_tbl_size, sizeof(u32), 12228 GFP_KERNEL); 12229 if (!rss_indir) 12230 return -ENOMEM; 12231 12232 for (i = 0; i < ae_dev->dev_specs.rss_ind_tbl_size; i++) 12233 rss_indir[i] = i % kinfo->rss_size; 12234 12235 ret = hclge_set_rss(handle, rss_indir, NULL, 0); 12236 if (ret) 12237 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n", 12238 ret); 12239 12240 kfree(rss_indir); 12241 12242 out: 12243 if (!ret) 12244 dev_info(&hdev->pdev->dev, 12245 "Channels changed, rss_size from %u to %u, tqps from %u to %u", 12246 cur_rss_size, kinfo->rss_size, 12247 cur_tqps, kinfo->rss_size * kinfo->tc_info.num_tc); 12248 12249 return ret; 12250 } 12251 12252 static int hclge_get_regs_num(struct hclge_dev *hdev, u32 *regs_num_32_bit, 12253 u32 *regs_num_64_bit) 12254 { 12255 struct hclge_desc desc; 12256 u32 total_num; 12257 int ret; 12258 12259 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_REG_NUM, true); 12260 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 12261 if (ret) { 12262 dev_err(&hdev->pdev->dev, 12263 "Query register number cmd failed, ret = %d.\n", ret); 12264 return ret; 12265 } 12266 12267 *regs_num_32_bit = le32_to_cpu(desc.data[0]); 12268 *regs_num_64_bit = le32_to_cpu(desc.data[1]); 12269 12270 total_num = *regs_num_32_bit + *regs_num_64_bit; 12271 if (!total_num) 12272 return -EINVAL; 12273 12274 return 0; 12275 } 12276 12277 static int hclge_get_32_bit_regs(struct hclge_dev *hdev, u32 regs_num, 12278 void *data) 12279 { 12280 #define HCLGE_32_BIT_REG_RTN_DATANUM 8 12281 #define HCLGE_32_BIT_DESC_NODATA_LEN 2 12282 12283 struct hclge_desc *desc; 12284 u32 *reg_val = data; 12285 __le32 *desc_data; 12286 int nodata_num; 12287 int cmd_num; 12288 int i, k, n; 12289 int ret; 12290 12291 if (regs_num == 0) 12292 return 0; 12293 12294 nodata_num = HCLGE_32_BIT_DESC_NODATA_LEN; 12295 cmd_num = DIV_ROUND_UP(regs_num + nodata_num, 12296 HCLGE_32_BIT_REG_RTN_DATANUM); 12297 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL); 12298 if (!desc) 12299 return -ENOMEM; 12300 12301 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_32_BIT_REG, true); 12302 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num); 12303 if (ret) { 12304 dev_err(&hdev->pdev->dev, 12305 "Query 32 bit register cmd failed, ret = %d.\n", ret); 12306 kfree(desc); 12307 return ret; 12308 } 12309 12310 for (i = 0; i < cmd_num; i++) { 12311 if (i == 0) { 12312 desc_data = (__le32 *)(&desc[i].data[0]); 12313 n = HCLGE_32_BIT_REG_RTN_DATANUM - nodata_num; 12314 } else { 12315 desc_data = (__le32 *)(&desc[i]); 12316 n = HCLGE_32_BIT_REG_RTN_DATANUM; 12317 } 12318 for (k = 0; k < n; k++) { 12319 *reg_val++ = le32_to_cpu(*desc_data++); 12320 12321 regs_num--; 12322 if (!regs_num) 12323 break; 12324 } 12325 } 12326 12327 kfree(desc); 12328 return 0; 12329 } 12330 12331 static int hclge_get_64_bit_regs(struct hclge_dev *hdev, u32 regs_num, 12332 void *data) 12333 { 12334 #define HCLGE_64_BIT_REG_RTN_DATANUM 4 12335 #define HCLGE_64_BIT_DESC_NODATA_LEN 1 12336 12337 struct hclge_desc *desc; 12338 u64 *reg_val = data; 12339 __le64 *desc_data; 12340 int nodata_len; 12341 int cmd_num; 12342 int i, k, n; 12343 int ret; 12344 12345 if (regs_num == 0) 12346 return 0; 12347 12348 nodata_len = HCLGE_64_BIT_DESC_NODATA_LEN; 12349 cmd_num = DIV_ROUND_UP(regs_num + nodata_len, 12350 HCLGE_64_BIT_REG_RTN_DATANUM); 12351 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL); 12352 if (!desc) 12353 return -ENOMEM; 12354 12355 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_64_BIT_REG, true); 12356 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num); 12357 if (ret) { 12358 dev_err(&hdev->pdev->dev, 12359 "Query 64 bit register cmd failed, ret = %d.\n", ret); 12360 kfree(desc); 12361 return ret; 12362 } 12363 12364 for (i = 0; i < cmd_num; i++) { 12365 if (i == 0) { 12366 desc_data = (__le64 *)(&desc[i].data[0]); 12367 n = HCLGE_64_BIT_REG_RTN_DATANUM - nodata_len; 12368 } else { 12369 desc_data = (__le64 *)(&desc[i]); 12370 n = HCLGE_64_BIT_REG_RTN_DATANUM; 12371 } 12372 for (k = 0; k < n; k++) { 12373 *reg_val++ = le64_to_cpu(*desc_data++); 12374 12375 regs_num--; 12376 if (!regs_num) 12377 break; 12378 } 12379 } 12380 12381 kfree(desc); 12382 return 0; 12383 } 12384 12385 #define MAX_SEPARATE_NUM 4 12386 #define SEPARATOR_VALUE 0xFDFCFBFA 12387 #define REG_NUM_PER_LINE 4 12388 #define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32)) 12389 #define REG_SEPARATOR_LINE 1 12390 #define REG_NUM_REMAIN_MASK 3 12391 12392 int hclge_query_bd_num_cmd_send(struct hclge_dev *hdev, struct hclge_desc *desc) 12393 { 12394 int i; 12395 12396 /* initialize command BD except the last one */ 12397 for (i = 0; i < HCLGE_GET_DFX_REG_TYPE_CNT - 1; i++) { 12398 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_DFX_BD_NUM, 12399 true); 12400 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 12401 } 12402 12403 /* initialize the last command BD */ 12404 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_DFX_BD_NUM, true); 12405 12406 return hclge_cmd_send(&hdev->hw, desc, HCLGE_GET_DFX_REG_TYPE_CNT); 12407 } 12408 12409 static int hclge_get_dfx_reg_bd_num(struct hclge_dev *hdev, 12410 int *bd_num_list, 12411 u32 type_num) 12412 { 12413 u32 entries_per_desc, desc_index, index, offset, i; 12414 struct hclge_desc desc[HCLGE_GET_DFX_REG_TYPE_CNT]; 12415 int ret; 12416 12417 ret = hclge_query_bd_num_cmd_send(hdev, desc); 12418 if (ret) { 12419 dev_err(&hdev->pdev->dev, 12420 "Get dfx bd num fail, status is %d.\n", ret); 12421 return ret; 12422 } 12423 12424 entries_per_desc = ARRAY_SIZE(desc[0].data); 12425 for (i = 0; i < type_num; i++) { 12426 offset = hclge_dfx_bd_offset_list[i]; 12427 index = offset % entries_per_desc; 12428 desc_index = offset / entries_per_desc; 12429 bd_num_list[i] = le32_to_cpu(desc[desc_index].data[index]); 12430 } 12431 12432 return ret; 12433 } 12434 12435 static int hclge_dfx_reg_cmd_send(struct hclge_dev *hdev, 12436 struct hclge_desc *desc_src, int bd_num, 12437 enum hclge_opcode_type cmd) 12438 { 12439 struct hclge_desc *desc = desc_src; 12440 int i, ret; 12441 12442 hclge_cmd_setup_basic_desc(desc, cmd, true); 12443 for (i = 0; i < bd_num - 1; i++) { 12444 desc->flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 12445 desc++; 12446 hclge_cmd_setup_basic_desc(desc, cmd, true); 12447 } 12448 12449 desc = desc_src; 12450 ret = hclge_cmd_send(&hdev->hw, desc, bd_num); 12451 if (ret) 12452 dev_err(&hdev->pdev->dev, 12453 "Query dfx reg cmd(0x%x) send fail, status is %d.\n", 12454 cmd, ret); 12455 12456 return ret; 12457 } 12458 12459 static int hclge_dfx_reg_fetch_data(struct hclge_desc *desc_src, int bd_num, 12460 void *data) 12461 { 12462 int entries_per_desc, reg_num, separator_num, desc_index, index, i; 12463 struct hclge_desc *desc = desc_src; 12464 u32 *reg = data; 12465 12466 entries_per_desc = ARRAY_SIZE(desc->data); 12467 reg_num = entries_per_desc * bd_num; 12468 separator_num = REG_NUM_PER_LINE - (reg_num & REG_NUM_REMAIN_MASK); 12469 for (i = 0; i < reg_num; i++) { 12470 index = i % entries_per_desc; 12471 desc_index = i / entries_per_desc; 12472 *reg++ = le32_to_cpu(desc[desc_index].data[index]); 12473 } 12474 for (i = 0; i < separator_num; i++) 12475 *reg++ = SEPARATOR_VALUE; 12476 12477 return reg_num + separator_num; 12478 } 12479 12480 static int hclge_get_dfx_reg_len(struct hclge_dev *hdev, int *len) 12481 { 12482 u32 dfx_reg_type_num = ARRAY_SIZE(hclge_dfx_bd_offset_list); 12483 int data_len_per_desc, bd_num, i; 12484 int *bd_num_list; 12485 u32 data_len; 12486 int ret; 12487 12488 bd_num_list = kcalloc(dfx_reg_type_num, sizeof(int), GFP_KERNEL); 12489 if (!bd_num_list) 12490 return -ENOMEM; 12491 12492 ret = hclge_get_dfx_reg_bd_num(hdev, bd_num_list, dfx_reg_type_num); 12493 if (ret) { 12494 dev_err(&hdev->pdev->dev, 12495 "Get dfx reg bd num fail, status is %d.\n", ret); 12496 goto out; 12497 } 12498 12499 data_len_per_desc = sizeof_field(struct hclge_desc, data); 12500 *len = 0; 12501 for (i = 0; i < dfx_reg_type_num; i++) { 12502 bd_num = bd_num_list[i]; 12503 data_len = data_len_per_desc * bd_num; 12504 *len += (data_len / REG_LEN_PER_LINE + 1) * REG_LEN_PER_LINE; 12505 } 12506 12507 out: 12508 kfree(bd_num_list); 12509 return ret; 12510 } 12511 12512 static int hclge_get_dfx_reg(struct hclge_dev *hdev, void *data) 12513 { 12514 u32 dfx_reg_type_num = ARRAY_SIZE(hclge_dfx_bd_offset_list); 12515 int bd_num, bd_num_max, buf_len, i; 12516 struct hclge_desc *desc_src; 12517 int *bd_num_list; 12518 u32 *reg = data; 12519 int ret; 12520 12521 bd_num_list = kcalloc(dfx_reg_type_num, sizeof(int), GFP_KERNEL); 12522 if (!bd_num_list) 12523 return -ENOMEM; 12524 12525 ret = hclge_get_dfx_reg_bd_num(hdev, bd_num_list, dfx_reg_type_num); 12526 if (ret) { 12527 dev_err(&hdev->pdev->dev, 12528 "Get dfx reg bd num fail, status is %d.\n", ret); 12529 goto out; 12530 } 12531 12532 bd_num_max = bd_num_list[0]; 12533 for (i = 1; i < dfx_reg_type_num; i++) 12534 bd_num_max = max_t(int, bd_num_max, bd_num_list[i]); 12535 12536 buf_len = sizeof(*desc_src) * bd_num_max; 12537 desc_src = kzalloc(buf_len, GFP_KERNEL); 12538 if (!desc_src) { 12539 ret = -ENOMEM; 12540 goto out; 12541 } 12542 12543 for (i = 0; i < dfx_reg_type_num; i++) { 12544 bd_num = bd_num_list[i]; 12545 ret = hclge_dfx_reg_cmd_send(hdev, desc_src, bd_num, 12546 hclge_dfx_reg_opcode_list[i]); 12547 if (ret) { 12548 dev_err(&hdev->pdev->dev, 12549 "Get dfx reg fail, status is %d.\n", ret); 12550 break; 12551 } 12552 12553 reg += hclge_dfx_reg_fetch_data(desc_src, bd_num, reg); 12554 } 12555 12556 kfree(desc_src); 12557 out: 12558 kfree(bd_num_list); 12559 return ret; 12560 } 12561 12562 static int hclge_fetch_pf_reg(struct hclge_dev *hdev, void *data, 12563 struct hnae3_knic_private_info *kinfo) 12564 { 12565 #define HCLGE_RING_REG_OFFSET 0x200 12566 #define HCLGE_RING_INT_REG_OFFSET 0x4 12567 12568 int i, j, reg_num, separator_num; 12569 int data_num_sum; 12570 u32 *reg = data; 12571 12572 /* fetching per-PF registers valus from PF PCIe register space */ 12573 reg_num = ARRAY_SIZE(cmdq_reg_addr_list); 12574 separator_num = MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK); 12575 for (i = 0; i < reg_num; i++) 12576 *reg++ = hclge_read_dev(&hdev->hw, cmdq_reg_addr_list[i]); 12577 for (i = 0; i < separator_num; i++) 12578 *reg++ = SEPARATOR_VALUE; 12579 data_num_sum = reg_num + separator_num; 12580 12581 reg_num = ARRAY_SIZE(common_reg_addr_list); 12582 separator_num = MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK); 12583 for (i = 0; i < reg_num; i++) 12584 *reg++ = hclge_read_dev(&hdev->hw, common_reg_addr_list[i]); 12585 for (i = 0; i < separator_num; i++) 12586 *reg++ = SEPARATOR_VALUE; 12587 data_num_sum += reg_num + separator_num; 12588 12589 reg_num = ARRAY_SIZE(ring_reg_addr_list); 12590 separator_num = MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK); 12591 for (j = 0; j < kinfo->num_tqps; j++) { 12592 for (i = 0; i < reg_num; i++) 12593 *reg++ = hclge_read_dev(&hdev->hw, 12594 ring_reg_addr_list[i] + 12595 HCLGE_RING_REG_OFFSET * j); 12596 for (i = 0; i < separator_num; i++) 12597 *reg++ = SEPARATOR_VALUE; 12598 } 12599 data_num_sum += (reg_num + separator_num) * kinfo->num_tqps; 12600 12601 reg_num = ARRAY_SIZE(tqp_intr_reg_addr_list); 12602 separator_num = MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK); 12603 for (j = 0; j < hdev->num_msi_used - 1; j++) { 12604 for (i = 0; i < reg_num; i++) 12605 *reg++ = hclge_read_dev(&hdev->hw, 12606 tqp_intr_reg_addr_list[i] + 12607 HCLGE_RING_INT_REG_OFFSET * j); 12608 for (i = 0; i < separator_num; i++) 12609 *reg++ = SEPARATOR_VALUE; 12610 } 12611 data_num_sum += (reg_num + separator_num) * (hdev->num_msi_used - 1); 12612 12613 return data_num_sum; 12614 } 12615 12616 static int hclge_get_regs_len(struct hnae3_handle *handle) 12617 { 12618 int cmdq_lines, common_lines, ring_lines, tqp_intr_lines; 12619 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 12620 struct hclge_vport *vport = hclge_get_vport(handle); 12621 struct hclge_dev *hdev = vport->back; 12622 int regs_num_32_bit, regs_num_64_bit, dfx_regs_len; 12623 int regs_lines_32_bit, regs_lines_64_bit; 12624 int ret; 12625 12626 ret = hclge_get_regs_num(hdev, ®s_num_32_bit, ®s_num_64_bit); 12627 if (ret) { 12628 dev_err(&hdev->pdev->dev, 12629 "Get register number failed, ret = %d.\n", ret); 12630 return ret; 12631 } 12632 12633 ret = hclge_get_dfx_reg_len(hdev, &dfx_regs_len); 12634 if (ret) { 12635 dev_err(&hdev->pdev->dev, 12636 "Get dfx reg len failed, ret = %d.\n", ret); 12637 return ret; 12638 } 12639 12640 cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 12641 REG_SEPARATOR_LINE; 12642 common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 12643 REG_SEPARATOR_LINE; 12644 ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 12645 REG_SEPARATOR_LINE; 12646 tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 12647 REG_SEPARATOR_LINE; 12648 regs_lines_32_bit = regs_num_32_bit * sizeof(u32) / REG_LEN_PER_LINE + 12649 REG_SEPARATOR_LINE; 12650 regs_lines_64_bit = regs_num_64_bit * sizeof(u64) / REG_LEN_PER_LINE + 12651 REG_SEPARATOR_LINE; 12652 12653 return (cmdq_lines + common_lines + ring_lines * kinfo->num_tqps + 12654 tqp_intr_lines * (hdev->num_msi_used - 1) + regs_lines_32_bit + 12655 regs_lines_64_bit) * REG_LEN_PER_LINE + dfx_regs_len; 12656 } 12657 12658 static void hclge_get_regs(struct hnae3_handle *handle, u32 *version, 12659 void *data) 12660 { 12661 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 12662 struct hclge_vport *vport = hclge_get_vport(handle); 12663 struct hclge_dev *hdev = vport->back; 12664 u32 regs_num_32_bit, regs_num_64_bit; 12665 int i, reg_num, separator_num, ret; 12666 u32 *reg = data; 12667 12668 *version = hdev->fw_version; 12669 12670 ret = hclge_get_regs_num(hdev, ®s_num_32_bit, ®s_num_64_bit); 12671 if (ret) { 12672 dev_err(&hdev->pdev->dev, 12673 "Get register number failed, ret = %d.\n", ret); 12674 return; 12675 } 12676 12677 reg += hclge_fetch_pf_reg(hdev, reg, kinfo); 12678 12679 ret = hclge_get_32_bit_regs(hdev, regs_num_32_bit, reg); 12680 if (ret) { 12681 dev_err(&hdev->pdev->dev, 12682 "Get 32 bit register failed, ret = %d.\n", ret); 12683 return; 12684 } 12685 reg_num = regs_num_32_bit; 12686 reg += reg_num; 12687 separator_num = MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK); 12688 for (i = 0; i < separator_num; i++) 12689 *reg++ = SEPARATOR_VALUE; 12690 12691 ret = hclge_get_64_bit_regs(hdev, regs_num_64_bit, reg); 12692 if (ret) { 12693 dev_err(&hdev->pdev->dev, 12694 "Get 64 bit register failed, ret = %d.\n", ret); 12695 return; 12696 } 12697 reg_num = regs_num_64_bit * 2; 12698 reg += reg_num; 12699 separator_num = MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK); 12700 for (i = 0; i < separator_num; i++) 12701 *reg++ = SEPARATOR_VALUE; 12702 12703 ret = hclge_get_dfx_reg(hdev, reg); 12704 if (ret) 12705 dev_err(&hdev->pdev->dev, 12706 "Get dfx register failed, ret = %d.\n", ret); 12707 } 12708 12709 static int hclge_set_led_status(struct hclge_dev *hdev, u8 locate_led_status) 12710 { 12711 struct hclge_set_led_state_cmd *req; 12712 struct hclge_desc desc; 12713 int ret; 12714 12715 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_LED_STATUS_CFG, false); 12716 12717 req = (struct hclge_set_led_state_cmd *)desc.data; 12718 hnae3_set_field(req->locate_led_config, HCLGE_LED_LOCATE_STATE_M, 12719 HCLGE_LED_LOCATE_STATE_S, locate_led_status); 12720 12721 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 12722 if (ret) 12723 dev_err(&hdev->pdev->dev, 12724 "Send set led state cmd error, ret =%d\n", ret); 12725 12726 return ret; 12727 } 12728 12729 enum hclge_led_status { 12730 HCLGE_LED_OFF, 12731 HCLGE_LED_ON, 12732 HCLGE_LED_NO_CHANGE = 0xFF, 12733 }; 12734 12735 static int hclge_set_led_id(struct hnae3_handle *handle, 12736 enum ethtool_phys_id_state status) 12737 { 12738 struct hclge_vport *vport = hclge_get_vport(handle); 12739 struct hclge_dev *hdev = vport->back; 12740 12741 switch (status) { 12742 case ETHTOOL_ID_ACTIVE: 12743 return hclge_set_led_status(hdev, HCLGE_LED_ON); 12744 case ETHTOOL_ID_INACTIVE: 12745 return hclge_set_led_status(hdev, HCLGE_LED_OFF); 12746 default: 12747 return -EINVAL; 12748 } 12749 } 12750 12751 static void hclge_get_link_mode(struct hnae3_handle *handle, 12752 unsigned long *supported, 12753 unsigned long *advertising) 12754 { 12755 unsigned int size = BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS); 12756 struct hclge_vport *vport = hclge_get_vport(handle); 12757 struct hclge_dev *hdev = vport->back; 12758 unsigned int idx = 0; 12759 12760 for (; idx < size; idx++) { 12761 supported[idx] = hdev->hw.mac.supported[idx]; 12762 advertising[idx] = hdev->hw.mac.advertising[idx]; 12763 } 12764 } 12765 12766 static int hclge_gro_en(struct hnae3_handle *handle, bool enable) 12767 { 12768 struct hclge_vport *vport = hclge_get_vport(handle); 12769 struct hclge_dev *hdev = vport->back; 12770 bool gro_en_old = hdev->gro_en; 12771 int ret; 12772 12773 hdev->gro_en = enable; 12774 ret = hclge_config_gro(hdev); 12775 if (ret) 12776 hdev->gro_en = gro_en_old; 12777 12778 return ret; 12779 } 12780 12781 static int hclge_sync_vport_promisc_mode(struct hclge_vport *vport) 12782 { 12783 struct hnae3_handle *handle = &vport->nic; 12784 struct hclge_dev *hdev = vport->back; 12785 bool uc_en = false; 12786 bool mc_en = false; 12787 u8 tmp_flags; 12788 bool bc_en; 12789 int ret; 12790 12791 if (vport->last_promisc_flags != vport->overflow_promisc_flags) { 12792 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 12793 vport->last_promisc_flags = vport->overflow_promisc_flags; 12794 } 12795 12796 if (!test_and_clear_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, 12797 &vport->state)) 12798 return 0; 12799 12800 /* for PF */ 12801 if (!vport->vport_id) { 12802 tmp_flags = handle->netdev_flags | vport->last_promisc_flags; 12803 ret = hclge_set_promisc_mode(handle, tmp_flags & HNAE3_UPE, 12804 tmp_flags & HNAE3_MPE); 12805 if (!ret) 12806 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 12807 &vport->state); 12808 else 12809 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, 12810 &vport->state); 12811 return ret; 12812 } 12813 12814 /* for VF */ 12815 if (vport->vf_info.trusted) { 12816 uc_en = vport->vf_info.request_uc_en > 0 || 12817 vport->overflow_promisc_flags & HNAE3_OVERFLOW_UPE; 12818 mc_en = vport->vf_info.request_mc_en > 0 || 12819 vport->overflow_promisc_flags & HNAE3_OVERFLOW_MPE; 12820 } 12821 bc_en = vport->vf_info.request_bc_en > 0; 12822 12823 ret = hclge_cmd_set_promisc_mode(hdev, vport->vport_id, uc_en, 12824 mc_en, bc_en); 12825 if (ret) { 12826 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 12827 return ret; 12828 } 12829 hclge_set_vport_vlan_fltr_change(vport); 12830 12831 return 0; 12832 } 12833 12834 static void hclge_sync_promisc_mode(struct hclge_dev *hdev) 12835 { 12836 struct hclge_vport *vport; 12837 int ret; 12838 u16 i; 12839 12840 for (i = 0; i < hdev->num_alloc_vport; i++) { 12841 vport = &hdev->vport[i]; 12842 12843 ret = hclge_sync_vport_promisc_mode(vport); 12844 if (ret) 12845 return; 12846 } 12847 } 12848 12849 static bool hclge_module_existed(struct hclge_dev *hdev) 12850 { 12851 struct hclge_desc desc; 12852 u32 existed; 12853 int ret; 12854 12855 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_EXIST, true); 12856 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 12857 if (ret) { 12858 dev_err(&hdev->pdev->dev, 12859 "failed to get SFP exist state, ret = %d\n", ret); 12860 return false; 12861 } 12862 12863 existed = le32_to_cpu(desc.data[0]); 12864 12865 return existed != 0; 12866 } 12867 12868 /* need 6 bds(total 140 bytes) in one reading 12869 * return the number of bytes actually read, 0 means read failed. 12870 */ 12871 static u16 hclge_get_sfp_eeprom_info(struct hclge_dev *hdev, u32 offset, 12872 u32 len, u8 *data) 12873 { 12874 struct hclge_desc desc[HCLGE_SFP_INFO_CMD_NUM]; 12875 struct hclge_sfp_info_bd0_cmd *sfp_info_bd0; 12876 u16 read_len; 12877 u16 copy_len; 12878 int ret; 12879 int i; 12880 12881 /* setup all 6 bds to read module eeprom info. */ 12882 for (i = 0; i < HCLGE_SFP_INFO_CMD_NUM; i++) { 12883 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_SFP_EEPROM, 12884 true); 12885 12886 /* bd0~bd4 need next flag */ 12887 if (i < HCLGE_SFP_INFO_CMD_NUM - 1) 12888 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 12889 } 12890 12891 /* setup bd0, this bd contains offset and read length. */ 12892 sfp_info_bd0 = (struct hclge_sfp_info_bd0_cmd *)desc[0].data; 12893 sfp_info_bd0->offset = cpu_to_le16((u16)offset); 12894 read_len = min_t(u16, len, HCLGE_SFP_INFO_MAX_LEN); 12895 sfp_info_bd0->read_len = cpu_to_le16(read_len); 12896 12897 ret = hclge_cmd_send(&hdev->hw, desc, i); 12898 if (ret) { 12899 dev_err(&hdev->pdev->dev, 12900 "failed to get SFP eeprom info, ret = %d\n", ret); 12901 return 0; 12902 } 12903 12904 /* copy sfp info from bd0 to out buffer. */ 12905 copy_len = min_t(u16, len, HCLGE_SFP_INFO_BD0_LEN); 12906 memcpy(data, sfp_info_bd0->data, copy_len); 12907 read_len = copy_len; 12908 12909 /* copy sfp info from bd1~bd5 to out buffer if needed. */ 12910 for (i = 1; i < HCLGE_SFP_INFO_CMD_NUM; i++) { 12911 if (read_len >= len) 12912 return read_len; 12913 12914 copy_len = min_t(u16, len - read_len, HCLGE_SFP_INFO_BDX_LEN); 12915 memcpy(data + read_len, desc[i].data, copy_len); 12916 read_len += copy_len; 12917 } 12918 12919 return read_len; 12920 } 12921 12922 static int hclge_get_module_eeprom(struct hnae3_handle *handle, u32 offset, 12923 u32 len, u8 *data) 12924 { 12925 struct hclge_vport *vport = hclge_get_vport(handle); 12926 struct hclge_dev *hdev = vport->back; 12927 u32 read_len = 0; 12928 u16 data_len; 12929 12930 if (hdev->hw.mac.media_type != HNAE3_MEDIA_TYPE_FIBER) 12931 return -EOPNOTSUPP; 12932 12933 if (!hclge_module_existed(hdev)) 12934 return -ENXIO; 12935 12936 while (read_len < len) { 12937 data_len = hclge_get_sfp_eeprom_info(hdev, 12938 offset + read_len, 12939 len - read_len, 12940 data + read_len); 12941 if (!data_len) 12942 return -EIO; 12943 12944 read_len += data_len; 12945 } 12946 12947 return 0; 12948 } 12949 12950 static int hclge_get_link_diagnosis_info(struct hnae3_handle *handle, 12951 u32 *status_code) 12952 { 12953 struct hclge_vport *vport = hclge_get_vport(handle); 12954 struct hclge_dev *hdev = vport->back; 12955 struct hclge_desc desc; 12956 int ret; 12957 12958 if (hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2) 12959 return -EOPNOTSUPP; 12960 12961 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_DIAGNOSIS, true); 12962 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 12963 if (ret) { 12964 dev_err(&hdev->pdev->dev, 12965 "failed to query link diagnosis info, ret = %d\n", ret); 12966 return ret; 12967 } 12968 12969 *status_code = le32_to_cpu(desc.data[0]); 12970 return 0; 12971 } 12972 12973 /* After disable sriov, VF still has some config and info need clean, 12974 * which configed by PF. 12975 */ 12976 static void hclge_clear_vport_vf_info(struct hclge_vport *vport, int vfid) 12977 { 12978 struct hclge_dev *hdev = vport->back; 12979 struct hclge_vlan_info vlan_info; 12980 int ret; 12981 12982 clear_bit(HCLGE_VPORT_STATE_INITED, &vport->state); 12983 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 12984 vport->need_notify = 0; 12985 vport->mps = 0; 12986 12987 /* after disable sriov, clean VF rate configured by PF */ 12988 ret = hclge_tm_qs_shaper_cfg(vport, 0); 12989 if (ret) 12990 dev_err(&hdev->pdev->dev, 12991 "failed to clean vf%d rate config, ret = %d\n", 12992 vfid, ret); 12993 12994 vlan_info.vlan_tag = 0; 12995 vlan_info.qos = 0; 12996 vlan_info.vlan_proto = ETH_P_8021Q; 12997 ret = hclge_update_port_base_vlan_cfg(vport, 12998 HNAE3_PORT_BASE_VLAN_DISABLE, 12999 &vlan_info); 13000 if (ret) 13001 dev_err(&hdev->pdev->dev, 13002 "failed to clean vf%d port base vlan, ret = %d\n", 13003 vfid, ret); 13004 13005 ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, false); 13006 if (ret) 13007 dev_err(&hdev->pdev->dev, 13008 "failed to clean vf%d spoof config, ret = %d\n", 13009 vfid, ret); 13010 13011 memset(&vport->vf_info, 0, sizeof(vport->vf_info)); 13012 } 13013 13014 static void hclge_clean_vport_config(struct hnae3_ae_dev *ae_dev, int num_vfs) 13015 { 13016 struct hclge_dev *hdev = ae_dev->priv; 13017 struct hclge_vport *vport; 13018 int i; 13019 13020 for (i = 0; i < num_vfs; i++) { 13021 vport = &hdev->vport[i + HCLGE_VF_VPORT_START_NUM]; 13022 13023 hclge_clear_vport_vf_info(vport, i); 13024 } 13025 } 13026 13027 static int hclge_get_dscp_prio(struct hnae3_handle *h, u8 dscp, u8 *tc_mode, 13028 u8 *priority) 13029 { 13030 struct hclge_vport *vport = hclge_get_vport(h); 13031 13032 if (dscp >= HNAE3_MAX_DSCP) 13033 return -EINVAL; 13034 13035 if (tc_mode) 13036 *tc_mode = vport->nic.kinfo.tc_map_mode; 13037 if (priority) 13038 *priority = vport->nic.kinfo.dscp_prio[dscp] == HNAE3_PRIO_ID_INVALID ? 0 : 13039 vport->nic.kinfo.dscp_prio[dscp]; 13040 13041 return 0; 13042 } 13043 13044 static const struct hnae3_ae_ops hclge_ops = { 13045 .init_ae_dev = hclge_init_ae_dev, 13046 .uninit_ae_dev = hclge_uninit_ae_dev, 13047 .reset_prepare = hclge_reset_prepare_general, 13048 .reset_done = hclge_reset_done, 13049 .init_client_instance = hclge_init_client_instance, 13050 .uninit_client_instance = hclge_uninit_client_instance, 13051 .map_ring_to_vector = hclge_map_ring_to_vector, 13052 .unmap_ring_from_vector = hclge_unmap_ring_frm_vector, 13053 .get_vector = hclge_get_vector, 13054 .put_vector = hclge_put_vector, 13055 .set_promisc_mode = hclge_set_promisc_mode, 13056 .request_update_promisc_mode = hclge_request_update_promisc_mode, 13057 .set_loopback = hclge_set_loopback, 13058 .start = hclge_ae_start, 13059 .stop = hclge_ae_stop, 13060 .client_start = hclge_client_start, 13061 .client_stop = hclge_client_stop, 13062 .get_status = hclge_get_status, 13063 .get_ksettings_an_result = hclge_get_ksettings_an_result, 13064 .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h, 13065 .get_media_type = hclge_get_media_type, 13066 .check_port_speed = hclge_check_port_speed, 13067 .get_fec_stats = hclge_get_fec_stats, 13068 .get_fec = hclge_get_fec, 13069 .set_fec = hclge_set_fec, 13070 .get_rss_key_size = hclge_comm_get_rss_key_size, 13071 .get_rss = hclge_get_rss, 13072 .set_rss = hclge_set_rss, 13073 .set_rss_tuple = hclge_set_rss_tuple, 13074 .get_rss_tuple = hclge_get_rss_tuple, 13075 .get_tc_size = hclge_get_tc_size, 13076 .get_mac_addr = hclge_get_mac_addr, 13077 .set_mac_addr = hclge_set_mac_addr, 13078 .do_ioctl = hclge_do_ioctl, 13079 .add_uc_addr = hclge_add_uc_addr, 13080 .rm_uc_addr = hclge_rm_uc_addr, 13081 .add_mc_addr = hclge_add_mc_addr, 13082 .rm_mc_addr = hclge_rm_mc_addr, 13083 .set_autoneg = hclge_set_autoneg, 13084 .get_autoneg = hclge_get_autoneg, 13085 .restart_autoneg = hclge_restart_autoneg, 13086 .halt_autoneg = hclge_halt_autoneg, 13087 .get_pauseparam = hclge_get_pauseparam, 13088 .set_pauseparam = hclge_set_pauseparam, 13089 .set_mtu = hclge_set_mtu, 13090 .reset_queue = hclge_reset_tqp, 13091 .get_stats = hclge_get_stats, 13092 .get_mac_stats = hclge_get_mac_stat, 13093 .update_stats = hclge_update_stats, 13094 .get_strings = hclge_get_strings, 13095 .get_sset_count = hclge_get_sset_count, 13096 .get_fw_version = hclge_get_fw_version, 13097 .get_mdix_mode = hclge_get_mdix_mode, 13098 .enable_vlan_filter = hclge_enable_vlan_filter, 13099 .set_vlan_filter = hclge_set_vlan_filter, 13100 .set_vf_vlan_filter = hclge_set_vf_vlan_filter, 13101 .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag, 13102 .reset_event = hclge_reset_event, 13103 .get_reset_level = hclge_get_reset_level, 13104 .set_default_reset_request = hclge_set_def_reset_request, 13105 .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info, 13106 .set_channels = hclge_set_channels, 13107 .get_channels = hclge_get_channels, 13108 .get_regs_len = hclge_get_regs_len, 13109 .get_regs = hclge_get_regs, 13110 .set_led_id = hclge_set_led_id, 13111 .get_link_mode = hclge_get_link_mode, 13112 .add_fd_entry = hclge_add_fd_entry, 13113 .del_fd_entry = hclge_del_fd_entry, 13114 .get_fd_rule_cnt = hclge_get_fd_rule_cnt, 13115 .get_fd_rule_info = hclge_get_fd_rule_info, 13116 .get_fd_all_rules = hclge_get_all_rules, 13117 .enable_fd = hclge_enable_fd, 13118 .add_arfs_entry = hclge_add_fd_entry_by_arfs, 13119 .dbg_read_cmd = hclge_dbg_read_cmd, 13120 .handle_hw_ras_error = hclge_handle_hw_ras_error, 13121 .get_hw_reset_stat = hclge_get_hw_reset_stat, 13122 .ae_dev_resetting = hclge_ae_dev_resetting, 13123 .ae_dev_reset_cnt = hclge_ae_dev_reset_cnt, 13124 .set_gro_en = hclge_gro_en, 13125 .get_global_queue_id = hclge_covert_handle_qid_global, 13126 .set_timer_task = hclge_set_timer_task, 13127 .mac_connect_phy = hclge_mac_connect_phy, 13128 .mac_disconnect_phy = hclge_mac_disconnect_phy, 13129 .get_vf_config = hclge_get_vf_config, 13130 .set_vf_link_state = hclge_set_vf_link_state, 13131 .set_vf_spoofchk = hclge_set_vf_spoofchk, 13132 .set_vf_trust = hclge_set_vf_trust, 13133 .set_vf_rate = hclge_set_vf_rate, 13134 .set_vf_mac = hclge_set_vf_mac, 13135 .get_module_eeprom = hclge_get_module_eeprom, 13136 .get_cmdq_stat = hclge_get_cmdq_stat, 13137 .add_cls_flower = hclge_add_cls_flower, 13138 .del_cls_flower = hclge_del_cls_flower, 13139 .cls_flower_active = hclge_is_cls_flower_active, 13140 .get_phy_link_ksettings = hclge_get_phy_link_ksettings, 13141 .set_phy_link_ksettings = hclge_set_phy_link_ksettings, 13142 .set_tx_hwts_info = hclge_ptp_set_tx_info, 13143 .get_rx_hwts = hclge_ptp_get_rx_hwts, 13144 .get_ts_info = hclge_ptp_get_ts_info, 13145 .get_link_diagnosis_info = hclge_get_link_diagnosis_info, 13146 .clean_vf_config = hclge_clean_vport_config, 13147 .get_dscp_prio = hclge_get_dscp_prio, 13148 }; 13149 13150 static struct hnae3_ae_algo ae_algo = { 13151 .ops = &hclge_ops, 13152 .pdev_id_table = ae_algo_pci_tbl, 13153 }; 13154 13155 static int __init hclge_init(void) 13156 { 13157 pr_info("%s is initializing\n", HCLGE_NAME); 13158 13159 hclge_wq = alloc_workqueue("%s", WQ_UNBOUND, 0, HCLGE_NAME); 13160 if (!hclge_wq) { 13161 pr_err("%s: failed to create workqueue\n", HCLGE_NAME); 13162 return -ENOMEM; 13163 } 13164 13165 hnae3_register_ae_algo(&ae_algo); 13166 13167 return 0; 13168 } 13169 13170 static void __exit hclge_exit(void) 13171 { 13172 hnae3_unregister_ae_algo_prepare(&ae_algo); 13173 hnae3_unregister_ae_algo(&ae_algo); 13174 destroy_workqueue(hclge_wq); 13175 } 13176 module_init(hclge_init); 13177 module_exit(hclge_exit); 13178 13179 MODULE_LICENSE("GPL"); 13180 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 13181 MODULE_DESCRIPTION("HCLGE Driver"); 13182 MODULE_VERSION(HCLGE_MOD_VERSION); 13183