1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2022 Intel Corporation. All rights reserved. */ 3 #undef TRACE_SYSTEM 4 #define TRACE_SYSTEM cxl 5 6 #if !defined(_CXL_EVENTS_H) || defined(TRACE_HEADER_MULTI_READ) 7 #define _CXL_EVENTS_H 8 9 #include <linux/tracepoint.h> 10 #include <asm-generic/unaligned.h> 11 12 #include <cxl.h> 13 #include <cxlmem.h> 14 15 #define CXL_RAS_UC_CACHE_DATA_PARITY BIT(0) 16 #define CXL_RAS_UC_CACHE_ADDR_PARITY BIT(1) 17 #define CXL_RAS_UC_CACHE_BE_PARITY BIT(2) 18 #define CXL_RAS_UC_CACHE_DATA_ECC BIT(3) 19 #define CXL_RAS_UC_MEM_DATA_PARITY BIT(4) 20 #define CXL_RAS_UC_MEM_ADDR_PARITY BIT(5) 21 #define CXL_RAS_UC_MEM_BE_PARITY BIT(6) 22 #define CXL_RAS_UC_MEM_DATA_ECC BIT(7) 23 #define CXL_RAS_UC_REINIT_THRESH BIT(8) 24 #define CXL_RAS_UC_RSVD_ENCODE BIT(9) 25 #define CXL_RAS_UC_POISON BIT(10) 26 #define CXL_RAS_UC_RECV_OVERFLOW BIT(11) 27 #define CXL_RAS_UC_INTERNAL_ERR BIT(14) 28 #define CXL_RAS_UC_IDE_TX_ERR BIT(15) 29 #define CXL_RAS_UC_IDE_RX_ERR BIT(16) 30 31 #define show_uc_errs(status) __print_flags(status, " | ", \ 32 { CXL_RAS_UC_CACHE_DATA_PARITY, "Cache Data Parity Error" }, \ 33 { CXL_RAS_UC_CACHE_ADDR_PARITY, "Cache Address Parity Error" }, \ 34 { CXL_RAS_UC_CACHE_BE_PARITY, "Cache Byte Enable Parity Error" }, \ 35 { CXL_RAS_UC_CACHE_DATA_ECC, "Cache Data ECC Error" }, \ 36 { CXL_RAS_UC_MEM_DATA_PARITY, "Memory Data Parity Error" }, \ 37 { CXL_RAS_UC_MEM_ADDR_PARITY, "Memory Address Parity Error" }, \ 38 { CXL_RAS_UC_MEM_BE_PARITY, "Memory Byte Enable Parity Error" }, \ 39 { CXL_RAS_UC_MEM_DATA_ECC, "Memory Data ECC Error" }, \ 40 { CXL_RAS_UC_REINIT_THRESH, "REINIT Threshold Hit" }, \ 41 { CXL_RAS_UC_RSVD_ENCODE, "Received Unrecognized Encoding" }, \ 42 { CXL_RAS_UC_POISON, "Received Poison From Peer" }, \ 43 { CXL_RAS_UC_RECV_OVERFLOW, "Receiver Overflow" }, \ 44 { CXL_RAS_UC_INTERNAL_ERR, "Component Specific Error" }, \ 45 { CXL_RAS_UC_IDE_TX_ERR, "IDE Tx Error" }, \ 46 { CXL_RAS_UC_IDE_RX_ERR, "IDE Rx Error" } \ 47 ) 48 49 TRACE_EVENT(cxl_aer_uncorrectable_error, 50 TP_PROTO(const struct cxl_memdev *cxlmd, u32 status, u32 fe, u32 *hl), 51 TP_ARGS(cxlmd, status, fe, hl), 52 TP_STRUCT__entry( 53 __string(memdev, dev_name(&cxlmd->dev)) 54 __string(host, dev_name(cxlmd->dev.parent)) 55 __field(u64, serial) 56 __field(u32, status) 57 __field(u32, first_error) 58 __array(u32, header_log, CXL_HEADERLOG_SIZE_U32) 59 ), 60 TP_fast_assign( 61 __assign_str(memdev, dev_name(&cxlmd->dev)); 62 __assign_str(host, dev_name(cxlmd->dev.parent)); 63 __entry->serial = cxlmd->cxlds->serial; 64 __entry->status = status; 65 __entry->first_error = fe; 66 /* 67 * Embed the 512B headerlog data for user app retrieval and 68 * parsing, but no need to print this in the trace buffer. 69 */ 70 memcpy(__entry->header_log, hl, CXL_HEADERLOG_SIZE); 71 ), 72 TP_printk("memdev=%s host=%s serial=%lld: status: '%s' first_error: '%s'", 73 __get_str(memdev), __get_str(host), __entry->serial, 74 show_uc_errs(__entry->status), 75 show_uc_errs(__entry->first_error) 76 ) 77 ); 78 79 #define CXL_RAS_CE_CACHE_DATA_ECC BIT(0) 80 #define CXL_RAS_CE_MEM_DATA_ECC BIT(1) 81 #define CXL_RAS_CE_CRC_THRESH BIT(2) 82 #define CLX_RAS_CE_RETRY_THRESH BIT(3) 83 #define CXL_RAS_CE_CACHE_POISON BIT(4) 84 #define CXL_RAS_CE_MEM_POISON BIT(5) 85 #define CXL_RAS_CE_PHYS_LAYER_ERR BIT(6) 86 87 #define show_ce_errs(status) __print_flags(status, " | ", \ 88 { CXL_RAS_CE_CACHE_DATA_ECC, "Cache Data ECC Error" }, \ 89 { CXL_RAS_CE_MEM_DATA_ECC, "Memory Data ECC Error" }, \ 90 { CXL_RAS_CE_CRC_THRESH, "CRC Threshold Hit" }, \ 91 { CLX_RAS_CE_RETRY_THRESH, "Retry Threshold" }, \ 92 { CXL_RAS_CE_CACHE_POISON, "Received Cache Poison From Peer" }, \ 93 { CXL_RAS_CE_MEM_POISON, "Received Memory Poison From Peer" }, \ 94 { CXL_RAS_CE_PHYS_LAYER_ERR, "Received Error From Physical Layer" } \ 95 ) 96 97 TRACE_EVENT(cxl_aer_correctable_error, 98 TP_PROTO(const struct cxl_memdev *cxlmd, u32 status), 99 TP_ARGS(cxlmd, status), 100 TP_STRUCT__entry( 101 __string(memdev, dev_name(&cxlmd->dev)) 102 __string(host, dev_name(cxlmd->dev.parent)) 103 __field(u64, serial) 104 __field(u32, status) 105 ), 106 TP_fast_assign( 107 __assign_str(memdev, dev_name(&cxlmd->dev)); 108 __assign_str(host, dev_name(cxlmd->dev.parent)); 109 __entry->serial = cxlmd->cxlds->serial; 110 __entry->status = status; 111 ), 112 TP_printk("memdev=%s host=%s serial=%lld: status: '%s'", 113 __get_str(memdev), __get_str(host), __entry->serial, 114 show_ce_errs(__entry->status) 115 ) 116 ); 117 118 #define cxl_event_log_type_str(type) \ 119 __print_symbolic(type, \ 120 { CXL_EVENT_TYPE_INFO, "Informational" }, \ 121 { CXL_EVENT_TYPE_WARN, "Warning" }, \ 122 { CXL_EVENT_TYPE_FAIL, "Failure" }, \ 123 { CXL_EVENT_TYPE_FATAL, "Fatal" }) 124 125 TRACE_EVENT(cxl_overflow, 126 127 TP_PROTO(const struct cxl_memdev *cxlmd, enum cxl_event_log_type log, 128 struct cxl_get_event_payload *payload), 129 130 TP_ARGS(cxlmd, log, payload), 131 132 TP_STRUCT__entry( 133 __string(memdev, dev_name(&cxlmd->dev)) 134 __string(host, dev_name(cxlmd->dev.parent)) 135 __field(int, log) 136 __field(u64, serial) 137 __field(u64, first_ts) 138 __field(u64, last_ts) 139 __field(u16, count) 140 ), 141 142 TP_fast_assign( 143 __assign_str(memdev, dev_name(&cxlmd->dev)); 144 __assign_str(host, dev_name(cxlmd->dev.parent)); 145 __entry->serial = cxlmd->cxlds->serial; 146 __entry->log = log; 147 __entry->count = le16_to_cpu(payload->overflow_err_count); 148 __entry->first_ts = le64_to_cpu(payload->first_overflow_timestamp); 149 __entry->last_ts = le64_to_cpu(payload->last_overflow_timestamp); 150 ), 151 152 TP_printk("memdev=%s host=%s serial=%lld: log=%s : %u records from %llu to %llu", 153 __get_str(memdev), __get_str(host), __entry->serial, 154 cxl_event_log_type_str(__entry->log), __entry->count, 155 __entry->first_ts, __entry->last_ts) 156 157 ); 158 159 /* 160 * Common Event Record Format 161 * CXL 3.0 section 8.2.9.2.1; Table 8-42 162 */ 163 #define CXL_EVENT_RECORD_FLAG_PERMANENT BIT(2) 164 #define CXL_EVENT_RECORD_FLAG_MAINT_NEEDED BIT(3) 165 #define CXL_EVENT_RECORD_FLAG_PERF_DEGRADED BIT(4) 166 #define CXL_EVENT_RECORD_FLAG_HW_REPLACE BIT(5) 167 #define show_hdr_flags(flags) __print_flags(flags, " | ", \ 168 { CXL_EVENT_RECORD_FLAG_PERMANENT, "PERMANENT_CONDITION" }, \ 169 { CXL_EVENT_RECORD_FLAG_MAINT_NEEDED, "MAINTENANCE_NEEDED" }, \ 170 { CXL_EVENT_RECORD_FLAG_PERF_DEGRADED, "PERFORMANCE_DEGRADED" }, \ 171 { CXL_EVENT_RECORD_FLAG_HW_REPLACE, "HARDWARE_REPLACEMENT_NEEDED" } \ 172 ) 173 174 /* 175 * Define macros for the common header of each CXL event. 176 * 177 * Tracepoints using these macros must do 3 things: 178 * 179 * 1) Add CXL_EVT_TP_entry to TP_STRUCT__entry 180 * 2) Use CXL_EVT_TP_fast_assign within TP_fast_assign; 181 * pass the dev, log, and CXL event header 182 * 3) Use CXL_EVT_TP_printk() instead of TP_printk() 183 * 184 * See the generic_event tracepoint as an example. 185 */ 186 #define CXL_EVT_TP_entry \ 187 __string(memdev, dev_name(&cxlmd->dev)) \ 188 __string(host, dev_name(cxlmd->dev.parent)) \ 189 __field(int, log) \ 190 __field_struct(uuid_t, hdr_uuid) \ 191 __field(u64, serial) \ 192 __field(u32, hdr_flags) \ 193 __field(u16, hdr_handle) \ 194 __field(u16, hdr_related_handle) \ 195 __field(u64, hdr_timestamp) \ 196 __field(u8, hdr_length) \ 197 __field(u8, hdr_maint_op_class) 198 199 #define CXL_EVT_TP_fast_assign(cxlmd, l, hdr) \ 200 __assign_str(memdev, dev_name(&(cxlmd)->dev)); \ 201 __assign_str(host, dev_name((cxlmd)->dev.parent)); \ 202 __entry->log = (l); \ 203 __entry->serial = (cxlmd)->cxlds->serial; \ 204 memcpy(&__entry->hdr_uuid, &(hdr).id, sizeof(uuid_t)); \ 205 __entry->hdr_length = (hdr).length; \ 206 __entry->hdr_flags = get_unaligned_le24((hdr).flags); \ 207 __entry->hdr_handle = le16_to_cpu((hdr).handle); \ 208 __entry->hdr_related_handle = le16_to_cpu((hdr).related_handle); \ 209 __entry->hdr_timestamp = le64_to_cpu((hdr).timestamp); \ 210 __entry->hdr_maint_op_class = (hdr).maint_op_class 211 212 #define CXL_EVT_TP_printk(fmt, ...) \ 213 TP_printk("memdev=%s host=%s serial=%lld log=%s : time=%llu uuid=%pUb " \ 214 "len=%d flags='%s' handle=%x related_handle=%x " \ 215 "maint_op_class=%u : " fmt, \ 216 __get_str(memdev), __get_str(host), __entry->serial, \ 217 cxl_event_log_type_str(__entry->log), \ 218 __entry->hdr_timestamp, &__entry->hdr_uuid, __entry->hdr_length,\ 219 show_hdr_flags(__entry->hdr_flags), __entry->hdr_handle, \ 220 __entry->hdr_related_handle, __entry->hdr_maint_op_class, \ 221 ##__VA_ARGS__) 222 223 TRACE_EVENT(cxl_generic_event, 224 225 TP_PROTO(const struct cxl_memdev *cxlmd, enum cxl_event_log_type log, 226 struct cxl_event_record_raw *rec), 227 228 TP_ARGS(cxlmd, log, rec), 229 230 TP_STRUCT__entry( 231 CXL_EVT_TP_entry 232 __array(u8, data, CXL_EVENT_RECORD_DATA_LENGTH) 233 ), 234 235 TP_fast_assign( 236 CXL_EVT_TP_fast_assign(cxlmd, log, rec->hdr); 237 memcpy(__entry->data, &rec->data, CXL_EVENT_RECORD_DATA_LENGTH); 238 ), 239 240 CXL_EVT_TP_printk("%s", 241 __print_hex(__entry->data, CXL_EVENT_RECORD_DATA_LENGTH)) 242 ); 243 244 /* 245 * Physical Address field masks 246 * 247 * General Media Event Record 248 * CXL rev 3.0 Section 8.2.9.2.1.1; Table 8-43 249 * 250 * DRAM Event Record 251 * CXL rev 3.0 section 8.2.9.2.1.2; Table 8-44 252 */ 253 #define CXL_DPA_FLAGS_MASK 0x3F 254 #define CXL_DPA_MASK (~CXL_DPA_FLAGS_MASK) 255 256 #define CXL_DPA_VOLATILE BIT(0) 257 #define CXL_DPA_NOT_REPAIRABLE BIT(1) 258 #define show_dpa_flags(flags) __print_flags(flags, "|", \ 259 { CXL_DPA_VOLATILE, "VOLATILE" }, \ 260 { CXL_DPA_NOT_REPAIRABLE, "NOT_REPAIRABLE" } \ 261 ) 262 263 /* 264 * General Media Event Record - GMER 265 * CXL rev 3.0 Section 8.2.9.2.1.1; Table 8-43 266 */ 267 #define CXL_GMER_EVT_DESC_UNCORECTABLE_EVENT BIT(0) 268 #define CXL_GMER_EVT_DESC_THRESHOLD_EVENT BIT(1) 269 #define CXL_GMER_EVT_DESC_POISON_LIST_OVERFLOW BIT(2) 270 #define show_event_desc_flags(flags) __print_flags(flags, "|", \ 271 { CXL_GMER_EVT_DESC_UNCORECTABLE_EVENT, "UNCORRECTABLE_EVENT" }, \ 272 { CXL_GMER_EVT_DESC_THRESHOLD_EVENT, "THRESHOLD_EVENT" }, \ 273 { CXL_GMER_EVT_DESC_POISON_LIST_OVERFLOW, "POISON_LIST_OVERFLOW" } \ 274 ) 275 276 #define CXL_GMER_MEM_EVT_TYPE_ECC_ERROR 0x00 277 #define CXL_GMER_MEM_EVT_TYPE_INV_ADDR 0x01 278 #define CXL_GMER_MEM_EVT_TYPE_DATA_PATH_ERROR 0x02 279 #define show_mem_event_type(type) __print_symbolic(type, \ 280 { CXL_GMER_MEM_EVT_TYPE_ECC_ERROR, "ECC Error" }, \ 281 { CXL_GMER_MEM_EVT_TYPE_INV_ADDR, "Invalid Address" }, \ 282 { CXL_GMER_MEM_EVT_TYPE_DATA_PATH_ERROR, "Data Path Error" } \ 283 ) 284 285 #define CXL_GMER_TRANS_UNKNOWN 0x00 286 #define CXL_GMER_TRANS_HOST_READ 0x01 287 #define CXL_GMER_TRANS_HOST_WRITE 0x02 288 #define CXL_GMER_TRANS_HOST_SCAN_MEDIA 0x03 289 #define CXL_GMER_TRANS_HOST_INJECT_POISON 0x04 290 #define CXL_GMER_TRANS_INTERNAL_MEDIA_SCRUB 0x05 291 #define CXL_GMER_TRANS_INTERNAL_MEDIA_MANAGEMENT 0x06 292 #define show_trans_type(type) __print_symbolic(type, \ 293 { CXL_GMER_TRANS_UNKNOWN, "Unknown" }, \ 294 { CXL_GMER_TRANS_HOST_READ, "Host Read" }, \ 295 { CXL_GMER_TRANS_HOST_WRITE, "Host Write" }, \ 296 { CXL_GMER_TRANS_HOST_SCAN_MEDIA, "Host Scan Media" }, \ 297 { CXL_GMER_TRANS_HOST_INJECT_POISON, "Host Inject Poison" }, \ 298 { CXL_GMER_TRANS_INTERNAL_MEDIA_SCRUB, "Internal Media Scrub" }, \ 299 { CXL_GMER_TRANS_INTERNAL_MEDIA_MANAGEMENT, "Internal Media Management" } \ 300 ) 301 302 #define CXL_GMER_VALID_CHANNEL BIT(0) 303 #define CXL_GMER_VALID_RANK BIT(1) 304 #define CXL_GMER_VALID_DEVICE BIT(2) 305 #define CXL_GMER_VALID_COMPONENT BIT(3) 306 #define show_valid_flags(flags) __print_flags(flags, "|", \ 307 { CXL_GMER_VALID_CHANNEL, "CHANNEL" }, \ 308 { CXL_GMER_VALID_RANK, "RANK" }, \ 309 { CXL_GMER_VALID_DEVICE, "DEVICE" }, \ 310 { CXL_GMER_VALID_COMPONENT, "COMPONENT" } \ 311 ) 312 313 TRACE_EVENT(cxl_general_media, 314 315 TP_PROTO(const struct cxl_memdev *cxlmd, enum cxl_event_log_type log, 316 struct cxl_event_gen_media *rec), 317 318 TP_ARGS(cxlmd, log, rec), 319 320 TP_STRUCT__entry( 321 CXL_EVT_TP_entry 322 /* General Media */ 323 __field(u64, dpa) 324 __field(u8, descriptor) 325 __field(u8, type) 326 __field(u8, transaction_type) 327 __field(u8, channel) 328 __field(u32, device) 329 __array(u8, comp_id, CXL_EVENT_GEN_MED_COMP_ID_SIZE) 330 __field(u16, validity_flags) 331 /* Following are out of order to pack trace record */ 332 __field(u8, rank) 333 __field(u8, dpa_flags) 334 ), 335 336 TP_fast_assign( 337 CXL_EVT_TP_fast_assign(cxlmd, log, rec->hdr); 338 339 /* General Media */ 340 __entry->dpa = le64_to_cpu(rec->phys_addr); 341 __entry->dpa_flags = __entry->dpa & CXL_DPA_FLAGS_MASK; 342 /* Mask after flags have been parsed */ 343 __entry->dpa &= CXL_DPA_MASK; 344 __entry->descriptor = rec->descriptor; 345 __entry->type = rec->type; 346 __entry->transaction_type = rec->transaction_type; 347 __entry->channel = rec->channel; 348 __entry->rank = rec->rank; 349 __entry->device = get_unaligned_le24(rec->device); 350 memcpy(__entry->comp_id, &rec->component_id, 351 CXL_EVENT_GEN_MED_COMP_ID_SIZE); 352 __entry->validity_flags = get_unaligned_le16(&rec->validity_flags); 353 ), 354 355 CXL_EVT_TP_printk("dpa=%llx dpa_flags='%s' " \ 356 "descriptor='%s' type='%s' transaction_type='%s' channel=%u rank=%u " \ 357 "device=%x comp_id=%s validity_flags='%s'", 358 __entry->dpa, show_dpa_flags(__entry->dpa_flags), 359 show_event_desc_flags(__entry->descriptor), 360 show_mem_event_type(__entry->type), 361 show_trans_type(__entry->transaction_type), 362 __entry->channel, __entry->rank, __entry->device, 363 __print_hex(__entry->comp_id, CXL_EVENT_GEN_MED_COMP_ID_SIZE), 364 show_valid_flags(__entry->validity_flags) 365 ) 366 ); 367 368 /* 369 * DRAM Event Record - DER 370 * 371 * CXL rev 3.0 section 8.2.9.2.1.2; Table 8-44 372 */ 373 /* 374 * DRAM Event Record defines many fields the same as the General Media Event 375 * Record. Reuse those definitions as appropriate. 376 */ 377 #define CXL_DER_VALID_CHANNEL BIT(0) 378 #define CXL_DER_VALID_RANK BIT(1) 379 #define CXL_DER_VALID_NIBBLE BIT(2) 380 #define CXL_DER_VALID_BANK_GROUP BIT(3) 381 #define CXL_DER_VALID_BANK BIT(4) 382 #define CXL_DER_VALID_ROW BIT(5) 383 #define CXL_DER_VALID_COLUMN BIT(6) 384 #define CXL_DER_VALID_CORRECTION_MASK BIT(7) 385 #define show_dram_valid_flags(flags) __print_flags(flags, "|", \ 386 { CXL_DER_VALID_CHANNEL, "CHANNEL" }, \ 387 { CXL_DER_VALID_RANK, "RANK" }, \ 388 { CXL_DER_VALID_NIBBLE, "NIBBLE" }, \ 389 { CXL_DER_VALID_BANK_GROUP, "BANK GROUP" }, \ 390 { CXL_DER_VALID_BANK, "BANK" }, \ 391 { CXL_DER_VALID_ROW, "ROW" }, \ 392 { CXL_DER_VALID_COLUMN, "COLUMN" }, \ 393 { CXL_DER_VALID_CORRECTION_MASK, "CORRECTION MASK" } \ 394 ) 395 396 TRACE_EVENT(cxl_dram, 397 398 TP_PROTO(const struct cxl_memdev *cxlmd, enum cxl_event_log_type log, 399 struct cxl_event_dram *rec), 400 401 TP_ARGS(cxlmd, log, rec), 402 403 TP_STRUCT__entry( 404 CXL_EVT_TP_entry 405 /* DRAM */ 406 __field(u64, dpa) 407 __field(u8, descriptor) 408 __field(u8, type) 409 __field(u8, transaction_type) 410 __field(u8, channel) 411 __field(u16, validity_flags) 412 __field(u16, column) /* Out of order to pack trace record */ 413 __field(u32, nibble_mask) 414 __field(u32, row) 415 __array(u8, cor_mask, CXL_EVENT_DER_CORRECTION_MASK_SIZE) 416 __field(u8, rank) /* Out of order to pack trace record */ 417 __field(u8, bank_group) /* Out of order to pack trace record */ 418 __field(u8, bank) /* Out of order to pack trace record */ 419 __field(u8, dpa_flags) /* Out of order to pack trace record */ 420 ), 421 422 TP_fast_assign( 423 CXL_EVT_TP_fast_assign(cxlmd, log, rec->hdr); 424 425 /* DRAM */ 426 __entry->dpa = le64_to_cpu(rec->phys_addr); 427 __entry->dpa_flags = __entry->dpa & CXL_DPA_FLAGS_MASK; 428 __entry->dpa &= CXL_DPA_MASK; 429 __entry->descriptor = rec->descriptor; 430 __entry->type = rec->type; 431 __entry->transaction_type = rec->transaction_type; 432 __entry->validity_flags = get_unaligned_le16(rec->validity_flags); 433 __entry->channel = rec->channel; 434 __entry->rank = rec->rank; 435 __entry->nibble_mask = get_unaligned_le24(rec->nibble_mask); 436 __entry->bank_group = rec->bank_group; 437 __entry->bank = rec->bank; 438 __entry->row = get_unaligned_le24(rec->row); 439 __entry->column = get_unaligned_le16(rec->column); 440 memcpy(__entry->cor_mask, &rec->correction_mask, 441 CXL_EVENT_DER_CORRECTION_MASK_SIZE); 442 ), 443 444 CXL_EVT_TP_printk("dpa=%llx dpa_flags='%s' descriptor='%s' type='%s' " \ 445 "transaction_type='%s' channel=%u rank=%u nibble_mask=%x " \ 446 "bank_group=%u bank=%u row=%u column=%u cor_mask=%s " \ 447 "validity_flags='%s'", 448 __entry->dpa, show_dpa_flags(__entry->dpa_flags), 449 show_event_desc_flags(__entry->descriptor), 450 show_mem_event_type(__entry->type), 451 show_trans_type(__entry->transaction_type), 452 __entry->channel, __entry->rank, __entry->nibble_mask, 453 __entry->bank_group, __entry->bank, 454 __entry->row, __entry->column, 455 __print_hex(__entry->cor_mask, CXL_EVENT_DER_CORRECTION_MASK_SIZE), 456 show_dram_valid_flags(__entry->validity_flags) 457 ) 458 ); 459 460 /* 461 * Memory Module Event Record - MMER 462 * 463 * CXL res 3.0 section 8.2.9.2.1.3; Table 8-45 464 */ 465 #define CXL_MMER_HEALTH_STATUS_CHANGE 0x00 466 #define CXL_MMER_MEDIA_STATUS_CHANGE 0x01 467 #define CXL_MMER_LIFE_USED_CHANGE 0x02 468 #define CXL_MMER_TEMP_CHANGE 0x03 469 #define CXL_MMER_DATA_PATH_ERROR 0x04 470 #define CXL_MMER_LSA_ERROR 0x05 471 #define show_dev_evt_type(type) __print_symbolic(type, \ 472 { CXL_MMER_HEALTH_STATUS_CHANGE, "Health Status Change" }, \ 473 { CXL_MMER_MEDIA_STATUS_CHANGE, "Media Status Change" }, \ 474 { CXL_MMER_LIFE_USED_CHANGE, "Life Used Change" }, \ 475 { CXL_MMER_TEMP_CHANGE, "Temperature Change" }, \ 476 { CXL_MMER_DATA_PATH_ERROR, "Data Path Error" }, \ 477 { CXL_MMER_LSA_ERROR, "LSA Error" } \ 478 ) 479 480 /* 481 * Device Health Information - DHI 482 * 483 * CXL res 3.0 section 8.2.9.8.3.1; Table 8-100 484 */ 485 #define CXL_DHI_HS_MAINTENANCE_NEEDED BIT(0) 486 #define CXL_DHI_HS_PERFORMANCE_DEGRADED BIT(1) 487 #define CXL_DHI_HS_HW_REPLACEMENT_NEEDED BIT(2) 488 #define show_health_status_flags(flags) __print_flags(flags, "|", \ 489 { CXL_DHI_HS_MAINTENANCE_NEEDED, "MAINTENANCE_NEEDED" }, \ 490 { CXL_DHI_HS_PERFORMANCE_DEGRADED, "PERFORMANCE_DEGRADED" }, \ 491 { CXL_DHI_HS_HW_REPLACEMENT_NEEDED, "REPLACEMENT_NEEDED" } \ 492 ) 493 494 #define CXL_DHI_MS_NORMAL 0x00 495 #define CXL_DHI_MS_NOT_READY 0x01 496 #define CXL_DHI_MS_WRITE_PERSISTENCY_LOST 0x02 497 #define CXL_DHI_MS_ALL_DATA_LOST 0x03 498 #define CXL_DHI_MS_WRITE_PERSISTENCY_LOSS_EVENT_POWER_LOSS 0x04 499 #define CXL_DHI_MS_WRITE_PERSISTENCY_LOSS_EVENT_SHUTDOWN 0x05 500 #define CXL_DHI_MS_WRITE_PERSISTENCY_LOSS_IMMINENT 0x06 501 #define CXL_DHI_MS_WRITE_ALL_DATA_LOSS_EVENT_POWER_LOSS 0x07 502 #define CXL_DHI_MS_WRITE_ALL_DATA_LOSS_EVENT_SHUTDOWN 0x08 503 #define CXL_DHI_MS_WRITE_ALL_DATA_LOSS_IMMINENT 0x09 504 #define show_media_status(ms) __print_symbolic(ms, \ 505 { CXL_DHI_MS_NORMAL, \ 506 "Normal" }, \ 507 { CXL_DHI_MS_NOT_READY, \ 508 "Not Ready" }, \ 509 { CXL_DHI_MS_WRITE_PERSISTENCY_LOST, \ 510 "Write Persistency Lost" }, \ 511 { CXL_DHI_MS_ALL_DATA_LOST, \ 512 "All Data Lost" }, \ 513 { CXL_DHI_MS_WRITE_PERSISTENCY_LOSS_EVENT_POWER_LOSS, \ 514 "Write Persistency Loss in the Event of Power Loss" }, \ 515 { CXL_DHI_MS_WRITE_PERSISTENCY_LOSS_EVENT_SHUTDOWN, \ 516 "Write Persistency Loss in Event of Shutdown" }, \ 517 { CXL_DHI_MS_WRITE_PERSISTENCY_LOSS_IMMINENT, \ 518 "Write Persistency Loss Imminent" }, \ 519 { CXL_DHI_MS_WRITE_ALL_DATA_LOSS_EVENT_POWER_LOSS, \ 520 "All Data Loss in Event of Power Loss" }, \ 521 { CXL_DHI_MS_WRITE_ALL_DATA_LOSS_EVENT_SHUTDOWN, \ 522 "All Data loss in the Event of Shutdown" }, \ 523 { CXL_DHI_MS_WRITE_ALL_DATA_LOSS_IMMINENT, \ 524 "All Data Loss Imminent" } \ 525 ) 526 527 #define CXL_DHI_AS_NORMAL 0x0 528 #define CXL_DHI_AS_WARNING 0x1 529 #define CXL_DHI_AS_CRITICAL 0x2 530 #define show_two_bit_status(as) __print_symbolic(as, \ 531 { CXL_DHI_AS_NORMAL, "Normal" }, \ 532 { CXL_DHI_AS_WARNING, "Warning" }, \ 533 { CXL_DHI_AS_CRITICAL, "Critical" } \ 534 ) 535 #define show_one_bit_status(as) __print_symbolic(as, \ 536 { CXL_DHI_AS_NORMAL, "Normal" }, \ 537 { CXL_DHI_AS_WARNING, "Warning" } \ 538 ) 539 540 #define CXL_DHI_AS_LIFE_USED(as) (as & 0x3) 541 #define CXL_DHI_AS_DEV_TEMP(as) ((as & 0xC) >> 2) 542 #define CXL_DHI_AS_COR_VOL_ERR_CNT(as) ((as & 0x10) >> 4) 543 #define CXL_DHI_AS_COR_PER_ERR_CNT(as) ((as & 0x20) >> 5) 544 545 TRACE_EVENT(cxl_memory_module, 546 547 TP_PROTO(const struct cxl_memdev *cxlmd, enum cxl_event_log_type log, 548 struct cxl_event_mem_module *rec), 549 550 TP_ARGS(cxlmd, log, rec), 551 552 TP_STRUCT__entry( 553 CXL_EVT_TP_entry 554 555 /* Memory Module Event */ 556 __field(u8, event_type) 557 558 /* Device Health Info */ 559 __field(u8, health_status) 560 __field(u8, media_status) 561 __field(u8, life_used) 562 __field(u32, dirty_shutdown_cnt) 563 __field(u32, cor_vol_err_cnt) 564 __field(u32, cor_per_err_cnt) 565 __field(s16, device_temp) 566 __field(u8, add_status) 567 ), 568 569 TP_fast_assign( 570 CXL_EVT_TP_fast_assign(cxlmd, log, rec->hdr); 571 572 /* Memory Module Event */ 573 __entry->event_type = rec->event_type; 574 575 /* Device Health Info */ 576 __entry->health_status = rec->info.health_status; 577 __entry->media_status = rec->info.media_status; 578 __entry->life_used = rec->info.life_used; 579 __entry->dirty_shutdown_cnt = get_unaligned_le32(rec->info.dirty_shutdown_cnt); 580 __entry->cor_vol_err_cnt = get_unaligned_le32(rec->info.cor_vol_err_cnt); 581 __entry->cor_per_err_cnt = get_unaligned_le32(rec->info.cor_per_err_cnt); 582 __entry->device_temp = get_unaligned_le16(rec->info.device_temp); 583 __entry->add_status = rec->info.add_status; 584 ), 585 586 CXL_EVT_TP_printk("event_type='%s' health_status='%s' media_status='%s' " \ 587 "as_life_used=%s as_dev_temp=%s as_cor_vol_err_cnt=%s " \ 588 "as_cor_per_err_cnt=%s life_used=%u device_temp=%d " \ 589 "dirty_shutdown_cnt=%u cor_vol_err_cnt=%u cor_per_err_cnt=%u", 590 show_dev_evt_type(__entry->event_type), 591 show_health_status_flags(__entry->health_status), 592 show_media_status(__entry->media_status), 593 show_two_bit_status(CXL_DHI_AS_LIFE_USED(__entry->add_status)), 594 show_two_bit_status(CXL_DHI_AS_DEV_TEMP(__entry->add_status)), 595 show_one_bit_status(CXL_DHI_AS_COR_VOL_ERR_CNT(__entry->add_status)), 596 show_one_bit_status(CXL_DHI_AS_COR_PER_ERR_CNT(__entry->add_status)), 597 __entry->life_used, __entry->device_temp, 598 __entry->dirty_shutdown_cnt, __entry->cor_vol_err_cnt, 599 __entry->cor_per_err_cnt 600 ) 601 ); 602 603 #endif /* _CXL_EVENTS_H */ 604 605 #define TRACE_INCLUDE_FILE trace 606 #include <trace/define_trace.h> 607