1// SPDX-License-Identifier: GPL-2.0 2 3#include <dt-bindings/clock/tegra234-clock.h> 4#include <dt-bindings/gpio/tegra234-gpio.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/mailbox/tegra186-hsp.h> 7#include <dt-bindings/memory/tegra234-mc.h> 8#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 9#include <dt-bindings/power/tegra234-powergate.h> 10#include <dt-bindings/reset/tegra234-reset.h> 11 12/ { 13 compatible = "nvidia,tegra234"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 bus@0 { 19 compatible = "simple-bus"; 20 21 #address-cells = <2>; 22 #size-cells = <2>; 23 ranges = <0x0 0x0 0x0 0x0 0x0 0x40000000>; 24 25 misc@100000 { 26 compatible = "nvidia,tegra234-misc"; 27 reg = <0x0 0x00100000 0x0 0xf000>, 28 <0x0 0x0010f000 0x0 0x1000>; 29 status = "okay"; 30 }; 31 32 timer@2080000 { 33 compatible = "nvidia,tegra234-timer"; 34 reg = <0x0 0x02080000 0x0 0x00121000>; 35 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 36 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 37 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 41 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 42 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 43 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 44 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 45 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 46 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 47 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 48 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 49 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 50 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 51 status = "okay"; 52 }; 53 54 gpio: gpio@2200000 { 55 compatible = "nvidia,tegra234-gpio"; 56 reg-names = "security", "gpio"; 57 reg = <0x0 0x02200000 0x0 0x10000>, 58 <0x0 0x02210000 0x0 0x10000>; 59 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 61 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 62 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 63 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 65 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 69 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 70 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 71 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 72 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 73 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 74 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 75 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 77 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 79 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 87 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 88 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 89 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 90 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 91 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 92 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 94 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 107 #interrupt-cells = <2>; 108 interrupt-controller; 109 #gpio-cells = <2>; 110 gpio-controller; 111 }; 112 113 gpcdma: dma-controller@2600000 { 114 compatible = "nvidia,tegra234-gpcdma", 115 "nvidia,tegra186-gpcdma"; 116 reg = <0x0 0x2600000 0x0 0x210000>; 117 resets = <&bpmp TEGRA234_RESET_GPCDMA>; 118 reset-names = "gpcdma"; 119 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 120 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 121 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 122 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 123 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 124 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 125 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 126 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 127 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 128 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 129 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 130 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 131 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 132 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 133 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 134 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 135 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 136 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 137 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 139 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 140 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 141 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 142 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 143 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 144 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 145 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 146 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 147 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 151 #dma-cells = <1>; 152 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 153 dma-channel-mask = <0xfffffffe>; 154 dma-coherent; 155 }; 156 157 aconnect@2900000 { 158 compatible = "nvidia,tegra234-aconnect", 159 "nvidia,tegra210-aconnect"; 160 clocks = <&bpmp TEGRA234_CLK_APE>, 161 <&bpmp TEGRA234_CLK_APB2APE>; 162 clock-names = "ape", "apb2ape"; 163 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_AUD>; 164 status = "disabled"; 165 166 #address-cells = <2>; 167 #size-cells = <2>; 168 ranges = <0x0 0x02900000 0x0 0x02900000 0x0 0x200000>; 169 170 tegra_ahub: ahub@2900800 { 171 compatible = "nvidia,tegra234-ahub"; 172 reg = <0x0 0x02900800 0x0 0x800>; 173 clocks = <&bpmp TEGRA234_CLK_AHUB>; 174 clock-names = "ahub"; 175 assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>; 176 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 177 status = "disabled"; 178 179 #address-cells = <2>; 180 #size-cells = <2>; 181 ranges = <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>; 182 183 tegra_i2s1: i2s@2901000 { 184 compatible = "nvidia,tegra234-i2s", 185 "nvidia,tegra210-i2s"; 186 reg = <0x0 0x2901000 0x0 0x100>; 187 clocks = <&bpmp TEGRA234_CLK_I2S1>, 188 <&bpmp TEGRA234_CLK_I2S1_SYNC_INPUT>; 189 clock-names = "i2s", "sync_input"; 190 assigned-clocks = <&bpmp TEGRA234_CLK_I2S1>; 191 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 192 assigned-clock-rates = <1536000>; 193 sound-name-prefix = "I2S1"; 194 status = "disabled"; 195 }; 196 197 tegra_i2s2: i2s@2901100 { 198 compatible = "nvidia,tegra234-i2s", 199 "nvidia,tegra210-i2s"; 200 reg = <0x0 0x2901100 0x0 0x100>; 201 clocks = <&bpmp TEGRA234_CLK_I2S2>, 202 <&bpmp TEGRA234_CLK_I2S2_SYNC_INPUT>; 203 clock-names = "i2s", "sync_input"; 204 assigned-clocks = <&bpmp TEGRA234_CLK_I2S2>; 205 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 206 assigned-clock-rates = <1536000>; 207 sound-name-prefix = "I2S2"; 208 status = "disabled"; 209 }; 210 211 tegra_i2s3: i2s@2901200 { 212 compatible = "nvidia,tegra234-i2s", 213 "nvidia,tegra210-i2s"; 214 reg = <0x0 0x2901200 0x0 0x100>; 215 clocks = <&bpmp TEGRA234_CLK_I2S3>, 216 <&bpmp TEGRA234_CLK_I2S3_SYNC_INPUT>; 217 clock-names = "i2s", "sync_input"; 218 assigned-clocks = <&bpmp TEGRA234_CLK_I2S3>; 219 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 220 assigned-clock-rates = <1536000>; 221 sound-name-prefix = "I2S3"; 222 status = "disabled"; 223 }; 224 225 tegra_i2s4: i2s@2901300 { 226 compatible = "nvidia,tegra234-i2s", 227 "nvidia,tegra210-i2s"; 228 reg = <0x0 0x2901300 0x0 0x100>; 229 clocks = <&bpmp TEGRA234_CLK_I2S4>, 230 <&bpmp TEGRA234_CLK_I2S4_SYNC_INPUT>; 231 clock-names = "i2s", "sync_input"; 232 assigned-clocks = <&bpmp TEGRA234_CLK_I2S4>; 233 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 234 assigned-clock-rates = <1536000>; 235 sound-name-prefix = "I2S4"; 236 status = "disabled"; 237 }; 238 239 tegra_i2s5: i2s@2901400 { 240 compatible = "nvidia,tegra234-i2s", 241 "nvidia,tegra210-i2s"; 242 reg = <0x0 0x2901400 0x0 0x100>; 243 clocks = <&bpmp TEGRA234_CLK_I2S5>, 244 <&bpmp TEGRA234_CLK_I2S5_SYNC_INPUT>; 245 clock-names = "i2s", "sync_input"; 246 assigned-clocks = <&bpmp TEGRA234_CLK_I2S5>; 247 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 248 assigned-clock-rates = <1536000>; 249 sound-name-prefix = "I2S5"; 250 status = "disabled"; 251 }; 252 253 tegra_i2s6: i2s@2901500 { 254 compatible = "nvidia,tegra234-i2s", 255 "nvidia,tegra210-i2s"; 256 reg = <0x0 0x2901500 0x0 0x100>; 257 clocks = <&bpmp TEGRA234_CLK_I2S6>, 258 <&bpmp TEGRA234_CLK_I2S6_SYNC_INPUT>; 259 clock-names = "i2s", "sync_input"; 260 assigned-clocks = <&bpmp TEGRA234_CLK_I2S6>; 261 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 262 assigned-clock-rates = <1536000>; 263 sound-name-prefix = "I2S6"; 264 status = "disabled"; 265 }; 266 267 tegra_sfc1: sfc@2902000 { 268 compatible = "nvidia,tegra234-sfc", 269 "nvidia,tegra210-sfc"; 270 reg = <0x0 0x2902000 0x0 0x200>; 271 sound-name-prefix = "SFC1"; 272 status = "disabled"; 273 }; 274 275 tegra_sfc2: sfc@2902200 { 276 compatible = "nvidia,tegra234-sfc", 277 "nvidia,tegra210-sfc"; 278 reg = <0x0 0x2902200 0x0 0x200>; 279 sound-name-prefix = "SFC2"; 280 status = "disabled"; 281 }; 282 283 tegra_sfc3: sfc@2902400 { 284 compatible = "nvidia,tegra234-sfc", 285 "nvidia,tegra210-sfc"; 286 reg = <0x0 0x2902400 0x0 0x200>; 287 sound-name-prefix = "SFC3"; 288 status = "disabled"; 289 }; 290 291 tegra_sfc4: sfc@2902600 { 292 compatible = "nvidia,tegra234-sfc", 293 "nvidia,tegra210-sfc"; 294 reg = <0x0 0x2902600 0x0 0x200>; 295 sound-name-prefix = "SFC4"; 296 status = "disabled"; 297 }; 298 299 tegra_amx1: amx@2903000 { 300 compatible = "nvidia,tegra234-amx", 301 "nvidia,tegra194-amx"; 302 reg = <0x0 0x2903000 0x0 0x100>; 303 sound-name-prefix = "AMX1"; 304 status = "disabled"; 305 }; 306 307 tegra_amx2: amx@2903100 { 308 compatible = "nvidia,tegra234-amx", 309 "nvidia,tegra194-amx"; 310 reg = <0x0 0x2903100 0x0 0x100>; 311 sound-name-prefix = "AMX2"; 312 status = "disabled"; 313 }; 314 315 tegra_amx3: amx@2903200 { 316 compatible = "nvidia,tegra234-amx", 317 "nvidia,tegra194-amx"; 318 reg = <0x0 0x2903200 0x0 0x100>; 319 sound-name-prefix = "AMX3"; 320 status = "disabled"; 321 }; 322 323 tegra_amx4: amx@2903300 { 324 compatible = "nvidia,tegra234-amx", 325 "nvidia,tegra194-amx"; 326 reg = <0x0 0x2903300 0x0 0x100>; 327 sound-name-prefix = "AMX4"; 328 status = "disabled"; 329 }; 330 331 tegra_adx1: adx@2903800 { 332 compatible = "nvidia,tegra234-adx", 333 "nvidia,tegra210-adx"; 334 reg = <0x0 0x2903800 0x0 0x100>; 335 sound-name-prefix = "ADX1"; 336 status = "disabled"; 337 }; 338 339 tegra_adx2: adx@2903900 { 340 compatible = "nvidia,tegra234-adx", 341 "nvidia,tegra210-adx"; 342 reg = <0x0 0x2903900 0x0 0x100>; 343 sound-name-prefix = "ADX2"; 344 status = "disabled"; 345 }; 346 347 tegra_adx3: adx@2903a00 { 348 compatible = "nvidia,tegra234-adx", 349 "nvidia,tegra210-adx"; 350 reg = <0x0 0x2903a00 0x0 0x100>; 351 sound-name-prefix = "ADX3"; 352 status = "disabled"; 353 }; 354 355 tegra_adx4: adx@2903b00 { 356 compatible = "nvidia,tegra234-adx", 357 "nvidia,tegra210-adx"; 358 reg = <0x0 0x2903b00 0x0 0x100>; 359 sound-name-prefix = "ADX4"; 360 status = "disabled"; 361 }; 362 363 364 tegra_dmic1: dmic@2904000 { 365 compatible = "nvidia,tegra234-dmic", 366 "nvidia,tegra210-dmic"; 367 reg = <0x0 0x2904000 0x0 0x100>; 368 clocks = <&bpmp TEGRA234_CLK_DMIC1>; 369 clock-names = "dmic"; 370 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC1>; 371 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 372 assigned-clock-rates = <3072000>; 373 sound-name-prefix = "DMIC1"; 374 status = "disabled"; 375 }; 376 377 tegra_dmic2: dmic@2904100 { 378 compatible = "nvidia,tegra234-dmic", 379 "nvidia,tegra210-dmic"; 380 reg = <0x0 0x2904100 0x0 0x100>; 381 clocks = <&bpmp TEGRA234_CLK_DMIC2>; 382 clock-names = "dmic"; 383 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC2>; 384 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 385 assigned-clock-rates = <3072000>; 386 sound-name-prefix = "DMIC2"; 387 status = "disabled"; 388 }; 389 390 tegra_dmic3: dmic@2904200 { 391 compatible = "nvidia,tegra234-dmic", 392 "nvidia,tegra210-dmic"; 393 reg = <0x0 0x2904200 0x0 0x100>; 394 clocks = <&bpmp TEGRA234_CLK_DMIC3>; 395 clock-names = "dmic"; 396 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC3>; 397 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 398 assigned-clock-rates = <3072000>; 399 sound-name-prefix = "DMIC3"; 400 status = "disabled"; 401 }; 402 403 tegra_dmic4: dmic@2904300 { 404 compatible = "nvidia,tegra234-dmic", 405 "nvidia,tegra210-dmic"; 406 reg = <0x0 0x2904300 0x0 0x100>; 407 clocks = <&bpmp TEGRA234_CLK_DMIC4>; 408 clock-names = "dmic"; 409 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC4>; 410 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 411 assigned-clock-rates = <3072000>; 412 sound-name-prefix = "DMIC4"; 413 status = "disabled"; 414 }; 415 416 tegra_dspk1: dspk@2905000 { 417 compatible = "nvidia,tegra234-dspk", 418 "nvidia,tegra186-dspk"; 419 reg = <0x0 0x2905000 0x0 0x100>; 420 clocks = <&bpmp TEGRA234_CLK_DSPK1>; 421 clock-names = "dspk"; 422 assigned-clocks = <&bpmp TEGRA234_CLK_DSPK1>; 423 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 424 assigned-clock-rates = <12288000>; 425 sound-name-prefix = "DSPK1"; 426 status = "disabled"; 427 }; 428 429 tegra_dspk2: dspk@2905100 { 430 compatible = "nvidia,tegra234-dspk", 431 "nvidia,tegra186-dspk"; 432 reg = <0x0 0x2905100 0x0 0x100>; 433 clocks = <&bpmp TEGRA234_CLK_DSPK2>; 434 clock-names = "dspk"; 435 assigned-clocks = <&bpmp TEGRA234_CLK_DSPK2>; 436 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 437 assigned-clock-rates = <12288000>; 438 sound-name-prefix = "DSPK2"; 439 status = "disabled"; 440 }; 441 442 tegra_ope1: processing-engine@2908000 { 443 compatible = "nvidia,tegra234-ope", 444 "nvidia,tegra210-ope"; 445 reg = <0x0 0x2908000 0x0 0x100>; 446 sound-name-prefix = "OPE1"; 447 status = "disabled"; 448 449 #address-cells = <2>; 450 #size-cells = <2>; 451 ranges; 452 453 equalizer@2908100 { 454 compatible = "nvidia,tegra234-peq", 455 "nvidia,tegra210-peq"; 456 reg = <0x0 0x2908100 0x0 0x100>; 457 }; 458 459 dynamic-range-compressor@2908200 { 460 compatible = "nvidia,tegra234-mbdrc", 461 "nvidia,tegra210-mbdrc"; 462 reg = <0x0 0x2908200 0x0 0x200>; 463 }; 464 }; 465 466 tegra_mvc1: mvc@290a000 { 467 compatible = "nvidia,tegra234-mvc", 468 "nvidia,tegra210-mvc"; 469 reg = <0x0 0x290a000 0x0 0x200>; 470 sound-name-prefix = "MVC1"; 471 status = "disabled"; 472 }; 473 474 tegra_mvc2: mvc@290a200 { 475 compatible = "nvidia,tegra234-mvc", 476 "nvidia,tegra210-mvc"; 477 reg = <0x0 0x290a200 0x0 0x200>; 478 sound-name-prefix = "MVC2"; 479 status = "disabled"; 480 }; 481 482 tegra_amixer: amixer@290bb00 { 483 compatible = "nvidia,tegra234-amixer", 484 "nvidia,tegra210-amixer"; 485 reg = <0x0 0x290bb00 0x0 0x800>; 486 sound-name-prefix = "MIXER1"; 487 status = "disabled"; 488 }; 489 490 tegra_admaif: admaif@290f000 { 491 compatible = "nvidia,tegra234-admaif", 492 "nvidia,tegra186-admaif"; 493 reg = <0x0 0x0290f000 0x0 0x1000>; 494 dmas = <&adma 1>, <&adma 1>, 495 <&adma 2>, <&adma 2>, 496 <&adma 3>, <&adma 3>, 497 <&adma 4>, <&adma 4>, 498 <&adma 5>, <&adma 5>, 499 <&adma 6>, <&adma 6>, 500 <&adma 7>, <&adma 7>, 501 <&adma 8>, <&adma 8>, 502 <&adma 9>, <&adma 9>, 503 <&adma 10>, <&adma 10>, 504 <&adma 11>, <&adma 11>, 505 <&adma 12>, <&adma 12>, 506 <&adma 13>, <&adma 13>, 507 <&adma 14>, <&adma 14>, 508 <&adma 15>, <&adma 15>, 509 <&adma 16>, <&adma 16>, 510 <&adma 17>, <&adma 17>, 511 <&adma 18>, <&adma 18>, 512 <&adma 19>, <&adma 19>, 513 <&adma 20>, <&adma 20>; 514 dma-names = "rx1", "tx1", 515 "rx2", "tx2", 516 "rx3", "tx3", 517 "rx4", "tx4", 518 "rx5", "tx5", 519 "rx6", "tx6", 520 "rx7", "tx7", 521 "rx8", "tx8", 522 "rx9", "tx9", 523 "rx10", "tx10", 524 "rx11", "tx11", 525 "rx12", "tx12", 526 "rx13", "tx13", 527 "rx14", "tx14", 528 "rx15", "tx15", 529 "rx16", "tx16", 530 "rx17", "tx17", 531 "rx18", "tx18", 532 "rx19", "tx19", 533 "rx20", "tx20"; 534 interconnects = <&mc TEGRA234_MEMORY_CLIENT_APEDMAR &emc>, 535 <&mc TEGRA234_MEMORY_CLIENT_APEDMAW &emc>; 536 interconnect-names = "dma-mem", "write"; 537 iommus = <&smmu_niso0 TEGRA234_SID_APE>; 538 status = "disabled"; 539 }; 540 541 tegra_asrc: asrc@2910000 { 542 compatible = "nvidia,tegra234-asrc", 543 "nvidia,tegra186-asrc"; 544 reg = <0x0 0x2910000 0x0 0x2000>; 545 sound-name-prefix = "ASRC1"; 546 status = "disabled"; 547 }; 548 }; 549 550 adma: dma-controller@2930000 { 551 compatible = "nvidia,tegra234-adma", 552 "nvidia,tegra186-adma"; 553 reg = <0x0 0x02930000 0x0 0x20000>; 554 interrupt-parent = <&agic>; 555 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 556 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 557 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 558 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 559 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 560 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 562 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 563 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 564 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 565 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 566 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 567 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 568 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 569 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 570 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 571 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 574 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 575 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 576 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 577 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 578 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 579 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 580 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 581 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 582 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 583 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 584 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 587 #dma-cells = <1>; 588 clocks = <&bpmp TEGRA234_CLK_AHUB>; 589 clock-names = "d_audio"; 590 status = "disabled"; 591 }; 592 593 agic: interrupt-controller@2a40000 { 594 compatible = "nvidia,tegra234-agic", 595 "nvidia,tegra210-agic"; 596 #interrupt-cells = <3>; 597 interrupt-controller; 598 reg = <0x0 0x02a41000 0x0 0x1000>, 599 <0x0 0x02a42000 0x0 0x2000>; 600 interrupts = <GIC_SPI 145 601 (GIC_CPU_MASK_SIMPLE(4) | 602 IRQ_TYPE_LEVEL_HIGH)>; 603 clocks = <&bpmp TEGRA234_CLK_APE>; 604 clock-names = "clk"; 605 status = "disabled"; 606 }; 607 }; 608 609 mc: memory-controller@2c00000 { 610 compatible = "nvidia,tegra234-mc"; 611 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ 612 <0x0 0x02c10000 0x0 0x10000>, /* MC Broadcast*/ 613 <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ 614 <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ 615 <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ 616 <0x0 0x02c50000 0x0 0x10000>, /* MC3 */ 617 <0x0 0x02b80000 0x0 0x10000>, /* MC4 */ 618 <0x0 0x02b90000 0x0 0x10000>, /* MC5 */ 619 <0x0 0x02ba0000 0x0 0x10000>, /* MC6 */ 620 <0x0 0x02bb0000 0x0 0x10000>, /* MC7 */ 621 <0x0 0x01700000 0x0 0x10000>, /* MC8 */ 622 <0x0 0x01710000 0x0 0x10000>, /* MC9 */ 623 <0x0 0x01720000 0x0 0x10000>, /* MC10 */ 624 <0x0 0x01730000 0x0 0x10000>, /* MC11 */ 625 <0x0 0x01740000 0x0 0x10000>, /* MC12 */ 626 <0x0 0x01750000 0x0 0x10000>, /* MC13 */ 627 <0x0 0x01760000 0x0 0x10000>, /* MC14 */ 628 <0x0 0x01770000 0x0 0x10000>; /* MC15 */ 629 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", 630 "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", 631 "ch11", "ch12", "ch13", "ch14", "ch15"; 632 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 633 #interconnect-cells = <1>; 634 status = "okay"; 635 636 #address-cells = <2>; 637 #size-cells = <2>; 638 ranges = <0x0 0x01700000 0x0 0x01700000 0x0 0x100000>, 639 <0x0 0x02b80000 0x0 0x02b80000 0x0 0x040000>, 640 <0x0 0x02c00000 0x0 0x02c00000 0x0 0x100000>; 641 642 /* 643 * Bit 39 of addresses passing through the memory 644 * controller selects the XBAR format used when memory 645 * is accessed. This is used to transparently access 646 * memory in the XBAR format used by the discrete GPU 647 * (bit 39 set) or Tegra (bit 39 clear). 648 * 649 * As a consequence, the operating system must ensure 650 * that bit 39 is never used implicitly, for example 651 * via an I/O virtual address mapping of an IOMMU. If 652 * devices require access to the XBAR switch, their 653 * drivers must set this bit explicitly. 654 * 655 * Limit the DMA range for memory clients to [38:0]. 656 */ 657 dma-ranges = <0x0 0x0 0x0 0x0 0x80 0x0>; 658 659 emc: external-memory-controller@2c60000 { 660 compatible = "nvidia,tegra234-emc"; 661 reg = <0x0 0x02c60000 0x0 0x90000>, 662 <0x0 0x01780000 0x0 0x80000>; 663 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 664 clocks = <&bpmp TEGRA234_CLK_EMC>; 665 clock-names = "emc"; 666 status = "okay"; 667 668 #interconnect-cells = <0>; 669 670 nvidia,bpmp = <&bpmp>; 671 }; 672 }; 673 674 uarta: serial@3100000 { 675 compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart"; 676 reg = <0x0 0x03100000 0x0 0x10000>; 677 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 678 clocks = <&bpmp TEGRA234_CLK_UARTA>; 679 clock-names = "serial"; 680 resets = <&bpmp TEGRA234_RESET_UARTA>; 681 reset-names = "serial"; 682 status = "disabled"; 683 }; 684 685 gen1_i2c: i2c@3160000 { 686 compatible = "nvidia,tegra194-i2c"; 687 reg = <0x0 0x3160000 0x0 0x100>; 688 status = "disabled"; 689 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 690 clock-frequency = <400000>; 691 clocks = <&bpmp TEGRA234_CLK_I2C1 692 &bpmp TEGRA234_CLK_PLLP_OUT0>; 693 assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>; 694 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 695 clock-names = "div-clk", "parent"; 696 resets = <&bpmp TEGRA234_RESET_I2C1>; 697 reset-names = "i2c"; 698 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 699 dma-coherent; 700 dmas = <&gpcdma 21>, <&gpcdma 21>; 701 dma-names = "rx", "tx"; 702 }; 703 704 cam_i2c: i2c@3180000 { 705 compatible = "nvidia,tegra194-i2c"; 706 reg = <0x0 0x3180000 0x0 0x100>; 707 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 708 status = "disabled"; 709 clock-frequency = <400000>; 710 clocks = <&bpmp TEGRA234_CLK_I2C3 711 &bpmp TEGRA234_CLK_PLLP_OUT0>; 712 assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>; 713 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 714 clock-names = "div-clk", "parent"; 715 resets = <&bpmp TEGRA234_RESET_I2C3>; 716 reset-names = "i2c"; 717 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 718 dma-coherent; 719 dmas = <&gpcdma 23>, <&gpcdma 23>; 720 dma-names = "rx", "tx"; 721 }; 722 723 dp_aux_ch1_i2c: i2c@3190000 { 724 compatible = "nvidia,tegra194-i2c"; 725 reg = <0x0 0x3190000 0x0 0x100>; 726 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 727 status = "disabled"; 728 clock-frequency = <100000>; 729 clocks = <&bpmp TEGRA234_CLK_I2C4 730 &bpmp TEGRA234_CLK_PLLP_OUT0>; 731 assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>; 732 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 733 clock-names = "div-clk", "parent"; 734 resets = <&bpmp TEGRA234_RESET_I2C4>; 735 reset-names = "i2c"; 736 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 737 dma-coherent; 738 dmas = <&gpcdma 26>, <&gpcdma 26>; 739 dma-names = "rx", "tx"; 740 }; 741 742 dp_aux_ch0_i2c: i2c@31b0000 { 743 compatible = "nvidia,tegra194-i2c"; 744 reg = <0x0 0x31b0000 0x0 0x100>; 745 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 746 status = "disabled"; 747 clock-frequency = <100000>; 748 clocks = <&bpmp TEGRA234_CLK_I2C6 749 &bpmp TEGRA234_CLK_PLLP_OUT0>; 750 assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>; 751 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 752 clock-names = "div-clk", "parent"; 753 resets = <&bpmp TEGRA234_RESET_I2C6>; 754 reset-names = "i2c"; 755 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 756 dma-coherent; 757 dmas = <&gpcdma 30>, <&gpcdma 30>; 758 dma-names = "rx", "tx"; 759 }; 760 761 dp_aux_ch2_i2c: i2c@31c0000 { 762 compatible = "nvidia,tegra194-i2c"; 763 reg = <0x0 0x31c0000 0x0 0x100>; 764 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 765 status = "disabled"; 766 clock-frequency = <100000>; 767 clocks = <&bpmp TEGRA234_CLK_I2C7 768 &bpmp TEGRA234_CLK_PLLP_OUT0>; 769 assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>; 770 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 771 clock-names = "div-clk", "parent"; 772 resets = <&bpmp TEGRA234_RESET_I2C7>; 773 reset-names = "i2c"; 774 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 775 dma-coherent; 776 dmas = <&gpcdma 27>, <&gpcdma 27>; 777 dma-names = "rx", "tx"; 778 }; 779 780 uarti: serial@31d0000 { 781 compatible = "arm,sbsa-uart"; 782 reg = <0x0 0x31d0000 0x0 0x10000>; 783 interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; 784 status = "disabled"; 785 }; 786 787 dp_aux_ch3_i2c: i2c@31e0000 { 788 compatible = "nvidia,tegra194-i2c"; 789 reg = <0x0 0x31e0000 0x0 0x100>; 790 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 791 status = "disabled"; 792 clock-frequency = <100000>; 793 clocks = <&bpmp TEGRA234_CLK_I2C9 794 &bpmp TEGRA234_CLK_PLLP_OUT0>; 795 assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>; 796 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 797 clock-names = "div-clk", "parent"; 798 resets = <&bpmp TEGRA234_RESET_I2C9>; 799 reset-names = "i2c"; 800 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 801 dma-coherent; 802 dmas = <&gpcdma 31>, <&gpcdma 31>; 803 dma-names = "rx", "tx"; 804 }; 805 806 spi@3270000 { 807 compatible = "nvidia,tegra234-qspi"; 808 reg = <0x0 0x3270000 0x0 0x1000>; 809 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 810 #address-cells = <1>; 811 #size-cells = <0>; 812 clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>, 813 <&bpmp TEGRA234_CLK_QSPI0_PM>; 814 clock-names = "qspi", "qspi_out"; 815 resets = <&bpmp TEGRA234_RESET_QSPI0>; 816 status = "disabled"; 817 }; 818 819 pwm1: pwm@3280000 { 820 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 821 reg = <0x0 0x3280000 0x0 0x10000>; 822 clocks = <&bpmp TEGRA234_CLK_PWM1>; 823 resets = <&bpmp TEGRA234_RESET_PWM1>; 824 reset-names = "pwm"; 825 status = "disabled"; 826 #pwm-cells = <2>; 827 }; 828 829 pwm2: pwm@3290000 { 830 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 831 reg = <0x0 0x3290000 0x0 0x10000>; 832 clocks = <&bpmp TEGRA234_CLK_PWM2>; 833 resets = <&bpmp TEGRA234_RESET_PWM2>; 834 reset-names = "pwm"; 835 status = "disabled"; 836 #pwm-cells = <2>; 837 }; 838 839 pwm3: pwm@32a0000 { 840 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 841 reg = <0x0 0x32a0000 0x0 0x10000>; 842 clocks = <&bpmp TEGRA234_CLK_PWM3>; 843 resets = <&bpmp TEGRA234_RESET_PWM3>; 844 reset-names = "pwm"; 845 status = "disabled"; 846 #pwm-cells = <2>; 847 }; 848 849 pwm5: pwm@32c0000 { 850 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 851 reg = <0x0 0x32c0000 0x0 0x10000>; 852 clocks = <&bpmp TEGRA234_CLK_PWM5>; 853 resets = <&bpmp TEGRA234_RESET_PWM5>; 854 reset-names = "pwm"; 855 status = "disabled"; 856 #pwm-cells = <2>; 857 }; 858 859 pwm6: pwm@32d0000 { 860 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 861 reg = <0x0 0x32d0000 0x0 0x10000>; 862 clocks = <&bpmp TEGRA234_CLK_PWM6>; 863 resets = <&bpmp TEGRA234_RESET_PWM6>; 864 reset-names = "pwm"; 865 status = "disabled"; 866 #pwm-cells = <2>; 867 }; 868 869 pwm7: pwm@32e0000 { 870 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 871 reg = <0x0 0x32e0000 0x0 0x10000>; 872 clocks = <&bpmp TEGRA234_CLK_PWM7>; 873 resets = <&bpmp TEGRA234_RESET_PWM7>; 874 reset-names = "pwm"; 875 status = "disabled"; 876 #pwm-cells = <2>; 877 }; 878 879 pwm8: pwm@32f0000 { 880 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 881 reg = <0x0 0x32f0000 0x0 0x10000>; 882 clocks = <&bpmp TEGRA234_CLK_PWM8>; 883 resets = <&bpmp TEGRA234_RESET_PWM8>; 884 reset-names = "pwm"; 885 status = "disabled"; 886 #pwm-cells = <2>; 887 }; 888 889 spi@3300000 { 890 compatible = "nvidia,tegra234-qspi"; 891 reg = <0x0 0x3300000 0x0 0x1000>; 892 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 893 #address-cells = <1>; 894 #size-cells = <0>; 895 clocks = <&bpmp TEGRA234_CLK_QSPI1_2X_PM>, 896 <&bpmp TEGRA234_CLK_QSPI1_PM>; 897 clock-names = "qspi", "qspi_out"; 898 resets = <&bpmp TEGRA234_RESET_QSPI1>; 899 status = "disabled"; 900 }; 901 902 mmc@3400000 { 903 compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; 904 reg = <0x0 0x03400000 0x0 0x20000>; 905 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 906 clocks = <&bpmp TEGRA234_CLK_SDMMC1>, 907 <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; 908 clock-names = "sdhci", "tmclk"; 909 assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC1>, 910 <&bpmp TEGRA234_CLK_PLLC4_MUXED>; 911 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4_MUXED>, 912 <&bpmp TEGRA234_CLK_PLLC4_VCO_DIV2>; 913 resets = <&bpmp TEGRA234_RESET_SDMMC1>; 914 reset-names = "sdhci"; 915 interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRA &emc>, 916 <&mc TEGRA234_MEMORY_CLIENT_SDMMCWA &emc>; 917 interconnect-names = "dma-mem", "write"; 918 iommus = <&smmu_niso1 TEGRA234_SID_SDMMC1A>; 919 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 920 pinctrl-0 = <&sdmmc1_3v3>; 921 pinctrl-1 = <&sdmmc1_1v8>; 922 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 923 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x07>; 924 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 925 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 926 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 927 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 928 nvidia,default-tap = <14>; 929 nvidia,default-trim = <0x8>; 930 sd-uhs-sdr25; 931 sd-uhs-sdr50; 932 sd-uhs-ddr50; 933 sd-uhs-sdr104; 934 status = "disabled"; 935 }; 936 937 mmc@3460000 { 938 compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; 939 reg = <0x0 0x03460000 0x0 0x20000>; 940 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 941 clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 942 <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; 943 clock-names = "sdhci", "tmclk"; 944 assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 945 <&bpmp TEGRA234_CLK_PLLC4>; 946 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>; 947 resets = <&bpmp TEGRA234_RESET_SDMMC4>; 948 reset-names = "sdhci"; 949 interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRAB &emc>, 950 <&mc TEGRA234_MEMORY_CLIENT_SDMMCWAB &emc>; 951 interconnect-names = "dma-mem", "write"; 952 iommus = <&smmu_niso1 TEGRA234_SID_SDMMC4>; 953 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 954 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 955 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 956 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 957 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 958 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 959 nvidia,default-tap = <0x8>; 960 nvidia,default-trim = <0x14>; 961 nvidia,dqs-trim = <40>; 962 supports-cqe; 963 status = "disabled"; 964 }; 965 966 hda@3510000 { 967 compatible = "nvidia,tegra234-hda"; 968 reg = <0x0 0x3510000 0x0 0x10000>; 969 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 970 clocks = <&bpmp TEGRA234_CLK_AZA_BIT>, 971 <&bpmp TEGRA234_CLK_AZA_2XBIT>; 972 clock-names = "hda", "hda2codec_2x"; 973 resets = <&bpmp TEGRA234_RESET_HDA>, 974 <&bpmp TEGRA234_RESET_HDACODEC>; 975 reset-names = "hda", "hda2codec_2x"; 976 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DISP>; 977 interconnects = <&mc TEGRA234_MEMORY_CLIENT_HDAR &emc>, 978 <&mc TEGRA234_MEMORY_CLIENT_HDAW &emc>; 979 interconnect-names = "dma-mem", "write"; 980 iommus = <&smmu_niso0 TEGRA234_SID_HDA>; 981 status = "disabled"; 982 }; 983 984 fuse@3810000 { 985 compatible = "nvidia,tegra234-efuse"; 986 reg = <0x0 0x03810000 0x0 0x10000>; 987 clocks = <&bpmp TEGRA234_CLK_FUSE>; 988 clock-names = "fuse"; 989 }; 990 991 hsp_top0: hsp@3c00000 { 992 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 993 reg = <0x0 0x03c00000 0x0 0xa0000>; 994 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 995 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 996 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 997 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 998 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 999 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1000 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1001 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1002 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1003 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 1004 "shared3", "shared4", "shared5", "shared6", 1005 "shared7"; 1006 #mbox-cells = <2>; 1007 }; 1008 1009 p2u_hsio_0: phy@3e00000 { 1010 compatible = "nvidia,tegra234-p2u"; 1011 reg = <0x0 0x03e00000 0x0 0x10000>; 1012 reg-names = "ctl"; 1013 1014 #phy-cells = <0>; 1015 }; 1016 1017 p2u_hsio_1: phy@3e10000 { 1018 compatible = "nvidia,tegra234-p2u"; 1019 reg = <0x0 0x03e10000 0x0 0x10000>; 1020 reg-names = "ctl"; 1021 1022 #phy-cells = <0>; 1023 }; 1024 1025 p2u_hsio_2: phy@3e20000 { 1026 compatible = "nvidia,tegra234-p2u"; 1027 reg = <0x0 0x03e20000 0x0 0x10000>; 1028 reg-names = "ctl"; 1029 1030 #phy-cells = <0>; 1031 }; 1032 1033 p2u_hsio_3: phy@3e30000 { 1034 compatible = "nvidia,tegra234-p2u"; 1035 reg = <0x0 0x03e30000 0x0 0x10000>; 1036 reg-names = "ctl"; 1037 1038 #phy-cells = <0>; 1039 }; 1040 1041 p2u_hsio_4: phy@3e40000 { 1042 compatible = "nvidia,tegra234-p2u"; 1043 reg = <0x0 0x03e40000 0x0 0x10000>; 1044 reg-names = "ctl"; 1045 1046 #phy-cells = <0>; 1047 }; 1048 1049 p2u_hsio_5: phy@3e50000 { 1050 compatible = "nvidia,tegra234-p2u"; 1051 reg = <0x0 0x03e50000 0x0 0x10000>; 1052 reg-names = "ctl"; 1053 1054 #phy-cells = <0>; 1055 }; 1056 1057 p2u_hsio_6: phy@3e60000 { 1058 compatible = "nvidia,tegra234-p2u"; 1059 reg = <0x0 0x03e60000 0x0 0x10000>; 1060 reg-names = "ctl"; 1061 1062 #phy-cells = <0>; 1063 }; 1064 1065 p2u_hsio_7: phy@3e70000 { 1066 compatible = "nvidia,tegra234-p2u"; 1067 reg = <0x0 0x03e70000 0x0 0x10000>; 1068 reg-names = "ctl"; 1069 1070 #phy-cells = <0>; 1071 }; 1072 1073 p2u_nvhs_0: phy@3e90000 { 1074 compatible = "nvidia,tegra234-p2u"; 1075 reg = <0x0 0x03e90000 0x0 0x10000>; 1076 reg-names = "ctl"; 1077 1078 #phy-cells = <0>; 1079 }; 1080 1081 p2u_nvhs_1: phy@3ea0000 { 1082 compatible = "nvidia,tegra234-p2u"; 1083 reg = <0x0 0x03ea0000 0x0 0x10000>; 1084 reg-names = "ctl"; 1085 1086 #phy-cells = <0>; 1087 }; 1088 1089 p2u_nvhs_2: phy@3eb0000 { 1090 compatible = "nvidia,tegra234-p2u"; 1091 reg = <0x0 0x03eb0000 0x0 0x10000>; 1092 reg-names = "ctl"; 1093 1094 #phy-cells = <0>; 1095 }; 1096 1097 p2u_nvhs_3: phy@3ec0000 { 1098 compatible = "nvidia,tegra234-p2u"; 1099 reg = <0x0 0x03ec0000 0x0 0x10000>; 1100 reg-names = "ctl"; 1101 1102 #phy-cells = <0>; 1103 }; 1104 1105 p2u_nvhs_4: phy@3ed0000 { 1106 compatible = "nvidia,tegra234-p2u"; 1107 reg = <0x0 0x03ed0000 0x0 0x10000>; 1108 reg-names = "ctl"; 1109 1110 #phy-cells = <0>; 1111 }; 1112 1113 p2u_nvhs_5: phy@3ee0000 { 1114 compatible = "nvidia,tegra234-p2u"; 1115 reg = <0x0 0x03ee0000 0x0 0x10000>; 1116 reg-names = "ctl"; 1117 1118 #phy-cells = <0>; 1119 }; 1120 1121 p2u_nvhs_6: phy@3ef0000 { 1122 compatible = "nvidia,tegra234-p2u"; 1123 reg = <0x0 0x03ef0000 0x0 0x10000>; 1124 reg-names = "ctl"; 1125 1126 #phy-cells = <0>; 1127 }; 1128 1129 p2u_nvhs_7: phy@3f00000 { 1130 compatible = "nvidia,tegra234-p2u"; 1131 reg = <0x0 0x03f00000 0x0 0x10000>; 1132 reg-names = "ctl"; 1133 1134 #phy-cells = <0>; 1135 }; 1136 1137 p2u_gbe_0: phy@3f20000 { 1138 compatible = "nvidia,tegra234-p2u"; 1139 reg = <0x0 0x03f20000 0x0 0x10000>; 1140 reg-names = "ctl"; 1141 1142 #phy-cells = <0>; 1143 }; 1144 1145 p2u_gbe_1: phy@3f30000 { 1146 compatible = "nvidia,tegra234-p2u"; 1147 reg = <0x0 0x03f30000 0x0 0x10000>; 1148 reg-names = "ctl"; 1149 1150 #phy-cells = <0>; 1151 }; 1152 1153 p2u_gbe_2: phy@3f40000 { 1154 compatible = "nvidia,tegra234-p2u"; 1155 reg = <0x0 0x03f40000 0x0 0x10000>; 1156 reg-names = "ctl"; 1157 1158 #phy-cells = <0>; 1159 }; 1160 1161 p2u_gbe_3: phy@3f50000 { 1162 compatible = "nvidia,tegra234-p2u"; 1163 reg = <0x0 0x03f50000 0x0 0x10000>; 1164 reg-names = "ctl"; 1165 1166 #phy-cells = <0>; 1167 }; 1168 1169 p2u_gbe_4: phy@3f60000 { 1170 compatible = "nvidia,tegra234-p2u"; 1171 reg = <0x0 0x03f60000 0x0 0x10000>; 1172 reg-names = "ctl"; 1173 1174 #phy-cells = <0>; 1175 }; 1176 1177 p2u_gbe_5: phy@3f70000 { 1178 compatible = "nvidia,tegra234-p2u"; 1179 reg = <0x0 0x03f70000 0x0 0x10000>; 1180 reg-names = "ctl"; 1181 1182 #phy-cells = <0>; 1183 }; 1184 1185 p2u_gbe_6: phy@3f80000 { 1186 compatible = "nvidia,tegra234-p2u"; 1187 reg = <0x0 0x03f80000 0x0 0x10000>; 1188 reg-names = "ctl"; 1189 1190 #phy-cells = <0>; 1191 }; 1192 1193 p2u_gbe_7: phy@3f90000 { 1194 compatible = "nvidia,tegra234-p2u"; 1195 reg = <0x0 0x03f90000 0x0 0x10000>; 1196 reg-names = "ctl"; 1197 1198 #phy-cells = <0>; 1199 }; 1200 1201 ethernet@6800000 { 1202 compatible = "nvidia,tegra234-mgbe"; 1203 reg = <0x0 0x06800000 0x0 0x10000>, 1204 <0x0 0x06810000 0x0 0x10000>, 1205 <0x0 0x068a0000 0x0 0x10000>; 1206 reg-names = "hypervisor", "mac", "xpcs"; 1207 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; 1208 interrupt-names = "common"; 1209 clocks = <&bpmp TEGRA234_CLK_MGBE0_APP>, 1210 <&bpmp TEGRA234_CLK_MGBE0_MAC>, 1211 <&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>, 1212 <&bpmp TEGRA234_CLK_MGBE0_PTP_REF>, 1213 <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>, 1214 <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>, 1215 <&bpmp TEGRA234_CLK_MGBE0_TX>, 1216 <&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>, 1217 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>, 1218 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>, 1219 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS>, 1220 <&bpmp TEGRA234_CLK_MGBE0_TX_PCS>; 1221 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1222 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1223 "rx-pcs", "tx-pcs"; 1224 resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>, 1225 <&bpmp TEGRA234_RESET_MGBE0_PCS>; 1226 reset-names = "mac", "pcs"; 1227 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEARD &emc>, 1228 <&mc TEGRA234_MEMORY_CLIENT_MGBEAWR &emc>; 1229 interconnect-names = "dma-mem", "write"; 1230 iommus = <&smmu_niso0 TEGRA234_SID_MGBE>; 1231 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEA>; 1232 status = "disabled"; 1233 }; 1234 1235 ethernet@6900000 { 1236 compatible = "nvidia,tegra234-mgbe"; 1237 reg = <0x0 0x06900000 0x0 0x10000>, 1238 <0x0 0x06910000 0x0 0x10000>, 1239 <0x0 0x069a0000 0x0 0x10000>; 1240 reg-names = "hypervisor", "mac", "xpcs"; 1241 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>; 1242 interrupt-names = "common"; 1243 clocks = <&bpmp TEGRA234_CLK_MGBE1_APP>, 1244 <&bpmp TEGRA234_CLK_MGBE1_MAC>, 1245 <&bpmp TEGRA234_CLK_MGBE1_MAC_DIVIDER>, 1246 <&bpmp TEGRA234_CLK_MGBE1_PTP_REF>, 1247 <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT_M>, 1248 <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT>, 1249 <&bpmp TEGRA234_CLK_MGBE1_TX>, 1250 <&bpmp TEGRA234_CLK_MGBE1_EEE_PCS>, 1251 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_INPUT>, 1252 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_M>, 1253 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS>, 1254 <&bpmp TEGRA234_CLK_MGBE1_TX_PCS>; 1255 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1256 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1257 "rx-pcs", "tx-pcs"; 1258 resets = <&bpmp TEGRA234_RESET_MGBE1_MAC>, 1259 <&bpmp TEGRA234_RESET_MGBE1_PCS>; 1260 reset-names = "mac", "pcs"; 1261 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEBRD &emc>, 1262 <&mc TEGRA234_MEMORY_CLIENT_MGBEBWR &emc>; 1263 interconnect-names = "dma-mem", "write"; 1264 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF1>; 1265 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEB>; 1266 status = "disabled"; 1267 }; 1268 1269 ethernet@6a00000 { 1270 compatible = "nvidia,tegra234-mgbe"; 1271 reg = <0x0 0x06a00000 0x0 0x10000>, 1272 <0x0 0x06a10000 0x0 0x10000>, 1273 <0x0 0x06aa0000 0x0 0x10000>; 1274 reg-names = "hypervisor", "mac", "xpcs"; 1275 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>; 1276 interrupt-names = "common"; 1277 clocks = <&bpmp TEGRA234_CLK_MGBE2_APP>, 1278 <&bpmp TEGRA234_CLK_MGBE2_MAC>, 1279 <&bpmp TEGRA234_CLK_MGBE2_MAC_DIVIDER>, 1280 <&bpmp TEGRA234_CLK_MGBE2_PTP_REF>, 1281 <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT_M>, 1282 <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT>, 1283 <&bpmp TEGRA234_CLK_MGBE2_TX>, 1284 <&bpmp TEGRA234_CLK_MGBE2_EEE_PCS>, 1285 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_INPUT>, 1286 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_M>, 1287 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS>, 1288 <&bpmp TEGRA234_CLK_MGBE2_TX_PCS>; 1289 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1290 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1291 "rx-pcs", "tx-pcs"; 1292 resets = <&bpmp TEGRA234_RESET_MGBE2_MAC>, 1293 <&bpmp TEGRA234_RESET_MGBE2_PCS>; 1294 reset-names = "mac", "pcs"; 1295 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBECRD &emc>, 1296 <&mc TEGRA234_MEMORY_CLIENT_MGBECWR &emc>; 1297 interconnect-names = "dma-mem", "write"; 1298 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF2>; 1299 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEC>; 1300 status = "disabled"; 1301 }; 1302 1303 ethernet@6b00000 { 1304 compatible = "nvidia,tegra234-mgbe"; 1305 reg = <0x0 0x06b00000 0x0 0x10000>, 1306 <0x0 0x06b10000 0x0 0x10000>, 1307 <0x0 0x06ba0000 0x0 0x10000>; 1308 reg-names = "hypervisor", "mac", "xpcs"; 1309 interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 1310 interrupt-names = "common"; 1311 clocks = <&bpmp TEGRA234_CLK_MGBE3_APP>, 1312 <&bpmp TEGRA234_CLK_MGBE3_MAC>, 1313 <&bpmp TEGRA234_CLK_MGBE3_MAC_DIVIDER>, 1314 <&bpmp TEGRA234_CLK_MGBE3_PTP_REF>, 1315 <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT_M>, 1316 <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT>, 1317 <&bpmp TEGRA234_CLK_MGBE3_TX>, 1318 <&bpmp TEGRA234_CLK_MGBE3_EEE_PCS>, 1319 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_INPUT>, 1320 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_M>, 1321 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS>, 1322 <&bpmp TEGRA234_CLK_MGBE3_TX_PCS>; 1323 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1324 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1325 "rx-pcs", "tx-pcs"; 1326 resets = <&bpmp TEGRA234_RESET_MGBE3_MAC>, 1327 <&bpmp TEGRA234_RESET_MGBE3_PCS>; 1328 reset-names = "mac", "pcs"; 1329 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEDRD &emc>, 1330 <&mc TEGRA234_MEMORY_CLIENT_MGBEDWR &emc>; 1331 interconnect-names = "dma-mem", "write"; 1332 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF3>; 1333 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBED>; 1334 status = "disabled"; 1335 }; 1336 1337 smmu_niso1: iommu@8000000 { 1338 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 1339 reg = <0x0 0x8000000 0x0 0x1000000>, 1340 <0x0 0x7000000 0x0 0x1000000>; 1341 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1342 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 1343 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1344 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 1345 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1346 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1347 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1348 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1349 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1350 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1351 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1352 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1353 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1354 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1355 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1356 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1357 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1358 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1359 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1360 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1361 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1362 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1363 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1364 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1365 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1366 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1367 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1368 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1369 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1370 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1371 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1372 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1373 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1374 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1375 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1376 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1377 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1378 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1379 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1380 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1381 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1382 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1383 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1384 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1385 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1386 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1387 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1388 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1389 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1390 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1391 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1392 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1393 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1394 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1395 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1396 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1397 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1398 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1399 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1400 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1401 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1402 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1403 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1404 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1405 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1406 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1407 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1408 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1409 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1410 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1411 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1412 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1413 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1414 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1415 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1416 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1417 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1418 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1419 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1420 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1421 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1422 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1423 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1424 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1425 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1426 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1427 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1428 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1429 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1430 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1431 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1432 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1433 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1434 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1435 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1436 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1437 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1438 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1439 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1440 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1441 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1442 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1443 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1444 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1445 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1446 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1447 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1448 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1449 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1450 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1451 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1452 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1453 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1454 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1455 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1456 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1457 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1458 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1459 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1460 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1461 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1462 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1463 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1464 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1465 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1466 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1467 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1468 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1469 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1470 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1471 stream-match-mask = <0x7f80>; 1472 #global-interrupts = <2>; 1473 #iommu-cells = <1>; 1474 1475 nvidia,memory-controller = <&mc>; 1476 status = "okay"; 1477 }; 1478 1479 sce-fabric@b600000 { 1480 compatible = "nvidia,tegra234-sce-fabric"; 1481 reg = <0x0 0xb600000 0x0 0x40000>; 1482 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 1483 status = "okay"; 1484 }; 1485 1486 rce-fabric@be00000 { 1487 compatible = "nvidia,tegra234-rce-fabric"; 1488 reg = <0x0 0xbe00000 0x0 0x40000>; 1489 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1490 status = "okay"; 1491 }; 1492 1493 hsp_aon: hsp@c150000 { 1494 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 1495 reg = <0x0 0x0c150000 0x0 0x90000>; 1496 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1497 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1498 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1499 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1500 /* 1501 * Shared interrupt 0 is routed only to AON/SPE, so 1502 * we only have 4 shared interrupts for the CCPLEX. 1503 */ 1504 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 1505 #mbox-cells = <2>; 1506 }; 1507 1508 gen2_i2c: i2c@c240000 { 1509 compatible = "nvidia,tegra194-i2c"; 1510 reg = <0x0 0xc240000 0x0 0x100>; 1511 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1512 status = "disabled"; 1513 clock-frequency = <100000>; 1514 clocks = <&bpmp TEGRA234_CLK_I2C2 1515 &bpmp TEGRA234_CLK_PLLP_OUT0>; 1516 clock-names = "div-clk", "parent"; 1517 assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>; 1518 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 1519 resets = <&bpmp TEGRA234_RESET_I2C2>; 1520 reset-names = "i2c"; 1521 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 1522 dma-coherent; 1523 dmas = <&gpcdma 22>, <&gpcdma 22>; 1524 dma-names = "rx", "tx"; 1525 }; 1526 1527 gen8_i2c: i2c@c250000 { 1528 compatible = "nvidia,tegra194-i2c"; 1529 reg = <0x0 0xc250000 0x0 0x100>; 1530 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1531 status = "disabled"; 1532 clock-frequency = <400000>; 1533 clocks = <&bpmp TEGRA234_CLK_I2C8 1534 &bpmp TEGRA234_CLK_PLLP_OUT0>; 1535 clock-names = "div-clk", "parent"; 1536 assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>; 1537 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 1538 resets = <&bpmp TEGRA234_RESET_I2C8>; 1539 reset-names = "i2c"; 1540 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 1541 dma-coherent; 1542 dmas = <&gpcdma 0>, <&gpcdma 0>; 1543 dma-names = "rx", "tx"; 1544 }; 1545 1546 rtc@c2a0000 { 1547 compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc"; 1548 reg = <0x0 0x0c2a0000 0x0 0x10000>; 1549 interrupt-parent = <&pmc>; 1550 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1551 clocks = <&bpmp TEGRA234_CLK_CLK_32K>; 1552 clock-names = "rtc"; 1553 status = "disabled"; 1554 }; 1555 1556 gpio_aon: gpio@c2f0000 { 1557 compatible = "nvidia,tegra234-gpio-aon"; 1558 reg-names = "security", "gpio"; 1559 reg = <0x0 0x0c2f0000 0x0 0x1000>, 1560 <0x0 0x0c2f1000 0x0 0x1000>; 1561 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1562 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1563 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1564 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1565 #interrupt-cells = <2>; 1566 interrupt-controller; 1567 #gpio-cells = <2>; 1568 gpio-controller; 1569 }; 1570 1571 pwm4: pwm@c340000 { 1572 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 1573 reg = <0x0 0xc340000 0x0 0x10000>; 1574 clocks = <&bpmp TEGRA234_CLK_PWM4>; 1575 resets = <&bpmp TEGRA234_RESET_PWM4>; 1576 reset-names = "pwm"; 1577 status = "disabled"; 1578 #pwm-cells = <2>; 1579 }; 1580 1581 pmc: pmc@c360000 { 1582 compatible = "nvidia,tegra234-pmc"; 1583 reg = <0x0 0x0c360000 0x0 0x10000>, 1584 <0x0 0x0c370000 0x0 0x10000>, 1585 <0x0 0x0c380000 0x0 0x10000>, 1586 <0x0 0x0c390000 0x0 0x10000>, 1587 <0x0 0x0c3a0000 0x0 0x10000>; 1588 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 1589 1590 #interrupt-cells = <2>; 1591 interrupt-controller; 1592 1593 sdmmc1_1v8: sdmmc1-1v8 { 1594 pins = "sdmmc1-hv"; 1595 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1596 }; 1597 1598 sdmmc1_3v3: sdmmc1-3v3 { 1599 pins = "sdmmc1-hv"; 1600 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1601 }; 1602 1603 sdmmc3_1v8: sdmmc3-1v8 { 1604 pins = "sdmmc3-hv"; 1605 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1606 }; 1607 1608 sdmmc3_3v3: sdmmc3-3v3 { 1609 pins = "sdmmc3-hv"; 1610 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1611 }; 1612 }; 1613 1614 aon-fabric@c600000 { 1615 compatible = "nvidia,tegra234-aon-fabric"; 1616 reg = <0x0 0xc600000 0x0 0x40000>; 1617 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 1618 status = "okay"; 1619 }; 1620 1621 bpmp-fabric@d600000 { 1622 compatible = "nvidia,tegra234-bpmp-fabric"; 1623 reg = <0x0 0xd600000 0x0 0x40000>; 1624 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1625 status = "okay"; 1626 }; 1627 1628 dce-fabric@de00000 { 1629 compatible = "nvidia,tegra234-sce-fabric"; 1630 reg = <0x0 0xde00000 0x0 0x40000>; 1631 interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>; 1632 status = "okay"; 1633 }; 1634 1635 ccplex@e000000 { 1636 compatible = "nvidia,tegra234-ccplex-cluster"; 1637 reg = <0x0 0x0e000000 0x0 0x5ffff>; 1638 nvidia,bpmp = <&bpmp>; 1639 status = "okay"; 1640 }; 1641 1642 gic: interrupt-controller@f400000 { 1643 compatible = "arm,gic-v3"; 1644 reg = <0x0 0x0f400000 0x0 0x010000>, /* GICD */ 1645 <0x0 0x0f440000 0x0 0x200000>; /* GICR */ 1646 interrupt-parent = <&gic>; 1647 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1648 1649 #redistributor-regions = <1>; 1650 #interrupt-cells = <3>; 1651 interrupt-controller; 1652 }; 1653 1654 smmu_iso: iommu@10000000 { 1655 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 1656 reg = <0x0 0x10000000 0x0 0x1000000>; 1657 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1658 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1659 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1660 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1661 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1662 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1663 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1664 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1665 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1666 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1667 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1668 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1669 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1670 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1671 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1672 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1673 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1674 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1675 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1676 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1677 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1678 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1679 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1680 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1681 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1682 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1683 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1684 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1685 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1686 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1687 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1688 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1689 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1690 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1691 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1692 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1693 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1694 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1695 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1696 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1697 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1698 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1699 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1700 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1701 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1702 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1703 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1704 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1705 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1706 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1707 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1708 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1709 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1710 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1711 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1712 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1713 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1714 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1715 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1716 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1717 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1718 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1719 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1720 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1721 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1722 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1723 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1724 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1725 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1726 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1727 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1728 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1729 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1730 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1731 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1732 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1733 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1734 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1735 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1736 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1737 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1738 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1739 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1740 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1741 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1742 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1743 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1744 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1745 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1746 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1747 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1748 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1749 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1750 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1751 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1752 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1753 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1754 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1755 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1756 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1757 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1758 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1759 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1760 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1761 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1762 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1763 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1764 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1765 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1766 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1767 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1768 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1769 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1770 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1771 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1772 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1773 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1774 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1775 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1776 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1777 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1778 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1779 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1780 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1781 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1782 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1783 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1784 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1785 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1786 stream-match-mask = <0x7f80>; 1787 #global-interrupts = <1>; 1788 #iommu-cells = <1>; 1789 1790 nvidia,memory-controller = <&mc>; 1791 status = "okay"; 1792 }; 1793 1794 smmu_niso0: iommu@12000000 { 1795 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 1796 reg = <0x0 0x12000000 0x0 0x1000000>, 1797 <0x0 0x11000000 0x0 0x1000000>; 1798 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1799 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1800 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1801 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1802 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1803 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1804 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1805 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1806 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1807 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1808 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1809 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1810 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1811 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1812 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1813 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1814 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1815 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1816 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1817 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1818 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1819 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1820 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1821 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1822 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1823 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1824 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1825 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1826 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1827 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1828 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1829 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1830 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1831 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1832 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1833 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1834 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1835 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1836 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1837 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1838 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1839 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1840 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1841 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1842 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1843 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1844 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1845 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1846 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1847 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1848 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1849 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1850 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1851 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1852 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1853 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1854 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1855 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1856 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1857 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1858 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1859 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1860 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1861 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1862 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1863 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1864 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1865 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1866 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1867 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1868 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1869 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1870 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1871 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1872 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1873 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1874 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1875 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1876 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1877 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1878 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1879 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1880 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1881 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1882 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1883 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1884 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1885 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1886 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1887 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1888 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1889 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1890 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1891 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1892 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1893 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1894 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1895 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1896 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1897 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1898 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1899 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1900 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1901 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1902 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1903 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1904 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1905 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1906 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1907 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1908 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1909 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1910 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1911 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1912 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1913 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1914 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1915 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1916 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1917 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1918 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1919 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1920 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1921 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1922 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1923 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1924 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1925 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1926 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1927 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1928 stream-match-mask = <0x7f80>; 1929 #global-interrupts = <2>; 1930 #iommu-cells = <1>; 1931 1932 nvidia,memory-controller = <&mc>; 1933 status = "okay"; 1934 }; 1935 1936 cbb-fabric@13a00000 { 1937 compatible = "nvidia,tegra234-cbb-fabric"; 1938 reg = <0x0 0x13a00000 0x0 0x400000>; 1939 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 1940 status = "okay"; 1941 }; 1942 1943 host1x@13e00000 { 1944 compatible = "nvidia,tegra234-host1x"; 1945 reg = <0x0 0x13e00000 0x0 0x10000>, 1946 <0x0 0x13e10000 0x0 0x10000>, 1947 <0x0 0x13e40000 0x0 0x10000>; 1948 reg-names = "common", "hypervisor", "vm"; 1949 interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 1950 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 1951 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 1952 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 1953 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 1954 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 1955 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, 1956 <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, 1957 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1958 interrupt-names = "syncpt0", "syncpt1", "syncpt2", "syncpt3", "syncpt4", 1959 "syncpt5", "syncpt6", "syncpt7", "host1x"; 1960 clocks = <&bpmp TEGRA234_CLK_HOST1X>; 1961 clock-names = "host1x"; 1962 1963 #address-cells = <2>; 1964 #size-cells = <2>; 1965 ranges = <0x0 0x14800000 0x0 0x14800000 0x0 0x02000000>; 1966 1967 interconnects = <&mc TEGRA234_MEMORY_CLIENT_HOST1XDMAR &emc>; 1968 interconnect-names = "dma-mem"; 1969 iommus = <&smmu_niso1 TEGRA234_SID_HOST1X>; 1970 1971 /* Context isolation domains */ 1972 iommu-map = <0 &smmu_niso0 TEGRA234_SID_HOST1X_CTX0 1>, 1973 <1 &smmu_niso0 TEGRA234_SID_HOST1X_CTX1 1>, 1974 <2 &smmu_niso0 TEGRA234_SID_HOST1X_CTX2 1>, 1975 <3 &smmu_niso0 TEGRA234_SID_HOST1X_CTX3 1>, 1976 <4 &smmu_niso0 TEGRA234_SID_HOST1X_CTX4 1>, 1977 <5 &smmu_niso0 TEGRA234_SID_HOST1X_CTX5 1>, 1978 <6 &smmu_niso0 TEGRA234_SID_HOST1X_CTX6 1>, 1979 <7 &smmu_niso0 TEGRA234_SID_HOST1X_CTX7 1>, 1980 <8 &smmu_niso1 TEGRA234_SID_HOST1X_CTX0 1>, 1981 <9 &smmu_niso1 TEGRA234_SID_HOST1X_CTX1 1>, 1982 <10 &smmu_niso1 TEGRA234_SID_HOST1X_CTX2 1>, 1983 <11 &smmu_niso1 TEGRA234_SID_HOST1X_CTX3 1>, 1984 <12 &smmu_niso1 TEGRA234_SID_HOST1X_CTX4 1>, 1985 <13 &smmu_niso1 TEGRA234_SID_HOST1X_CTX5 1>, 1986 <14 &smmu_niso1 TEGRA234_SID_HOST1X_CTX6 1>, 1987 <15 &smmu_niso1 TEGRA234_SID_HOST1X_CTX7 1>; 1988 1989 vic@15340000 { 1990 compatible = "nvidia,tegra234-vic"; 1991 reg = <0x0 0x15340000 0x0 0x00040000>; 1992 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1993 clocks = <&bpmp TEGRA234_CLK_VIC>; 1994 clock-names = "vic"; 1995 resets = <&bpmp TEGRA234_RESET_VIC>; 1996 reset-names = "vic"; 1997 1998 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_VIC>; 1999 interconnects = <&mc TEGRA234_MEMORY_CLIENT_VICSRD &emc>, 2000 <&mc TEGRA234_MEMORY_CLIENT_VICSWR &emc>; 2001 interconnect-names = "dma-mem", "write"; 2002 iommus = <&smmu_niso1 TEGRA234_SID_VIC>; 2003 dma-coherent; 2004 }; 2005 2006 nvdec@15480000 { 2007 compatible = "nvidia,tegra234-nvdec"; 2008 reg = <0x0 0x15480000 0x0 0x00040000>; 2009 clocks = <&bpmp TEGRA234_CLK_NVDEC>, 2010 <&bpmp TEGRA234_CLK_FUSE>, 2011 <&bpmp TEGRA234_CLK_TSEC_PKA>; 2012 clock-names = "nvdec", "fuse", "tsec_pka"; 2013 resets = <&bpmp TEGRA234_RESET_NVDEC>; 2014 reset-names = "nvdec"; 2015 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>; 2016 interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDECSRD &emc>, 2017 <&mc TEGRA234_MEMORY_CLIENT_NVDECSWR &emc>; 2018 interconnect-names = "dma-mem", "write"; 2019 iommus = <&smmu_niso1 TEGRA234_SID_NVDEC>; 2020 dma-coherent; 2021 2022 nvidia,memory-controller = <&mc>; 2023 2024 /* 2025 * Placeholder values that firmware needs to update with the real 2026 * offsets parsed from the microcode headers. 2027 */ 2028 nvidia,bl-manifest-offset = <0>; 2029 nvidia,bl-data-offset = <0>; 2030 nvidia,bl-code-offset = <0>; 2031 nvidia,os-manifest-offset = <0>; 2032 nvidia,os-data-offset = <0>; 2033 nvidia,os-code-offset = <0>; 2034 2035 /* 2036 * Firmware needs to set this to "okay" once the above values have 2037 * been updated. 2038 */ 2039 status = "disabled"; 2040 }; 2041 }; 2042 2043 pcie@140a0000 { 2044 compatible = "nvidia,tegra234-pcie"; 2045 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CA>; 2046 reg = <0x00 0x140a0000 0x0 0x00020000>, /* appl registers (128K) */ 2047 <0x00 0x2a000000 0x0 0x00040000>, /* configuration space (256K) */ 2048 <0x00 0x2a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2049 <0x00 0x2a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2050 <0x35 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2051 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2052 2053 #address-cells = <3>; 2054 #size-cells = <2>; 2055 device_type = "pci"; 2056 num-lanes = <4>; 2057 num-viewport = <8>; 2058 linux,pci-domain = <8>; 2059 2060 clocks = <&bpmp TEGRA234_CLK_PEX2_C8_CORE>; 2061 clock-names = "core"; 2062 2063 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_8_APB>, 2064 <&bpmp TEGRA234_RESET_PEX2_CORE_8>; 2065 reset-names = "apb", "core"; 2066 2067 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2068 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2069 interrupt-names = "intr", "msi"; 2070 2071 #interrupt-cells = <1>; 2072 interrupt-map-mask = <0 0 0 0>; 2073 interrupt-map = <0 0 0 0 &gic GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 2074 2075 nvidia,bpmp = <&bpmp 8>; 2076 2077 nvidia,aspm-cmrt-us = <60>; 2078 nvidia,aspm-pwr-on-t-us = <20>; 2079 nvidia,aspm-l0s-entrance-latency-us = <3>; 2080 2081 bus-range = <0x0 0xff>; 2082 2083 ranges = <0x43000000 0x32 0x40000000 0x32 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2084 <0x02000000 0x0 0x40000000 0x35 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2085 <0x01000000 0x0 0x2a100000 0x00 0x2a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2086 2087 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE8AR &emc>, 2088 <&mc TEGRA234_MEMORY_CLIENT_PCIE8AW &emc>; 2089 interconnect-names = "dma-mem", "write"; 2090 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE8 0x1000>; 2091 iommu-map-mask = <0x0>; 2092 dma-coherent; 2093 2094 status = "disabled"; 2095 }; 2096 2097 pcie@140c0000 { 2098 compatible = "nvidia,tegra234-pcie"; 2099 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CB>; 2100 reg = <0x00 0x140c0000 0x0 0x00020000>, /* appl registers (128K) */ 2101 <0x00 0x2c000000 0x0 0x00040000>, /* configuration space (256K) */ 2102 <0x00 0x2c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2103 <0x00 0x2c080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2104 <0x38 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2105 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2106 2107 #address-cells = <3>; 2108 #size-cells = <2>; 2109 device_type = "pci"; 2110 num-lanes = <4>; 2111 num-viewport = <8>; 2112 linux,pci-domain = <9>; 2113 2114 clocks = <&bpmp TEGRA234_CLK_PEX2_C9_CORE>; 2115 clock-names = "core"; 2116 2117 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_9_APB>, 2118 <&bpmp TEGRA234_RESET_PEX2_CORE_9>; 2119 reset-names = "apb", "core"; 2120 2121 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2122 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2123 interrupt-names = "intr", "msi"; 2124 2125 #interrupt-cells = <1>; 2126 interrupt-map-mask = <0 0 0 0>; 2127 interrupt-map = <0 0 0 0 &gic GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2128 2129 nvidia,bpmp = <&bpmp 9>; 2130 2131 nvidia,aspm-cmrt-us = <60>; 2132 nvidia,aspm-pwr-on-t-us = <20>; 2133 nvidia,aspm-l0s-entrance-latency-us = <3>; 2134 2135 bus-range = <0x0 0xff>; 2136 2137 ranges = <0x43000000 0x35 0x40000000 0x35 0x40000000 0x2 0xc0000000>, /* prefetchable memory (11264 MB) */ 2138 <0x02000000 0x0 0x40000000 0x38 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2139 <0x01000000 0x0 0x2c100000 0x00 0x2c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2140 2141 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE9AR &emc>, 2142 <&mc TEGRA234_MEMORY_CLIENT_PCIE9AW &emc>; 2143 interconnect-names = "dma-mem", "write"; 2144 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE9 0x1000>; 2145 iommu-map-mask = <0x0>; 2146 dma-coherent; 2147 2148 status = "disabled"; 2149 }; 2150 2151 pcie@140e0000 { 2152 compatible = "nvidia,tegra234-pcie"; 2153 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>; 2154 reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */ 2155 <0x00 0x2e000000 0x0 0x00040000>, /* configuration space (256K) */ 2156 <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2157 <0x00 0x2e080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2158 <0x3b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2159 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2160 2161 #address-cells = <3>; 2162 #size-cells = <2>; 2163 device_type = "pci"; 2164 num-lanes = <4>; 2165 num-viewport = <8>; 2166 linux,pci-domain = <10>; 2167 2168 clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>; 2169 clock-names = "core"; 2170 2171 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>, 2172 <&bpmp TEGRA234_RESET_PEX2_CORE_10>; 2173 reset-names = "apb", "core"; 2174 2175 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2176 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2177 interrupt-names = "intr", "msi"; 2178 2179 #interrupt-cells = <1>; 2180 interrupt-map-mask = <0 0 0 0>; 2181 interrupt-map = <0 0 0 0 &gic GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 2182 2183 nvidia,bpmp = <&bpmp 10>; 2184 2185 nvidia,aspm-cmrt-us = <60>; 2186 nvidia,aspm-pwr-on-t-us = <20>; 2187 nvidia,aspm-l0s-entrance-latency-us = <3>; 2188 2189 bus-range = <0x0 0xff>; 2190 2191 ranges = <0x43000000 0x38 0x40000000 0x38 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2192 <0x02000000 0x0 0x40000000 0x3b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2193 <0x01000000 0x0 0x2e100000 0x00 0x2e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2194 2195 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, 2196 <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; 2197 interconnect-names = "dma-mem", "write"; 2198 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>; 2199 iommu-map-mask = <0x0>; 2200 dma-coherent; 2201 2202 status = "disabled"; 2203 }; 2204 2205 pcie-ep@140e0000 { 2206 compatible = "nvidia,tegra234-pcie-ep"; 2207 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>; 2208 reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */ 2209 <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2210 <0x00 0x2e080000 0x0 0x00040000>, /* DBI space (256K) */ 2211 <0x38 0x40000000 0x3 0x00000000>; /* Address Space (12G) */ 2212 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2213 2214 num-lanes = <4>; 2215 2216 clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>; 2217 clock-names = "core"; 2218 2219 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>, 2220 <&bpmp TEGRA234_RESET_PEX2_CORE_10>; 2221 reset-names = "apb", "core"; 2222 2223 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2224 interrupt-names = "intr"; 2225 2226 nvidia,bpmp = <&bpmp 10>; 2227 2228 nvidia,enable-ext-refclk; 2229 nvidia,aspm-cmrt-us = <60>; 2230 nvidia,aspm-pwr-on-t-us = <20>; 2231 nvidia,aspm-l0s-entrance-latency-us = <3>; 2232 2233 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, 2234 <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; 2235 interconnect-names = "dma-mem", "write"; 2236 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>; 2237 iommu-map-mask = <0x0>; 2238 dma-coherent; 2239 2240 status = "disabled"; 2241 }; 2242 2243 pcie@14100000 { 2244 compatible = "nvidia,tegra234-pcie"; 2245 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 2246 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 2247 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 2248 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2249 <0x00 0x30080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2250 <0x20 0xb0000000 0x0 0x10000000>; /* ECAM (256MB) */ 2251 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2252 2253 #address-cells = <3>; 2254 #size-cells = <2>; 2255 device_type = "pci"; 2256 num-lanes = <1>; 2257 num-viewport = <8>; 2258 linux,pci-domain = <1>; 2259 2260 clocks = <&bpmp TEGRA234_CLK_PEX0_C1_CORE>; 2261 clock-names = "core"; 2262 2263 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_1_APB>, 2264 <&bpmp TEGRA234_RESET_PEX0_CORE_1>; 2265 reset-names = "apb", "core"; 2266 2267 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2268 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2269 interrupt-names = "intr", "msi"; 2270 2271 #interrupt-cells = <1>; 2272 interrupt-map-mask = <0 0 0 0>; 2273 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 2274 2275 nvidia,bpmp = <&bpmp 1>; 2276 2277 nvidia,aspm-cmrt-us = <60>; 2278 nvidia,aspm-pwr-on-t-us = <20>; 2279 nvidia,aspm-l0s-entrance-latency-us = <3>; 2280 2281 bus-range = <0x0 0xff>; 2282 2283 ranges = <0x43000000 0x20 0x80000000 0x20 0x80000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 2284 <0x02000000 0x0 0x40000000 0x20 0xa8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2285 <0x01000000 0x0 0x30100000 0x00 0x30100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2286 2287 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE1R &emc>, 2288 <&mc TEGRA234_MEMORY_CLIENT_PCIE1W &emc>; 2289 interconnect-names = "dma-mem", "write"; 2290 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE1 0x1000>; 2291 iommu-map-mask = <0x0>; 2292 dma-coherent; 2293 2294 status = "disabled"; 2295 }; 2296 2297 pcie@14120000 { 2298 compatible = "nvidia,tegra234-pcie"; 2299 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 2300 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 2301 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 2302 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2303 <0x00 0x32080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2304 <0x20 0xf0000000 0x0 0x10000000>; /* ECAM (256MB) */ 2305 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2306 2307 #address-cells = <3>; 2308 #size-cells = <2>; 2309 device_type = "pci"; 2310 num-lanes = <1>; 2311 num-viewport = <8>; 2312 linux,pci-domain = <2>; 2313 2314 clocks = <&bpmp TEGRA234_CLK_PEX0_C2_CORE>; 2315 clock-names = "core"; 2316 2317 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_2_APB>, 2318 <&bpmp TEGRA234_RESET_PEX0_CORE_2>; 2319 reset-names = "apb", "core"; 2320 2321 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2322 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2323 interrupt-names = "intr", "msi"; 2324 2325 #interrupt-cells = <1>; 2326 interrupt-map-mask = <0 0 0 0>; 2327 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 2328 2329 nvidia,bpmp = <&bpmp 2>; 2330 2331 nvidia,aspm-cmrt-us = <60>; 2332 nvidia,aspm-pwr-on-t-us = <20>; 2333 nvidia,aspm-l0s-entrance-latency-us = <3>; 2334 2335 bus-range = <0x0 0xff>; 2336 2337 ranges = <0x43000000 0x20 0xc0000000 0x20 0xc0000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 2338 <0x02000000 0x0 0x40000000 0x20 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2339 <0x01000000 0x0 0x32100000 0x00 0x32100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2340 2341 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE2AR &emc>, 2342 <&mc TEGRA234_MEMORY_CLIENT_PCIE2AW &emc>; 2343 interconnect-names = "dma-mem", "write"; 2344 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE2 0x1000>; 2345 iommu-map-mask = <0x0>; 2346 dma-coherent; 2347 2348 status = "disabled"; 2349 }; 2350 2351 pcie@14140000 { 2352 compatible = "nvidia,tegra234-pcie"; 2353 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 2354 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 2355 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 2356 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2357 <0x00 0x34080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2358 <0x21 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2359 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2360 2361 #address-cells = <3>; 2362 #size-cells = <2>; 2363 device_type = "pci"; 2364 num-lanes = <1>; 2365 num-viewport = <8>; 2366 linux,pci-domain = <3>; 2367 2368 clocks = <&bpmp TEGRA234_CLK_PEX0_C3_CORE>; 2369 clock-names = "core"; 2370 2371 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_3_APB>, 2372 <&bpmp TEGRA234_RESET_PEX0_CORE_3>; 2373 reset-names = "apb", "core"; 2374 2375 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2376 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2377 interrupt-names = "intr", "msi"; 2378 2379 #interrupt-cells = <1>; 2380 interrupt-map-mask = <0 0 0 0>; 2381 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 2382 2383 nvidia,bpmp = <&bpmp 3>; 2384 2385 nvidia,aspm-cmrt-us = <60>; 2386 nvidia,aspm-pwr-on-t-us = <20>; 2387 nvidia,aspm-l0s-entrance-latency-us = <3>; 2388 2389 bus-range = <0x0 0xff>; 2390 2391 ranges = <0x43000000 0x21 0x00000000 0x21 0x00000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 2392 <0x02000000 0x0 0x40000000 0x21 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2393 <0x01000000 0x0 0x34100000 0x00 0x34100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2394 2395 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE3R &emc>, 2396 <&mc TEGRA234_MEMORY_CLIENT_PCIE3W &emc>; 2397 interconnect-names = "dma-mem", "write"; 2398 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE3 0x1000>; 2399 iommu-map-mask = <0x0>; 2400 dma-coherent; 2401 2402 status = "disabled"; 2403 }; 2404 2405 pcie@14160000 { 2406 compatible = "nvidia,tegra234-pcie"; 2407 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>; 2408 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2409 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2410 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2411 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2412 <0x24 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2413 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2414 2415 #address-cells = <3>; 2416 #size-cells = <2>; 2417 device_type = "pci"; 2418 num-lanes = <4>; 2419 num-viewport = <8>; 2420 linux,pci-domain = <4>; 2421 2422 clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>; 2423 clock-names = "core"; 2424 2425 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>, 2426 <&bpmp TEGRA234_RESET_PEX0_CORE_4>; 2427 reset-names = "apb", "core"; 2428 2429 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2430 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2431 interrupt-names = "intr", "msi"; 2432 2433 #interrupt-cells = <1>; 2434 interrupt-map-mask = <0 0 0 0>; 2435 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 2436 2437 nvidia,bpmp = <&bpmp 4>; 2438 2439 nvidia,aspm-cmrt-us = <60>; 2440 nvidia,aspm-pwr-on-t-us = <20>; 2441 nvidia,aspm-l0s-entrance-latency-us = <3>; 2442 2443 bus-range = <0x0 0xff>; 2444 2445 ranges = <0x43000000 0x21 0x40000000 0x21 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2446 <0x02000000 0x0 0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2447 <0x01000000 0x0 0x36100000 0x00 0x36100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2448 2449 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE4R &emc>, 2450 <&mc TEGRA234_MEMORY_CLIENT_PCIE4W &emc>; 2451 interconnect-names = "dma-mem", "write"; 2452 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE4 0x1000>; 2453 iommu-map-mask = <0x0>; 2454 dma-coherent; 2455 2456 status = "disabled"; 2457 }; 2458 2459 pcie@14180000 { 2460 compatible = "nvidia,tegra234-pcie"; 2461 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BA>; 2462 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2463 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2464 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2465 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2466 <0x27 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2467 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2468 2469 #address-cells = <3>; 2470 #size-cells = <2>; 2471 device_type = "pci"; 2472 num-lanes = <4>; 2473 num-viewport = <8>; 2474 linux,pci-domain = <0>; 2475 2476 clocks = <&bpmp TEGRA234_CLK_PEX0_C0_CORE>; 2477 clock-names = "core"; 2478 2479 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_0_APB>, 2480 <&bpmp TEGRA234_RESET_PEX0_CORE_0>; 2481 reset-names = "apb", "core"; 2482 2483 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2484 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2485 interrupt-names = "intr", "msi"; 2486 2487 #interrupt-cells = <1>; 2488 interrupt-map-mask = <0 0 0 0>; 2489 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 2490 2491 nvidia,bpmp = <&bpmp 0>; 2492 2493 nvidia,aspm-cmrt-us = <60>; 2494 nvidia,aspm-pwr-on-t-us = <20>; 2495 nvidia,aspm-l0s-entrance-latency-us = <3>; 2496 2497 bus-range = <0x0 0xff>; 2498 2499 ranges = <0x43000000 0x24 0x40000000 0x24 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2500 <0x02000000 0x0 0x40000000 0x27 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2501 <0x01000000 0x0 0x38100000 0x00 0x38100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2502 2503 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE0R &emc>, 2504 <&mc TEGRA234_MEMORY_CLIENT_PCIE0W &emc>; 2505 interconnect-names = "dma-mem", "write"; 2506 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE0 0x1000>; 2507 iommu-map-mask = <0x0>; 2508 dma-coherent; 2509 2510 status = "disabled"; 2511 }; 2512 2513 pcie@141a0000 { 2514 compatible = "nvidia,tegra234-pcie"; 2515 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>; 2516 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2517 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2518 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2519 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2520 <0x2b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2521 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2522 2523 #address-cells = <3>; 2524 #size-cells = <2>; 2525 device_type = "pci"; 2526 num-lanes = <8>; 2527 num-viewport = <8>; 2528 linux,pci-domain = <5>; 2529 2530 clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>; 2531 clock-names = "core"; 2532 2533 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>, 2534 <&bpmp TEGRA234_RESET_PEX1_CORE_5>; 2535 reset-names = "apb", "core"; 2536 2537 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2538 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2539 interrupt-names = "intr", "msi"; 2540 2541 #interrupt-cells = <1>; 2542 interrupt-map-mask = <0 0 0 0>; 2543 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 2544 2545 nvidia,bpmp = <&bpmp 5>; 2546 2547 nvidia,aspm-cmrt-us = <60>; 2548 nvidia,aspm-pwr-on-t-us = <20>; 2549 nvidia,aspm-l0s-entrance-latency-us = <3>; 2550 2551 bus-range = <0x0 0xff>; 2552 2553 ranges = <0x43000000 0x28 0x00000000 0x28 0x00000000 0x3 0x28000000>, /* prefetchable memory (12928 MB) */ 2554 <0x02000000 0x0 0x40000000 0x2b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2555 <0x01000000 0x0 0x3a100000 0x00 0x3a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2556 2557 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, 2558 <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; 2559 interconnect-names = "dma-mem", "write"; 2560 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>; 2561 iommu-map-mask = <0x0>; 2562 dma-coherent; 2563 2564 status = "disabled"; 2565 }; 2566 2567 pcie-ep@141a0000 { 2568 compatible = "nvidia,tegra234-pcie-ep"; 2569 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>; 2570 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2571 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2572 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2573 <0x27 0x40000000 0x4 0x00000000>; /* Address Space (16G) */ 2574 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2575 2576 num-lanes = <8>; 2577 2578 clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>; 2579 clock-names = "core"; 2580 2581 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>, 2582 <&bpmp TEGRA234_RESET_PEX1_CORE_5>; 2583 reset-names = "apb", "core"; 2584 2585 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2586 interrupt-names = "intr"; 2587 2588 nvidia,bpmp = <&bpmp 5>; 2589 2590 nvidia,enable-ext-refclk; 2591 nvidia,aspm-cmrt-us = <60>; 2592 nvidia,aspm-pwr-on-t-us = <20>; 2593 nvidia,aspm-l0s-entrance-latency-us = <3>; 2594 2595 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, 2596 <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; 2597 interconnect-names = "dma-mem", "write"; 2598 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>; 2599 iommu-map-mask = <0x0>; 2600 dma-coherent; 2601 2602 status = "disabled"; 2603 }; 2604 2605 pcie@141c0000 { 2606 compatible = "nvidia,tegra234-pcie"; 2607 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>; 2608 reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */ 2609 <0x00 0x3c000000 0x0 0x00040000>, /* configuration space (256K) */ 2610 <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2611 <0x00 0x3c080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2612 <0x2e 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2613 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2614 2615 #address-cells = <3>; 2616 #size-cells = <2>; 2617 device_type = "pci"; 2618 num-lanes = <4>; 2619 num-viewport = <8>; 2620 linux,pci-domain = <6>; 2621 2622 clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>; 2623 clock-names = "core"; 2624 2625 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>, 2626 <&bpmp TEGRA234_RESET_PEX1_CORE_6>; 2627 reset-names = "apb", "core"; 2628 2629 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2630 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2631 interrupt-names = "intr", "msi"; 2632 2633 #interrupt-cells = <1>; 2634 interrupt-map-mask = <0 0 0 0>; 2635 interrupt-map = <0 0 0 0 &gic GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 2636 2637 nvidia,bpmp = <&bpmp 6>; 2638 2639 nvidia,aspm-cmrt-us = <60>; 2640 nvidia,aspm-pwr-on-t-us = <20>; 2641 nvidia,aspm-l0s-entrance-latency-us = <3>; 2642 2643 bus-range = <0x0 0xff>; 2644 2645 ranges = <0x43000000 0x2b 0x40000000 0x2b 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2646 <0x02000000 0x0 0x40000000 0x2e 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2647 <0x01000000 0x0 0x3c100000 0x00 0x3c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2648 2649 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, 2650 <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; 2651 interconnect-names = "dma-mem", "write"; 2652 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>; 2653 iommu-map-mask = <0x0>; 2654 dma-coherent; 2655 2656 status = "disabled"; 2657 }; 2658 2659 pcie-ep@141c0000 { 2660 compatible = "nvidia,tegra234-pcie-ep"; 2661 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>; 2662 reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */ 2663 <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2664 <0x00 0x3c080000 0x0 0x00040000>, /* DBI space (256K) */ 2665 <0x2b 0x40000000 0x3 0x00000000>; /* Address Space (12G) */ 2666 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2667 2668 num-lanes = <4>; 2669 2670 clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>; 2671 clock-names = "core"; 2672 2673 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>, 2674 <&bpmp TEGRA234_RESET_PEX1_CORE_6>; 2675 reset-names = "apb", "core"; 2676 2677 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2678 interrupt-names = "intr"; 2679 2680 nvidia,bpmp = <&bpmp 6>; 2681 2682 nvidia,enable-ext-refclk; 2683 nvidia,aspm-cmrt-us = <60>; 2684 nvidia,aspm-pwr-on-t-us = <20>; 2685 nvidia,aspm-l0s-entrance-latency-us = <3>; 2686 2687 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, 2688 <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; 2689 interconnect-names = "dma-mem", "write"; 2690 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>; 2691 iommu-map-mask = <0x0>; 2692 dma-coherent; 2693 2694 status = "disabled"; 2695 }; 2696 2697 pcie@141e0000 { 2698 compatible = "nvidia,tegra234-pcie"; 2699 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>; 2700 reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */ 2701 <0x00 0x3e000000 0x0 0x00040000>, /* configuration space (256K) */ 2702 <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2703 <0x00 0x3e080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2704 <0x32 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2705 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2706 2707 #address-cells = <3>; 2708 #size-cells = <2>; 2709 device_type = "pci"; 2710 num-lanes = <8>; 2711 num-viewport = <8>; 2712 linux,pci-domain = <7>; 2713 2714 clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>; 2715 clock-names = "core"; 2716 2717 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>, 2718 <&bpmp TEGRA234_RESET_PEX2_CORE_7>; 2719 reset-names = "apb", "core"; 2720 2721 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2722 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2723 interrupt-names = "intr", "msi"; 2724 2725 #interrupt-cells = <1>; 2726 interrupt-map-mask = <0 0 0 0>; 2727 interrupt-map = <0 0 0 0 &gic GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 2728 2729 nvidia,bpmp = <&bpmp 7>; 2730 2731 nvidia,aspm-cmrt-us = <60>; 2732 nvidia,aspm-pwr-on-t-us = <20>; 2733 nvidia,aspm-l0s-entrance-latency-us = <3>; 2734 2735 bus-range = <0x0 0xff>; 2736 2737 ranges = <0x43000000 0x30 0x00000000 0x30 0x00000000 0x2 0x28000000>, /* prefetchable memory (8832 MB) */ 2738 <0x02000000 0x0 0x40000000 0x32 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2739 <0x01000000 0x0 0x3e100000 0x00 0x3e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2740 2741 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>, 2742 <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>; 2743 interconnect-names = "dma-mem", "write"; 2744 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>; 2745 iommu-map-mask = <0x0>; 2746 dma-coherent; 2747 2748 status = "disabled"; 2749 }; 2750 2751 pcie-ep@141e0000 { 2752 compatible = "nvidia,tegra234-pcie-ep"; 2753 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>; 2754 reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */ 2755 <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2756 <0x00 0x3e080000 0x0 0x00040000>, /* DBI space (256K) */ 2757 <0x2e 0x40000000 0x4 0x00000000>; /* Address Space (16G) */ 2758 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2759 2760 num-lanes = <8>; 2761 2762 clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>; 2763 clock-names = "core"; 2764 2765 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>, 2766 <&bpmp TEGRA234_RESET_PEX2_CORE_7>; 2767 reset-names = "apb", "core"; 2768 2769 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2770 interrupt-names = "intr"; 2771 2772 nvidia,bpmp = <&bpmp 7>; 2773 2774 nvidia,enable-ext-refclk; 2775 nvidia,aspm-cmrt-us = <60>; 2776 nvidia,aspm-pwr-on-t-us = <20>; 2777 nvidia,aspm-l0s-entrance-latency-us = <3>; 2778 2779 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>, 2780 <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>; 2781 interconnect-names = "dma-mem", "write"; 2782 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>; 2783 iommu-map-mask = <0x0>; 2784 dma-coherent; 2785 2786 status = "disabled"; 2787 }; 2788 }; 2789 2790 sram@40000000 { 2791 compatible = "nvidia,tegra234-sysram", "mmio-sram"; 2792 reg = <0x0 0x40000000 0x0 0x80000>; 2793 2794 #address-cells = <1>; 2795 #size-cells = <1>; 2796 ranges = <0x0 0x0 0x40000000 0x80000>; 2797 2798 no-memory-wc; 2799 2800 cpu_bpmp_tx: sram@70000 { 2801 reg = <0x70000 0x1000>; 2802 label = "cpu-bpmp-tx"; 2803 pool; 2804 }; 2805 2806 cpu_bpmp_rx: sram@71000 { 2807 reg = <0x71000 0x1000>; 2808 label = "cpu-bpmp-rx"; 2809 pool; 2810 }; 2811 }; 2812 2813 bpmp: bpmp { 2814 compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp"; 2815 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 2816 TEGRA_HSP_DB_MASTER_BPMP>; 2817 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 2818 #clock-cells = <1>; 2819 #reset-cells = <1>; 2820 #power-domain-cells = <1>; 2821 interconnects = <&mc TEGRA234_MEMORY_CLIENT_BPMPR &emc>, 2822 <&mc TEGRA234_MEMORY_CLIENT_BPMPW &emc>, 2823 <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAR &emc>, 2824 <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAW &emc>; 2825 interconnect-names = "read", "write", "dma-mem", "dma-write"; 2826 iommus = <&smmu_niso1 TEGRA234_SID_BPMP>; 2827 2828 bpmp_i2c: i2c { 2829 compatible = "nvidia,tegra186-bpmp-i2c"; 2830 nvidia,bpmp-bus-id = <5>; 2831 #address-cells = <1>; 2832 #size-cells = <0>; 2833 }; 2834 }; 2835 2836 cpus { 2837 #address-cells = <1>; 2838 #size-cells = <0>; 2839 2840 cpu0_0: cpu@0 { 2841 compatible = "arm,cortex-a78"; 2842 device_type = "cpu"; 2843 reg = <0x00000>; 2844 2845 enable-method = "psci"; 2846 2847 i-cache-size = <65536>; 2848 i-cache-line-size = <64>; 2849 i-cache-sets = <256>; 2850 d-cache-size = <65536>; 2851 d-cache-line-size = <64>; 2852 d-cache-sets = <256>; 2853 next-level-cache = <&l2c0_0>; 2854 }; 2855 2856 cpu0_1: cpu@100 { 2857 compatible = "arm,cortex-a78"; 2858 device_type = "cpu"; 2859 reg = <0x00100>; 2860 2861 enable-method = "psci"; 2862 2863 i-cache-size = <65536>; 2864 i-cache-line-size = <64>; 2865 i-cache-sets = <256>; 2866 d-cache-size = <65536>; 2867 d-cache-line-size = <64>; 2868 d-cache-sets = <256>; 2869 next-level-cache = <&l2c0_1>; 2870 }; 2871 2872 cpu0_2: cpu@200 { 2873 compatible = "arm,cortex-a78"; 2874 device_type = "cpu"; 2875 reg = <0x00200>; 2876 2877 enable-method = "psci"; 2878 2879 i-cache-size = <65536>; 2880 i-cache-line-size = <64>; 2881 i-cache-sets = <256>; 2882 d-cache-size = <65536>; 2883 d-cache-line-size = <64>; 2884 d-cache-sets = <256>; 2885 next-level-cache = <&l2c0_2>; 2886 }; 2887 2888 cpu0_3: cpu@300 { 2889 compatible = "arm,cortex-a78"; 2890 device_type = "cpu"; 2891 reg = <0x00300>; 2892 2893 enable-method = "psci"; 2894 2895 i-cache-size = <65536>; 2896 i-cache-line-size = <64>; 2897 i-cache-sets = <256>; 2898 d-cache-size = <65536>; 2899 d-cache-line-size = <64>; 2900 d-cache-sets = <256>; 2901 next-level-cache = <&l2c0_3>; 2902 }; 2903 2904 cpu1_0: cpu@10000 { 2905 compatible = "arm,cortex-a78"; 2906 device_type = "cpu"; 2907 reg = <0x10000>; 2908 2909 enable-method = "psci"; 2910 2911 i-cache-size = <65536>; 2912 i-cache-line-size = <64>; 2913 i-cache-sets = <256>; 2914 d-cache-size = <65536>; 2915 d-cache-line-size = <64>; 2916 d-cache-sets = <256>; 2917 next-level-cache = <&l2c1_0>; 2918 }; 2919 2920 cpu1_1: cpu@10100 { 2921 compatible = "arm,cortex-a78"; 2922 device_type = "cpu"; 2923 reg = <0x10100>; 2924 2925 enable-method = "psci"; 2926 2927 i-cache-size = <65536>; 2928 i-cache-line-size = <64>; 2929 i-cache-sets = <256>; 2930 d-cache-size = <65536>; 2931 d-cache-line-size = <64>; 2932 d-cache-sets = <256>; 2933 next-level-cache = <&l2c1_1>; 2934 }; 2935 2936 cpu1_2: cpu@10200 { 2937 compatible = "arm,cortex-a78"; 2938 device_type = "cpu"; 2939 reg = <0x10200>; 2940 2941 enable-method = "psci"; 2942 2943 i-cache-size = <65536>; 2944 i-cache-line-size = <64>; 2945 i-cache-sets = <256>; 2946 d-cache-size = <65536>; 2947 d-cache-line-size = <64>; 2948 d-cache-sets = <256>; 2949 next-level-cache = <&l2c1_2>; 2950 }; 2951 2952 cpu1_3: cpu@10300 { 2953 compatible = "arm,cortex-a78"; 2954 device_type = "cpu"; 2955 reg = <0x10300>; 2956 2957 enable-method = "psci"; 2958 2959 i-cache-size = <65536>; 2960 i-cache-line-size = <64>; 2961 i-cache-sets = <256>; 2962 d-cache-size = <65536>; 2963 d-cache-line-size = <64>; 2964 d-cache-sets = <256>; 2965 next-level-cache = <&l2c1_3>; 2966 }; 2967 2968 cpu2_0: cpu@20000 { 2969 compatible = "arm,cortex-a78"; 2970 device_type = "cpu"; 2971 reg = <0x20000>; 2972 2973 enable-method = "psci"; 2974 2975 i-cache-size = <65536>; 2976 i-cache-line-size = <64>; 2977 i-cache-sets = <256>; 2978 d-cache-size = <65536>; 2979 d-cache-line-size = <64>; 2980 d-cache-sets = <256>; 2981 next-level-cache = <&l2c2_0>; 2982 }; 2983 2984 cpu2_1: cpu@20100 { 2985 compatible = "arm,cortex-a78"; 2986 device_type = "cpu"; 2987 reg = <0x20100>; 2988 2989 enable-method = "psci"; 2990 2991 i-cache-size = <65536>; 2992 i-cache-line-size = <64>; 2993 i-cache-sets = <256>; 2994 d-cache-size = <65536>; 2995 d-cache-line-size = <64>; 2996 d-cache-sets = <256>; 2997 next-level-cache = <&l2c2_1>; 2998 }; 2999 3000 cpu2_2: cpu@20200 { 3001 compatible = "arm,cortex-a78"; 3002 device_type = "cpu"; 3003 reg = <0x20200>; 3004 3005 enable-method = "psci"; 3006 3007 i-cache-size = <65536>; 3008 i-cache-line-size = <64>; 3009 i-cache-sets = <256>; 3010 d-cache-size = <65536>; 3011 d-cache-line-size = <64>; 3012 d-cache-sets = <256>; 3013 next-level-cache = <&l2c2_2>; 3014 }; 3015 3016 cpu2_3: cpu@20300 { 3017 compatible = "arm,cortex-a78"; 3018 device_type = "cpu"; 3019 reg = <0x20300>; 3020 3021 enable-method = "psci"; 3022 3023 i-cache-size = <65536>; 3024 i-cache-line-size = <64>; 3025 i-cache-sets = <256>; 3026 d-cache-size = <65536>; 3027 d-cache-line-size = <64>; 3028 d-cache-sets = <256>; 3029 next-level-cache = <&l2c2_3>; 3030 }; 3031 3032 cpu-map { 3033 cluster0 { 3034 core0 { 3035 cpu = <&cpu0_0>; 3036 }; 3037 3038 core1 { 3039 cpu = <&cpu0_1>; 3040 }; 3041 3042 core2 { 3043 cpu = <&cpu0_2>; 3044 }; 3045 3046 core3 { 3047 cpu = <&cpu0_3>; 3048 }; 3049 }; 3050 3051 cluster1 { 3052 core0 { 3053 cpu = <&cpu1_0>; 3054 }; 3055 3056 core1 { 3057 cpu = <&cpu1_1>; 3058 }; 3059 3060 core2 { 3061 cpu = <&cpu1_2>; 3062 }; 3063 3064 core3 { 3065 cpu = <&cpu1_3>; 3066 }; 3067 }; 3068 3069 cluster2 { 3070 core0 { 3071 cpu = <&cpu2_0>; 3072 }; 3073 3074 core1 { 3075 cpu = <&cpu2_1>; 3076 }; 3077 3078 core2 { 3079 cpu = <&cpu2_2>; 3080 }; 3081 3082 core3 { 3083 cpu = <&cpu2_3>; 3084 }; 3085 }; 3086 }; 3087 3088 l2c0_0: l2-cache00 { 3089 compatible = "cache"; 3090 cache-size = <262144>; 3091 cache-line-size = <64>; 3092 cache-sets = <512>; 3093 cache-unified; 3094 cache-level = <2>; 3095 next-level-cache = <&l3c0>; 3096 }; 3097 3098 l2c0_1: l2-cache01 { 3099 compatible = "cache"; 3100 cache-size = <262144>; 3101 cache-line-size = <64>; 3102 cache-sets = <512>; 3103 cache-unified; 3104 cache-level = <2>; 3105 next-level-cache = <&l3c0>; 3106 }; 3107 3108 l2c0_2: l2-cache02 { 3109 compatible = "cache"; 3110 cache-size = <262144>; 3111 cache-line-size = <64>; 3112 cache-sets = <512>; 3113 cache-unified; 3114 cache-level = <2>; 3115 next-level-cache = <&l3c0>; 3116 }; 3117 3118 l2c0_3: l2-cache03 { 3119 compatible = "cache"; 3120 cache-size = <262144>; 3121 cache-line-size = <64>; 3122 cache-sets = <512>; 3123 cache-unified; 3124 cache-level = <2>; 3125 next-level-cache = <&l3c0>; 3126 }; 3127 3128 l2c1_0: l2-cache10 { 3129 compatible = "cache"; 3130 cache-size = <262144>; 3131 cache-line-size = <64>; 3132 cache-sets = <512>; 3133 cache-unified; 3134 cache-level = <2>; 3135 next-level-cache = <&l3c1>; 3136 }; 3137 3138 l2c1_1: l2-cache11 { 3139 compatible = "cache"; 3140 cache-size = <262144>; 3141 cache-line-size = <64>; 3142 cache-sets = <512>; 3143 cache-unified; 3144 cache-level = <2>; 3145 next-level-cache = <&l3c1>; 3146 }; 3147 3148 l2c1_2: l2-cache12 { 3149 compatible = "cache"; 3150 cache-size = <262144>; 3151 cache-line-size = <64>; 3152 cache-sets = <512>; 3153 cache-unified; 3154 cache-level = <2>; 3155 next-level-cache = <&l3c1>; 3156 }; 3157 3158 l2c1_3: l2-cache13 { 3159 compatible = "cache"; 3160 cache-size = <262144>; 3161 cache-line-size = <64>; 3162 cache-sets = <512>; 3163 cache-unified; 3164 cache-level = <2>; 3165 next-level-cache = <&l3c1>; 3166 }; 3167 3168 l2c2_0: l2-cache20 { 3169 compatible = "cache"; 3170 cache-size = <262144>; 3171 cache-line-size = <64>; 3172 cache-sets = <512>; 3173 cache-unified; 3174 cache-level = <2>; 3175 next-level-cache = <&l3c2>; 3176 }; 3177 3178 l2c2_1: l2-cache21 { 3179 compatible = "cache"; 3180 cache-size = <262144>; 3181 cache-line-size = <64>; 3182 cache-sets = <512>; 3183 cache-unified; 3184 cache-level = <2>; 3185 next-level-cache = <&l3c2>; 3186 }; 3187 3188 l2c2_2: l2-cache22 { 3189 compatible = "cache"; 3190 cache-size = <262144>; 3191 cache-line-size = <64>; 3192 cache-sets = <512>; 3193 cache-unified; 3194 cache-level = <2>; 3195 next-level-cache = <&l3c2>; 3196 }; 3197 3198 l2c2_3: l2-cache23 { 3199 compatible = "cache"; 3200 cache-size = <262144>; 3201 cache-line-size = <64>; 3202 cache-sets = <512>; 3203 cache-unified; 3204 cache-level = <2>; 3205 next-level-cache = <&l3c2>; 3206 }; 3207 3208 l3c0: l3-cache0 { 3209 compatible = "cache"; 3210 cache-unified; 3211 cache-size = <2097152>; 3212 cache-line-size = <64>; 3213 cache-sets = <2048>; 3214 cache-level = <3>; 3215 }; 3216 3217 l3c1: l3-cache1 { 3218 compatible = "cache"; 3219 cache-unified; 3220 cache-size = <2097152>; 3221 cache-line-size = <64>; 3222 cache-sets = <2048>; 3223 cache-level = <3>; 3224 }; 3225 3226 l3c2: l3-cache2 { 3227 compatible = "cache"; 3228 cache-unified; 3229 cache-size = <2097152>; 3230 cache-line-size = <64>; 3231 cache-sets = <2048>; 3232 cache-level = <3>; 3233 }; 3234 }; 3235 3236 pmu { 3237 compatible = "arm,cortex-a78-pmu"; 3238 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 3239 status = "okay"; 3240 }; 3241 3242 psci { 3243 compatible = "arm,psci-1.0"; 3244 status = "okay"; 3245 method = "smc"; 3246 }; 3247 3248 tcu: serial { 3249 compatible = "nvidia,tegra234-tcu", "nvidia,tegra194-tcu"; 3250 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 3251 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 3252 mbox-names = "rx", "tx"; 3253 status = "disabled"; 3254 }; 3255 3256 sound { 3257 status = "disabled"; 3258 3259 clocks = <&bpmp TEGRA234_CLK_PLLA>, 3260 <&bpmp TEGRA234_CLK_PLLA_OUT0>; 3261 clock-names = "pll_a", "plla_out0"; 3262 assigned-clocks = <&bpmp TEGRA234_CLK_PLLA>, 3263 <&bpmp TEGRA234_CLK_PLLA_OUT0>, 3264 <&bpmp TEGRA234_CLK_AUD_MCLK>; 3265 assigned-clock-parents = <0>, 3266 <&bpmp TEGRA234_CLK_PLLA>, 3267 <&bpmp TEGRA234_CLK_PLLA_OUT0>; 3268 }; 3269 3270 timer { 3271 compatible = "arm,armv8-timer"; 3272 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3273 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3274 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3275 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 3276 interrupt-parent = <&gic>; 3277 always-on; 3278 }; 3279}; 3280