1 /* 2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3 * VA Linux Systems Inc., Fremont, California. 4 * Copyright 2008 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Original Authors: 25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane 26 * 27 * Kernel port Author: Dave Airlie 28 */ 29 30 #ifndef AMDGPU_MODE_H 31 #define AMDGPU_MODE_H 32 33 #include <drm/display/drm_dp_helper.h> 34 #include <drm/drm_crtc.h> 35 #include <drm/drm_edid.h> 36 #include <drm/drm_encoder.h> 37 #include <drm/drm_fixed.h> 38 #include <drm/drm_crtc_helper.h> 39 #include <drm/drm_framebuffer.h> 40 #include <drm/drm_probe_helper.h> 41 #include <linux/i2c.h> 42 #include <linux/i2c-algo-bit.h> 43 #include <linux/hrtimer.h> 44 #include "amdgpu_irq.h" 45 46 #include <drm/display/drm_dp_mst_helper.h> 47 #include "modules/inc/mod_freesync.h" 48 #include "amdgpu_dm_irq_params.h" 49 50 struct amdgpu_bo; 51 struct amdgpu_device; 52 struct amdgpu_encoder; 53 struct amdgpu_router; 54 struct amdgpu_hpd; 55 56 #define to_amdgpu_crtc(x) container_of(x, struct amdgpu_crtc, base) 57 #define to_amdgpu_connector(x) container_of(x, struct amdgpu_connector, base) 58 #define to_amdgpu_encoder(x) container_of(x, struct amdgpu_encoder, base) 59 #define to_amdgpu_framebuffer(x) container_of(x, struct amdgpu_framebuffer, base) 60 61 #define to_dm_plane_state(x) container_of(x, struct dm_plane_state, base) 62 63 #define AMDGPU_MAX_HPD_PINS 6 64 #define AMDGPU_MAX_CRTCS 6 65 #define AMDGPU_MAX_PLANES 6 66 #define AMDGPU_MAX_AFMT_BLOCKS 9 67 68 enum amdgpu_rmx_type { 69 RMX_OFF, 70 RMX_FULL, 71 RMX_CENTER, 72 RMX_ASPECT 73 }; 74 75 enum amdgpu_underscan_type { 76 UNDERSCAN_OFF, 77 UNDERSCAN_ON, 78 UNDERSCAN_AUTO, 79 }; 80 81 #define AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS 50 82 #define AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS 10 83 84 enum amdgpu_hpd_id { 85 AMDGPU_HPD_1 = 0, 86 AMDGPU_HPD_2, 87 AMDGPU_HPD_3, 88 AMDGPU_HPD_4, 89 AMDGPU_HPD_5, 90 AMDGPU_HPD_6, 91 AMDGPU_HPD_NONE = 0xff, 92 }; 93 94 enum amdgpu_crtc_irq { 95 AMDGPU_CRTC_IRQ_VBLANK1 = 0, 96 AMDGPU_CRTC_IRQ_VBLANK2, 97 AMDGPU_CRTC_IRQ_VBLANK3, 98 AMDGPU_CRTC_IRQ_VBLANK4, 99 AMDGPU_CRTC_IRQ_VBLANK5, 100 AMDGPU_CRTC_IRQ_VBLANK6, 101 AMDGPU_CRTC_IRQ_VLINE1, 102 AMDGPU_CRTC_IRQ_VLINE2, 103 AMDGPU_CRTC_IRQ_VLINE3, 104 AMDGPU_CRTC_IRQ_VLINE4, 105 AMDGPU_CRTC_IRQ_VLINE5, 106 AMDGPU_CRTC_IRQ_VLINE6, 107 AMDGPU_CRTC_IRQ_NONE = 0xff 108 }; 109 110 enum amdgpu_pageflip_irq { 111 AMDGPU_PAGEFLIP_IRQ_D1 = 0, 112 AMDGPU_PAGEFLIP_IRQ_D2, 113 AMDGPU_PAGEFLIP_IRQ_D3, 114 AMDGPU_PAGEFLIP_IRQ_D4, 115 AMDGPU_PAGEFLIP_IRQ_D5, 116 AMDGPU_PAGEFLIP_IRQ_D6, 117 AMDGPU_PAGEFLIP_IRQ_NONE = 0xff 118 }; 119 120 enum amdgpu_flip_status { 121 AMDGPU_FLIP_NONE, 122 AMDGPU_FLIP_PENDING, 123 AMDGPU_FLIP_SUBMITTED 124 }; 125 126 #define AMDGPU_MAX_I2C_BUS 16 127 128 /* amdgpu gpio-based i2c 129 * 1. "mask" reg and bits 130 * grabs the gpio pins for software use 131 * 0=not held 1=held 132 * 2. "a" reg and bits 133 * output pin value 134 * 0=low 1=high 135 * 3. "en" reg and bits 136 * sets the pin direction 137 * 0=input 1=output 138 * 4. "y" reg and bits 139 * input pin value 140 * 0=low 1=high 141 */ 142 struct amdgpu_i2c_bus_rec { 143 bool valid; 144 /* id used by atom */ 145 uint8_t i2c_id; 146 /* id used by atom */ 147 enum amdgpu_hpd_id hpd; 148 /* can be used with hw i2c engine */ 149 bool hw_capable; 150 /* uses multi-media i2c engine */ 151 bool mm_i2c; 152 /* regs and bits */ 153 uint32_t mask_clk_reg; 154 uint32_t mask_data_reg; 155 uint32_t a_clk_reg; 156 uint32_t a_data_reg; 157 uint32_t en_clk_reg; 158 uint32_t en_data_reg; 159 uint32_t y_clk_reg; 160 uint32_t y_data_reg; 161 uint32_t mask_clk_mask; 162 uint32_t mask_data_mask; 163 uint32_t a_clk_mask; 164 uint32_t a_data_mask; 165 uint32_t en_clk_mask; 166 uint32_t en_data_mask; 167 uint32_t y_clk_mask; 168 uint32_t y_data_mask; 169 }; 170 171 #define AMDGPU_MAX_BIOS_CONNECTOR 16 172 173 /* pll flags */ 174 #define AMDGPU_PLL_USE_BIOS_DIVS (1 << 0) 175 #define AMDGPU_PLL_NO_ODD_POST_DIV (1 << 1) 176 #define AMDGPU_PLL_USE_REF_DIV (1 << 2) 177 #define AMDGPU_PLL_LEGACY (1 << 3) 178 #define AMDGPU_PLL_PREFER_LOW_REF_DIV (1 << 4) 179 #define AMDGPU_PLL_PREFER_HIGH_REF_DIV (1 << 5) 180 #define AMDGPU_PLL_PREFER_LOW_FB_DIV (1 << 6) 181 #define AMDGPU_PLL_PREFER_HIGH_FB_DIV (1 << 7) 182 #define AMDGPU_PLL_PREFER_LOW_POST_DIV (1 << 8) 183 #define AMDGPU_PLL_PREFER_HIGH_POST_DIV (1 << 9) 184 #define AMDGPU_PLL_USE_FRAC_FB_DIV (1 << 10) 185 #define AMDGPU_PLL_PREFER_CLOSEST_LOWER (1 << 11) 186 #define AMDGPU_PLL_USE_POST_DIV (1 << 12) 187 #define AMDGPU_PLL_IS_LCD (1 << 13) 188 #define AMDGPU_PLL_PREFER_MINM_OVER_MAXP (1 << 14) 189 190 struct amdgpu_pll { 191 /* reference frequency */ 192 uint32_t reference_freq; 193 194 /* fixed dividers */ 195 uint32_t reference_div; 196 uint32_t post_div; 197 198 /* pll in/out limits */ 199 uint32_t pll_in_min; 200 uint32_t pll_in_max; 201 uint32_t pll_out_min; 202 uint32_t pll_out_max; 203 uint32_t lcd_pll_out_min; 204 uint32_t lcd_pll_out_max; 205 uint32_t best_vco; 206 207 /* divider limits */ 208 uint32_t min_ref_div; 209 uint32_t max_ref_div; 210 uint32_t min_post_div; 211 uint32_t max_post_div; 212 uint32_t min_feedback_div; 213 uint32_t max_feedback_div; 214 uint32_t min_frac_feedback_div; 215 uint32_t max_frac_feedback_div; 216 217 /* flags for the current clock */ 218 uint32_t flags; 219 220 /* pll id */ 221 uint32_t id; 222 }; 223 224 struct amdgpu_i2c_chan { 225 struct i2c_adapter adapter; 226 struct drm_device *dev; 227 struct i2c_algo_bit_data bit; 228 struct amdgpu_i2c_bus_rec rec; 229 struct drm_dp_aux aux; 230 bool has_aux; 231 struct mutex mutex; 232 }; 233 234 struct amdgpu_afmt { 235 bool enabled; 236 int offset; 237 bool last_buffer_filled_status; 238 int id; 239 struct amdgpu_audio_pin *pin; 240 }; 241 242 /* 243 * Audio 244 */ 245 struct amdgpu_audio_pin { 246 int channels; 247 int rate; 248 int bits_per_sample; 249 u8 status_bits; 250 u8 category_code; 251 u32 offset; 252 bool connected; 253 u32 id; 254 }; 255 256 struct amdgpu_audio { 257 bool enabled; 258 struct amdgpu_audio_pin pin[AMDGPU_MAX_AFMT_BLOCKS]; 259 int num_pins; 260 }; 261 262 struct amdgpu_display_funcs { 263 /* display watermarks */ 264 void (*bandwidth_update)(struct amdgpu_device *adev); 265 /* get frame count */ 266 u32 (*vblank_get_counter)(struct amdgpu_device *adev, int crtc); 267 /* set backlight level */ 268 void (*backlight_set_level)(struct amdgpu_encoder *amdgpu_encoder, 269 u8 level); 270 /* get backlight level */ 271 u8 (*backlight_get_level)(struct amdgpu_encoder *amdgpu_encoder); 272 /* hotplug detect */ 273 bool (*hpd_sense)(struct amdgpu_device *adev, enum amdgpu_hpd_id hpd); 274 void (*hpd_set_polarity)(struct amdgpu_device *adev, 275 enum amdgpu_hpd_id hpd); 276 u32 (*hpd_get_gpio_reg)(struct amdgpu_device *adev); 277 /* pageflipping */ 278 void (*page_flip)(struct amdgpu_device *adev, 279 int crtc_id, u64 crtc_base, bool async); 280 int (*page_flip_get_scanoutpos)(struct amdgpu_device *adev, int crtc, 281 u32 *vbl, u32 *position); 282 /* display topology setup */ 283 void (*add_encoder)(struct amdgpu_device *adev, 284 uint32_t encoder_enum, 285 uint32_t supported_device, 286 u16 caps); 287 void (*add_connector)(struct amdgpu_device *adev, 288 uint32_t connector_id, 289 uint32_t supported_device, 290 int connector_type, 291 struct amdgpu_i2c_bus_rec *i2c_bus, 292 uint16_t connector_object_id, 293 struct amdgpu_hpd *hpd, 294 struct amdgpu_router *router); 295 296 297 }; 298 299 struct amdgpu_framebuffer { 300 struct drm_framebuffer base; 301 302 uint64_t tiling_flags; 303 bool tmz_surface; 304 305 /* caching for later use */ 306 uint64_t address; 307 }; 308 309 struct amdgpu_mode_info { 310 struct atom_context *atom_context; 311 struct card_info *atom_card_info; 312 bool mode_config_initialized; 313 struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS]; 314 struct drm_plane *planes[AMDGPU_MAX_PLANES]; 315 struct amdgpu_afmt *afmt[AMDGPU_MAX_AFMT_BLOCKS]; 316 /* DVI-I properties */ 317 struct drm_property *coherent_mode_property; 318 /* DAC enable load detect */ 319 struct drm_property *load_detect_property; 320 /* underscan */ 321 struct drm_property *underscan_property; 322 struct drm_property *underscan_hborder_property; 323 struct drm_property *underscan_vborder_property; 324 /* audio */ 325 struct drm_property *audio_property; 326 /* FMT dithering */ 327 struct drm_property *dither_property; 328 /* Adaptive Backlight Modulation (power feature) */ 329 struct drm_property *abm_level_property; 330 /* hardcoded DFP edid from BIOS */ 331 struct edid *bios_hardcoded_edid; 332 int bios_hardcoded_edid_size; 333 334 /* firmware flags */ 335 u32 firmware_flags; 336 /* pointer to backlight encoder */ 337 struct amdgpu_encoder *bl_encoder; 338 u8 bl_level; /* saved backlight level */ 339 struct amdgpu_audio audio; /* audio stuff */ 340 int num_crtc; /* number of crtcs */ 341 int num_hpd; /* number of hpd pins */ 342 int num_dig; /* number of dig blocks */ 343 bool gpu_vm_support; /* supports display from GTT */ 344 int disp_priority; 345 const struct amdgpu_display_funcs *funcs; 346 const enum drm_plane_type *plane_type; 347 }; 348 349 #define AMDGPU_MAX_BL_LEVEL 0xFF 350 351 struct amdgpu_backlight_privdata { 352 struct amdgpu_encoder *encoder; 353 uint8_t negative; 354 }; 355 356 struct amdgpu_atom_ss { 357 uint16_t percentage; 358 uint16_t percentage_divider; 359 uint8_t type; 360 uint16_t step; 361 uint8_t delay; 362 uint8_t range; 363 uint8_t refdiv; 364 /* asic_ss */ 365 uint16_t rate; 366 uint16_t amount; 367 }; 368 369 struct amdgpu_crtc { 370 struct drm_crtc base; 371 int crtc_id; 372 bool enabled; 373 bool can_tile; 374 uint32_t crtc_offset; 375 struct drm_gem_object *cursor_bo; 376 uint64_t cursor_addr; 377 int cursor_x; 378 int cursor_y; 379 int cursor_hot_x; 380 int cursor_hot_y; 381 int cursor_width; 382 int cursor_height; 383 int max_cursor_width; 384 int max_cursor_height; 385 enum amdgpu_rmx_type rmx_type; 386 u8 h_border; 387 u8 v_border; 388 fixed20_12 vsc; 389 fixed20_12 hsc; 390 struct drm_display_mode native_mode; 391 u32 pll_id; 392 /* page flipping */ 393 struct amdgpu_flip_work *pflip_works; 394 enum amdgpu_flip_status pflip_status; 395 int deferred_flip_completion; 396 /* parameters access from DM IRQ handler */ 397 struct dm_irq_params dm_irq_params; 398 /* pll sharing */ 399 struct amdgpu_atom_ss ss; 400 bool ss_enabled; 401 u32 adjusted_clock; 402 int bpc; 403 u32 pll_reference_div; 404 u32 pll_post_div; 405 u32 pll_flags; 406 struct drm_encoder *encoder; 407 struct drm_connector *connector; 408 /* for dpm */ 409 u32 line_time; 410 u32 wm_low; 411 u32 wm_high; 412 u32 lb_vblank_lead_lines; 413 struct drm_display_mode hw_mode; 414 /* for virtual dce */ 415 struct hrtimer vblank_timer; 416 enum amdgpu_interrupt_state vsync_timer_enabled; 417 418 int otg_inst; 419 struct drm_pending_vblank_event *event; 420 }; 421 422 struct amdgpu_encoder_atom_dig { 423 bool linkb; 424 /* atom dig */ 425 bool coherent_mode; 426 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */ 427 /* atom lvds/edp */ 428 uint32_t lcd_misc; 429 uint16_t panel_pwr_delay; 430 uint32_t lcd_ss_id; 431 /* panel mode */ 432 struct drm_display_mode native_mode; 433 struct backlight_device *bl_dev; 434 int dpms_mode; 435 uint8_t backlight_level; 436 int panel_mode; 437 struct amdgpu_afmt *afmt; 438 }; 439 440 struct amdgpu_encoder { 441 struct drm_encoder base; 442 uint32_t encoder_enum; 443 uint32_t encoder_id; 444 uint32_t devices; 445 uint32_t active_device; 446 uint32_t flags; 447 uint32_t pixel_clock; 448 enum amdgpu_rmx_type rmx_type; 449 enum amdgpu_underscan_type underscan_type; 450 uint32_t underscan_hborder; 451 uint32_t underscan_vborder; 452 struct drm_display_mode native_mode; 453 void *enc_priv; 454 int audio_polling_active; 455 bool is_ext_encoder; 456 u16 caps; 457 }; 458 459 struct amdgpu_connector_atom_dig { 460 /* displayport */ 461 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 462 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; 463 u8 dp_sink_type; 464 int dp_clock; 465 int dp_lane_count; 466 bool edp_on; 467 }; 468 469 struct amdgpu_gpio_rec { 470 bool valid; 471 u8 id; 472 u32 reg; 473 u32 mask; 474 u32 shift; 475 }; 476 477 struct amdgpu_hpd { 478 enum amdgpu_hpd_id hpd; 479 u8 plugged_state; 480 struct amdgpu_gpio_rec gpio; 481 }; 482 483 struct amdgpu_router { 484 u32 router_id; 485 struct amdgpu_i2c_bus_rec i2c_info; 486 u8 i2c_addr; 487 /* i2c mux */ 488 bool ddc_valid; 489 u8 ddc_mux_type; 490 u8 ddc_mux_control_pin; 491 u8 ddc_mux_state; 492 /* clock/data mux */ 493 bool cd_valid; 494 u8 cd_mux_type; 495 u8 cd_mux_control_pin; 496 u8 cd_mux_state; 497 }; 498 499 enum amdgpu_connector_audio { 500 AMDGPU_AUDIO_DISABLE = 0, 501 AMDGPU_AUDIO_ENABLE = 1, 502 AMDGPU_AUDIO_AUTO = 2 503 }; 504 505 enum amdgpu_connector_dither { 506 AMDGPU_FMT_DITHER_DISABLE = 0, 507 AMDGPU_FMT_DITHER_ENABLE = 1, 508 }; 509 510 struct amdgpu_dm_dp_aux { 511 struct drm_dp_aux aux; 512 struct ddc_service *ddc_service; 513 }; 514 515 struct amdgpu_i2c_adapter { 516 struct i2c_adapter base; 517 518 struct ddc_service *ddc_service; 519 }; 520 521 #define TO_DM_AUX(x) container_of((x), struct amdgpu_dm_dp_aux, aux) 522 523 struct amdgpu_connector { 524 struct drm_connector base; 525 uint32_t connector_id; 526 uint32_t devices; 527 struct amdgpu_i2c_chan *ddc_bus; 528 /* some systems have an hdmi and vga port with a shared ddc line */ 529 bool shared_ddc; 530 bool use_digital; 531 /* we need to mind the EDID between detect 532 and get modes due to analog/digital/tvencoder */ 533 struct edid *edid; 534 void *con_priv; 535 bool dac_load_detect; 536 bool detected_by_load; /* if the connection status was determined by load */ 537 uint16_t connector_object_id; 538 struct amdgpu_hpd hpd; 539 struct amdgpu_router router; 540 struct amdgpu_i2c_chan *router_bus; 541 enum amdgpu_connector_audio audio; 542 enum amdgpu_connector_dither dither; 543 unsigned pixelclock_for_modeset; 544 }; 545 546 /* TODO: start to use this struct and remove same field from base one */ 547 struct amdgpu_mst_connector { 548 struct amdgpu_connector base; 549 550 struct drm_dp_mst_topology_mgr mst_mgr; 551 struct amdgpu_dm_dp_aux dm_dp_aux; 552 struct drm_dp_mst_port *port; 553 struct amdgpu_connector *mst_port; 554 bool is_mst_connector; 555 struct amdgpu_encoder *mst_encoder; 556 }; 557 558 #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \ 559 ((em) == ATOM_ENCODER_MODE_DP_MST)) 560 561 /* Driver internal use only flags of amdgpu_display_get_crtc_scanoutpos() */ 562 #define DRM_SCANOUTPOS_VALID (1 << 0) 563 #define DRM_SCANOUTPOS_IN_VBLANK (1 << 1) 564 #define DRM_SCANOUTPOS_ACCURATE (1 << 2) 565 #define USE_REAL_VBLANKSTART (1 << 30) 566 #define GET_DISTANCE_TO_VBLANKSTART (1 << 31) 567 568 void amdgpu_link_encoder_connector(struct drm_device *dev); 569 570 struct drm_connector * 571 amdgpu_get_connector_for_encoder(struct drm_encoder *encoder); 572 struct drm_connector * 573 amdgpu_get_connector_for_encoder_init(struct drm_encoder *encoder); 574 bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder, 575 u32 pixel_clock); 576 577 u16 amdgpu_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder); 578 struct drm_encoder *amdgpu_get_external_encoder(struct drm_encoder *encoder); 579 580 bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector, 581 bool use_aux); 582 583 void amdgpu_encoder_set_active_device(struct drm_encoder *encoder); 584 585 int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev, 586 unsigned int pipe, unsigned int flags, int *vpos, 587 int *hpos, ktime_t *stime, ktime_t *etime, 588 const struct drm_display_mode *mode); 589 590 int amdgpufb_remove(struct drm_device *dev, struct drm_framebuffer *fb); 591 592 void amdgpu_enc_destroy(struct drm_encoder *encoder); 593 void amdgpu_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); 594 bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 595 const struct drm_display_mode *mode, 596 struct drm_display_mode *adjusted_mode); 597 void amdgpu_panel_mode_fixup(struct drm_encoder *encoder, 598 struct drm_display_mode *adjusted_mode); 599 int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc); 600 601 bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc, 602 bool in_vblank_irq, int *vpos, 603 int *hpos, ktime_t *stime, ktime_t *etime, 604 const struct drm_display_mode *mode); 605 606 /* amdgpu_display.c */ 607 void amdgpu_display_print_display_setup(struct drm_device *dev); 608 int amdgpu_display_modeset_create_props(struct amdgpu_device *adev); 609 int amdgpu_display_crtc_set_config(struct drm_mode_set *set, 610 struct drm_modeset_acquire_ctx *ctx); 611 int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, 612 struct drm_framebuffer *fb, 613 struct drm_pending_vblank_event *event, 614 uint32_t page_flip_flags, uint32_t target, 615 struct drm_modeset_acquire_ctx *ctx); 616 extern const struct drm_mode_config_funcs amdgpu_mode_funcs; 617 618 #endif 619