1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/include/kvm_emulate.h 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Author: Christoffer Dall <c.dall@virtualopensystems.com> 9 */ 10 11 #ifndef __ARM64_KVM_EMULATE_H__ 12 #define __ARM64_KVM_EMULATE_H__ 13 14 #include <linux/kvm_host.h> 15 16 #include <asm/debug-monitors.h> 17 #include <asm/esr.h> 18 #include <asm/kvm_arm.h> 19 #include <asm/kvm_hyp.h> 20 #include <asm/ptrace.h> 21 #include <asm/cputype.h> 22 #include <asm/virt.h> 23 24 #define CURRENT_EL_SP_EL0_VECTOR 0x0 25 #define CURRENT_EL_SP_ELx_VECTOR 0x200 26 #define LOWER_EL_AArch64_VECTOR 0x400 27 #define LOWER_EL_AArch32_VECTOR 0x600 28 29 enum exception_type { 30 except_type_sync = 0, 31 except_type_irq = 0x80, 32 except_type_fiq = 0x100, 33 except_type_serror = 0x180, 34 }; 35 36 #define kvm_exception_type_names \ 37 { except_type_sync, "SYNC" }, \ 38 { except_type_irq, "IRQ" }, \ 39 { except_type_fiq, "FIQ" }, \ 40 { except_type_serror, "SERROR" } 41 42 bool kvm_condition_valid32(const struct kvm_vcpu *vcpu); 43 void kvm_skip_instr32(struct kvm_vcpu *vcpu); 44 45 void kvm_inject_undefined(struct kvm_vcpu *vcpu); 46 void kvm_inject_vabt(struct kvm_vcpu *vcpu); 47 void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr); 48 void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr); 49 void kvm_inject_size_fault(struct kvm_vcpu *vcpu); 50 51 void kvm_vcpu_wfi(struct kvm_vcpu *vcpu); 52 53 void kvm_emulate_nested_eret(struct kvm_vcpu *vcpu); 54 int kvm_inject_nested_sync(struct kvm_vcpu *vcpu, u64 esr_el2); 55 int kvm_inject_nested_irq(struct kvm_vcpu *vcpu); 56 57 #if defined(__KVM_VHE_HYPERVISOR__) || defined(__KVM_NVHE_HYPERVISOR__) 58 static __always_inline bool vcpu_el1_is_32bit(struct kvm_vcpu *vcpu) 59 { 60 return !(vcpu->arch.hcr_el2 & HCR_RW); 61 } 62 #else 63 static __always_inline bool vcpu_el1_is_32bit(struct kvm_vcpu *vcpu) 64 { 65 struct kvm *kvm = vcpu->kvm; 66 67 WARN_ON_ONCE(!test_bit(KVM_ARCH_FLAG_REG_WIDTH_CONFIGURED, 68 &kvm->arch.flags)); 69 70 return test_bit(KVM_ARCH_FLAG_EL1_32BIT, &kvm->arch.flags); 71 } 72 #endif 73 74 static inline void vcpu_reset_hcr(struct kvm_vcpu *vcpu) 75 { 76 vcpu->arch.hcr_el2 = HCR_GUEST_FLAGS; 77 if (is_kernel_in_hyp_mode()) 78 vcpu->arch.hcr_el2 |= HCR_E2H; 79 if (cpus_have_const_cap(ARM64_HAS_RAS_EXTN)) { 80 /* route synchronous external abort exceptions to EL2 */ 81 vcpu->arch.hcr_el2 |= HCR_TEA; 82 /* trap error record accesses */ 83 vcpu->arch.hcr_el2 |= HCR_TERR; 84 } 85 86 if (cpus_have_const_cap(ARM64_HAS_STAGE2_FWB)) { 87 vcpu->arch.hcr_el2 |= HCR_FWB; 88 } else { 89 /* 90 * For non-FWB CPUs, we trap VM ops (HCR_EL2.TVM) until M+C 91 * get set in SCTLR_EL1 such that we can detect when the guest 92 * MMU gets turned on and do the necessary cache maintenance 93 * then. 94 */ 95 vcpu->arch.hcr_el2 |= HCR_TVM; 96 } 97 98 if (vcpu_el1_is_32bit(vcpu)) 99 vcpu->arch.hcr_el2 &= ~HCR_RW; 100 101 if (kvm_has_mte(vcpu->kvm)) 102 vcpu->arch.hcr_el2 |= HCR_ATA; 103 } 104 105 static inline unsigned long *vcpu_hcr(struct kvm_vcpu *vcpu) 106 { 107 return (unsigned long *)&vcpu->arch.hcr_el2; 108 } 109 110 static inline void vcpu_clear_wfx_traps(struct kvm_vcpu *vcpu) 111 { 112 vcpu->arch.hcr_el2 &= ~HCR_TWE; 113 if (atomic_read(&vcpu->arch.vgic_cpu.vgic_v3.its_vpe.vlpi_count) || 114 vcpu->kvm->arch.vgic.nassgireq) 115 vcpu->arch.hcr_el2 &= ~HCR_TWI; 116 else 117 vcpu->arch.hcr_el2 |= HCR_TWI; 118 } 119 120 static inline void vcpu_set_wfx_traps(struct kvm_vcpu *vcpu) 121 { 122 vcpu->arch.hcr_el2 |= HCR_TWE; 123 vcpu->arch.hcr_el2 |= HCR_TWI; 124 } 125 126 static inline void vcpu_ptrauth_enable(struct kvm_vcpu *vcpu) 127 { 128 vcpu->arch.hcr_el2 |= (HCR_API | HCR_APK); 129 } 130 131 static inline void vcpu_ptrauth_disable(struct kvm_vcpu *vcpu) 132 { 133 vcpu->arch.hcr_el2 &= ~(HCR_API | HCR_APK); 134 } 135 136 static inline unsigned long vcpu_get_vsesr(struct kvm_vcpu *vcpu) 137 { 138 return vcpu->arch.vsesr_el2; 139 } 140 141 static inline void vcpu_set_vsesr(struct kvm_vcpu *vcpu, u64 vsesr) 142 { 143 vcpu->arch.vsesr_el2 = vsesr; 144 } 145 146 static __always_inline unsigned long *vcpu_pc(const struct kvm_vcpu *vcpu) 147 { 148 return (unsigned long *)&vcpu_gp_regs(vcpu)->pc; 149 } 150 151 static __always_inline unsigned long *vcpu_cpsr(const struct kvm_vcpu *vcpu) 152 { 153 return (unsigned long *)&vcpu_gp_regs(vcpu)->pstate; 154 } 155 156 static __always_inline bool vcpu_mode_is_32bit(const struct kvm_vcpu *vcpu) 157 { 158 return !!(*vcpu_cpsr(vcpu) & PSR_MODE32_BIT); 159 } 160 161 static __always_inline bool kvm_condition_valid(const struct kvm_vcpu *vcpu) 162 { 163 if (vcpu_mode_is_32bit(vcpu)) 164 return kvm_condition_valid32(vcpu); 165 166 return true; 167 } 168 169 static inline void vcpu_set_thumb(struct kvm_vcpu *vcpu) 170 { 171 *vcpu_cpsr(vcpu) |= PSR_AA32_T_BIT; 172 } 173 174 /* 175 * vcpu_get_reg and vcpu_set_reg should always be passed a register number 176 * coming from a read of ESR_EL2. Otherwise, it may give the wrong result on 177 * AArch32 with banked registers. 178 */ 179 static __always_inline unsigned long vcpu_get_reg(const struct kvm_vcpu *vcpu, 180 u8 reg_num) 181 { 182 return (reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[reg_num]; 183 } 184 185 static __always_inline void vcpu_set_reg(struct kvm_vcpu *vcpu, u8 reg_num, 186 unsigned long val) 187 { 188 if (reg_num != 31) 189 vcpu_gp_regs(vcpu)->regs[reg_num] = val; 190 } 191 192 static inline bool vcpu_is_el2_ctxt(const struct kvm_cpu_context *ctxt) 193 { 194 switch (ctxt->regs.pstate & (PSR_MODE32_BIT | PSR_MODE_MASK)) { 195 case PSR_MODE_EL2h: 196 case PSR_MODE_EL2t: 197 return true; 198 default: 199 return false; 200 } 201 } 202 203 static inline bool vcpu_is_el2(const struct kvm_vcpu *vcpu) 204 { 205 return vcpu_is_el2_ctxt(&vcpu->arch.ctxt); 206 } 207 208 static inline bool __vcpu_el2_e2h_is_set(const struct kvm_cpu_context *ctxt) 209 { 210 return ctxt_sys_reg(ctxt, HCR_EL2) & HCR_E2H; 211 } 212 213 static inline bool vcpu_el2_e2h_is_set(const struct kvm_vcpu *vcpu) 214 { 215 return __vcpu_el2_e2h_is_set(&vcpu->arch.ctxt); 216 } 217 218 static inline bool __vcpu_el2_tge_is_set(const struct kvm_cpu_context *ctxt) 219 { 220 return ctxt_sys_reg(ctxt, HCR_EL2) & HCR_TGE; 221 } 222 223 static inline bool vcpu_el2_tge_is_set(const struct kvm_vcpu *vcpu) 224 { 225 return __vcpu_el2_tge_is_set(&vcpu->arch.ctxt); 226 } 227 228 static inline bool __is_hyp_ctxt(const struct kvm_cpu_context *ctxt) 229 { 230 /* 231 * We are in a hypervisor context if the vcpu mode is EL2 or 232 * E2H and TGE bits are set. The latter means we are in the user space 233 * of the VHE kernel. ARMv8.1 ARM describes this as 'InHost' 234 * 235 * Note that the HCR_EL2.{E2H,TGE}={0,1} isn't really handled in the 236 * rest of the KVM code, and will result in a misbehaving guest. 237 */ 238 return vcpu_is_el2_ctxt(ctxt) || 239 (__vcpu_el2_e2h_is_set(ctxt) && __vcpu_el2_tge_is_set(ctxt)) || 240 __vcpu_el2_tge_is_set(ctxt); 241 } 242 243 static inline bool is_hyp_ctxt(const struct kvm_vcpu *vcpu) 244 { 245 return __is_hyp_ctxt(&vcpu->arch.ctxt); 246 } 247 248 /* 249 * The layout of SPSR for an AArch32 state is different when observed from an 250 * AArch64 SPSR_ELx or an AArch32 SPSR_*. This function generates the AArch32 251 * view given an AArch64 view. 252 * 253 * In ARM DDI 0487E.a see: 254 * 255 * - The AArch64 view (SPSR_EL2) in section C5.2.18, page C5-426 256 * - The AArch32 view (SPSR_abt) in section G8.2.126, page G8-6256 257 * - The AArch32 view (SPSR_und) in section G8.2.132, page G8-6280 258 * 259 * Which show the following differences: 260 * 261 * | Bit | AA64 | AA32 | Notes | 262 * +-----+------+------+-----------------------------| 263 * | 24 | DIT | J | J is RES0 in ARMv8 | 264 * | 21 | SS | DIT | SS doesn't exist in AArch32 | 265 * 266 * ... and all other bits are (currently) common. 267 */ 268 static inline unsigned long host_spsr_to_spsr32(unsigned long spsr) 269 { 270 const unsigned long overlap = BIT(24) | BIT(21); 271 unsigned long dit = !!(spsr & PSR_AA32_DIT_BIT); 272 273 spsr &= ~overlap; 274 275 spsr |= dit << 21; 276 277 return spsr; 278 } 279 280 static inline bool vcpu_mode_priv(const struct kvm_vcpu *vcpu) 281 { 282 u32 mode; 283 284 if (vcpu_mode_is_32bit(vcpu)) { 285 mode = *vcpu_cpsr(vcpu) & PSR_AA32_MODE_MASK; 286 return mode > PSR_AA32_MODE_USR; 287 } 288 289 mode = *vcpu_cpsr(vcpu) & PSR_MODE_MASK; 290 291 return mode != PSR_MODE_EL0t; 292 } 293 294 static __always_inline u64 kvm_vcpu_get_esr(const struct kvm_vcpu *vcpu) 295 { 296 return vcpu->arch.fault.esr_el2; 297 } 298 299 static __always_inline int kvm_vcpu_get_condition(const struct kvm_vcpu *vcpu) 300 { 301 u64 esr = kvm_vcpu_get_esr(vcpu); 302 303 if (esr & ESR_ELx_CV) 304 return (esr & ESR_ELx_COND_MASK) >> ESR_ELx_COND_SHIFT; 305 306 return -1; 307 } 308 309 static __always_inline unsigned long kvm_vcpu_get_hfar(const struct kvm_vcpu *vcpu) 310 { 311 return vcpu->arch.fault.far_el2; 312 } 313 314 static __always_inline phys_addr_t kvm_vcpu_get_fault_ipa(const struct kvm_vcpu *vcpu) 315 { 316 return ((phys_addr_t)vcpu->arch.fault.hpfar_el2 & HPFAR_MASK) << 8; 317 } 318 319 static inline u64 kvm_vcpu_get_disr(const struct kvm_vcpu *vcpu) 320 { 321 return vcpu->arch.fault.disr_el1; 322 } 323 324 static inline u32 kvm_vcpu_hvc_get_imm(const struct kvm_vcpu *vcpu) 325 { 326 return kvm_vcpu_get_esr(vcpu) & ESR_ELx_xVC_IMM_MASK; 327 } 328 329 static __always_inline bool kvm_vcpu_dabt_isvalid(const struct kvm_vcpu *vcpu) 330 { 331 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_ISV); 332 } 333 334 static inline unsigned long kvm_vcpu_dabt_iss_nisv_sanitized(const struct kvm_vcpu *vcpu) 335 { 336 return kvm_vcpu_get_esr(vcpu) & (ESR_ELx_CM | ESR_ELx_WNR | ESR_ELx_FSC); 337 } 338 339 static inline bool kvm_vcpu_dabt_issext(const struct kvm_vcpu *vcpu) 340 { 341 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_SSE); 342 } 343 344 static inline bool kvm_vcpu_dabt_issf(const struct kvm_vcpu *vcpu) 345 { 346 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_SF); 347 } 348 349 static __always_inline int kvm_vcpu_dabt_get_rd(const struct kvm_vcpu *vcpu) 350 { 351 return (kvm_vcpu_get_esr(vcpu) & ESR_ELx_SRT_MASK) >> ESR_ELx_SRT_SHIFT; 352 } 353 354 static __always_inline bool kvm_vcpu_abt_iss1tw(const struct kvm_vcpu *vcpu) 355 { 356 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_S1PTW); 357 } 358 359 /* Always check for S1PTW *before* using this. */ 360 static __always_inline bool kvm_vcpu_dabt_iswrite(const struct kvm_vcpu *vcpu) 361 { 362 return kvm_vcpu_get_esr(vcpu) & ESR_ELx_WNR; 363 } 364 365 static inline bool kvm_vcpu_dabt_is_cm(const struct kvm_vcpu *vcpu) 366 { 367 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_CM); 368 } 369 370 static __always_inline unsigned int kvm_vcpu_dabt_get_as(const struct kvm_vcpu *vcpu) 371 { 372 return 1 << ((kvm_vcpu_get_esr(vcpu) & ESR_ELx_SAS) >> ESR_ELx_SAS_SHIFT); 373 } 374 375 /* This one is not specific to Data Abort */ 376 static __always_inline bool kvm_vcpu_trap_il_is32bit(const struct kvm_vcpu *vcpu) 377 { 378 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_IL); 379 } 380 381 static __always_inline u8 kvm_vcpu_trap_get_class(const struct kvm_vcpu *vcpu) 382 { 383 return ESR_ELx_EC(kvm_vcpu_get_esr(vcpu)); 384 } 385 386 static inline bool kvm_vcpu_trap_is_iabt(const struct kvm_vcpu *vcpu) 387 { 388 return kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_IABT_LOW; 389 } 390 391 static inline bool kvm_vcpu_trap_is_exec_fault(const struct kvm_vcpu *vcpu) 392 { 393 return kvm_vcpu_trap_is_iabt(vcpu) && !kvm_vcpu_abt_iss1tw(vcpu); 394 } 395 396 static __always_inline u8 kvm_vcpu_trap_get_fault(const struct kvm_vcpu *vcpu) 397 { 398 return kvm_vcpu_get_esr(vcpu) & ESR_ELx_FSC; 399 } 400 401 static __always_inline u8 kvm_vcpu_trap_get_fault_type(const struct kvm_vcpu *vcpu) 402 { 403 return kvm_vcpu_get_esr(vcpu) & ESR_ELx_FSC_TYPE; 404 } 405 406 static __always_inline u8 kvm_vcpu_trap_get_fault_level(const struct kvm_vcpu *vcpu) 407 { 408 return kvm_vcpu_get_esr(vcpu) & ESR_ELx_FSC_LEVEL; 409 } 410 411 static __always_inline bool kvm_vcpu_abt_issea(const struct kvm_vcpu *vcpu) 412 { 413 switch (kvm_vcpu_trap_get_fault(vcpu)) { 414 case ESR_ELx_FSC_EXTABT: 415 case ESR_ELx_FSC_SEA_TTW0: 416 case ESR_ELx_FSC_SEA_TTW1: 417 case ESR_ELx_FSC_SEA_TTW2: 418 case ESR_ELx_FSC_SEA_TTW3: 419 case ESR_ELx_FSC_SECC: 420 case ESR_ELx_FSC_SECC_TTW0: 421 case ESR_ELx_FSC_SECC_TTW1: 422 case ESR_ELx_FSC_SECC_TTW2: 423 case ESR_ELx_FSC_SECC_TTW3: 424 return true; 425 default: 426 return false; 427 } 428 } 429 430 static __always_inline int kvm_vcpu_sys_get_rt(struct kvm_vcpu *vcpu) 431 { 432 u64 esr = kvm_vcpu_get_esr(vcpu); 433 return ESR_ELx_SYS64_ISS_RT(esr); 434 } 435 436 static inline bool kvm_is_write_fault(struct kvm_vcpu *vcpu) 437 { 438 if (kvm_vcpu_abt_iss1tw(vcpu)) { 439 /* 440 * Only a permission fault on a S1PTW should be 441 * considered as a write. Otherwise, page tables baked 442 * in a read-only memslot will result in an exception 443 * being delivered in the guest. 444 * 445 * The drawback is that we end-up faulting twice if the 446 * guest is using any of HW AF/DB: a translation fault 447 * to map the page containing the PT (read only at 448 * first), then a permission fault to allow the flags 449 * to be set. 450 */ 451 switch (kvm_vcpu_trap_get_fault_type(vcpu)) { 452 case ESR_ELx_FSC_PERM: 453 return true; 454 default: 455 return false; 456 } 457 } 458 459 if (kvm_vcpu_trap_is_iabt(vcpu)) 460 return false; 461 462 return kvm_vcpu_dabt_iswrite(vcpu); 463 } 464 465 static inline unsigned long kvm_vcpu_get_mpidr_aff(struct kvm_vcpu *vcpu) 466 { 467 return vcpu_read_sys_reg(vcpu, MPIDR_EL1) & MPIDR_HWID_BITMASK; 468 } 469 470 static inline void kvm_vcpu_set_be(struct kvm_vcpu *vcpu) 471 { 472 if (vcpu_mode_is_32bit(vcpu)) { 473 *vcpu_cpsr(vcpu) |= PSR_AA32_E_BIT; 474 } else { 475 u64 sctlr = vcpu_read_sys_reg(vcpu, SCTLR_EL1); 476 sctlr |= SCTLR_ELx_EE; 477 vcpu_write_sys_reg(vcpu, sctlr, SCTLR_EL1); 478 } 479 } 480 481 static inline bool kvm_vcpu_is_be(struct kvm_vcpu *vcpu) 482 { 483 if (vcpu_mode_is_32bit(vcpu)) 484 return !!(*vcpu_cpsr(vcpu) & PSR_AA32_E_BIT); 485 486 if (vcpu_mode_priv(vcpu)) 487 return !!(vcpu_read_sys_reg(vcpu, SCTLR_EL1) & SCTLR_ELx_EE); 488 else 489 return !!(vcpu_read_sys_reg(vcpu, SCTLR_EL1) & SCTLR_EL1_E0E); 490 } 491 492 static inline unsigned long vcpu_data_guest_to_host(struct kvm_vcpu *vcpu, 493 unsigned long data, 494 unsigned int len) 495 { 496 if (kvm_vcpu_is_be(vcpu)) { 497 switch (len) { 498 case 1: 499 return data & 0xff; 500 case 2: 501 return be16_to_cpu(data & 0xffff); 502 case 4: 503 return be32_to_cpu(data & 0xffffffff); 504 default: 505 return be64_to_cpu(data); 506 } 507 } else { 508 switch (len) { 509 case 1: 510 return data & 0xff; 511 case 2: 512 return le16_to_cpu(data & 0xffff); 513 case 4: 514 return le32_to_cpu(data & 0xffffffff); 515 default: 516 return le64_to_cpu(data); 517 } 518 } 519 520 return data; /* Leave LE untouched */ 521 } 522 523 static inline unsigned long vcpu_data_host_to_guest(struct kvm_vcpu *vcpu, 524 unsigned long data, 525 unsigned int len) 526 { 527 if (kvm_vcpu_is_be(vcpu)) { 528 switch (len) { 529 case 1: 530 return data & 0xff; 531 case 2: 532 return cpu_to_be16(data & 0xffff); 533 case 4: 534 return cpu_to_be32(data & 0xffffffff); 535 default: 536 return cpu_to_be64(data); 537 } 538 } else { 539 switch (len) { 540 case 1: 541 return data & 0xff; 542 case 2: 543 return cpu_to_le16(data & 0xffff); 544 case 4: 545 return cpu_to_le32(data & 0xffffffff); 546 default: 547 return cpu_to_le64(data); 548 } 549 } 550 551 return data; /* Leave LE untouched */ 552 } 553 554 static __always_inline void kvm_incr_pc(struct kvm_vcpu *vcpu) 555 { 556 WARN_ON(vcpu_get_flag(vcpu, PENDING_EXCEPTION)); 557 vcpu_set_flag(vcpu, INCREMENT_PC); 558 } 559 560 #define kvm_pend_exception(v, e) \ 561 do { \ 562 WARN_ON(vcpu_get_flag((v), INCREMENT_PC)); \ 563 vcpu_set_flag((v), PENDING_EXCEPTION); \ 564 vcpu_set_flag((v), e); \ 565 } while (0) 566 567 568 static inline bool vcpu_has_feature(struct kvm_vcpu *vcpu, int feature) 569 { 570 return test_bit(feature, vcpu->arch.features); 571 } 572 573 #endif /* __ARM64_KVM_EMULATE_H__ */ 574