1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/bridge/renesas,dsi.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas RZ/G2L MIPI DSI Encoder
8
9maintainers:
10  - Biju Das <biju.das.jz@bp.renesas.com>
11
12description: |
13  This binding describes the MIPI DSI encoder embedded in the Renesas
14  RZ/G2L alike family of SoC's. The encoder can operate in DSI mode, with
15  up to four data lanes.
16
17allOf:
18  - $ref: /schemas/display/dsi-controller.yaml#
19
20properties:
21  compatible:
22    items:
23      - enum:
24          - renesas,r9a07g044-mipi-dsi # RZ/G2{L,LC}
25      - const: renesas,rzg2l-mipi-dsi
26
27  reg:
28    maxItems: 1
29
30  interrupts:
31    items:
32      - description: Sequence operation channel 0 interrupt
33      - description: Sequence operation channel 1 interrupt
34      - description: Video-Input operation channel 1 interrupt
35      - description: DSI Packet Receive interrupt
36      - description: DSI Fatal Error interrupt
37      - description: DSI D-PHY PPI interrupt
38      - description: Debug interrupt
39
40  interrupt-names:
41    items:
42      - const: seq0
43      - const: seq1
44      - const: vin1
45      - const: rcv
46      - const: ferr
47      - const: ppi
48      - const: debug
49
50  clocks:
51    items:
52      - description: DSI D-PHY PLL multiplied clock
53      - description: DSI D-PHY system clock
54      - description: DSI AXI bus clock
55      - description: DSI Register access clock
56      - description: DSI Video clock
57      - description: DSI D-PHY Escape mode transmit clock
58
59  clock-names:
60    items:
61      - const: pllclk
62      - const: sysclk
63      - const: aclk
64      - const: pclk
65      - const: vclk
66      - const: lpclk
67
68  resets:
69    items:
70      - description: MIPI_DSI_CMN_RSTB
71      - description: MIPI_DSI_ARESET_N
72      - description: MIPI_DSI_PRESET_N
73
74  reset-names:
75    items:
76      - const: rst
77      - const: arst
78      - const: prst
79
80  power-domains:
81    maxItems: 1
82
83  ports:
84    $ref: /schemas/graph.yaml#/properties/ports
85
86    properties:
87      port@0:
88        $ref: /schemas/graph.yaml#/properties/port
89        description: Parallel input port
90
91      port@1:
92        $ref: /schemas/graph.yaml#/$defs/port-base
93        unevaluatedProperties: false
94        description: DSI output port
95
96        properties:
97          endpoint:
98            $ref: /schemas/media/video-interfaces.yaml#
99            unevaluatedProperties: false
100
101            properties:
102              data-lanes:
103                description: array of physical DSI data lane indexes.
104                minItems: 1
105                items:
106                  - const: 1
107                  - const: 2
108                  - const: 3
109                  - const: 4
110
111            required:
112              - data-lanes
113
114    required:
115      - port@0
116      - port@1
117
118required:
119  - compatible
120  - reg
121  - interrupts
122  - interrupt-names
123  - clocks
124  - clock-names
125  - resets
126  - reset-names
127  - power-domains
128  - ports
129
130additionalProperties: false
131
132examples:
133  - |
134    #include <dt-bindings/clock/r9a07g044-cpg.h>
135    #include <dt-bindings/interrupt-controller/arm-gic.h>
136
137    dsi0: dsi@10850000 {
138        compatible = "renesas,r9a07g044-mipi-dsi", "renesas,rzg2l-mipi-dsi";
139        reg = <0x10850000 0x20000>;
140        interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
141                     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
142                     <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
143                     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
144                     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
145                     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
146                     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
147        interrupt-names = "seq0", "seq1", "vin1", "rcv",
148                          "ferr", "ppi", "debug";
149        clocks = <&cpg CPG_MOD R9A07G044_MIPI_DSI_PLLCLK>,
150                 <&cpg CPG_MOD R9A07G044_MIPI_DSI_SYSCLK>,
151                 <&cpg CPG_MOD R9A07G044_MIPI_DSI_ACLK>,
152                 <&cpg CPG_MOD R9A07G044_MIPI_DSI_PCLK>,
153                 <&cpg CPG_MOD R9A07G044_MIPI_DSI_VCLK>,
154                 <&cpg CPG_MOD R9A07G044_MIPI_DSI_LPCLK>;
155        clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk";
156        resets = <&cpg R9A07G044_MIPI_DSI_CMN_RSTB>,
157                 <&cpg R9A07G044_MIPI_DSI_ARESET_N>,
158                 <&cpg R9A07G044_MIPI_DSI_PRESET_N>;
159        reset-names = "rst", "arst", "prst";
160        power-domains = <&cpg>;
161
162        ports {
163            #address-cells = <1>;
164            #size-cells = <0>;
165
166            port@0 {
167                reg = <0>;
168                dsi0_in: endpoint {
169                    remote-endpoint = <&du_out_dsi0>;
170                };
171            };
172
173            port@1 {
174                reg = <1>;
175                dsi0_out: endpoint {
176                    data-lanes = <1 2 3 4>;
177                    remote-endpoint = <&adv7535_in>;
178                };
179            };
180        };
181    };
182...
183