1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra186-clock.h> 3#include <dt-bindings/gpio/tegra186-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/memory/tegra186-mc.h> 7#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 8#include <dt-bindings/power/tegra186-powergate.h> 9#include <dt-bindings/reset/tegra186-reset.h> 10#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 11 12/ { 13 compatible = "nvidia,tegra186"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 misc@100000 { 19 compatible = "nvidia,tegra186-misc"; 20 reg = <0x0 0x00100000 0x0 0xf000>, 21 <0x0 0x0010f000 0x0 0x1000>; 22 }; 23 24 gpio: gpio@2200000 { 25 compatible = "nvidia,tegra186-gpio"; 26 reg-names = "security", "gpio"; 27 reg = <0x0 0x2200000 0x0 0x10000>, 28 <0x0 0x2210000 0x0 0x10000>; 29 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 34 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 35 #interrupt-cells = <2>; 36 interrupt-controller; 37 #gpio-cells = <2>; 38 gpio-controller; 39 }; 40 41 ethernet@2490000 { 42 compatible = "nvidia,tegra186-eqos", 43 "snps,dwc-qos-ethernet-4.10"; 44 reg = <0x0 0x02490000 0x0 0x10000>; 45 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 46 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 47 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 48 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 49 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 50 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 51 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 52 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 53 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 54 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 55 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 56 <&bpmp TEGRA186_CLK_EQOS_AXI>, 57 <&bpmp TEGRA186_CLK_EQOS_RX>, 58 <&bpmp TEGRA186_CLK_EQOS_TX>, 59 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 60 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 61 resets = <&bpmp TEGRA186_RESET_EQOS>; 62 reset-names = "eqos"; 63 interconnects = <&mc TEGRA186_MEMORY_CLIENT_EQOSR &emc>, 64 <&mc TEGRA186_MEMORY_CLIENT_EQOSW &emc>; 65 interconnect-names = "dma-mem", "write"; 66 iommus = <&smmu TEGRA186_SID_EQOS>; 67 status = "disabled"; 68 69 snps,write-requests = <1>; 70 snps,read-requests = <3>; 71 snps,burst-map = <0x7>; 72 snps,txpbl = <32>; 73 snps,rxpbl = <8>; 74 }; 75 76 gpcdma: dma-controller@2600000 { 77 compatible = "nvidia,tegra186-gpcdma"; 78 reg = <0x0 0x2600000 0x0 0x210000>; 79 resets = <&bpmp TEGRA186_RESET_GPCDMA>; 80 reset-names = "gpcdma"; 81 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 87 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 88 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 89 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 90 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 91 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 92 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 94 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 108 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 109 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 110 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 111 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 112 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 113 #dma-cells = <1>; 114 iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 115 dma-coherent; 116 dma-channel-mask = <0xfffffffe>; 117 status = "okay"; 118 }; 119 120 aconnect@2900000 { 121 compatible = "nvidia,tegra186-aconnect", 122 "nvidia,tegra210-aconnect"; 123 clocks = <&bpmp TEGRA186_CLK_APE>, 124 <&bpmp TEGRA186_CLK_APB2APE>; 125 clock-names = "ape", "apb2ape"; 126 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>; 127 #address-cells = <1>; 128 #size-cells = <1>; 129 ranges = <0x02900000 0x0 0x02900000 0x200000>; 130 status = "disabled"; 131 132 tegra_ahub: ahub@2900800 { 133 compatible = "nvidia,tegra186-ahub"; 134 reg = <0x02900800 0x800>; 135 clocks = <&bpmp TEGRA186_CLK_AHUB>; 136 clock-names = "ahub"; 137 assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>; 138 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 139 #address-cells = <1>; 140 #size-cells = <1>; 141 ranges = <0x02900800 0x02900800 0x11800>; 142 status = "disabled"; 143 144 tegra_i2s1: i2s@2901000 { 145 compatible = "nvidia,tegra186-i2s", 146 "nvidia,tegra210-i2s"; 147 reg = <0x2901000 0x100>; 148 clocks = <&bpmp TEGRA186_CLK_I2S1>, 149 <&bpmp TEGRA186_CLK_I2S1_SYNC_INPUT>; 150 clock-names = "i2s", "sync_input"; 151 assigned-clocks = <&bpmp TEGRA186_CLK_I2S1>; 152 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 153 assigned-clock-rates = <1536000>; 154 sound-name-prefix = "I2S1"; 155 status = "disabled"; 156 }; 157 158 tegra_i2s2: i2s@2901100 { 159 compatible = "nvidia,tegra186-i2s", 160 "nvidia,tegra210-i2s"; 161 reg = <0x2901100 0x100>; 162 clocks = <&bpmp TEGRA186_CLK_I2S2>, 163 <&bpmp TEGRA186_CLK_I2S2_SYNC_INPUT>; 164 clock-names = "i2s", "sync_input"; 165 assigned-clocks = <&bpmp TEGRA186_CLK_I2S2>; 166 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 167 assigned-clock-rates = <1536000>; 168 sound-name-prefix = "I2S2"; 169 status = "disabled"; 170 }; 171 172 tegra_i2s3: i2s@2901200 { 173 compatible = "nvidia,tegra186-i2s", 174 "nvidia,tegra210-i2s"; 175 reg = <0x2901200 0x100>; 176 clocks = <&bpmp TEGRA186_CLK_I2S3>, 177 <&bpmp TEGRA186_CLK_I2S3_SYNC_INPUT>; 178 clock-names = "i2s", "sync_input"; 179 assigned-clocks = <&bpmp TEGRA186_CLK_I2S3>; 180 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 181 assigned-clock-rates = <1536000>; 182 sound-name-prefix = "I2S3"; 183 status = "disabled"; 184 }; 185 186 tegra_i2s4: i2s@2901300 { 187 compatible = "nvidia,tegra186-i2s", 188 "nvidia,tegra210-i2s"; 189 reg = <0x2901300 0x100>; 190 clocks = <&bpmp TEGRA186_CLK_I2S4>, 191 <&bpmp TEGRA186_CLK_I2S4_SYNC_INPUT>; 192 clock-names = "i2s", "sync_input"; 193 assigned-clocks = <&bpmp TEGRA186_CLK_I2S4>; 194 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 195 assigned-clock-rates = <1536000>; 196 sound-name-prefix = "I2S4"; 197 status = "disabled"; 198 }; 199 200 tegra_i2s5: i2s@2901400 { 201 compatible = "nvidia,tegra186-i2s", 202 "nvidia,tegra210-i2s"; 203 reg = <0x2901400 0x100>; 204 clocks = <&bpmp TEGRA186_CLK_I2S5>, 205 <&bpmp TEGRA186_CLK_I2S5_SYNC_INPUT>; 206 clock-names = "i2s", "sync_input"; 207 assigned-clocks = <&bpmp TEGRA186_CLK_I2S5>; 208 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 209 assigned-clock-rates = <1536000>; 210 sound-name-prefix = "I2S5"; 211 status = "disabled"; 212 }; 213 214 tegra_i2s6: i2s@2901500 { 215 compatible = "nvidia,tegra186-i2s", 216 "nvidia,tegra210-i2s"; 217 reg = <0x2901500 0x100>; 218 clocks = <&bpmp TEGRA186_CLK_I2S6>, 219 <&bpmp TEGRA186_CLK_I2S6_SYNC_INPUT>; 220 clock-names = "i2s", "sync_input"; 221 assigned-clocks = <&bpmp TEGRA186_CLK_I2S6>; 222 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 223 assigned-clock-rates = <1536000>; 224 sound-name-prefix = "I2S6"; 225 status = "disabled"; 226 }; 227 228 tegra_sfc1: sfc@2902000 { 229 compatible = "nvidia,tegra186-sfc", 230 "nvidia,tegra210-sfc"; 231 reg = <0x2902000 0x200>; 232 sound-name-prefix = "SFC1"; 233 status = "disabled"; 234 }; 235 236 tegra_sfc2: sfc@2902200 { 237 compatible = "nvidia,tegra186-sfc", 238 "nvidia,tegra210-sfc"; 239 reg = <0x2902200 0x200>; 240 sound-name-prefix = "SFC2"; 241 status = "disabled"; 242 }; 243 244 tegra_sfc3: sfc@2902400 { 245 compatible = "nvidia,tegra186-sfc", 246 "nvidia,tegra210-sfc"; 247 reg = <0x2902400 0x200>; 248 sound-name-prefix = "SFC3"; 249 status = "disabled"; 250 }; 251 252 tegra_sfc4: sfc@2902600 { 253 compatible = "nvidia,tegra186-sfc", 254 "nvidia,tegra210-sfc"; 255 reg = <0x2902600 0x200>; 256 sound-name-prefix = "SFC4"; 257 status = "disabled"; 258 }; 259 260 tegra_amx1: amx@2903000 { 261 compatible = "nvidia,tegra186-amx", 262 "nvidia,tegra210-amx"; 263 reg = <0x2903000 0x100>; 264 sound-name-prefix = "AMX1"; 265 status = "disabled"; 266 }; 267 268 tegra_amx2: amx@2903100 { 269 compatible = "nvidia,tegra186-amx", 270 "nvidia,tegra210-amx"; 271 reg = <0x2903100 0x100>; 272 sound-name-prefix = "AMX2"; 273 status = "disabled"; 274 }; 275 276 tegra_amx3: amx@2903200 { 277 compatible = "nvidia,tegra186-amx", 278 "nvidia,tegra210-amx"; 279 reg = <0x2903200 0x100>; 280 sound-name-prefix = "AMX3"; 281 status = "disabled"; 282 }; 283 284 tegra_amx4: amx@2903300 { 285 compatible = "nvidia,tegra186-amx", 286 "nvidia,tegra210-amx"; 287 reg = <0x2903300 0x100>; 288 sound-name-prefix = "AMX4"; 289 status = "disabled"; 290 }; 291 292 tegra_adx1: adx@2903800 { 293 compatible = "nvidia,tegra186-adx", 294 "nvidia,tegra210-adx"; 295 reg = <0x2903800 0x100>; 296 sound-name-prefix = "ADX1"; 297 status = "disabled"; 298 }; 299 300 tegra_adx2: adx@2903900 { 301 compatible = "nvidia,tegra186-adx", 302 "nvidia,tegra210-adx"; 303 reg = <0x2903900 0x100>; 304 sound-name-prefix = "ADX2"; 305 status = "disabled"; 306 }; 307 308 tegra_adx3: adx@2903a00 { 309 compatible = "nvidia,tegra186-adx", 310 "nvidia,tegra210-adx"; 311 reg = <0x2903a00 0x100>; 312 sound-name-prefix = "ADX3"; 313 status = "disabled"; 314 }; 315 316 tegra_adx4: adx@2903b00 { 317 compatible = "nvidia,tegra186-adx", 318 "nvidia,tegra210-adx"; 319 reg = <0x2903b00 0x100>; 320 sound-name-prefix = "ADX4"; 321 status = "disabled"; 322 }; 323 324 tegra_dmic1: dmic@2904000 { 325 compatible = "nvidia,tegra210-dmic"; 326 reg = <0x2904000 0x100>; 327 clocks = <&bpmp TEGRA186_CLK_DMIC1>; 328 clock-names = "dmic"; 329 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>; 330 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 331 assigned-clock-rates = <3072000>; 332 sound-name-prefix = "DMIC1"; 333 status = "disabled"; 334 }; 335 336 tegra_dmic2: dmic@2904100 { 337 compatible = "nvidia,tegra210-dmic"; 338 reg = <0x2904100 0x100>; 339 clocks = <&bpmp TEGRA186_CLK_DMIC2>; 340 clock-names = "dmic"; 341 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>; 342 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 343 assigned-clock-rates = <3072000>; 344 sound-name-prefix = "DMIC2"; 345 status = "disabled"; 346 }; 347 348 tegra_dmic3: dmic@2904200 { 349 compatible = "nvidia,tegra210-dmic"; 350 reg = <0x2904200 0x100>; 351 clocks = <&bpmp TEGRA186_CLK_DMIC3>; 352 clock-names = "dmic"; 353 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>; 354 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 355 assigned-clock-rates = <3072000>; 356 sound-name-prefix = "DMIC3"; 357 status = "disabled"; 358 }; 359 360 tegra_dmic4: dmic@2904300 { 361 compatible = "nvidia,tegra210-dmic"; 362 reg = <0x2904300 0x100>; 363 clocks = <&bpmp TEGRA186_CLK_DMIC4>; 364 clock-names = "dmic"; 365 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>; 366 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 367 assigned-clock-rates = <3072000>; 368 sound-name-prefix = "DMIC4"; 369 status = "disabled"; 370 }; 371 372 tegra_dspk1: dspk@2905000 { 373 compatible = "nvidia,tegra186-dspk"; 374 reg = <0x2905000 0x100>; 375 clocks = <&bpmp TEGRA186_CLK_DSPK1>; 376 clock-names = "dspk"; 377 assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>; 378 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 379 assigned-clock-rates = <12288000>; 380 sound-name-prefix = "DSPK1"; 381 status = "disabled"; 382 }; 383 384 tegra_dspk2: dspk@2905100 { 385 compatible = "nvidia,tegra186-dspk"; 386 reg = <0x2905100 0x100>; 387 clocks = <&bpmp TEGRA186_CLK_DSPK2>; 388 clock-names = "dspk"; 389 assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>; 390 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 391 assigned-clock-rates = <12288000>; 392 sound-name-prefix = "DSPK2"; 393 status = "disabled"; 394 }; 395 396 tegra_ope1: processing-engine@2908000 { 397 compatible = "nvidia,tegra186-ope", 398 "nvidia,tegra210-ope"; 399 reg = <0x2908000 0x100>; 400 #address-cells = <1>; 401 #size-cells = <1>; 402 ranges; 403 sound-name-prefix = "OPE1"; 404 status = "disabled"; 405 406 equalizer@2908100 { 407 compatible = "nvidia,tegra186-peq", 408 "nvidia,tegra210-peq"; 409 reg = <0x2908100 0x100>; 410 }; 411 412 dynamic-range-compressor@2908200 { 413 compatible = "nvidia,tegra186-mbdrc", 414 "nvidia,tegra210-mbdrc"; 415 reg = <0x2908200 0x200>; 416 }; 417 }; 418 419 tegra_mvc1: mvc@290a000 { 420 compatible = "nvidia,tegra186-mvc", 421 "nvidia,tegra210-mvc"; 422 reg = <0x290a000 0x200>; 423 sound-name-prefix = "MVC1"; 424 status = "disabled"; 425 }; 426 427 tegra_mvc2: mvc@290a200 { 428 compatible = "nvidia,tegra186-mvc", 429 "nvidia,tegra210-mvc"; 430 reg = <0x290a200 0x200>; 431 sound-name-prefix = "MVC2"; 432 status = "disabled"; 433 }; 434 435 tegra_amixer: amixer@290bb00 { 436 compatible = "nvidia,tegra186-amixer", 437 "nvidia,tegra210-amixer"; 438 reg = <0x290bb00 0x800>; 439 sound-name-prefix = "MIXER1"; 440 status = "disabled"; 441 }; 442 443 tegra_admaif: admaif@290f000 { 444 compatible = "nvidia,tegra186-admaif"; 445 reg = <0x0290f000 0x1000>; 446 dmas = <&adma 1>, <&adma 1>, 447 <&adma 2>, <&adma 2>, 448 <&adma 3>, <&adma 3>, 449 <&adma 4>, <&adma 4>, 450 <&adma 5>, <&adma 5>, 451 <&adma 6>, <&adma 6>, 452 <&adma 7>, <&adma 7>, 453 <&adma 8>, <&adma 8>, 454 <&adma 9>, <&adma 9>, 455 <&adma 10>, <&adma 10>, 456 <&adma 11>, <&adma 11>, 457 <&adma 12>, <&adma 12>, 458 <&adma 13>, <&adma 13>, 459 <&adma 14>, <&adma 14>, 460 <&adma 15>, <&adma 15>, 461 <&adma 16>, <&adma 16>, 462 <&adma 17>, <&adma 17>, 463 <&adma 18>, <&adma 18>, 464 <&adma 19>, <&adma 19>, 465 <&adma 20>, <&adma 20>; 466 dma-names = "rx1", "tx1", 467 "rx2", "tx2", 468 "rx3", "tx3", 469 "rx4", "tx4", 470 "rx5", "tx5", 471 "rx6", "tx6", 472 "rx7", "tx7", 473 "rx8", "tx8", 474 "rx9", "tx9", 475 "rx10", "tx10", 476 "rx11", "tx11", 477 "rx12", "tx12", 478 "rx13", "tx13", 479 "rx14", "tx14", 480 "rx15", "tx15", 481 "rx16", "tx16", 482 "rx17", "tx17", 483 "rx18", "tx18", 484 "rx19", "tx19", 485 "rx20", "tx20"; 486 status = "disabled"; 487 }; 488 489 tegra_asrc: asrc@2910000 { 490 compatible = "nvidia,tegra186-asrc"; 491 reg = <0x2910000 0x2000>; 492 sound-name-prefix = "ASRC1"; 493 status = "disabled"; 494 }; 495 }; 496 497 adma: dma-controller@2930000 { 498 compatible = "nvidia,tegra186-adma"; 499 reg = <0x02930000 0x20000>; 500 interrupt-parent = <&agic>; 501 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 502 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 503 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 504 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 505 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 506 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 507 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 508 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 509 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 510 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 511 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 519 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 522 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 523 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 525 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 526 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 527 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 528 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 533 #dma-cells = <1>; 534 clocks = <&bpmp TEGRA186_CLK_AHUB>; 535 clock-names = "d_audio"; 536 status = "disabled"; 537 }; 538 539 agic: interrupt-controller@2a40000 { 540 compatible = "nvidia,tegra186-agic", 541 "nvidia,tegra210-agic"; 542 #interrupt-cells = <3>; 543 interrupt-controller; 544 reg = <0x02a41000 0x1000>, 545 <0x02a42000 0x2000>; 546 interrupts = <GIC_SPI 145 547 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 548 clocks = <&bpmp TEGRA186_CLK_APE>; 549 clock-names = "clk"; 550 status = "disabled"; 551 }; 552 }; 553 554 mc: memory-controller@2c00000 { 555 compatible = "nvidia,tegra186-mc"; 556 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ 557 <0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */ 558 <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ 559 <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ 560 <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ 561 <0x0 0x02c50000 0x0 0x10000>; /* MC3 */ 562 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3"; 563 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 564 status = "disabled"; 565 566 #interconnect-cells = <1>; 567 #address-cells = <2>; 568 #size-cells = <2>; 569 570 ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>; 571 572 /* 573 * Memory clients have access to all 40 bits that the memory 574 * controller can address. 575 */ 576 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 577 578 emc: external-memory-controller@2c60000 { 579 compatible = "nvidia,tegra186-emc"; 580 reg = <0x0 0x02c60000 0x0 0x50000>; 581 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 582 clocks = <&bpmp TEGRA186_CLK_EMC>; 583 clock-names = "emc"; 584 585 #interconnect-cells = <0>; 586 587 nvidia,bpmp = <&bpmp>; 588 }; 589 }; 590 591 timer@3010000 { 592 compatible = "nvidia,tegra186-timer"; 593 reg = <0x0 0x03010000 0x0 0x000e0000>; 594 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 595 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 597 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 602 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 603 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 604 status = "okay"; 605 }; 606 607 uarta: serial@3100000 { 608 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 609 reg = <0x0 0x03100000 0x0 0x40>; 610 reg-shift = <2>; 611 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 612 clocks = <&bpmp TEGRA186_CLK_UARTA>; 613 clock-names = "serial"; 614 resets = <&bpmp TEGRA186_RESET_UARTA>; 615 reset-names = "serial"; 616 status = "disabled"; 617 }; 618 619 uartb: serial@3110000 { 620 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 621 reg = <0x0 0x03110000 0x0 0x40>; 622 reg-shift = <2>; 623 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 624 clocks = <&bpmp TEGRA186_CLK_UARTB>; 625 clock-names = "serial"; 626 resets = <&bpmp TEGRA186_RESET_UARTB>; 627 reset-names = "serial"; 628 status = "disabled"; 629 }; 630 631 uartd: serial@3130000 { 632 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 633 reg = <0x0 0x03130000 0x0 0x40>; 634 reg-shift = <2>; 635 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 636 clocks = <&bpmp TEGRA186_CLK_UARTD>; 637 clock-names = "serial"; 638 resets = <&bpmp TEGRA186_RESET_UARTD>; 639 reset-names = "serial"; 640 status = "disabled"; 641 }; 642 643 uarte: serial@3140000 { 644 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 645 reg = <0x0 0x03140000 0x0 0x40>; 646 reg-shift = <2>; 647 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 648 clocks = <&bpmp TEGRA186_CLK_UARTE>; 649 clock-names = "serial"; 650 resets = <&bpmp TEGRA186_RESET_UARTE>; 651 reset-names = "serial"; 652 status = "disabled"; 653 }; 654 655 uartf: serial@3150000 { 656 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 657 reg = <0x0 0x03150000 0x0 0x40>; 658 reg-shift = <2>; 659 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 660 clocks = <&bpmp TEGRA186_CLK_UARTF>; 661 clock-names = "serial"; 662 resets = <&bpmp TEGRA186_RESET_UARTF>; 663 reset-names = "serial"; 664 status = "disabled"; 665 }; 666 667 gen1_i2c: i2c@3160000 { 668 compatible = "nvidia,tegra186-i2c"; 669 reg = <0x0 0x03160000 0x0 0x10000>; 670 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 671 #address-cells = <1>; 672 #size-cells = <0>; 673 clocks = <&bpmp TEGRA186_CLK_I2C1>; 674 clock-names = "div-clk"; 675 resets = <&bpmp TEGRA186_RESET_I2C1>; 676 reset-names = "i2c"; 677 iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 678 dma-coherent; 679 dmas = <&gpcdma 21>, <&gpcdma 21>; 680 dma-names = "rx", "tx"; 681 status = "disabled"; 682 }; 683 684 cam_i2c: i2c@3180000 { 685 compatible = "nvidia,tegra186-i2c"; 686 reg = <0x0 0x03180000 0x0 0x10000>; 687 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 688 #address-cells = <1>; 689 #size-cells = <0>; 690 clocks = <&bpmp TEGRA186_CLK_I2C3>; 691 clock-names = "div-clk"; 692 resets = <&bpmp TEGRA186_RESET_I2C3>; 693 reset-names = "i2c"; 694 iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 695 dma-coherent; 696 dmas = <&gpcdma 23>, <&gpcdma 23>; 697 dma-names = "rx", "tx"; 698 status = "disabled"; 699 }; 700 701 /* shares pads with dpaux1 */ 702 dp_aux_ch1_i2c: i2c@3190000 { 703 compatible = "nvidia,tegra186-i2c"; 704 reg = <0x0 0x03190000 0x0 0x10000>; 705 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 706 #address-cells = <1>; 707 #size-cells = <0>; 708 clocks = <&bpmp TEGRA186_CLK_I2C4>; 709 clock-names = "div-clk"; 710 resets = <&bpmp TEGRA186_RESET_I2C4>; 711 reset-names = "i2c"; 712 pinctrl-names = "default", "idle"; 713 pinctrl-0 = <&state_dpaux1_i2c>; 714 pinctrl-1 = <&state_dpaux1_off>; 715 iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 716 dma-coherent; 717 dmas = <&gpcdma 26>, <&gpcdma 26>; 718 dma-names = "rx", "tx"; 719 status = "disabled"; 720 }; 721 722 /* controlled by BPMP, should not be enabled */ 723 pwr_i2c: i2c@31a0000 { 724 compatible = "nvidia,tegra186-i2c"; 725 reg = <0x0 0x031a0000 0x0 0x10000>; 726 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 727 #address-cells = <1>; 728 #size-cells = <0>; 729 clocks = <&bpmp TEGRA186_CLK_I2C5>; 730 clock-names = "div-clk"; 731 resets = <&bpmp TEGRA186_RESET_I2C5>; 732 reset-names = "i2c"; 733 status = "disabled"; 734 }; 735 736 /* shares pads with dpaux0 */ 737 dp_aux_ch0_i2c: i2c@31b0000 { 738 compatible = "nvidia,tegra186-i2c"; 739 reg = <0x0 0x031b0000 0x0 0x10000>; 740 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 741 #address-cells = <1>; 742 #size-cells = <0>; 743 clocks = <&bpmp TEGRA186_CLK_I2C6>; 744 clock-names = "div-clk"; 745 resets = <&bpmp TEGRA186_RESET_I2C6>; 746 reset-names = "i2c"; 747 pinctrl-names = "default", "idle"; 748 pinctrl-0 = <&state_dpaux_i2c>; 749 pinctrl-1 = <&state_dpaux_off>; 750 iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 751 dma-coherent; 752 dmas = <&gpcdma 30>, <&gpcdma 30>; 753 dma-names = "rx", "tx"; 754 status = "disabled"; 755 }; 756 757 gen7_i2c: i2c@31c0000 { 758 compatible = "nvidia,tegra186-i2c"; 759 reg = <0x0 0x031c0000 0x0 0x10000>; 760 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 761 #address-cells = <1>; 762 #size-cells = <0>; 763 clocks = <&bpmp TEGRA186_CLK_I2C7>; 764 clock-names = "div-clk"; 765 resets = <&bpmp TEGRA186_RESET_I2C7>; 766 reset-names = "i2c"; 767 iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 768 dma-coherent; 769 dmas = <&gpcdma 27>, <&gpcdma 27>; 770 dma-names = "rx", "tx"; 771 status = "disabled"; 772 }; 773 774 gen9_i2c: i2c@31e0000 { 775 compatible = "nvidia,tegra186-i2c"; 776 reg = <0x0 0x031e0000 0x0 0x10000>; 777 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 778 #address-cells = <1>; 779 #size-cells = <0>; 780 clocks = <&bpmp TEGRA186_CLK_I2C9>; 781 clock-names = "div-clk"; 782 resets = <&bpmp TEGRA186_RESET_I2C9>; 783 reset-names = "i2c"; 784 iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 785 dma-coherent; 786 dmas = <&gpcdma 31>, <&gpcdma 31>; 787 dma-names = "rx", "tx"; 788 status = "disabled"; 789 }; 790 791 pwm1: pwm@3280000 { 792 compatible = "nvidia,tegra186-pwm"; 793 reg = <0x0 0x3280000 0x0 0x10000>; 794 clocks = <&bpmp TEGRA186_CLK_PWM1>; 795 resets = <&bpmp TEGRA186_RESET_PWM1>; 796 reset-names = "pwm"; 797 status = "disabled"; 798 #pwm-cells = <2>; 799 }; 800 801 pwm2: pwm@3290000 { 802 compatible = "nvidia,tegra186-pwm"; 803 reg = <0x0 0x3290000 0x0 0x10000>; 804 clocks = <&bpmp TEGRA186_CLK_PWM2>; 805 resets = <&bpmp TEGRA186_RESET_PWM2>; 806 reset-names = "pwm"; 807 status = "disabled"; 808 #pwm-cells = <2>; 809 }; 810 811 pwm3: pwm@32a0000 { 812 compatible = "nvidia,tegra186-pwm"; 813 reg = <0x0 0x32a0000 0x0 0x10000>; 814 clocks = <&bpmp TEGRA186_CLK_PWM3>; 815 resets = <&bpmp TEGRA186_RESET_PWM3>; 816 reset-names = "pwm"; 817 status = "disabled"; 818 #pwm-cells = <2>; 819 }; 820 821 pwm5: pwm@32c0000 { 822 compatible = "nvidia,tegra186-pwm"; 823 reg = <0x0 0x32c0000 0x0 0x10000>; 824 clocks = <&bpmp TEGRA186_CLK_PWM5>; 825 resets = <&bpmp TEGRA186_RESET_PWM5>; 826 reset-names = "pwm"; 827 status = "disabled"; 828 #pwm-cells = <2>; 829 }; 830 831 pwm6: pwm@32d0000 { 832 compatible = "nvidia,tegra186-pwm"; 833 reg = <0x0 0x32d0000 0x0 0x10000>; 834 clocks = <&bpmp TEGRA186_CLK_PWM6>; 835 resets = <&bpmp TEGRA186_RESET_PWM6>; 836 reset-names = "pwm"; 837 status = "disabled"; 838 #pwm-cells = <2>; 839 }; 840 841 pwm7: pwm@32e0000 { 842 compatible = "nvidia,tegra186-pwm"; 843 reg = <0x0 0x32e0000 0x0 0x10000>; 844 clocks = <&bpmp TEGRA186_CLK_PWM7>; 845 resets = <&bpmp TEGRA186_RESET_PWM7>; 846 reset-names = "pwm"; 847 status = "disabled"; 848 #pwm-cells = <2>; 849 }; 850 851 pwm8: pwm@32f0000 { 852 compatible = "nvidia,tegra186-pwm"; 853 reg = <0x0 0x32f0000 0x0 0x10000>; 854 clocks = <&bpmp TEGRA186_CLK_PWM8>; 855 resets = <&bpmp TEGRA186_RESET_PWM8>; 856 reset-names = "pwm"; 857 status = "disabled"; 858 #pwm-cells = <2>; 859 }; 860 861 sdmmc1: mmc@3400000 { 862 compatible = "nvidia,tegra186-sdhci"; 863 reg = <0x0 0x03400000 0x0 0x10000>; 864 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 865 clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 866 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 867 clock-names = "sdhci", "tmclk"; 868 resets = <&bpmp TEGRA186_RESET_SDMMC1>; 869 reset-names = "sdhci"; 870 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>, 871 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>; 872 interconnect-names = "dma-mem", "write"; 873 iommus = <&smmu TEGRA186_SID_SDMMC1>; 874 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 875 pinctrl-0 = <&sdmmc1_3v3>; 876 pinctrl-1 = <&sdmmc1_1v8>; 877 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 878 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 879 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 880 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 881 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>; 882 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>; 883 nvidia,default-tap = <0x5>; 884 nvidia,default-trim = <0xb>; 885 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 886 <&bpmp TEGRA186_CLK_PLLP_OUT0>; 887 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; 888 status = "disabled"; 889 }; 890 891 sdmmc2: mmc@3420000 { 892 compatible = "nvidia,tegra186-sdhci"; 893 reg = <0x0 0x03420000 0x0 0x10000>; 894 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 895 clocks = <&bpmp TEGRA186_CLK_SDMMC2>, 896 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 897 clock-names = "sdhci", "tmclk"; 898 resets = <&bpmp TEGRA186_RESET_SDMMC2>; 899 reset-names = "sdhci"; 900 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAA &emc>, 901 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAA &emc>; 902 interconnect-names = "dma-mem", "write"; 903 iommus = <&smmu TEGRA186_SID_SDMMC2>; 904 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 905 pinctrl-0 = <&sdmmc2_3v3>; 906 pinctrl-1 = <&sdmmc2_1v8>; 907 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 908 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 909 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 910 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 911 nvidia,default-tap = <0x5>; 912 nvidia,default-trim = <0xb>; 913 status = "disabled"; 914 }; 915 916 sdmmc3: mmc@3440000 { 917 compatible = "nvidia,tegra186-sdhci"; 918 reg = <0x0 0x03440000 0x0 0x10000>; 919 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 920 clocks = <&bpmp TEGRA186_CLK_SDMMC3>, 921 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 922 clock-names = "sdhci", "tmclk"; 923 resets = <&bpmp TEGRA186_RESET_SDMMC3>; 924 reset-names = "sdhci"; 925 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCR &emc>, 926 <&mc TEGRA186_MEMORY_CLIENT_SDMMCW &emc>; 927 interconnect-names = "dma-mem", "write"; 928 iommus = <&smmu TEGRA186_SID_SDMMC3>; 929 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 930 pinctrl-0 = <&sdmmc3_3v3>; 931 pinctrl-1 = <&sdmmc3_1v8>; 932 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 933 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 934 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 935 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 936 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 937 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 938 nvidia,default-tap = <0x5>; 939 nvidia,default-trim = <0xb>; 940 status = "disabled"; 941 }; 942 943 sdmmc4: mmc@3460000 { 944 compatible = "nvidia,tegra186-sdhci"; 945 reg = <0x0 0x03460000 0x0 0x10000>; 946 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 947 clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 948 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 949 clock-names = "sdhci", "tmclk"; 950 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 951 <&bpmp TEGRA186_CLK_PLLC4_VCO>; 952 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>; 953 resets = <&bpmp TEGRA186_RESET_SDMMC4>; 954 reset-names = "sdhci"; 955 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAB &emc>, 956 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAB &emc>; 957 interconnect-names = "dma-mem", "write"; 958 iommus = <&smmu TEGRA186_SID_SDMMC4>; 959 nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>; 960 nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>; 961 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 962 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 963 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 964 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 965 nvidia,default-tap = <0x9>; 966 nvidia,default-trim = <0x5>; 967 nvidia,dqs-trim = <63>; 968 mmc-hs400-1_8v; 969 supports-cqe; 970 status = "disabled"; 971 }; 972 973 sata@3507000 { 974 compatible = "nvidia,tegra186-ahci"; 975 reg = <0x0 0x03507000 0x0 0x00002000>, /* AHCI */ 976 <0x0 0x03500000 0x0 0x00007000>, /* SATA */ 977 <0x0 0x03A90000 0x0 0x00010000>; /* SATA AUX */ 978 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 979 980 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_SAX>; 981 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SATAR &emc>, 982 <&mc TEGRA186_MEMORY_CLIENT_SATAW &emc>; 983 interconnect-names = "dma-mem", "write"; 984 iommus = <&smmu TEGRA186_SID_SATA>; 985 986 clocks = <&bpmp TEGRA186_CLK_SATA>, 987 <&bpmp TEGRA186_CLK_SATA_OOB>; 988 clock-names = "sata", "sata-oob"; 989 assigned-clocks = <&bpmp TEGRA186_CLK_SATA>, 990 <&bpmp TEGRA186_CLK_SATA_OOB>; 991 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>, 992 <&bpmp TEGRA186_CLK_PLLP>; 993 assigned-clock-rates = <102000000>, 994 <204000000>; 995 resets = <&bpmp TEGRA186_RESET_SATA>, 996 <&bpmp TEGRA186_RESET_SATACOLD>; 997 reset-names = "sata", "sata-cold"; 998 status = "disabled"; 999 }; 1000 1001 hda@3510000 { 1002 compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda"; 1003 reg = <0x0 0x03510000 0x0 0x10000>; 1004 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 1005 clocks = <&bpmp TEGRA186_CLK_HDA>, 1006 <&bpmp TEGRA186_CLK_HDA2HDMICODEC>, 1007 <&bpmp TEGRA186_CLK_HDA2CODEC_2X>; 1008 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 1009 resets = <&bpmp TEGRA186_RESET_HDA>, 1010 <&bpmp TEGRA186_RESET_HDA2HDMICODEC>, 1011 <&bpmp TEGRA186_RESET_HDA2CODEC_2X>; 1012 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 1013 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1014 interconnects = <&mc TEGRA186_MEMORY_CLIENT_HDAR &emc>, 1015 <&mc TEGRA186_MEMORY_CLIENT_HDAW &emc>; 1016 interconnect-names = "dma-mem", "write"; 1017 iommus = <&smmu TEGRA186_SID_HDA>; 1018 status = "disabled"; 1019 }; 1020 1021 padctl: padctl@3520000 { 1022 compatible = "nvidia,tegra186-xusb-padctl"; 1023 reg = <0x0 0x03520000 0x0 0x1000>, 1024 <0x0 0x03540000 0x0 0x1000>; 1025 reg-names = "padctl", "ao"; 1026 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1027 1028 resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>; 1029 reset-names = "padctl"; 1030 1031 status = "disabled"; 1032 1033 pads { 1034 usb2 { 1035 clocks = <&bpmp TEGRA186_CLK_USB2_TRK>; 1036 clock-names = "trk"; 1037 status = "disabled"; 1038 1039 lanes { 1040 usb2-0 { 1041 status = "disabled"; 1042 #phy-cells = <0>; 1043 }; 1044 1045 usb2-1 { 1046 status = "disabled"; 1047 #phy-cells = <0>; 1048 }; 1049 1050 usb2-2 { 1051 status = "disabled"; 1052 #phy-cells = <0>; 1053 }; 1054 }; 1055 }; 1056 1057 hsic { 1058 clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>; 1059 clock-names = "trk"; 1060 status = "disabled"; 1061 1062 lanes { 1063 hsic-0 { 1064 status = "disabled"; 1065 #phy-cells = <0>; 1066 }; 1067 }; 1068 }; 1069 1070 usb3 { 1071 status = "disabled"; 1072 1073 lanes { 1074 usb3-0 { 1075 status = "disabled"; 1076 #phy-cells = <0>; 1077 }; 1078 1079 usb3-1 { 1080 status = "disabled"; 1081 #phy-cells = <0>; 1082 }; 1083 1084 usb3-2 { 1085 status = "disabled"; 1086 #phy-cells = <0>; 1087 }; 1088 }; 1089 }; 1090 }; 1091 1092 ports { 1093 usb2-0 { 1094 status = "disabled"; 1095 }; 1096 1097 usb2-1 { 1098 status = "disabled"; 1099 }; 1100 1101 usb2-2 { 1102 status = "disabled"; 1103 }; 1104 1105 hsic-0 { 1106 status = "disabled"; 1107 }; 1108 1109 usb3-0 { 1110 status = "disabled"; 1111 }; 1112 1113 usb3-1 { 1114 status = "disabled"; 1115 }; 1116 1117 usb3-2 { 1118 status = "disabled"; 1119 }; 1120 }; 1121 }; 1122 1123 usb@3530000 { 1124 compatible = "nvidia,tegra186-xusb"; 1125 reg = <0x0 0x03530000 0x0 0x8000>, 1126 <0x0 0x03538000 0x0 0x1000>; 1127 reg-names = "hcd", "fpci"; 1128 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1129 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1130 clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>, 1131 <&bpmp TEGRA186_CLK_XUSB_FALCON>, 1132 <&bpmp TEGRA186_CLK_XUSB_SS>, 1133 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 1134 <&bpmp TEGRA186_CLK_CLK_M>, 1135 <&bpmp TEGRA186_CLK_XUSB_FS>, 1136 <&bpmp TEGRA186_CLK_PLLU>, 1137 <&bpmp TEGRA186_CLK_CLK_M>, 1138 <&bpmp TEGRA186_CLK_PLLE>; 1139 clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss", 1140 "xusb_ss_src", "xusb_hs_src", "xusb_fs_src", 1141 "pll_u_480m", "clk_m", "pll_e"; 1142 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>, 1143 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 1144 power-domain-names = "xusb_host", "xusb_ss"; 1145 interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1146 <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1147 interconnect-names = "dma-mem", "write"; 1148 iommus = <&smmu TEGRA186_SID_XUSB_HOST>; 1149 #address-cells = <1>; 1150 #size-cells = <0>; 1151 status = "disabled"; 1152 1153 nvidia,xusb-padctl = <&padctl>; 1154 }; 1155 1156 usb@3550000 { 1157 compatible = "nvidia,tegra186-xudc"; 1158 reg = <0x0 0x03550000 0x0 0x8000>, 1159 <0x0 0x03558000 0x0 0x1000>; 1160 reg-names = "base", "fpci"; 1161 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1162 clocks = <&bpmp TEGRA186_CLK_XUSB_CORE_DEV>, 1163 <&bpmp TEGRA186_CLK_XUSB_SS>, 1164 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 1165 <&bpmp TEGRA186_CLK_XUSB_FS>; 1166 clock-names = "dev", "ss", "ss_src", "fs_src"; 1167 interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVR &emc>, 1168 <&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVW &emc>; 1169 interconnect-names = "dma-mem", "write"; 1170 iommus = <&smmu TEGRA186_SID_XUSB_DEV>; 1171 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBB>, 1172 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 1173 power-domain-names = "dev", "ss"; 1174 nvidia,xusb-padctl = <&padctl>; 1175 status = "disabled"; 1176 }; 1177 1178 fuse@3820000 { 1179 compatible = "nvidia,tegra186-efuse"; 1180 reg = <0x0 0x03820000 0x0 0x10000>; 1181 clocks = <&bpmp TEGRA186_CLK_FUSE>; 1182 clock-names = "fuse"; 1183 }; 1184 1185 gic: interrupt-controller@3881000 { 1186 compatible = "arm,gic-400"; 1187 #interrupt-cells = <3>; 1188 interrupt-controller; 1189 reg = <0x0 0x03881000 0x0 0x1000>, 1190 <0x0 0x03882000 0x0 0x2000>, 1191 <0x0 0x03884000 0x0 0x2000>, 1192 <0x0 0x03886000 0x0 0x2000>; 1193 interrupts = <GIC_PPI 9 1194 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1195 interrupt-parent = <&gic>; 1196 }; 1197 1198 cec@3960000 { 1199 compatible = "nvidia,tegra186-cec"; 1200 reg = <0x0 0x03960000 0x0 0x10000>; 1201 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1202 clocks = <&bpmp TEGRA186_CLK_CEC>; 1203 clock-names = "cec"; 1204 status = "disabled"; 1205 }; 1206 1207 hsp_top0: hsp@3c00000 { 1208 compatible = "nvidia,tegra186-hsp"; 1209 reg = <0x0 0x03c00000 0x0 0xa0000>; 1210 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 1211 interrupt-names = "doorbell"; 1212 #mbox-cells = <2>; 1213 status = "disabled"; 1214 }; 1215 1216 gen2_i2c: i2c@c240000 { 1217 compatible = "nvidia,tegra186-i2c"; 1218 reg = <0x0 0x0c240000 0x0 0x10000>; 1219 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1220 #address-cells = <1>; 1221 #size-cells = <0>; 1222 clocks = <&bpmp TEGRA186_CLK_I2C2>; 1223 clock-names = "div-clk"; 1224 resets = <&bpmp TEGRA186_RESET_I2C2>; 1225 reset-names = "i2c"; 1226 iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 1227 dma-coherent; 1228 dmas = <&gpcdma 22>, <&gpcdma 22>; 1229 dma-names = "rx", "tx"; 1230 status = "disabled"; 1231 }; 1232 1233 gen8_i2c: i2c@c250000 { 1234 compatible = "nvidia,tegra186-i2c"; 1235 reg = <0x0 0x0c250000 0x0 0x10000>; 1236 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1237 #address-cells = <1>; 1238 #size-cells = <0>; 1239 clocks = <&bpmp TEGRA186_CLK_I2C8>; 1240 clock-names = "div-clk"; 1241 resets = <&bpmp TEGRA186_RESET_I2C8>; 1242 reset-names = "i2c"; 1243 iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 1244 dma-coherent; 1245 dmas = <&gpcdma 0>, <&gpcdma 0>; 1246 dma-names = "rx", "tx"; 1247 status = "disabled"; 1248 }; 1249 1250 uartc: serial@c280000 { 1251 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 1252 reg = <0x0 0x0c280000 0x0 0x40>; 1253 reg-shift = <2>; 1254 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1255 clocks = <&bpmp TEGRA186_CLK_UARTC>; 1256 clock-names = "serial"; 1257 resets = <&bpmp TEGRA186_RESET_UARTC>; 1258 reset-names = "serial"; 1259 status = "disabled"; 1260 }; 1261 1262 uartg: serial@c290000 { 1263 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 1264 reg = <0x0 0x0c290000 0x0 0x40>; 1265 reg-shift = <2>; 1266 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1267 clocks = <&bpmp TEGRA186_CLK_UARTG>; 1268 clock-names = "serial"; 1269 resets = <&bpmp TEGRA186_RESET_UARTG>; 1270 reset-names = "serial"; 1271 status = "disabled"; 1272 }; 1273 1274 rtc: rtc@c2a0000 { 1275 compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc"; 1276 reg = <0 0x0c2a0000 0 0x10000>; 1277 interrupt-parent = <&pmc>; 1278 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1279 clocks = <&bpmp TEGRA186_CLK_CLK_32K>; 1280 clock-names = "rtc"; 1281 status = "disabled"; 1282 }; 1283 1284 gpio_aon: gpio@c2f0000 { 1285 compatible = "nvidia,tegra186-gpio-aon"; 1286 reg-names = "security", "gpio"; 1287 reg = <0x0 0xc2f0000 0x0 0x1000>, 1288 <0x0 0xc2f1000 0x0 0x1000>; 1289 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 1290 gpio-controller; 1291 #gpio-cells = <2>; 1292 interrupt-controller; 1293 #interrupt-cells = <2>; 1294 }; 1295 1296 pwm4: pwm@c340000 { 1297 compatible = "nvidia,tegra186-pwm"; 1298 reg = <0x0 0xc340000 0x0 0x10000>; 1299 clocks = <&bpmp TEGRA186_CLK_PWM4>; 1300 resets = <&bpmp TEGRA186_RESET_PWM4>; 1301 reset-names = "pwm"; 1302 status = "disabled"; 1303 #pwm-cells = <2>; 1304 }; 1305 1306 pmc: pmc@c360000 { 1307 compatible = "nvidia,tegra186-pmc"; 1308 reg = <0 0x0c360000 0 0x10000>, 1309 <0 0x0c370000 0 0x10000>, 1310 <0 0x0c380000 0 0x10000>, 1311 <0 0x0c390000 0 0x10000>; 1312 reg-names = "pmc", "wake", "aotag", "scratch"; 1313 1314 #interrupt-cells = <2>; 1315 interrupt-controller; 1316 1317 sdmmc1_1v8: sdmmc1-1v8 { 1318 pins = "sdmmc1-hv"; 1319 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1320 }; 1321 1322 sdmmc1_3v3: sdmmc1-3v3 { 1323 pins = "sdmmc1-hv"; 1324 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1325 }; 1326 1327 sdmmc2_1v8: sdmmc2-1v8 { 1328 pins = "sdmmc2-hv"; 1329 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1330 }; 1331 1332 sdmmc2_3v3: sdmmc2-3v3 { 1333 pins = "sdmmc2-hv"; 1334 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1335 }; 1336 1337 sdmmc3_1v8: sdmmc3-1v8 { 1338 pins = "sdmmc3-hv"; 1339 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1340 }; 1341 1342 sdmmc3_3v3: sdmmc3-3v3 { 1343 pins = "sdmmc3-hv"; 1344 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1345 }; 1346 }; 1347 1348 ccplex@e000000 { 1349 compatible = "nvidia,tegra186-ccplex-cluster"; 1350 reg = <0x0 0x0e000000 0x0 0x400000>; 1351 1352 nvidia,bpmp = <&bpmp>; 1353 }; 1354 1355 pcie@10003000 { 1356 compatible = "nvidia,tegra186-pcie"; 1357 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 1358 device_type = "pci"; 1359 reg = <0x0 0x10003000 0x0 0x00000800>, /* PADS registers */ 1360 <0x0 0x10003800 0x0 0x00000800>, /* AFI registers */ 1361 <0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 1362 reg-names = "pads", "afi", "cs"; 1363 1364 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1365 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1366 interrupt-names = "intr", "msi"; 1367 1368 #interrupt-cells = <1>; 1369 interrupt-map-mask = <0 0 0 0>; 1370 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1371 1372 bus-range = <0x00 0xff>; 1373 #address-cells = <3>; 1374 #size-cells = <2>; 1375 1376 ranges = <0x02000000 0 0x10000000 0x0 0x10000000 0 0x00001000>, /* port 0 configuration space */ 1377 <0x02000000 0 0x10001000 0x0 0x10001000 0 0x00001000>,/* port 1 configuration space */ 1378 <0x02000000 0 0x10004000 0x0 0x10004000 0 0x00001000>, /* port 2 configuration space */ 1379 <0x01000000 0 0x0 0x0 0x50000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 1380 <0x02000000 0 0x50100000 0x0 0x50100000 0 0x07f00000>, /* non-prefetchable memory (127 MiB) */ 1381 <0x42000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 1382 1383 clocks = <&bpmp TEGRA186_CLK_PCIE>, 1384 <&bpmp TEGRA186_CLK_AFI>, 1385 <&bpmp TEGRA186_CLK_PLLE>; 1386 clock-names = "pex", "afi", "pll_e"; 1387 1388 resets = <&bpmp TEGRA186_RESET_PCIE>, 1389 <&bpmp TEGRA186_RESET_AFI>, 1390 <&bpmp TEGRA186_RESET_PCIEXCLK>; 1391 reset-names = "pex", "afi", "pcie_x"; 1392 1393 interconnects = <&mc TEGRA186_MEMORY_CLIENT_AFIR &emc>, 1394 <&mc TEGRA186_MEMORY_CLIENT_AFIW &emc>; 1395 interconnect-names = "dma-mem", "write"; 1396 1397 iommus = <&smmu TEGRA186_SID_AFI>; 1398 iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>; 1399 iommu-map-mask = <0x0>; 1400 1401 status = "disabled"; 1402 1403 pci@1,0 { 1404 device_type = "pci"; 1405 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 1406 reg = <0x000800 0 0 0 0>; 1407 status = "disabled"; 1408 1409 #address-cells = <3>; 1410 #size-cells = <2>; 1411 ranges; 1412 1413 nvidia,num-lanes = <2>; 1414 }; 1415 1416 pci@2,0 { 1417 device_type = "pci"; 1418 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 1419 reg = <0x001000 0 0 0 0>; 1420 status = "disabled"; 1421 1422 #address-cells = <3>; 1423 #size-cells = <2>; 1424 ranges; 1425 1426 nvidia,num-lanes = <1>; 1427 }; 1428 1429 pci@3,0 { 1430 device_type = "pci"; 1431 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 1432 reg = <0x001800 0 0 0 0>; 1433 status = "disabled"; 1434 1435 #address-cells = <3>; 1436 #size-cells = <2>; 1437 ranges; 1438 1439 nvidia,num-lanes = <1>; 1440 }; 1441 }; 1442 1443 smmu: iommu@12000000 { 1444 compatible = "nvidia,tegra186-smmu", "nvidia,smmu-500"; 1445 reg = <0 0x12000000 0 0x800000>; 1446 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1447 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1448 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1449 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1450 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1451 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1452 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1453 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1454 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1455 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1456 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1457 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1458 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1459 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1460 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1461 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1462 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1463 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1464 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1465 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1466 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1467 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1468 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1469 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1470 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1471 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1472 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1473 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1474 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1475 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1476 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1477 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1478 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1479 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1480 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1481 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1482 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1483 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1484 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1485 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1486 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1487 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1488 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1489 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1490 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1491 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1492 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1493 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1494 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1495 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1496 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1497 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1498 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1499 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1500 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1501 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1502 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1503 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1504 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1505 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1506 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1507 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1508 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1509 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1510 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1511 stream-match-mask = <0x7f80>; 1512 #global-interrupts = <1>; 1513 #iommu-cells = <1>; 1514 1515 nvidia,memory-controller = <&mc>; 1516 }; 1517 1518 host1x@13e00000 { 1519 compatible = "nvidia,tegra186-host1x"; 1520 reg = <0x0 0x13e00000 0x0 0x10000>, 1521 <0x0 0x13e10000 0x0 0x10000>; 1522 reg-names = "hypervisor", "vm"; 1523 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1524 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1525 interrupt-names = "syncpt", "host1x"; 1526 clocks = <&bpmp TEGRA186_CLK_HOST1X>; 1527 clock-names = "host1x"; 1528 resets = <&bpmp TEGRA186_RESET_HOST1X>; 1529 reset-names = "host1x"; 1530 1531 #address-cells = <1>; 1532 #size-cells = <1>; 1533 1534 ranges = <0x15000000 0x0 0x15000000 0x01000000>; 1535 1536 interconnects = <&mc TEGRA186_MEMORY_CLIENT_HOST1XDMAR &emc>; 1537 interconnect-names = "dma-mem"; 1538 1539 iommus = <&smmu TEGRA186_SID_HOST1X>; 1540 1541 /* Context isolation domains */ 1542 iommu-map = <0 &smmu TEGRA186_SID_HOST1X_CTX0 1>, 1543 <1 &smmu TEGRA186_SID_HOST1X_CTX1 1>, 1544 <2 &smmu TEGRA186_SID_HOST1X_CTX2 1>, 1545 <3 &smmu TEGRA186_SID_HOST1X_CTX3 1>, 1546 <4 &smmu TEGRA186_SID_HOST1X_CTX4 1>, 1547 <5 &smmu TEGRA186_SID_HOST1X_CTX5 1>, 1548 <6 &smmu TEGRA186_SID_HOST1X_CTX6 1>, 1549 <7 &smmu TEGRA186_SID_HOST1X_CTX7 1>; 1550 1551 dpaux1: dpaux@15040000 { 1552 compatible = "nvidia,tegra186-dpaux"; 1553 reg = <0x15040000 0x10000>; 1554 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1555 clocks = <&bpmp TEGRA186_CLK_DPAUX1>, 1556 <&bpmp TEGRA186_CLK_PLLDP>; 1557 clock-names = "dpaux", "parent"; 1558 resets = <&bpmp TEGRA186_RESET_DPAUX1>; 1559 reset-names = "dpaux"; 1560 status = "disabled"; 1561 1562 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1563 1564 state_dpaux1_aux: pinmux-aux { 1565 groups = "dpaux-io"; 1566 function = "aux"; 1567 }; 1568 1569 state_dpaux1_i2c: pinmux-i2c { 1570 groups = "dpaux-io"; 1571 function = "i2c"; 1572 }; 1573 1574 state_dpaux1_off: pinmux-off { 1575 groups = "dpaux-io"; 1576 function = "off"; 1577 }; 1578 1579 i2c-bus { 1580 #address-cells = <1>; 1581 #size-cells = <0>; 1582 }; 1583 }; 1584 1585 display-hub@15200000 { 1586 compatible = "nvidia,tegra186-display"; 1587 reg = <0x15200000 0x00040000>; 1588 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, 1589 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, 1590 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, 1591 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, 1592 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, 1593 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, 1594 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; 1595 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1596 "wgrp3", "wgrp4", "wgrp5"; 1597 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, 1598 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, 1599 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; 1600 clock-names = "disp", "dsc", "hub"; 1601 status = "disabled"; 1602 1603 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1604 1605 #address-cells = <1>; 1606 #size-cells = <1>; 1607 1608 ranges = <0x15200000 0x15200000 0x40000>; 1609 1610 display@15200000 { 1611 compatible = "nvidia,tegra186-dc"; 1612 reg = <0x15200000 0x10000>; 1613 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1614 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; 1615 clock-names = "dc"; 1616 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; 1617 reset-names = "dc"; 1618 1619 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1620 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1621 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1622 interconnect-names = "dma-mem", "read-1"; 1623 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1624 1625 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 1626 nvidia,head = <0>; 1627 }; 1628 1629 display@15210000 { 1630 compatible = "nvidia,tegra186-dc"; 1631 reg = <0x15210000 0x10000>; 1632 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1633 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; 1634 clock-names = "dc"; 1635 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; 1636 reset-names = "dc"; 1637 1638 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; 1639 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1640 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1641 interconnect-names = "dma-mem", "read-1"; 1642 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1643 1644 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 1645 nvidia,head = <1>; 1646 }; 1647 1648 display@15220000 { 1649 compatible = "nvidia,tegra186-dc"; 1650 reg = <0x15220000 0x10000>; 1651 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1652 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; 1653 clock-names = "dc"; 1654 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; 1655 reset-names = "dc"; 1656 1657 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; 1658 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1659 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1660 interconnect-names = "dma-mem", "read-1"; 1661 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1662 1663 nvidia,outputs = <&sor0 &sor1>; 1664 nvidia,head = <2>; 1665 }; 1666 }; 1667 1668 dsia: dsi@15300000 { 1669 compatible = "nvidia,tegra186-dsi"; 1670 reg = <0x15300000 0x10000>; 1671 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1672 clocks = <&bpmp TEGRA186_CLK_DSI>, 1673 <&bpmp TEGRA186_CLK_DSIA_LP>, 1674 <&bpmp TEGRA186_CLK_PLLD>; 1675 clock-names = "dsi", "lp", "parent"; 1676 resets = <&bpmp TEGRA186_RESET_DSI>; 1677 reset-names = "dsi"; 1678 status = "disabled"; 1679 1680 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1681 }; 1682 1683 vic@15340000 { 1684 compatible = "nvidia,tegra186-vic"; 1685 reg = <0x15340000 0x40000>; 1686 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1687 clocks = <&bpmp TEGRA186_CLK_VIC>; 1688 clock-names = "vic"; 1689 resets = <&bpmp TEGRA186_RESET_VIC>; 1690 reset-names = "vic"; 1691 1692 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 1693 interconnects = <&mc TEGRA186_MEMORY_CLIENT_VICSRD &emc>, 1694 <&mc TEGRA186_MEMORY_CLIENT_VICSWR &emc>; 1695 interconnect-names = "dma-mem", "write"; 1696 iommus = <&smmu TEGRA186_SID_VIC>; 1697 }; 1698 1699 nvjpg@15380000 { 1700 compatible = "nvidia,tegra186-nvjpg"; 1701 reg = <0x15380000 0x40000>; 1702 clocks = <&bpmp TEGRA186_CLK_NVJPG>; 1703 clock-names = "nvjpg"; 1704 resets = <&bpmp TEGRA186_RESET_NVJPG>; 1705 reset-names = "nvjpg"; 1706 1707 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVJPG>; 1708 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVJPGSRD &emc>, 1709 <&mc TEGRA186_MEMORY_CLIENT_NVJPGSWR &emc>; 1710 interconnect-names = "dma-mem", "write"; 1711 iommus = <&smmu TEGRA186_SID_NVJPG>; 1712 }; 1713 1714 dsib: dsi@15400000 { 1715 compatible = "nvidia,tegra186-dsi"; 1716 reg = <0x15400000 0x10000>; 1717 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1718 clocks = <&bpmp TEGRA186_CLK_DSIB>, 1719 <&bpmp TEGRA186_CLK_DSIB_LP>, 1720 <&bpmp TEGRA186_CLK_PLLD>; 1721 clock-names = "dsi", "lp", "parent"; 1722 resets = <&bpmp TEGRA186_RESET_DSIB>; 1723 reset-names = "dsi"; 1724 status = "disabled"; 1725 1726 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1727 }; 1728 1729 nvdec@15480000 { 1730 compatible = "nvidia,tegra186-nvdec"; 1731 reg = <0x15480000 0x40000>; 1732 clocks = <&bpmp TEGRA186_CLK_NVDEC>; 1733 clock-names = "nvdec"; 1734 resets = <&bpmp TEGRA186_RESET_NVDEC>; 1735 reset-names = "nvdec"; 1736 1737 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVDEC>; 1738 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD &emc>, 1739 <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD1 &emc>, 1740 <&mc TEGRA186_MEMORY_CLIENT_NVDECSWR &emc>; 1741 interconnect-names = "dma-mem", "read-1", "write"; 1742 iommus = <&smmu TEGRA186_SID_NVDEC>; 1743 }; 1744 1745 nvenc@154c0000 { 1746 compatible = "nvidia,tegra186-nvenc"; 1747 reg = <0x154c0000 0x40000>; 1748 clocks = <&bpmp TEGRA186_CLK_NVENC>; 1749 clock-names = "nvenc"; 1750 resets = <&bpmp TEGRA186_RESET_NVENC>; 1751 reset-names = "nvenc"; 1752 1753 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_MPE>; 1754 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVENCSRD &emc>, 1755 <&mc TEGRA186_MEMORY_CLIENT_NVENCSWR &emc>; 1756 interconnect-names = "dma-mem", "write"; 1757 iommus = <&smmu TEGRA186_SID_NVENC>; 1758 }; 1759 1760 sor0: sor@15540000 { 1761 compatible = "nvidia,tegra186-sor"; 1762 reg = <0x15540000 0x10000>; 1763 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1764 clocks = <&bpmp TEGRA186_CLK_SOR0>, 1765 <&bpmp TEGRA186_CLK_SOR0_OUT>, 1766 <&bpmp TEGRA186_CLK_PLLD2>, 1767 <&bpmp TEGRA186_CLK_PLLDP>, 1768 <&bpmp TEGRA186_CLK_SOR_SAFE>, 1769 <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>; 1770 clock-names = "sor", "out", "parent", "dp", "safe", 1771 "pad"; 1772 resets = <&bpmp TEGRA186_RESET_SOR0>; 1773 reset-names = "sor"; 1774 pinctrl-0 = <&state_dpaux_aux>; 1775 pinctrl-1 = <&state_dpaux_i2c>; 1776 pinctrl-2 = <&state_dpaux_off>; 1777 pinctrl-names = "aux", "i2c", "off"; 1778 status = "disabled"; 1779 1780 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1781 nvidia,interface = <0>; 1782 }; 1783 1784 sor1: sor@15580000 { 1785 compatible = "nvidia,tegra186-sor"; 1786 reg = <0x15580000 0x10000>; 1787 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1788 clocks = <&bpmp TEGRA186_CLK_SOR1>, 1789 <&bpmp TEGRA186_CLK_SOR1_OUT>, 1790 <&bpmp TEGRA186_CLK_PLLD3>, 1791 <&bpmp TEGRA186_CLK_PLLDP>, 1792 <&bpmp TEGRA186_CLK_SOR_SAFE>, 1793 <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>; 1794 clock-names = "sor", "out", "parent", "dp", "safe", 1795 "pad"; 1796 resets = <&bpmp TEGRA186_RESET_SOR1>; 1797 reset-names = "sor"; 1798 pinctrl-0 = <&state_dpaux1_aux>; 1799 pinctrl-1 = <&state_dpaux1_i2c>; 1800 pinctrl-2 = <&state_dpaux1_off>; 1801 pinctrl-names = "aux", "i2c", "off"; 1802 status = "disabled"; 1803 1804 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1805 nvidia,interface = <1>; 1806 }; 1807 1808 dpaux: dpaux@155c0000 { 1809 compatible = "nvidia,tegra186-dpaux"; 1810 reg = <0x155c0000 0x10000>; 1811 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1812 clocks = <&bpmp TEGRA186_CLK_DPAUX>, 1813 <&bpmp TEGRA186_CLK_PLLDP>; 1814 clock-names = "dpaux", "parent"; 1815 resets = <&bpmp TEGRA186_RESET_DPAUX>; 1816 reset-names = "dpaux"; 1817 status = "disabled"; 1818 1819 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1820 1821 state_dpaux_aux: pinmux-aux { 1822 groups = "dpaux-io"; 1823 function = "aux"; 1824 }; 1825 1826 state_dpaux_i2c: pinmux-i2c { 1827 groups = "dpaux-io"; 1828 function = "i2c"; 1829 }; 1830 1831 state_dpaux_off: pinmux-off { 1832 groups = "dpaux-io"; 1833 function = "off"; 1834 }; 1835 1836 i2c-bus { 1837 #address-cells = <1>; 1838 #size-cells = <0>; 1839 }; 1840 }; 1841 1842 padctl@15880000 { 1843 compatible = "nvidia,tegra186-dsi-padctl"; 1844 reg = <0x15880000 0x10000>; 1845 resets = <&bpmp TEGRA186_RESET_DSI>; 1846 reset-names = "dsi"; 1847 status = "disabled"; 1848 }; 1849 1850 dsic: dsi@15900000 { 1851 compatible = "nvidia,tegra186-dsi"; 1852 reg = <0x15900000 0x10000>; 1853 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1854 clocks = <&bpmp TEGRA186_CLK_DSIC>, 1855 <&bpmp TEGRA186_CLK_DSIC_LP>, 1856 <&bpmp TEGRA186_CLK_PLLD>; 1857 clock-names = "dsi", "lp", "parent"; 1858 resets = <&bpmp TEGRA186_RESET_DSIC>; 1859 reset-names = "dsi"; 1860 status = "disabled"; 1861 1862 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1863 }; 1864 1865 dsid: dsi@15940000 { 1866 compatible = "nvidia,tegra186-dsi"; 1867 reg = <0x15940000 0x10000>; 1868 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1869 clocks = <&bpmp TEGRA186_CLK_DSID>, 1870 <&bpmp TEGRA186_CLK_DSID_LP>, 1871 <&bpmp TEGRA186_CLK_PLLD>; 1872 clock-names = "dsi", "lp", "parent"; 1873 resets = <&bpmp TEGRA186_RESET_DSID>; 1874 reset-names = "dsi"; 1875 status = "disabled"; 1876 1877 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1878 }; 1879 }; 1880 1881 gpu@17000000 { 1882 compatible = "nvidia,gp10b"; 1883 reg = <0x0 0x17000000 0x0 0x1000000>, 1884 <0x0 0x18000000 0x0 0x1000000>; 1885 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 1886 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1887 interrupt-names = "stall", "nonstall"; 1888 1889 clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 1890 <&bpmp TEGRA186_CLK_GPU>; 1891 clock-names = "gpu", "pwr"; 1892 resets = <&bpmp TEGRA186_RESET_GPU>; 1893 reset-names = "gpu"; 1894 status = "disabled"; 1895 1896 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 1897 interconnects = <&mc TEGRA186_MEMORY_CLIENT_GPUSRD &emc>, 1898 <&mc TEGRA186_MEMORY_CLIENT_GPUSWR &emc>, 1899 <&mc TEGRA186_MEMORY_CLIENT_GPUSRD2 &emc>, 1900 <&mc TEGRA186_MEMORY_CLIENT_GPUSWR2 &emc>; 1901 interconnect-names = "dma-mem", "write-0", "read-1", "write-1"; 1902 }; 1903 1904 sram@30000000 { 1905 compatible = "nvidia,tegra186-sysram", "mmio-sram"; 1906 reg = <0x0 0x30000000 0x0 0x50000>; 1907 #address-cells = <1>; 1908 #size-cells = <1>; 1909 ranges = <0x0 0x0 0x30000000 0x50000>; 1910 no-memory-wc; 1911 1912 cpu_bpmp_tx: sram@4e000 { 1913 reg = <0x4e000 0x1000>; 1914 label = "cpu-bpmp-tx"; 1915 pool; 1916 }; 1917 1918 cpu_bpmp_rx: sram@4f000 { 1919 reg = <0x4f000 0x1000>; 1920 label = "cpu-bpmp-rx"; 1921 pool; 1922 }; 1923 }; 1924 1925 bpmp: bpmp { 1926 compatible = "nvidia,tegra186-bpmp"; 1927 interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>, 1928 <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>, 1929 <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>, 1930 <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>; 1931 interconnect-names = "read", "write", "dma-mem", "dma-write"; 1932 iommus = <&smmu TEGRA186_SID_BPMP>; 1933 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 1934 TEGRA_HSP_DB_MASTER_BPMP>; 1935 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 1936 #clock-cells = <1>; 1937 #reset-cells = <1>; 1938 #power-domain-cells = <1>; 1939 1940 bpmp_i2c: i2c { 1941 compatible = "nvidia,tegra186-bpmp-i2c"; 1942 nvidia,bpmp-bus-id = <5>; 1943 #address-cells = <1>; 1944 #size-cells = <0>; 1945 status = "disabled"; 1946 }; 1947 1948 bpmp_thermal: thermal { 1949 compatible = "nvidia,tegra186-bpmp-thermal"; 1950 #thermal-sensor-cells = <1>; 1951 }; 1952 }; 1953 1954 cpus { 1955 #address-cells = <1>; 1956 #size-cells = <0>; 1957 1958 denver_0: cpu@0 { 1959 compatible = "nvidia,tegra186-denver"; 1960 device_type = "cpu"; 1961 i-cache-size = <0x20000>; 1962 i-cache-line-size = <64>; 1963 i-cache-sets = <512>; 1964 d-cache-size = <0x10000>; 1965 d-cache-line-size = <64>; 1966 d-cache-sets = <256>; 1967 next-level-cache = <&L2_DENVER>; 1968 reg = <0x000>; 1969 }; 1970 1971 denver_1: cpu@1 { 1972 compatible = "nvidia,tegra186-denver"; 1973 device_type = "cpu"; 1974 i-cache-size = <0x20000>; 1975 i-cache-line-size = <64>; 1976 i-cache-sets = <512>; 1977 d-cache-size = <0x10000>; 1978 d-cache-line-size = <64>; 1979 d-cache-sets = <256>; 1980 next-level-cache = <&L2_DENVER>; 1981 reg = <0x001>; 1982 }; 1983 1984 ca57_0: cpu@2 { 1985 compatible = "arm,cortex-a57"; 1986 device_type = "cpu"; 1987 i-cache-size = <0xC000>; 1988 i-cache-line-size = <64>; 1989 i-cache-sets = <256>; 1990 d-cache-size = <0x8000>; 1991 d-cache-line-size = <64>; 1992 d-cache-sets = <256>; 1993 next-level-cache = <&L2_A57>; 1994 reg = <0x100>; 1995 }; 1996 1997 ca57_1: cpu@3 { 1998 compatible = "arm,cortex-a57"; 1999 device_type = "cpu"; 2000 i-cache-size = <0xC000>; 2001 i-cache-line-size = <64>; 2002 i-cache-sets = <256>; 2003 d-cache-size = <0x8000>; 2004 d-cache-line-size = <64>; 2005 d-cache-sets = <256>; 2006 next-level-cache = <&L2_A57>; 2007 reg = <0x101>; 2008 }; 2009 2010 ca57_2: cpu@4 { 2011 compatible = "arm,cortex-a57"; 2012 device_type = "cpu"; 2013 i-cache-size = <0xC000>; 2014 i-cache-line-size = <64>; 2015 i-cache-sets = <256>; 2016 d-cache-size = <0x8000>; 2017 d-cache-line-size = <64>; 2018 d-cache-sets = <256>; 2019 next-level-cache = <&L2_A57>; 2020 reg = <0x102>; 2021 }; 2022 2023 ca57_3: cpu@5 { 2024 compatible = "arm,cortex-a57"; 2025 device_type = "cpu"; 2026 i-cache-size = <0xC000>; 2027 i-cache-line-size = <64>; 2028 i-cache-sets = <256>; 2029 d-cache-size = <0x8000>; 2030 d-cache-line-size = <64>; 2031 d-cache-sets = <256>; 2032 next-level-cache = <&L2_A57>; 2033 reg = <0x103>; 2034 }; 2035 2036 L2_DENVER: l2-cache0 { 2037 compatible = "cache"; 2038 cache-unified; 2039 cache-level = <2>; 2040 cache-size = <0x200000>; 2041 cache-line-size = <64>; 2042 cache-sets = <2048>; 2043 }; 2044 2045 L2_A57: l2-cache1 { 2046 compatible = "cache"; 2047 cache-unified; 2048 cache-level = <2>; 2049 cache-size = <0x200000>; 2050 cache-line-size = <64>; 2051 cache-sets = <2048>; 2052 }; 2053 }; 2054 2055 pmu-a57 { 2056 compatible = "arm,cortex-a57-pmu"; 2057 interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 2058 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 2059 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 2060 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 2061 interrupt-affinity = <&ca57_0 &ca57_1 &ca57_2 &ca57_3>; 2062 }; 2063 2064 pmu-denver { 2065 compatible = "nvidia,denver-pmu"; 2066 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2067 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 2068 interrupt-affinity = <&denver_0 &denver_1>; 2069 }; 2070 2071 sound { 2072 status = "disabled"; 2073 2074 clocks = <&bpmp TEGRA186_CLK_PLLA>, 2075 <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 2076 clock-names = "pll_a", "plla_out0"; 2077 assigned-clocks = <&bpmp TEGRA186_CLK_PLLA>, 2078 <&bpmp TEGRA186_CLK_PLL_A_OUT0>, 2079 <&bpmp TEGRA186_CLK_AUD_MCLK>; 2080 assigned-clock-parents = <0>, 2081 <&bpmp TEGRA186_CLK_PLLA>, 2082 <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 2083 /* 2084 * PLLA supports dynamic ramp. Below initial rate is chosen 2085 * for this to work and oscillate between base rates required 2086 * for 8x and 11.025x sample rate streams. 2087 */ 2088 assigned-clock-rates = <258000000>; 2089 2090 iommus = <&smmu TEGRA186_SID_APE>; 2091 }; 2092 2093 thermal-zones { 2094 /* Cortex-A57 cluster */ 2095 cpu-thermal { 2096 polling-delay = <0>; 2097 polling-delay-passive = <1000>; 2098 2099 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 2100 2101 trips { 2102 critical { 2103 temperature = <101000>; 2104 hysteresis = <0>; 2105 type = "critical"; 2106 }; 2107 }; 2108 2109 cooling-maps { 2110 }; 2111 }; 2112 2113 /* Denver cluster */ 2114 aux-thermal { 2115 polling-delay = <0>; 2116 polling-delay-passive = <1000>; 2117 2118 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 2119 2120 trips { 2121 critical { 2122 temperature = <101000>; 2123 hysteresis = <0>; 2124 type = "critical"; 2125 }; 2126 }; 2127 2128 cooling-maps { 2129 }; 2130 }; 2131 2132 gpu-thermal { 2133 polling-delay = <0>; 2134 polling-delay-passive = <1000>; 2135 2136 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 2137 2138 trips { 2139 critical { 2140 temperature = <101000>; 2141 hysteresis = <0>; 2142 type = "critical"; 2143 }; 2144 }; 2145 2146 cooling-maps { 2147 }; 2148 }; 2149 2150 pll-thermal { 2151 polling-delay = <0>; 2152 polling-delay-passive = <1000>; 2153 2154 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 2155 2156 trips { 2157 critical { 2158 temperature = <101000>; 2159 hysteresis = <0>; 2160 type = "critical"; 2161 }; 2162 }; 2163 2164 cooling-maps { 2165 }; 2166 }; 2167 2168 ao-thermal { 2169 polling-delay = <0>; 2170 polling-delay-passive = <1000>; 2171 2172 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 2173 2174 trips { 2175 critical { 2176 temperature = <101000>; 2177 hysteresis = <0>; 2178 type = "critical"; 2179 }; 2180 }; 2181 2182 cooling-maps { 2183 }; 2184 }; 2185 }; 2186 2187 timer { 2188 compatible = "arm,armv8-timer"; 2189 interrupts = <GIC_PPI 13 2190 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2191 <GIC_PPI 14 2192 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2193 <GIC_PPI 11 2194 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2195 <GIC_PPI 10 2196 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2197 interrupt-parent = <&gic>; 2198 always-on; 2199 }; 2200}; 2201