1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * QLogic Fibre Channel HBA Driver 4 * Copyright (c) 2003-2014 QLogic Corporation 5 */ 6 #ifndef __QLA_DEF_H 7 #define __QLA_DEF_H 8 9 #include <linux/kernel.h> 10 #include <linux/init.h> 11 #include <linux/types.h> 12 #include <linux/module.h> 13 #include <linux/list.h> 14 #include <linux/pci.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/sched.h> 17 #include <linux/slab.h> 18 #include <linux/dmapool.h> 19 #include <linux/mempool.h> 20 #include <linux/spinlock.h> 21 #include <linux/completion.h> 22 #include <linux/interrupt.h> 23 #include <linux/workqueue.h> 24 #include <linux/firmware.h> 25 #include <linux/aer.h> 26 #include <linux/mutex.h> 27 #include <linux/btree.h> 28 29 #include <scsi/scsi.h> 30 #include <scsi/scsi_host.h> 31 #include <scsi/scsi_device.h> 32 #include <scsi/scsi_cmnd.h> 33 #include <scsi/scsi_transport_fc.h> 34 #include <scsi/scsi_bsg_fc.h> 35 36 #include <uapi/scsi/fc/fc_els.h> 37 38 #define QLA_DFS_DEFINE_DENTRY(_debugfs_file_name) \ 39 struct dentry *dfs_##_debugfs_file_name 40 #define QLA_DFS_ROOT_DEFINE_DENTRY(_debugfs_file_name) \ 41 struct dentry *qla_dfs_##_debugfs_file_name 42 43 /* Big endian Fibre Channel S_ID (source ID) or D_ID (destination ID). */ 44 typedef struct { 45 uint8_t domain; 46 uint8_t area; 47 uint8_t al_pa; 48 } be_id_t; 49 50 /* Little endian Fibre Channel S_ID (source ID) or D_ID (destination ID). */ 51 typedef struct { 52 uint8_t al_pa; 53 uint8_t area; 54 uint8_t domain; 55 } le_id_t; 56 57 /* 58 * 24 bit port ID type definition. 59 */ 60 typedef union { 61 uint32_t b24 : 24; 62 struct { 63 #ifdef __BIG_ENDIAN 64 uint8_t domain; 65 uint8_t area; 66 uint8_t al_pa; 67 #elif defined(__LITTLE_ENDIAN) 68 uint8_t al_pa; 69 uint8_t area; 70 uint8_t domain; 71 #else 72 #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!" 73 #endif 74 uint8_t rsvd_1; 75 } b; 76 } port_id_t; 77 #define INVALID_PORT_ID 0xFFFFFF 78 79 #include "qla_bsg.h" 80 #include "qla_dsd.h" 81 #include "qla_nx.h" 82 #include "qla_nx2.h" 83 #include "qla_nvme.h" 84 #define QLA2XXX_DRIVER_NAME "qla2xxx" 85 #define QLA2XXX_APIDEV "ql2xapidev" 86 #define QLA2XXX_MANUFACTURER "Marvell Semiconductor, Inc." 87 88 /* 89 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places, 90 * but that's fine as we don't look at the last 24 ones for 91 * ISP2100 HBAs. 92 */ 93 #define MAILBOX_REGISTER_COUNT_2100 8 94 #define MAILBOX_REGISTER_COUNT_2200 24 95 #define MAILBOX_REGISTER_COUNT 32 96 97 #define QLA2200A_RISC_ROM_VER 4 98 #define FPM_2300 6 99 #define FPM_2310 7 100 101 #include "qla_settings.h" 102 103 #define MODE_DUAL (MODE_TARGET | MODE_INITIATOR) 104 105 /* 106 * Data bit definitions 107 */ 108 #define BIT_0 0x1 109 #define BIT_1 0x2 110 #define BIT_2 0x4 111 #define BIT_3 0x8 112 #define BIT_4 0x10 113 #define BIT_5 0x20 114 #define BIT_6 0x40 115 #define BIT_7 0x80 116 #define BIT_8 0x100 117 #define BIT_9 0x200 118 #define BIT_10 0x400 119 #define BIT_11 0x800 120 #define BIT_12 0x1000 121 #define BIT_13 0x2000 122 #define BIT_14 0x4000 123 #define BIT_15 0x8000 124 #define BIT_16 0x10000 125 #define BIT_17 0x20000 126 #define BIT_18 0x40000 127 #define BIT_19 0x80000 128 #define BIT_20 0x100000 129 #define BIT_21 0x200000 130 #define BIT_22 0x400000 131 #define BIT_23 0x800000 132 #define BIT_24 0x1000000 133 #define BIT_25 0x2000000 134 #define BIT_26 0x4000000 135 #define BIT_27 0x8000000 136 #define BIT_28 0x10000000 137 #define BIT_29 0x20000000 138 #define BIT_30 0x40000000 139 #define BIT_31 0x80000000 140 141 #define LSB(x) ((uint8_t)(x)) 142 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8)) 143 144 #define LSW(x) ((uint16_t)(x)) 145 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16)) 146 147 #define LSD(x) ((uint32_t)((uint64_t)(x))) 148 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16)) 149 150 static inline uint32_t make_handle(uint16_t x, uint16_t y) 151 { 152 return ((uint32_t)x << 16) | y; 153 } 154 155 /* 156 * I/O register 157 */ 158 159 static inline u8 rd_reg_byte(const volatile u8 __iomem *addr) 160 { 161 return readb(addr); 162 } 163 164 static inline u16 rd_reg_word(const volatile __le16 __iomem *addr) 165 { 166 return readw(addr); 167 } 168 169 static inline u32 rd_reg_dword(const volatile __le32 __iomem *addr) 170 { 171 return readl(addr); 172 } 173 174 static inline u8 rd_reg_byte_relaxed(const volatile u8 __iomem *addr) 175 { 176 return readb_relaxed(addr); 177 } 178 179 static inline u16 rd_reg_word_relaxed(const volatile __le16 __iomem *addr) 180 { 181 return readw_relaxed(addr); 182 } 183 184 static inline u32 rd_reg_dword_relaxed(const volatile __le32 __iomem *addr) 185 { 186 return readl_relaxed(addr); 187 } 188 189 static inline void wrt_reg_byte(volatile u8 __iomem *addr, u8 data) 190 { 191 return writeb(data, addr); 192 } 193 194 static inline void wrt_reg_word(volatile __le16 __iomem *addr, u16 data) 195 { 196 return writew(data, addr); 197 } 198 199 static inline void wrt_reg_dword(volatile __le32 __iomem *addr, u32 data) 200 { 201 return writel(data, addr); 202 } 203 204 /* 205 * ISP83XX specific remote register addresses 206 */ 207 #define QLA83XX_LED_PORT0 0x00201320 208 #define QLA83XX_LED_PORT1 0x00201328 209 #define QLA83XX_IDC_DEV_STATE 0x22102384 210 #define QLA83XX_IDC_MAJOR_VERSION 0x22102380 211 #define QLA83XX_IDC_MINOR_VERSION 0x22102398 212 #define QLA83XX_IDC_DRV_PRESENCE 0x22102388 213 #define QLA83XX_IDC_DRIVER_ACK 0x2210238c 214 #define QLA83XX_IDC_CONTROL 0x22102390 215 #define QLA83XX_IDC_AUDIT 0x22102394 216 #define QLA83XX_IDC_LOCK_RECOVERY 0x2210239c 217 #define QLA83XX_DRIVER_LOCKID 0x22102104 218 #define QLA83XX_DRIVER_LOCK 0x8111c028 219 #define QLA83XX_DRIVER_UNLOCK 0x8111c02c 220 #define QLA83XX_FLASH_LOCKID 0x22102100 221 #define QLA83XX_FLASH_LOCK 0x8111c010 222 #define QLA83XX_FLASH_UNLOCK 0x8111c014 223 #define QLA83XX_DEV_PARTINFO1 0x221023e0 224 #define QLA83XX_DEV_PARTINFO2 0x221023e4 225 #define QLA83XX_FW_HEARTBEAT 0x221020b0 226 #define QLA83XX_PEG_HALT_STATUS1 0x221020a8 227 #define QLA83XX_PEG_HALT_STATUS2 0x221020ac 228 229 /* 83XX: Macros defining 8200 AEN Reason codes */ 230 #define IDC_DEVICE_STATE_CHANGE BIT_0 231 #define IDC_PEG_HALT_STATUS_CHANGE BIT_1 232 #define IDC_NIC_FW_REPORTED_FAILURE BIT_2 233 #define IDC_HEARTBEAT_FAILURE BIT_3 234 235 /* 83XX: Macros defining 8200 AEN Error-levels */ 236 #define ERR_LEVEL_NON_FATAL 0x1 237 #define ERR_LEVEL_RECOVERABLE_FATAL 0x2 238 #define ERR_LEVEL_UNRECOVERABLE_FATAL 0x4 239 240 /* 83XX: Macros for IDC Version */ 241 #define QLA83XX_SUPP_IDC_MAJOR_VERSION 0x01 242 #define QLA83XX_SUPP_IDC_MINOR_VERSION 0x0 243 244 /* 83XX: Macros for scheduling dpc tasks */ 245 #define QLA83XX_NIC_CORE_RESET 0x1 246 #define QLA83XX_IDC_STATE_HANDLER 0x2 247 #define QLA83XX_NIC_CORE_UNRECOVERABLE 0x3 248 249 /* 83XX: Macros for defining IDC-Control bits */ 250 #define QLA83XX_IDC_RESET_DISABLED BIT_0 251 #define QLA83XX_IDC_GRACEFUL_RESET BIT_1 252 253 /* 83XX: Macros for different timeouts */ 254 #define QLA83XX_IDC_INITIALIZATION_TIMEOUT 30 255 #define QLA83XX_IDC_RESET_ACK_TIMEOUT 10 256 #define QLA83XX_MAX_LOCK_RECOVERY_WAIT (2 * HZ) 257 258 /* 83XX: Macros for defining class in DEV-Partition Info register */ 259 #define QLA83XX_CLASS_TYPE_NONE 0x0 260 #define QLA83XX_CLASS_TYPE_NIC 0x1 261 #define QLA83XX_CLASS_TYPE_FCOE 0x2 262 #define QLA83XX_CLASS_TYPE_ISCSI 0x3 263 264 /* 83XX: Macros for IDC Lock-Recovery stages */ 265 #define IDC_LOCK_RECOVERY_STAGE1 0x1 /* Stage1: Intent for 266 * lock-recovery 267 */ 268 #define IDC_LOCK_RECOVERY_STAGE2 0x2 /* Stage2: Perform lock-recovery */ 269 270 /* 83XX: Macros for IDC Audit type */ 271 #define IDC_AUDIT_TIMESTAMP 0x0 /* IDC-AUDIT: Record timestamp of 272 * dev-state change to NEED-RESET 273 * or NEED-QUIESCENT 274 */ 275 #define IDC_AUDIT_COMPLETION 0x1 /* IDC-AUDIT: Record duration of 276 * reset-recovery completion is 277 * second 278 */ 279 /* ISP2031: Values for laser on/off */ 280 #define PORT_0_2031 0x00201340 281 #define PORT_1_2031 0x00201350 282 #define LASER_ON_2031 0x01800100 283 #define LASER_OFF_2031 0x01800180 284 285 /* 286 * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an 287 * 133Mhz slot. 288 */ 289 #define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr)) 290 #define WRT_REG_WORD_PIO(addr, data) (outw(data, (unsigned long)addr)) 291 292 /* 293 * Fibre Channel device definitions. 294 */ 295 #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */ 296 #define MAX_FIBRE_DEVICES_2100 512 297 #define MAX_FIBRE_DEVICES_2400 2048 298 #define MAX_FIBRE_DEVICES_LOOP 128 299 #define MAX_FIBRE_DEVICES_MAX MAX_FIBRE_DEVICES_2400 300 #define LOOPID_MAP_SIZE (ha->max_fibre_devices) 301 #define MAX_FIBRE_LUNS 0xFFFF 302 #define MAX_HOST_COUNT 16 303 304 /* 305 * Host adapter default definitions. 306 */ 307 #define MAX_BUSES 1 /* We only have one bus today */ 308 #define MIN_LUNS 8 309 #define MAX_LUNS MAX_FIBRE_LUNS 310 #define MAX_CMDS_PER_LUN 255 311 312 /* 313 * Fibre Channel device definitions. 314 */ 315 #define SNS_LAST_LOOP_ID_2100 0xfe 316 #define SNS_LAST_LOOP_ID_2300 0x7ff 317 318 #define LAST_LOCAL_LOOP_ID 0x7d 319 #define SNS_FL_PORT 0x7e 320 #define FABRIC_CONTROLLER 0x7f 321 #define SIMPLE_NAME_SERVER 0x80 322 #define SNS_FIRST_LOOP_ID 0x81 323 #define MANAGEMENT_SERVER 0xfe 324 #define BROADCAST 0xff 325 326 /* 327 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the 328 * valid range of an N-PORT id is 0 through 0x7ef. 329 */ 330 #define NPH_LAST_HANDLE 0x7ee 331 #define NPH_MGMT_SERVER 0x7ef /* FFFFEF */ 332 #define NPH_SNS 0x7fc /* FFFFFC */ 333 #define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */ 334 #define NPH_F_PORT 0x7fe /* FFFFFE */ 335 #define NPH_IP_BROADCAST 0x7ff /* FFFFFF */ 336 337 #define NPH_SNS_LID(ha) (IS_FWI2_CAPABLE(ha) ? NPH_SNS : SIMPLE_NAME_SERVER) 338 339 #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */ 340 #include "qla_fw.h" 341 342 struct name_list_extended { 343 struct get_name_list_extended *l; 344 dma_addr_t ldma; 345 struct list_head fcports; 346 u32 size; 347 u8 sent; 348 }; 349 350 struct els_reject { 351 struct fc_els_ls_rjt *c; 352 dma_addr_t cdma; 353 u16 size; 354 }; 355 356 /* 357 * Timeout timer counts in seconds 358 */ 359 #define PORT_RETRY_TIME 1 360 #define LOOP_DOWN_TIMEOUT 60 361 #define LOOP_DOWN_TIME 255 /* 240 */ 362 #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30) 363 364 #define DEFAULT_OUTSTANDING_COMMANDS 4096 365 #define MIN_OUTSTANDING_COMMANDS 128 366 367 /* ISP request and response entry counts (37-65535) */ 368 #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */ 369 #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */ 370 #define REQUEST_ENTRY_CNT_24XX 2048 /* Number of request entries. */ 371 #define REQUEST_ENTRY_CNT_83XX 8192 /* Number of request entries. */ 372 #define RESPONSE_ENTRY_CNT_83XX 4096 /* Number of response entries.*/ 373 #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/ 374 #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/ 375 #define RESPONSE_ENTRY_CNT_MQ 128 /* Number of response entries.*/ 376 #define ATIO_ENTRY_CNT_24XX 4096 /* Number of ATIO entries. */ 377 #define RESPONSE_ENTRY_CNT_FX00 256 /* Number of response entries.*/ 378 #define FW_DEF_EXCHANGES_CNT 2048 379 #define FW_MAX_EXCHANGES_CNT (32 * 1024) 380 #define REDUCE_EXCHANGES_CNT (8 * 1024) 381 382 #define SET_DID_STATUS(stat_var, status) (stat_var = status << 16) 383 384 struct req_que; 385 struct qla_tgt_sess; 386 387 struct qla_buf_dsc { 388 u16 tag; 389 #define TAG_FREED 0xffff 390 void *buf; 391 dma_addr_t buf_dma; 392 }; 393 394 /* 395 * SCSI Request Block 396 */ 397 struct srb_cmd { 398 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */ 399 uint32_t request_sense_length; 400 uint32_t fw_sense_length; 401 uint8_t *request_sense_ptr; 402 struct crc_context *crc_ctx; 403 struct ct6_dsd ct6_ctx; 404 struct qla_buf_dsc buf_dsc; 405 }; 406 407 /* 408 * SRB flag definitions 409 */ 410 #define SRB_DMA_VALID BIT_0 /* Command sent to ISP */ 411 #define SRB_GOT_BUF BIT_1 412 #define SRB_FCP_CMND_DMA_VALID BIT_12 /* DIF: DSD List valid */ 413 #define SRB_CRC_CTX_DMA_VALID BIT_2 /* DIF: context DMA valid */ 414 #define SRB_CRC_PROT_DMA_VALID BIT_4 /* DIF: prot DMA valid */ 415 #define SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */ 416 #define SRB_WAKEUP_ON_COMP BIT_6 417 #define SRB_DIF_BUNDL_DMA_VALID BIT_7 /* DIF: DMA list valid */ 418 #define SRB_EDIF_CLEANUP_DELETE BIT_9 419 420 /* To identify if a srb is of T10-CRC type. @sp => srb_t pointer */ 421 #define IS_PROT_IO(sp) (sp->flags & SRB_CRC_CTX_DSD_VALID) 422 #define ISP_REG16_DISCONNECT 0xFFFF 423 424 static inline le_id_t be_id_to_le(be_id_t id) 425 { 426 le_id_t res; 427 428 res.domain = id.domain; 429 res.area = id.area; 430 res.al_pa = id.al_pa; 431 432 return res; 433 } 434 435 static inline be_id_t le_id_to_be(le_id_t id) 436 { 437 be_id_t res; 438 439 res.domain = id.domain; 440 res.area = id.area; 441 res.al_pa = id.al_pa; 442 443 return res; 444 } 445 446 static inline port_id_t be_to_port_id(be_id_t id) 447 { 448 port_id_t res; 449 450 res.b.domain = id.domain; 451 res.b.area = id.area; 452 res.b.al_pa = id.al_pa; 453 res.b.rsvd_1 = 0; 454 455 return res; 456 } 457 458 static inline be_id_t port_id_to_be_id(port_id_t port_id) 459 { 460 be_id_t res; 461 462 res.domain = port_id.b.domain; 463 res.area = port_id.b.area; 464 res.al_pa = port_id.b.al_pa; 465 466 return res; 467 } 468 469 struct els_logo_payload { 470 uint8_t opcode; 471 uint8_t rsvd[3]; 472 uint8_t s_id[3]; 473 uint8_t rsvd1[1]; 474 uint8_t wwpn[WWN_SIZE]; 475 }; 476 477 struct els_plogi_payload { 478 uint8_t opcode; 479 uint8_t rsvd[3]; 480 __be32 data[112 / 4]; 481 }; 482 483 struct ct_arg { 484 void *iocb; 485 u16 nport_handle; 486 dma_addr_t req_dma; 487 dma_addr_t rsp_dma; 488 u32 req_size; 489 u32 rsp_size; 490 u32 req_allocated_size; 491 u32 rsp_allocated_size; 492 void *req; 493 void *rsp; 494 port_id_t id; 495 }; 496 497 /* 498 * SRB extensions. 499 */ 500 struct srb_iocb { 501 union { 502 struct { 503 uint16_t flags; 504 #define SRB_LOGIN_RETRIED BIT_0 505 #define SRB_LOGIN_COND_PLOGI BIT_1 506 #define SRB_LOGIN_SKIP_PRLI BIT_2 507 #define SRB_LOGIN_NVME_PRLI BIT_3 508 #define SRB_LOGIN_PRLI_ONLY BIT_4 509 #define SRB_LOGIN_FCSP BIT_5 510 uint16_t data[2]; 511 u32 iop[2]; 512 } logio; 513 struct { 514 #define ELS_DCMD_TIMEOUT 20 515 #define ELS_DCMD_LOGO 0x5 516 uint32_t flags; 517 uint32_t els_cmd; 518 struct completion comp; 519 struct els_logo_payload *els_logo_pyld; 520 dma_addr_t els_logo_pyld_dma; 521 } els_logo; 522 struct els_plogi { 523 #define ELS_DCMD_PLOGI 0x3 524 uint32_t flags; 525 uint32_t els_cmd; 526 struct completion comp; 527 struct els_plogi_payload *els_plogi_pyld; 528 struct els_plogi_payload *els_resp_pyld; 529 u32 tx_size; 530 u32 rx_size; 531 dma_addr_t els_plogi_pyld_dma; 532 dma_addr_t els_resp_pyld_dma; 533 __le32 fw_status[3]; 534 __le16 comp_status; 535 __le16 len; 536 } els_plogi; 537 struct { 538 /* 539 * Values for flags field below are as 540 * defined in tsk_mgmt_entry struct 541 * for control_flags field in qla_fw.h. 542 */ 543 uint64_t lun; 544 uint32_t flags; 545 uint32_t data; 546 struct completion comp; 547 __le16 comp_status; 548 } tmf; 549 struct { 550 #define SRB_FXDISC_REQ_DMA_VALID BIT_0 551 #define SRB_FXDISC_RESP_DMA_VALID BIT_1 552 #define SRB_FXDISC_REQ_DWRD_VALID BIT_2 553 #define SRB_FXDISC_RSP_DWRD_VALID BIT_3 554 #define FXDISC_TIMEOUT 20 555 uint8_t flags; 556 uint32_t req_len; 557 uint32_t rsp_len; 558 void *req_addr; 559 void *rsp_addr; 560 dma_addr_t req_dma_handle; 561 dma_addr_t rsp_dma_handle; 562 __le32 adapter_id; 563 __le32 adapter_id_hi; 564 __le16 req_func_type; 565 __le32 req_data; 566 __le32 req_data_extra; 567 __le32 result; 568 __le32 seq_number; 569 __le16 fw_flags; 570 struct completion fxiocb_comp; 571 __le32 reserved_0; 572 uint8_t reserved_1; 573 } fxiocb; 574 struct { 575 uint32_t cmd_hndl; 576 __le16 comp_status; 577 __le16 req_que_no; 578 struct completion comp; 579 } abt; 580 struct ct_arg ctarg; 581 #define MAX_IOCB_MB_REG 28 582 #define SIZEOF_IOCB_MB_REG (MAX_IOCB_MB_REG * sizeof(uint16_t)) 583 struct { 584 u16 in_mb[MAX_IOCB_MB_REG]; /* from FW */ 585 u16 out_mb[MAX_IOCB_MB_REG]; /* to FW */ 586 void *out, *in; 587 dma_addr_t out_dma, in_dma; 588 struct completion comp; 589 int rc; 590 } mbx; 591 struct { 592 struct imm_ntfy_from_isp *ntfy; 593 } nack; 594 struct { 595 __le16 comp_status; 596 __le16 rsp_pyld_len; 597 uint8_t aen_op; 598 void *desc; 599 600 /* These are only used with ls4 requests */ 601 int cmd_len; 602 int rsp_len; 603 dma_addr_t cmd_dma; 604 dma_addr_t rsp_dma; 605 enum nvmefc_fcp_datadir dir; 606 uint32_t dl; 607 uint32_t timeout_sec; 608 struct list_head entry; 609 } nvme; 610 struct { 611 u16 cmd; 612 u16 vp_index; 613 } ctrlvp; 614 struct { 615 struct edif_sa_ctl *sa_ctl; 616 struct qla_sa_update_frame sa_frame; 617 } sa_update; 618 } u; 619 620 struct timer_list timer; 621 void (*timeout)(void *); 622 }; 623 624 /* Values for srb_ctx type */ 625 #define SRB_LOGIN_CMD 1 626 #define SRB_LOGOUT_CMD 2 627 #define SRB_ELS_CMD_RPT 3 628 #define SRB_ELS_CMD_HST 4 629 #define SRB_CT_CMD 5 630 #define SRB_ADISC_CMD 6 631 #define SRB_TM_CMD 7 632 #define SRB_SCSI_CMD 8 633 #define SRB_BIDI_CMD 9 634 #define SRB_FXIOCB_DCMD 10 635 #define SRB_FXIOCB_BCMD 11 636 #define SRB_ABT_CMD 12 637 #define SRB_ELS_DCMD 13 638 #define SRB_MB_IOCB 14 639 #define SRB_CT_PTHRU_CMD 15 640 #define SRB_NACK_PLOGI 16 641 #define SRB_NACK_PRLI 17 642 #define SRB_NACK_LOGO 18 643 #define SRB_NVME_CMD 19 644 #define SRB_NVME_LS 20 645 #define SRB_PRLI_CMD 21 646 #define SRB_CTRL_VP 22 647 #define SRB_PRLO_CMD 23 648 #define SRB_SA_UPDATE 25 649 #define SRB_ELS_CMD_HST_NOLOGIN 26 650 #define SRB_SA_REPLACE 27 651 652 struct qla_els_pt_arg { 653 u8 els_opcode; 654 u8 vp_idx; 655 __le16 nport_handle; 656 u16 control_flags, ox_id; 657 __le32 rx_xchg_address; 658 port_id_t did, sid; 659 u32 tx_len, tx_byte_count, rx_len, rx_byte_count; 660 dma_addr_t tx_addr, rx_addr; 661 662 }; 663 664 enum { 665 TYPE_SRB, 666 TYPE_TGT_CMD, 667 TYPE_TGT_TMCMD, /* task management */ 668 }; 669 670 struct iocb_resource { 671 u8 res_type; 672 u8 exch_cnt; 673 u16 iocb_cnt; 674 }; 675 676 struct bsg_cmd { 677 struct bsg_job *bsg_job; 678 union { 679 struct qla_els_pt_arg els_arg; 680 } u; 681 }; 682 683 typedef struct srb { 684 /* 685 * Do not move cmd_type field, it needs to 686 * line up with qla_tgt_cmd->cmd_type 687 */ 688 uint8_t cmd_type; 689 uint8_t pad[3]; 690 struct iocb_resource iores; 691 struct kref cmd_kref; /* need to migrate ref_count over to this */ 692 void *priv; 693 wait_queue_head_t nvme_ls_waitq; 694 struct fc_port *fcport; 695 struct scsi_qla_host *vha; 696 unsigned int start_timer:1; 697 698 uint32_t handle; 699 uint16_t flags; 700 uint16_t type; 701 const char *name; 702 int iocbs; 703 struct qla_qpair *qpair; 704 struct srb *cmd_sp; 705 struct list_head elem; 706 u32 gen1; /* scratch */ 707 u32 gen2; /* scratch */ 708 int rc; 709 int retry_count; 710 struct completion *comp; 711 union { 712 struct srb_iocb iocb_cmd; 713 struct bsg_job *bsg_job; 714 struct srb_cmd scmd; 715 struct bsg_cmd bsg_cmd; 716 } u; 717 struct { 718 bool remapped; 719 struct { 720 dma_addr_t dma; 721 void *buf; 722 uint len; 723 } req; 724 struct { 725 dma_addr_t dma; 726 void *buf; 727 uint len; 728 } rsp; 729 } remap; 730 /* 731 * Report completion status @res and call sp_put(@sp). @res is 732 * an NVMe status code, a SCSI result (e.g. DID_OK << 16) or a 733 * QLA_* status value. 734 */ 735 void (*done)(struct srb *sp, int res); 736 /* Stop the timer and free @sp. Only used by the FCP code. */ 737 void (*free)(struct srb *sp); 738 /* 739 * Call nvme_private->fd->done() and free @sp. Only used by the NVMe 740 * code. 741 */ 742 void (*put_fn)(struct kref *kref); 743 744 /* 745 * Report completion for asynchronous commands. 746 */ 747 void (*async_done)(struct srb *sp, int res); 748 } srb_t; 749 750 #define GET_CMD_SP(sp) (sp->u.scmd.cmd) 751 752 #define GET_CMD_SENSE_LEN(sp) \ 753 (sp->u.scmd.request_sense_length) 754 #define SET_CMD_SENSE_LEN(sp, len) \ 755 (sp->u.scmd.request_sense_length = len) 756 #define GET_CMD_SENSE_PTR(sp) \ 757 (sp->u.scmd.request_sense_ptr) 758 #define SET_CMD_SENSE_PTR(sp, ptr) \ 759 (sp->u.scmd.request_sense_ptr = ptr) 760 #define GET_FW_SENSE_LEN(sp) \ 761 (sp->u.scmd.fw_sense_length) 762 #define SET_FW_SENSE_LEN(sp, len) \ 763 (sp->u.scmd.fw_sense_length = len) 764 765 struct msg_echo_lb { 766 dma_addr_t send_dma; 767 dma_addr_t rcv_dma; 768 uint16_t req_sg_cnt; 769 uint16_t rsp_sg_cnt; 770 uint16_t options; 771 uint32_t transfer_size; 772 uint32_t iteration_count; 773 }; 774 775 /* 776 * ISP I/O Register Set structure definitions. 777 */ 778 struct device_reg_2xxx { 779 __le16 flash_address; /* Flash BIOS address */ 780 __le16 flash_data; /* Flash BIOS data */ 781 __le16 unused_1[1]; /* Gap */ 782 __le16 ctrl_status; /* Control/Status */ 783 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */ 784 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */ 785 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */ 786 787 __le16 ictrl; /* Interrupt control */ 788 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */ 789 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */ 790 791 __le16 istatus; /* Interrupt status */ 792 #define ISR_RISC_INT BIT_3 /* RISC interrupt */ 793 794 __le16 semaphore; /* Semaphore */ 795 __le16 nvram; /* NVRAM register. */ 796 #define NVR_DESELECT 0 797 #define NVR_BUSY BIT_15 798 #define NVR_WRT_ENABLE BIT_14 /* Write enable */ 799 #define NVR_PR_ENABLE BIT_13 /* Protection register enable */ 800 #define NVR_DATA_IN BIT_3 801 #define NVR_DATA_OUT BIT_2 802 #define NVR_SELECT BIT_1 803 #define NVR_CLOCK BIT_0 804 805 #define NVR_WAIT_CNT 20000 806 807 union { 808 struct { 809 __le16 mailbox0; 810 __le16 mailbox1; 811 __le16 mailbox2; 812 __le16 mailbox3; 813 __le16 mailbox4; 814 __le16 mailbox5; 815 __le16 mailbox6; 816 __le16 mailbox7; 817 __le16 unused_2[59]; /* Gap */ 818 } __attribute__((packed)) isp2100; 819 struct { 820 /* Request Queue */ 821 __le16 req_q_in; /* In-Pointer */ 822 __le16 req_q_out; /* Out-Pointer */ 823 /* Response Queue */ 824 __le16 rsp_q_in; /* In-Pointer */ 825 __le16 rsp_q_out; /* Out-Pointer */ 826 827 /* RISC to Host Status */ 828 __le32 host_status; 829 #define HSR_RISC_INT BIT_15 /* RISC interrupt */ 830 #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */ 831 832 /* Host to Host Semaphore */ 833 __le16 host_semaphore; 834 __le16 unused_3[17]; /* Gap */ 835 __le16 mailbox0; 836 __le16 mailbox1; 837 __le16 mailbox2; 838 __le16 mailbox3; 839 __le16 mailbox4; 840 __le16 mailbox5; 841 __le16 mailbox6; 842 __le16 mailbox7; 843 __le16 mailbox8; 844 __le16 mailbox9; 845 __le16 mailbox10; 846 __le16 mailbox11; 847 __le16 mailbox12; 848 __le16 mailbox13; 849 __le16 mailbox14; 850 __le16 mailbox15; 851 __le16 mailbox16; 852 __le16 mailbox17; 853 __le16 mailbox18; 854 __le16 mailbox19; 855 __le16 mailbox20; 856 __le16 mailbox21; 857 __le16 mailbox22; 858 __le16 mailbox23; 859 __le16 mailbox24; 860 __le16 mailbox25; 861 __le16 mailbox26; 862 __le16 mailbox27; 863 __le16 mailbox28; 864 __le16 mailbox29; 865 __le16 mailbox30; 866 __le16 mailbox31; 867 __le16 fb_cmd; 868 __le16 unused_4[10]; /* Gap */ 869 } __attribute__((packed)) isp2300; 870 } u; 871 872 __le16 fpm_diag_config; 873 __le16 unused_5[0x4]; /* Gap */ 874 __le16 risc_hw; 875 __le16 unused_5_1; /* Gap */ 876 __le16 pcr; /* Processor Control Register. */ 877 __le16 unused_6[0x5]; /* Gap */ 878 __le16 mctr; /* Memory Configuration and Timing. */ 879 __le16 unused_7[0x3]; /* Gap */ 880 __le16 fb_cmd_2100; /* Unused on 23XX */ 881 __le16 unused_8[0x3]; /* Gap */ 882 __le16 hccr; /* Host command & control register. */ 883 #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */ 884 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */ 885 /* HCCR commands */ 886 #define HCCR_RESET_RISC 0x1000 /* Reset RISC */ 887 #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */ 888 #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */ 889 #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */ 890 #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */ 891 #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */ 892 #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */ 893 #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */ 894 895 __le16 unused_9[5]; /* Gap */ 896 __le16 gpiod; /* GPIO Data register. */ 897 __le16 gpioe; /* GPIO Enable register. */ 898 #define GPIO_LED_MASK 0x00C0 899 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000 900 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040 901 #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080 902 #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0 903 #define GPIO_LED_ALL_OFF 0x0000 904 #define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */ 905 #define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */ 906 907 union { 908 struct { 909 __le16 unused_10[8]; /* Gap */ 910 __le16 mailbox8; 911 __le16 mailbox9; 912 __le16 mailbox10; 913 __le16 mailbox11; 914 __le16 mailbox12; 915 __le16 mailbox13; 916 __le16 mailbox14; 917 __le16 mailbox15; 918 __le16 mailbox16; 919 __le16 mailbox17; 920 __le16 mailbox18; 921 __le16 mailbox19; 922 __le16 mailbox20; 923 __le16 mailbox21; 924 __le16 mailbox22; 925 __le16 mailbox23; /* Also probe reg. */ 926 } __attribute__((packed)) isp2200; 927 } u_end; 928 }; 929 930 struct device_reg_25xxmq { 931 __le32 req_q_in; 932 __le32 req_q_out; 933 __le32 rsp_q_in; 934 __le32 rsp_q_out; 935 __le32 atio_q_in; 936 __le32 atio_q_out; 937 }; 938 939 940 struct device_reg_fx00 { 941 __le32 mailbox0; /* 00 */ 942 __le32 mailbox1; /* 04 */ 943 __le32 mailbox2; /* 08 */ 944 __le32 mailbox3; /* 0C */ 945 __le32 mailbox4; /* 10 */ 946 __le32 mailbox5; /* 14 */ 947 __le32 mailbox6; /* 18 */ 948 __le32 mailbox7; /* 1C */ 949 __le32 mailbox8; /* 20 */ 950 __le32 mailbox9; /* 24 */ 951 __le32 mailbox10; /* 28 */ 952 __le32 mailbox11; 953 __le32 mailbox12; 954 __le32 mailbox13; 955 __le32 mailbox14; 956 __le32 mailbox15; 957 __le32 mailbox16; 958 __le32 mailbox17; 959 __le32 mailbox18; 960 __le32 mailbox19; 961 __le32 mailbox20; 962 __le32 mailbox21; 963 __le32 mailbox22; 964 __le32 mailbox23; 965 __le32 mailbox24; 966 __le32 mailbox25; 967 __le32 mailbox26; 968 __le32 mailbox27; 969 __le32 mailbox28; 970 __le32 mailbox29; 971 __le32 mailbox30; 972 __le32 mailbox31; 973 __le32 aenmailbox0; 974 __le32 aenmailbox1; 975 __le32 aenmailbox2; 976 __le32 aenmailbox3; 977 __le32 aenmailbox4; 978 __le32 aenmailbox5; 979 __le32 aenmailbox6; 980 __le32 aenmailbox7; 981 /* Request Queue. */ 982 __le32 req_q_in; /* A0 - Request Queue In-Pointer */ 983 __le32 req_q_out; /* A4 - Request Queue Out-Pointer */ 984 /* Response Queue. */ 985 __le32 rsp_q_in; /* A8 - Response Queue In-Pointer */ 986 __le32 rsp_q_out; /* AC - Response Queue Out-Pointer */ 987 /* Init values shadowed on FW Up Event */ 988 __le32 initval0; /* B0 */ 989 __le32 initval1; /* B4 */ 990 __le32 initval2; /* B8 */ 991 __le32 initval3; /* BC */ 992 __le32 initval4; /* C0 */ 993 __le32 initval5; /* C4 */ 994 __le32 initval6; /* C8 */ 995 __le32 initval7; /* CC */ 996 __le32 fwheartbeat; /* D0 */ 997 __le32 pseudoaen; /* D4 */ 998 }; 999 1000 1001 1002 typedef union { 1003 struct device_reg_2xxx isp; 1004 struct device_reg_24xx isp24; 1005 struct device_reg_25xxmq isp25mq; 1006 struct device_reg_82xx isp82; 1007 struct device_reg_fx00 ispfx00; 1008 } __iomem device_reg_t; 1009 1010 #define ISP_REQ_Q_IN(ha, reg) \ 1011 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 1012 &(reg)->u.isp2100.mailbox4 : \ 1013 &(reg)->u.isp2300.req_q_in) 1014 #define ISP_REQ_Q_OUT(ha, reg) \ 1015 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 1016 &(reg)->u.isp2100.mailbox4 : \ 1017 &(reg)->u.isp2300.req_q_out) 1018 #define ISP_RSP_Q_IN(ha, reg) \ 1019 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 1020 &(reg)->u.isp2100.mailbox5 : \ 1021 &(reg)->u.isp2300.rsp_q_in) 1022 #define ISP_RSP_Q_OUT(ha, reg) \ 1023 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 1024 &(reg)->u.isp2100.mailbox5 : \ 1025 &(reg)->u.isp2300.rsp_q_out) 1026 1027 #define ISP_ATIO_Q_IN(vha) (vha->hw->tgt.atio_q_in) 1028 #define ISP_ATIO_Q_OUT(vha) (vha->hw->tgt.atio_q_out) 1029 1030 #define MAILBOX_REG(ha, reg, num) \ 1031 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 1032 (num < 8 ? \ 1033 &(reg)->u.isp2100.mailbox0 + (num) : \ 1034 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \ 1035 &(reg)->u.isp2300.mailbox0 + (num)) 1036 #define RD_MAILBOX_REG(ha, reg, num) \ 1037 rd_reg_word(MAILBOX_REG(ha, reg, num)) 1038 #define WRT_MAILBOX_REG(ha, reg, num, data) \ 1039 wrt_reg_word(MAILBOX_REG(ha, reg, num), data) 1040 1041 #define FB_CMD_REG(ha, reg) \ 1042 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 1043 &(reg)->fb_cmd_2100 : \ 1044 &(reg)->u.isp2300.fb_cmd) 1045 #define RD_FB_CMD_REG(ha, reg) \ 1046 rd_reg_word(FB_CMD_REG(ha, reg)) 1047 #define WRT_FB_CMD_REG(ha, reg, data) \ 1048 wrt_reg_word(FB_CMD_REG(ha, reg), data) 1049 1050 typedef struct { 1051 uint32_t out_mb; /* outbound from driver */ 1052 uint32_t in_mb; /* Incoming from RISC */ 1053 uint16_t mb[MAILBOX_REGISTER_COUNT]; 1054 long buf_size; 1055 void *bufp; 1056 uint32_t tov; 1057 uint8_t flags; 1058 #define MBX_DMA_IN BIT_0 1059 #define MBX_DMA_OUT BIT_1 1060 #define IOCTL_CMD BIT_2 1061 } mbx_cmd_t; 1062 1063 struct mbx_cmd_32 { 1064 uint32_t out_mb; /* outbound from driver */ 1065 uint32_t in_mb; /* Incoming from RISC */ 1066 uint32_t mb[MAILBOX_REGISTER_COUNT]; 1067 long buf_size; 1068 void *bufp; 1069 uint32_t tov; 1070 uint8_t flags; 1071 #define MBX_DMA_IN BIT_0 1072 #define MBX_DMA_OUT BIT_1 1073 #define IOCTL_CMD BIT_2 1074 }; 1075 1076 1077 #define MBX_TOV_SECONDS 30 1078 1079 /* 1080 * ISP product identification definitions in mailboxes after reset. 1081 */ 1082 #define PROD_ID_1 0x4953 1083 #define PROD_ID_2 0x0000 1084 #define PROD_ID_2a 0x5020 1085 #define PROD_ID_3 0x2020 1086 1087 /* 1088 * ISP mailbox Self-Test status codes 1089 */ 1090 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */ 1091 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */ 1092 #define MBS_BUSY 4 /* Busy. */ 1093 1094 /* 1095 * ISP mailbox command complete status codes 1096 */ 1097 #define MBS_COMMAND_COMPLETE 0x4000 1098 #define MBS_INVALID_COMMAND 0x4001 1099 #define MBS_HOST_INTERFACE_ERROR 0x4002 1100 #define MBS_TEST_FAILED 0x4003 1101 #define MBS_COMMAND_ERROR 0x4005 1102 #define MBS_COMMAND_PARAMETER_ERROR 0x4006 1103 #define MBS_PORT_ID_USED 0x4007 1104 #define MBS_LOOP_ID_USED 0x4008 1105 #define MBS_ALL_IDS_IN_USE 0x4009 1106 #define MBS_NOT_LOGGED_IN 0x400A 1107 #define MBS_LINK_DOWN_ERROR 0x400B 1108 #define MBS_DIAG_ECHO_TEST_ERROR 0x400C 1109 1110 static inline bool qla2xxx_is_valid_mbs(unsigned int mbs) 1111 { 1112 return MBS_COMMAND_COMPLETE <= mbs && mbs <= MBS_DIAG_ECHO_TEST_ERROR; 1113 } 1114 1115 /* 1116 * ISP mailbox asynchronous event status codes 1117 */ 1118 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */ 1119 #define MBA_RESET 0x8001 /* Reset Detected. */ 1120 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */ 1121 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */ 1122 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */ 1123 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */ 1124 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */ 1125 /* occurred. */ 1126 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */ 1127 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */ 1128 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */ 1129 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */ 1130 #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */ 1131 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */ 1132 #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */ 1133 #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */ 1134 #define MBA_CONGN_NOTI_RECV 0x801e /* Congestion Notification Received */ 1135 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */ 1136 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */ 1137 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */ 1138 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */ 1139 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */ 1140 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */ 1141 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */ 1142 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */ 1143 /* used. */ 1144 #define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */ 1145 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */ 1146 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */ 1147 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */ 1148 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */ 1149 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */ 1150 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */ 1151 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */ 1152 #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */ 1153 #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */ 1154 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */ 1155 #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */ 1156 #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */ 1157 #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */ 1158 #define MBA_FW_NOT_STARTED 0x8050 /* Firmware not started */ 1159 #define MBA_FW_STARTING 0x8051 /* Firmware starting */ 1160 #define MBA_FW_RESTART_CMPLT 0x8060 /* Firmware restart complete */ 1161 #define MBA_INIT_REQUIRED 0x8061 /* Initialization required */ 1162 #define MBA_SHUTDOWN_REQUESTED 0x8062 /* Shutdown Requested */ 1163 #define MBA_TEMPERATURE_ALERT 0x8070 /* Temperature Alert */ 1164 #define MBA_DPORT_DIAGNOSTICS 0x8080 /* D-port Diagnostics */ 1165 #define MBA_TRANS_INSERT 0x8130 /* Transceiver Insertion */ 1166 #define MBA_TRANS_REMOVE 0x8131 /* Transceiver Removal */ 1167 #define MBA_FW_INIT_FAILURE 0x8401 /* Firmware initialization failure */ 1168 #define MBA_MIRROR_LUN_CHANGE 0x8402 /* Mirror LUN State Change 1169 Notification */ 1170 #define MBA_FW_POLL_STATE 0x8600 /* Firmware in poll diagnostic state */ 1171 #define MBA_FW_RESET_FCT 0x8502 /* Firmware reset factory defaults */ 1172 #define MBA_FW_INIT_INPROGRESS 0x8500 /* Firmware boot in progress */ 1173 /* 83XX FCoE specific */ 1174 #define MBA_IDC_AEN 0x8200 /* FCoE: NIC Core state change AEN */ 1175 1176 /* Interrupt type codes */ 1177 #define INTR_ROM_MB_SUCCESS 0x1 1178 #define INTR_ROM_MB_FAILED 0x2 1179 #define INTR_MB_SUCCESS 0x10 1180 #define INTR_MB_FAILED 0x11 1181 #define INTR_ASYNC_EVENT 0x12 1182 #define INTR_RSP_QUE_UPDATE 0x13 1183 #define INTR_RSP_QUE_UPDATE_83XX 0x14 1184 #define INTR_ATIO_QUE_UPDATE 0x1C 1185 #define INTR_ATIO_RSP_QUE_UPDATE 0x1D 1186 #define INTR_ATIO_QUE_UPDATE_27XX 0x1E 1187 1188 /* ISP mailbox loopback echo diagnostic error code */ 1189 #define MBS_LB_RESET 0x17 1190 1191 /* AEN mailbox Port Diagnostics test */ 1192 #define AEN_START_DIAG_TEST 0x0 /* start the diagnostics */ 1193 #define AEN_DONE_DIAG_TEST_WITH_NOERR 0x1 /* Done with no errors */ 1194 #define AEN_DONE_DIAG_TEST_WITH_ERR 0x2 /* Done with error.*/ 1195 1196 /* 1197 * Firmware options 1, 2, 3. 1198 */ 1199 #define FO1_AE_ON_LIPF8 BIT_0 1200 #define FO1_AE_ALL_LIP_RESET BIT_1 1201 #define FO1_CTIO_RETRY BIT_3 1202 #define FO1_DISABLE_LIP_F7_SW BIT_4 1203 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5 1204 #define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */ 1205 #define FO1_AE_ON_LOOP_INIT_ERR BIT_7 1206 #define FO1_SET_EMPHASIS_SWING BIT_8 1207 #define FO1_AE_AUTO_BYPASS BIT_9 1208 #define FO1_ENABLE_PURE_IOCB BIT_10 1209 #define FO1_AE_PLOGI_RJT BIT_11 1210 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12 1211 #define FO1_AE_QUEUE_FULL BIT_13 1212 1213 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0 1214 #define FO2_REV_LOOPBACK BIT_1 1215 1216 #define FO3_ENABLE_EMERG_IOCB BIT_0 1217 #define FO3_AE_RND_ERROR BIT_1 1218 1219 /* 24XX additional firmware options */ 1220 #define ADD_FO_COUNT 3 1221 #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */ 1222 #define ADD_FO1_ENABLE_PUREX_IOCB BIT_10 1223 1224 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5 1225 1226 #define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14 1227 1228 /* 1229 * ISP mailbox commands 1230 */ 1231 #define MBC_LOAD_RAM 1 /* Load RAM. */ 1232 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */ 1233 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */ 1234 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */ 1235 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */ 1236 #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */ 1237 #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */ 1238 #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */ 1239 #define MBC_SECURE_FLASH_UPDATE 0xa /* Secure Flash Update(28xx) */ 1240 #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */ 1241 #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */ 1242 #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */ 1243 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */ 1244 #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */ 1245 #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */ 1246 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */ 1247 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */ 1248 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */ 1249 #define MBC_RESET 0x18 /* Reset. */ 1250 #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */ 1251 #define MBC_GET_SET_ZIO_THRESHOLD 0x21 /* Get/SET ZIO THRESHOLD. */ 1252 #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */ 1253 #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */ 1254 #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */ 1255 #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */ 1256 #define MBC_GET_MEM_OFFLOAD_CNTRL_STAT 0x34 /* Memory Offload ctrl/Stat*/ 1257 #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */ 1258 #define MBC_SET_GET_FC_LED_CONFIG 0x3b /* Set/Get FC LED config */ 1259 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */ 1260 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */ 1261 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */ 1262 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */ 1263 #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */ 1264 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */ 1265 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */ 1266 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */ 1267 #define MBC_CONFIGURE_VF 0x4b /* Configure VFs */ 1268 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */ 1269 #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */ 1270 #define MBC_PORT_LOGOUT 0x56 /* Port Logout request */ 1271 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */ 1272 #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */ 1273 #define MBC_GET_RNID_PARAMS 0x5a /* Get RNID parameters */ 1274 #define MBC_DATA_RATE 0x5d /* Data Rate */ 1275 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */ 1276 #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */ 1277 /* Initialization Procedure */ 1278 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */ 1279 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */ 1280 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */ 1281 #define MBC_TARGET_RESET 0x66 /* Target Reset. */ 1282 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */ 1283 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */ 1284 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */ 1285 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */ 1286 #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */ 1287 #define MBC_LIP_RESET 0x6c /* LIP reset. */ 1288 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */ 1289 /* commandd. */ 1290 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */ 1291 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */ 1292 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */ 1293 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */ 1294 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */ 1295 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */ 1296 #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */ 1297 #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */ 1298 #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */ 1299 #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */ 1300 #define MBC_LUN_RESET 0x7E /* Send LUN reset */ 1301 1302 /* 1303 * all the Mt. Rainier mailbox command codes that clash with FC/FCoE ones 1304 * should be defined with MBC_MR_* 1305 */ 1306 #define MBC_MR_DRV_SHUTDOWN 0x6A 1307 1308 /* 1309 * ISP24xx mailbox commands 1310 */ 1311 #define MBC_WRITE_SERDES 0x3 /* Write serdes word. */ 1312 #define MBC_READ_SERDES 0x4 /* Read serdes word. */ 1313 #define MBC_LOAD_DUMP_MPI_RAM 0x5 /* Load/Dump MPI RAM. */ 1314 #define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */ 1315 #define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */ 1316 #define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */ 1317 #define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */ 1318 #define MBC_TRACE_CONTROL 0x27 /* Trace control command. */ 1319 #define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */ 1320 #define MBC_WRITE_SFP 0x30 /* Write SFP Data. */ 1321 #define MBC_READ_SFP 0x31 /* Read SFP Data. */ 1322 #define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */ 1323 #define MBC_DPORT_DIAGNOSTICS 0x47 /* D-Port Diagnostics */ 1324 #define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */ 1325 #define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */ 1326 #define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */ 1327 #define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */ 1328 #define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */ 1329 #define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */ 1330 #define MBC_LINK_INITIALIZATION 0x72 /* Do link initialization. */ 1331 #define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */ 1332 #define MBC_PORT_RESET 0x120 /* Port Reset */ 1333 #define MBC_SET_PORT_CONFIG 0x122 /* Set port configuration */ 1334 #define MBC_GET_PORT_CONFIG 0x123 /* Get port configuration */ 1335 1336 /* 1337 * ISP81xx mailbox commands 1338 */ 1339 #define MBC_WRITE_MPI_REGISTER 0x01 /* Write MPI Register. */ 1340 1341 /* 1342 * ISP8044 mailbox commands 1343 */ 1344 #define MBC_SET_GET_ETH_SERDES_REG 0x150 1345 #define HCS_WRITE_SERDES 0x3 1346 #define HCS_READ_SERDES 0x4 1347 1348 /* Firmware return data sizes */ 1349 #define FCAL_MAP_SIZE 128 1350 1351 /* Mailbox bit definitions for out_mb and in_mb */ 1352 #define MBX_31 BIT_31 1353 #define MBX_30 BIT_30 1354 #define MBX_29 BIT_29 1355 #define MBX_28 BIT_28 1356 #define MBX_27 BIT_27 1357 #define MBX_26 BIT_26 1358 #define MBX_25 BIT_25 1359 #define MBX_24 BIT_24 1360 #define MBX_23 BIT_23 1361 #define MBX_22 BIT_22 1362 #define MBX_21 BIT_21 1363 #define MBX_20 BIT_20 1364 #define MBX_19 BIT_19 1365 #define MBX_18 BIT_18 1366 #define MBX_17 BIT_17 1367 #define MBX_16 BIT_16 1368 #define MBX_15 BIT_15 1369 #define MBX_14 BIT_14 1370 #define MBX_13 BIT_13 1371 #define MBX_12 BIT_12 1372 #define MBX_11 BIT_11 1373 #define MBX_10 BIT_10 1374 #define MBX_9 BIT_9 1375 #define MBX_8 BIT_8 1376 #define MBX_7 BIT_7 1377 #define MBX_6 BIT_6 1378 #define MBX_5 BIT_5 1379 #define MBX_4 BIT_4 1380 #define MBX_3 BIT_3 1381 #define MBX_2 BIT_2 1382 #define MBX_1 BIT_1 1383 #define MBX_0 BIT_0 1384 1385 #define RNID_TYPE_ELS_CMD 0x5 1386 #define RNID_TYPE_PORT_LOGIN 0x7 1387 #define RNID_BUFFER_CREDITS 0x8 1388 #define RNID_TYPE_SET_VERSION 0x9 1389 #define RNID_TYPE_ASIC_TEMP 0xC 1390 1391 #define ELS_CMD_MAP_SIZE 32 1392 1393 /* 1394 * Firmware state codes from get firmware state mailbox command 1395 */ 1396 #define FSTATE_CONFIG_WAIT 0 1397 #define FSTATE_WAIT_AL_PA 1 1398 #define FSTATE_WAIT_LOGIN 2 1399 #define FSTATE_READY 3 1400 #define FSTATE_LOSS_OF_SYNC 4 1401 #define FSTATE_ERROR 5 1402 #define FSTATE_REINIT 6 1403 #define FSTATE_NON_PART 7 1404 1405 #define FSTATE_CONFIG_CORRECT 0 1406 #define FSTATE_P2P_RCV_LIP 1 1407 #define FSTATE_P2P_CHOOSE_LOOP 2 1408 #define FSTATE_P2P_RCV_UNIDEN_LIP 3 1409 #define FSTATE_FATAL_ERROR 4 1410 #define FSTATE_LOOP_BACK_CONN 5 1411 1412 #define QLA27XX_IMG_STATUS_VER_MAJOR 0x01 1413 #define QLA27XX_IMG_STATUS_VER_MINOR 0x00 1414 #define QLA27XX_IMG_STATUS_SIGN 0xFACEFADE 1415 #define QLA28XX_IMG_STATUS_SIGN 0xFACEFADF 1416 #define QLA28XX_IMG_STATUS_SIGN 0xFACEFADF 1417 #define QLA28XX_AUX_IMG_STATUS_SIGN 0xFACEFAED 1418 #define QLA27XX_DEFAULT_IMAGE 0 1419 #define QLA27XX_PRIMARY_IMAGE 1 1420 #define QLA27XX_SECONDARY_IMAGE 2 1421 1422 /* 1423 * Port Database structure definition 1424 * Little endian except where noted. 1425 */ 1426 #define PORT_DATABASE_SIZE 128 /* bytes */ 1427 typedef struct { 1428 uint8_t options; 1429 uint8_t control; 1430 uint8_t master_state; 1431 uint8_t slave_state; 1432 uint8_t reserved[2]; 1433 uint8_t hard_address; 1434 uint8_t reserved_1; 1435 uint8_t port_id[4]; 1436 uint8_t node_name[WWN_SIZE]; 1437 uint8_t port_name[WWN_SIZE]; 1438 __le16 execution_throttle; 1439 uint16_t execution_count; 1440 uint8_t reset_count; 1441 uint8_t reserved_2; 1442 uint16_t resource_allocation; 1443 uint16_t current_allocation; 1444 uint16_t queue_head; 1445 uint16_t queue_tail; 1446 uint16_t transmit_execution_list_next; 1447 uint16_t transmit_execution_list_previous; 1448 uint16_t common_features; 1449 uint16_t total_concurrent_sequences; 1450 uint16_t RO_by_information_category; 1451 uint8_t recipient; 1452 uint8_t initiator; 1453 uint16_t receive_data_size; 1454 uint16_t concurrent_sequences; 1455 uint16_t open_sequences_per_exchange; 1456 uint16_t lun_abort_flags; 1457 uint16_t lun_stop_flags; 1458 uint16_t stop_queue_head; 1459 uint16_t stop_queue_tail; 1460 uint16_t port_retry_timer; 1461 uint16_t next_sequence_id; 1462 uint16_t frame_count; 1463 uint16_t PRLI_payload_length; 1464 uint8_t prli_svc_param_word_0[2]; /* Big endian */ 1465 /* Bits 15-0 of word 0 */ 1466 uint8_t prli_svc_param_word_3[2]; /* Big endian */ 1467 /* Bits 15-0 of word 3 */ 1468 uint16_t loop_id; 1469 uint16_t extended_lun_info_list_pointer; 1470 uint16_t extended_lun_stop_list_pointer; 1471 } port_database_t; 1472 1473 /* 1474 * Port database slave/master states 1475 */ 1476 #define PD_STATE_DISCOVERY 0 1477 #define PD_STATE_WAIT_DISCOVERY_ACK 1 1478 #define PD_STATE_PORT_LOGIN 2 1479 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3 1480 #define PD_STATE_PROCESS_LOGIN 4 1481 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5 1482 #define PD_STATE_PORT_LOGGED_IN 6 1483 #define PD_STATE_PORT_UNAVAILABLE 7 1484 #define PD_STATE_PROCESS_LOGOUT 8 1485 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9 1486 #define PD_STATE_PORT_LOGOUT 10 1487 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11 1488 1489 1490 #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1) 1491 #define QLA_ZIO_DISABLED 0 1492 #define QLA_ZIO_DEFAULT_TIMER 2 1493 1494 /* 1495 * ISP Initialization Control Block. 1496 * Little endian except where noted. 1497 */ 1498 #define ICB_VERSION 1 1499 typedef struct { 1500 uint8_t version; 1501 uint8_t reserved_1; 1502 1503 /* 1504 * LSB BIT 0 = Enable Hard Loop Id 1505 * LSB BIT 1 = Enable Fairness 1506 * LSB BIT 2 = Enable Full-Duplex 1507 * LSB BIT 3 = Enable Fast Posting 1508 * LSB BIT 4 = Enable Target Mode 1509 * LSB BIT 5 = Disable Initiator Mode 1510 * LSB BIT 6 = Enable ADISC 1511 * LSB BIT 7 = Enable Target Inquiry Data 1512 * 1513 * MSB BIT 0 = Enable PDBC Notify 1514 * MSB BIT 1 = Non Participating LIP 1515 * MSB BIT 2 = Descending Loop ID Search 1516 * MSB BIT 3 = Acquire Loop ID in LIPA 1517 * MSB BIT 4 = Stop PortQ on Full Status 1518 * MSB BIT 5 = Full Login after LIP 1519 * MSB BIT 6 = Node Name Option 1520 * MSB BIT 7 = Ext IFWCB enable bit 1521 */ 1522 uint8_t firmware_options[2]; 1523 1524 __le16 frame_payload_size; 1525 __le16 max_iocb_allocation; 1526 __le16 execution_throttle; 1527 uint8_t retry_count; 1528 uint8_t retry_delay; /* unused */ 1529 uint8_t port_name[WWN_SIZE]; /* Big endian. */ 1530 uint16_t hard_address; 1531 uint8_t inquiry_data; 1532 uint8_t login_timeout; 1533 uint8_t node_name[WWN_SIZE]; /* Big endian. */ 1534 1535 __le16 request_q_outpointer; 1536 __le16 response_q_inpointer; 1537 __le16 request_q_length; 1538 __le16 response_q_length; 1539 __le64 request_q_address __packed; 1540 __le64 response_q_address __packed; 1541 1542 __le16 lun_enables; 1543 uint8_t command_resource_count; 1544 uint8_t immediate_notify_resource_count; 1545 __le16 timeout; 1546 uint8_t reserved_2[2]; 1547 1548 /* 1549 * LSB BIT 0 = Timer Operation mode bit 0 1550 * LSB BIT 1 = Timer Operation mode bit 1 1551 * LSB BIT 2 = Timer Operation mode bit 2 1552 * LSB BIT 3 = Timer Operation mode bit 3 1553 * LSB BIT 4 = Init Config Mode bit 0 1554 * LSB BIT 5 = Init Config Mode bit 1 1555 * LSB BIT 6 = Init Config Mode bit 2 1556 * LSB BIT 7 = Enable Non part on LIHA failure 1557 * 1558 * MSB BIT 0 = Enable class 2 1559 * MSB BIT 1 = Enable ACK0 1560 * MSB BIT 2 = 1561 * MSB BIT 3 = 1562 * MSB BIT 4 = FC Tape Enable 1563 * MSB BIT 5 = Enable FC Confirm 1564 * MSB BIT 6 = Enable command queuing in target mode 1565 * MSB BIT 7 = No Logo On Link Down 1566 */ 1567 uint8_t add_firmware_options[2]; 1568 1569 uint8_t response_accumulation_timer; 1570 uint8_t interrupt_delay_timer; 1571 1572 /* 1573 * LSB BIT 0 = Enable Read xfr_rdy 1574 * LSB BIT 1 = Soft ID only 1575 * LSB BIT 2 = 1576 * LSB BIT 3 = 1577 * LSB BIT 4 = FCP RSP Payload [0] 1578 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200 1579 * LSB BIT 6 = Enable Out-of-Order frame handling 1580 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop 1581 * 1582 * MSB BIT 0 = Sbus enable - 2300 1583 * MSB BIT 1 = 1584 * MSB BIT 2 = 1585 * MSB BIT 3 = 1586 * MSB BIT 4 = LED mode 1587 * MSB BIT 5 = enable 50 ohm termination 1588 * MSB BIT 6 = Data Rate (2300 only) 1589 * MSB BIT 7 = Data Rate (2300 only) 1590 */ 1591 uint8_t special_options[2]; 1592 1593 uint8_t reserved_3[26]; 1594 } init_cb_t; 1595 1596 /* Special Features Control Block */ 1597 struct init_sf_cb { 1598 uint8_t format; 1599 uint8_t reserved0; 1600 /* 1601 * BIT 15-14 = Reserved 1602 * BIT_13 = SAN Congestion Management (1 - Enabled, 0 - Disabled) 1603 * BIT_12 = Remote Write Optimization (1 - Enabled, 0 - Disabled) 1604 * BIT 11-0 = Reserved 1605 */ 1606 __le16 flags; 1607 uint8_t reserved1[32]; 1608 uint16_t discard_OHRB_timeout_value; 1609 uint16_t remote_write_opt_queue_num; 1610 uint8_t reserved2[40]; 1611 uint8_t scm_related_parameter[16]; 1612 uint8_t reserved3[32]; 1613 }; 1614 1615 /* 1616 * Get Link Status mailbox command return buffer. 1617 */ 1618 #define GLSO_SEND_RPS BIT_0 1619 #define GLSO_USE_DID BIT_3 1620 1621 struct link_statistics { 1622 __le32 link_fail_cnt; 1623 __le32 loss_sync_cnt; 1624 __le32 loss_sig_cnt; 1625 __le32 prim_seq_err_cnt; 1626 __le32 inval_xmit_word_cnt; 1627 __le32 inval_crc_cnt; 1628 __le32 lip_cnt; 1629 __le32 link_up_cnt; 1630 __le32 link_down_loop_init_tmo; 1631 __le32 link_down_los; 1632 __le32 link_down_loss_rcv_clk; 1633 uint32_t reserved0[5]; 1634 __le32 port_cfg_chg; 1635 uint32_t reserved1[11]; 1636 __le32 rsp_q_full; 1637 __le32 atio_q_full; 1638 __le32 drop_ae; 1639 __le32 els_proto_err; 1640 __le32 reserved2; 1641 __le32 tx_frames; 1642 __le32 rx_frames; 1643 __le32 discarded_frames; 1644 __le32 dropped_frames; 1645 uint32_t reserved3; 1646 __le32 nos_rcvd; 1647 uint32_t reserved4[4]; 1648 __le32 tx_prjt; 1649 __le32 rcv_exfail; 1650 __le32 rcv_abts; 1651 __le32 seq_frm_miss; 1652 __le32 corr_err; 1653 __le32 mb_rqst; 1654 __le32 nport_full; 1655 __le32 eofa; 1656 uint32_t reserved5; 1657 __le64 fpm_recv_word_cnt; 1658 __le64 fpm_disc_word_cnt; 1659 __le64 fpm_xmit_word_cnt; 1660 uint32_t reserved6[70]; 1661 }; 1662 1663 /* 1664 * NVRAM Command values. 1665 */ 1666 #define NV_START_BIT BIT_2 1667 #define NV_WRITE_OP (BIT_26+BIT_24) 1668 #define NV_READ_OP (BIT_26+BIT_25) 1669 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24) 1670 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24) 1671 #define NV_DELAY_COUNT 10 1672 1673 /* 1674 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition. 1675 */ 1676 typedef struct { 1677 /* 1678 * NVRAM header 1679 */ 1680 uint8_t id[4]; 1681 uint8_t nvram_version; 1682 uint8_t reserved_0; 1683 1684 /* 1685 * NVRAM RISC parameter block 1686 */ 1687 uint8_t parameter_block_version; 1688 uint8_t reserved_1; 1689 1690 /* 1691 * LSB BIT 0 = Enable Hard Loop Id 1692 * LSB BIT 1 = Enable Fairness 1693 * LSB BIT 2 = Enable Full-Duplex 1694 * LSB BIT 3 = Enable Fast Posting 1695 * LSB BIT 4 = Enable Target Mode 1696 * LSB BIT 5 = Disable Initiator Mode 1697 * LSB BIT 6 = Enable ADISC 1698 * LSB BIT 7 = Enable Target Inquiry Data 1699 * 1700 * MSB BIT 0 = Enable PDBC Notify 1701 * MSB BIT 1 = Non Participating LIP 1702 * MSB BIT 2 = Descending Loop ID Search 1703 * MSB BIT 3 = Acquire Loop ID in LIPA 1704 * MSB BIT 4 = Stop PortQ on Full Status 1705 * MSB BIT 5 = Full Login after LIP 1706 * MSB BIT 6 = Node Name Option 1707 * MSB BIT 7 = Ext IFWCB enable bit 1708 */ 1709 uint8_t firmware_options[2]; 1710 1711 __le16 frame_payload_size; 1712 __le16 max_iocb_allocation; 1713 __le16 execution_throttle; 1714 uint8_t retry_count; 1715 uint8_t retry_delay; /* unused */ 1716 uint8_t port_name[WWN_SIZE]; /* Big endian. */ 1717 uint16_t hard_address; 1718 uint8_t inquiry_data; 1719 uint8_t login_timeout; 1720 uint8_t node_name[WWN_SIZE]; /* Big endian. */ 1721 1722 /* 1723 * LSB BIT 0 = Timer Operation mode bit 0 1724 * LSB BIT 1 = Timer Operation mode bit 1 1725 * LSB BIT 2 = Timer Operation mode bit 2 1726 * LSB BIT 3 = Timer Operation mode bit 3 1727 * LSB BIT 4 = Init Config Mode bit 0 1728 * LSB BIT 5 = Init Config Mode bit 1 1729 * LSB BIT 6 = Init Config Mode bit 2 1730 * LSB BIT 7 = Enable Non part on LIHA failure 1731 * 1732 * MSB BIT 0 = Enable class 2 1733 * MSB BIT 1 = Enable ACK0 1734 * MSB BIT 2 = 1735 * MSB BIT 3 = 1736 * MSB BIT 4 = FC Tape Enable 1737 * MSB BIT 5 = Enable FC Confirm 1738 * MSB BIT 6 = Enable command queuing in target mode 1739 * MSB BIT 7 = No Logo On Link Down 1740 */ 1741 uint8_t add_firmware_options[2]; 1742 1743 uint8_t response_accumulation_timer; 1744 uint8_t interrupt_delay_timer; 1745 1746 /* 1747 * LSB BIT 0 = Enable Read xfr_rdy 1748 * LSB BIT 1 = Soft ID only 1749 * LSB BIT 2 = 1750 * LSB BIT 3 = 1751 * LSB BIT 4 = FCP RSP Payload [0] 1752 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200 1753 * LSB BIT 6 = Enable Out-of-Order frame handling 1754 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop 1755 * 1756 * MSB BIT 0 = Sbus enable - 2300 1757 * MSB BIT 1 = 1758 * MSB BIT 2 = 1759 * MSB BIT 3 = 1760 * MSB BIT 4 = LED mode 1761 * MSB BIT 5 = enable 50 ohm termination 1762 * MSB BIT 6 = Data Rate (2300 only) 1763 * MSB BIT 7 = Data Rate (2300 only) 1764 */ 1765 uint8_t special_options[2]; 1766 1767 /* Reserved for expanded RISC parameter block */ 1768 uint8_t reserved_2[22]; 1769 1770 /* 1771 * LSB BIT 0 = Tx Sensitivity 1G bit 0 1772 * LSB BIT 1 = Tx Sensitivity 1G bit 1 1773 * LSB BIT 2 = Tx Sensitivity 1G bit 2 1774 * LSB BIT 3 = Tx Sensitivity 1G bit 3 1775 * LSB BIT 4 = Rx Sensitivity 1G bit 0 1776 * LSB BIT 5 = Rx Sensitivity 1G bit 1 1777 * LSB BIT 6 = Rx Sensitivity 1G bit 2 1778 * LSB BIT 7 = Rx Sensitivity 1G bit 3 1779 * 1780 * MSB BIT 0 = Tx Sensitivity 2G bit 0 1781 * MSB BIT 1 = Tx Sensitivity 2G bit 1 1782 * MSB BIT 2 = Tx Sensitivity 2G bit 2 1783 * MSB BIT 3 = Tx Sensitivity 2G bit 3 1784 * MSB BIT 4 = Rx Sensitivity 2G bit 0 1785 * MSB BIT 5 = Rx Sensitivity 2G bit 1 1786 * MSB BIT 6 = Rx Sensitivity 2G bit 2 1787 * MSB BIT 7 = Rx Sensitivity 2G bit 3 1788 * 1789 * LSB BIT 0 = Output Swing 1G bit 0 1790 * LSB BIT 1 = Output Swing 1G bit 1 1791 * LSB BIT 2 = Output Swing 1G bit 2 1792 * LSB BIT 3 = Output Emphasis 1G bit 0 1793 * LSB BIT 4 = Output Emphasis 1G bit 1 1794 * LSB BIT 5 = Output Swing 2G bit 0 1795 * LSB BIT 6 = Output Swing 2G bit 1 1796 * LSB BIT 7 = Output Swing 2G bit 2 1797 * 1798 * MSB BIT 0 = Output Emphasis 2G bit 0 1799 * MSB BIT 1 = Output Emphasis 2G bit 1 1800 * MSB BIT 2 = Output Enable 1801 * MSB BIT 3 = 1802 * MSB BIT 4 = 1803 * MSB BIT 5 = 1804 * MSB BIT 6 = 1805 * MSB BIT 7 = 1806 */ 1807 uint8_t seriallink_options[4]; 1808 1809 /* 1810 * NVRAM host parameter block 1811 * 1812 * LSB BIT 0 = Enable spinup delay 1813 * LSB BIT 1 = Disable BIOS 1814 * LSB BIT 2 = Enable Memory Map BIOS 1815 * LSB BIT 3 = Enable Selectable Boot 1816 * LSB BIT 4 = Disable RISC code load 1817 * LSB BIT 5 = Set cache line size 1 1818 * LSB BIT 6 = PCI Parity Disable 1819 * LSB BIT 7 = Enable extended logging 1820 * 1821 * MSB BIT 0 = Enable 64bit addressing 1822 * MSB BIT 1 = Enable lip reset 1823 * MSB BIT 2 = Enable lip full login 1824 * MSB BIT 3 = Enable target reset 1825 * MSB BIT 4 = Enable database storage 1826 * MSB BIT 5 = Enable cache flush read 1827 * MSB BIT 6 = Enable database load 1828 * MSB BIT 7 = Enable alternate WWN 1829 */ 1830 uint8_t host_p[2]; 1831 1832 uint8_t boot_node_name[WWN_SIZE]; 1833 uint8_t boot_lun_number; 1834 uint8_t reset_delay; 1835 uint8_t port_down_retry_count; 1836 uint8_t boot_id_number; 1837 __le16 max_luns_per_target; 1838 uint8_t fcode_boot_port_name[WWN_SIZE]; 1839 uint8_t alternate_port_name[WWN_SIZE]; 1840 uint8_t alternate_node_name[WWN_SIZE]; 1841 1842 /* 1843 * BIT 0 = Selective Login 1844 * BIT 1 = Alt-Boot Enable 1845 * BIT 2 = 1846 * BIT 3 = Boot Order List 1847 * BIT 4 = 1848 * BIT 5 = Selective LUN 1849 * BIT 6 = 1850 * BIT 7 = unused 1851 */ 1852 uint8_t efi_parameters; 1853 1854 uint8_t link_down_timeout; 1855 1856 uint8_t adapter_id[16]; 1857 1858 uint8_t alt1_boot_node_name[WWN_SIZE]; 1859 uint16_t alt1_boot_lun_number; 1860 uint8_t alt2_boot_node_name[WWN_SIZE]; 1861 uint16_t alt2_boot_lun_number; 1862 uint8_t alt3_boot_node_name[WWN_SIZE]; 1863 uint16_t alt3_boot_lun_number; 1864 uint8_t alt4_boot_node_name[WWN_SIZE]; 1865 uint16_t alt4_boot_lun_number; 1866 uint8_t alt5_boot_node_name[WWN_SIZE]; 1867 uint16_t alt5_boot_lun_number; 1868 uint8_t alt6_boot_node_name[WWN_SIZE]; 1869 uint16_t alt6_boot_lun_number; 1870 uint8_t alt7_boot_node_name[WWN_SIZE]; 1871 uint16_t alt7_boot_lun_number; 1872 1873 uint8_t reserved_3[2]; 1874 1875 /* Offset 200-215 : Model Number */ 1876 uint8_t model_number[16]; 1877 1878 /* OEM related items */ 1879 uint8_t oem_specific[16]; 1880 1881 /* 1882 * NVRAM Adapter Features offset 232-239 1883 * 1884 * LSB BIT 0 = External GBIC 1885 * LSB BIT 1 = Risc RAM parity 1886 * LSB BIT 2 = Buffer Plus Module 1887 * LSB BIT 3 = Multi Chip Adapter 1888 * LSB BIT 4 = Internal connector 1889 * LSB BIT 5 = 1890 * LSB BIT 6 = 1891 * LSB BIT 7 = 1892 * 1893 * MSB BIT 0 = 1894 * MSB BIT 1 = 1895 * MSB BIT 2 = 1896 * MSB BIT 3 = 1897 * MSB BIT 4 = 1898 * MSB BIT 5 = 1899 * MSB BIT 6 = 1900 * MSB BIT 7 = 1901 */ 1902 uint8_t adapter_features[2]; 1903 1904 uint8_t reserved_4[16]; 1905 1906 /* Subsystem vendor ID for ISP2200 */ 1907 uint16_t subsystem_vendor_id_2200; 1908 1909 /* Subsystem device ID for ISP2200 */ 1910 uint16_t subsystem_device_id_2200; 1911 1912 uint8_t reserved_5; 1913 uint8_t checksum; 1914 } nvram_t; 1915 1916 /* 1917 * ISP queue - response queue entry definition. 1918 */ 1919 typedef struct { 1920 uint8_t entry_type; /* Entry type. */ 1921 uint8_t entry_count; /* Entry count. */ 1922 uint8_t sys_define; /* System defined. */ 1923 uint8_t entry_status; /* Entry Status. */ 1924 uint32_t handle; /* System defined handle */ 1925 uint8_t data[52]; 1926 uint32_t signature; 1927 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */ 1928 } response_t; 1929 1930 /* 1931 * ISP queue - ATIO queue entry definition. 1932 */ 1933 struct atio { 1934 uint8_t entry_type; /* Entry type. */ 1935 uint8_t entry_count; /* Entry count. */ 1936 __le16 attr_n_length; 1937 uint8_t data[56]; 1938 uint32_t signature; 1939 #define ATIO_PROCESSED 0xDEADDEAD /* Signature */ 1940 }; 1941 1942 typedef union { 1943 __le16 extended; 1944 struct { 1945 uint8_t reserved; 1946 uint8_t standard; 1947 } id; 1948 } target_id_t; 1949 1950 #define SET_TARGET_ID(ha, to, from) \ 1951 do { \ 1952 if (HAS_EXTENDED_IDS(ha)) \ 1953 to.extended = cpu_to_le16(from); \ 1954 else \ 1955 to.id.standard = (uint8_t)from; \ 1956 } while (0) 1957 1958 /* 1959 * ISP queue - command entry structure definition. 1960 */ 1961 #define COMMAND_TYPE 0x11 /* Command entry */ 1962 typedef struct { 1963 uint8_t entry_type; /* Entry type. */ 1964 uint8_t entry_count; /* Entry count. */ 1965 uint8_t sys_define; /* System defined. */ 1966 uint8_t entry_status; /* Entry Status. */ 1967 uint32_t handle; /* System handle. */ 1968 target_id_t target; /* SCSI ID */ 1969 __le16 lun; /* SCSI LUN */ 1970 __le16 control_flags; /* Control flags. */ 1971 #define CF_WRITE BIT_6 1972 #define CF_READ BIT_5 1973 #define CF_SIMPLE_TAG BIT_3 1974 #define CF_ORDERED_TAG BIT_2 1975 #define CF_HEAD_TAG BIT_1 1976 uint16_t reserved_1; 1977 __le16 timeout; /* Command timeout. */ 1978 __le16 dseg_count; /* Data segment count. */ 1979 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ 1980 __le32 byte_count; /* Total byte count. */ 1981 union { 1982 struct dsd32 dsd32[3]; 1983 struct dsd64 dsd64[2]; 1984 }; 1985 } cmd_entry_t; 1986 1987 /* 1988 * ISP queue - 64-Bit addressing, command entry structure definition. 1989 */ 1990 #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */ 1991 typedef struct { 1992 uint8_t entry_type; /* Entry type. */ 1993 uint8_t entry_count; /* Entry count. */ 1994 uint8_t sys_define; /* System defined. */ 1995 uint8_t entry_status; /* Entry Status. */ 1996 uint32_t handle; /* System handle. */ 1997 target_id_t target; /* SCSI ID */ 1998 __le16 lun; /* SCSI LUN */ 1999 __le16 control_flags; /* Control flags. */ 2000 uint16_t reserved_1; 2001 __le16 timeout; /* Command timeout. */ 2002 __le16 dseg_count; /* Data segment count. */ 2003 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ 2004 uint32_t byte_count; /* Total byte count. */ 2005 struct dsd64 dsd[2]; 2006 } cmd_a64_entry_t, request_t; 2007 2008 /* 2009 * ISP queue - continuation entry structure definition. 2010 */ 2011 #define CONTINUE_TYPE 0x02 /* Continuation entry. */ 2012 typedef struct { 2013 uint8_t entry_type; /* Entry type. */ 2014 uint8_t entry_count; /* Entry count. */ 2015 uint8_t sys_define; /* System defined. */ 2016 uint8_t entry_status; /* Entry Status. */ 2017 uint32_t reserved; 2018 struct dsd32 dsd[7]; 2019 } cont_entry_t; 2020 2021 /* 2022 * ISP queue - 64-Bit addressing, continuation entry structure definition. 2023 */ 2024 #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */ 2025 typedef struct { 2026 uint8_t entry_type; /* Entry type. */ 2027 uint8_t entry_count; /* Entry count. */ 2028 uint8_t sys_define; /* System defined. */ 2029 uint8_t entry_status; /* Entry Status. */ 2030 struct dsd64 dsd[5]; 2031 } cont_a64_entry_t; 2032 2033 #define PO_MODE_DIF_INSERT 0 2034 #define PO_MODE_DIF_REMOVE 1 2035 #define PO_MODE_DIF_PASS 2 2036 #define PO_MODE_DIF_REPLACE 3 2037 #define PO_MODE_DIF_TCP_CKSUM 6 2038 #define PO_ENABLE_INCR_GUARD_SEED BIT_3 2039 #define PO_DISABLE_GUARD_CHECK BIT_4 2040 #define PO_DISABLE_INCR_REF_TAG BIT_5 2041 #define PO_DIS_HEADER_MODE BIT_7 2042 #define PO_ENABLE_DIF_BUNDLING BIT_8 2043 #define PO_DIS_FRAME_MODE BIT_9 2044 #define PO_DIS_VALD_APP_ESC BIT_10 /* Dis validation for escape tag/ffffh */ 2045 #define PO_DIS_VALD_APP_REF_ESC BIT_11 2046 2047 #define PO_DIS_APP_TAG_REPL BIT_12 /* disable REG Tag replacement */ 2048 #define PO_DIS_REF_TAG_REPL BIT_13 2049 #define PO_DIS_APP_TAG_VALD BIT_14 /* disable REF Tag validation */ 2050 #define PO_DIS_REF_TAG_VALD BIT_15 2051 2052 /* 2053 * ISP queue - 64-Bit addressing, continuation crc entry structure definition. 2054 */ 2055 struct crc_context { 2056 uint32_t handle; /* System handle. */ 2057 __le32 ref_tag; 2058 __le16 app_tag; 2059 uint8_t ref_tag_mask[4]; /* Validation/Replacement Mask*/ 2060 uint8_t app_tag_mask[2]; /* Validation/Replacement Mask*/ 2061 __le16 guard_seed; /* Initial Guard Seed */ 2062 __le16 prot_opts; /* Requested Data Protection Mode */ 2063 __le16 blk_size; /* Data size in bytes */ 2064 __le16 runt_blk_guard; /* Guard value for runt block (tape 2065 * only) */ 2066 __le32 byte_count; /* Total byte count/ total data 2067 * transfer count */ 2068 union { 2069 struct { 2070 uint32_t reserved_1; 2071 uint16_t reserved_2; 2072 uint16_t reserved_3; 2073 uint32_t reserved_4; 2074 struct dsd64 data_dsd[1]; 2075 uint32_t reserved_5[2]; 2076 uint32_t reserved_6; 2077 } nobundling; 2078 struct { 2079 __le32 dif_byte_count; /* Total DIF byte 2080 * count */ 2081 uint16_t reserved_1; 2082 __le16 dseg_count; /* Data segment count */ 2083 uint32_t reserved_2; 2084 struct dsd64 data_dsd[1]; 2085 struct dsd64 dif_dsd; 2086 } bundling; 2087 } u; 2088 2089 struct fcp_cmnd fcp_cmnd; 2090 dma_addr_t crc_ctx_dma; 2091 /* List of DMA context transfers */ 2092 struct list_head dsd_list; 2093 2094 /* List of DIF Bundling context DMA address */ 2095 struct list_head ldif_dsd_list; 2096 u8 no_ldif_dsd; 2097 2098 struct list_head ldif_dma_hndl_list; 2099 u32 dif_bundl_len; 2100 u8 no_dif_bundl; 2101 /* This structure should not exceed 512 bytes */ 2102 }; 2103 2104 #define CRC_CONTEXT_LEN_FW (offsetof(struct crc_context, fcp_cmnd.lun)) 2105 #define CRC_CONTEXT_FCPCMND_OFF (offsetof(struct crc_context, fcp_cmnd.lun)) 2106 2107 /* 2108 * ISP queue - status entry structure definition. 2109 */ 2110 #define STATUS_TYPE 0x03 /* Status entry. */ 2111 typedef struct { 2112 uint8_t entry_type; /* Entry type. */ 2113 uint8_t entry_count; /* Entry count. */ 2114 uint8_t sys_define; /* System defined. */ 2115 uint8_t entry_status; /* Entry Status. */ 2116 uint32_t handle; /* System handle. */ 2117 __le16 scsi_status; /* SCSI status. */ 2118 __le16 comp_status; /* Completion status. */ 2119 __le16 state_flags; /* State flags. */ 2120 __le16 status_flags; /* Status flags. */ 2121 __le16 rsp_info_len; /* Response Info Length. */ 2122 __le16 req_sense_length; /* Request sense data length. */ 2123 __le32 residual_length; /* Residual transfer length. */ 2124 uint8_t rsp_info[8]; /* FCP response information. */ 2125 uint8_t req_sense_data[32]; /* Request sense data. */ 2126 } sts_entry_t; 2127 2128 /* 2129 * Status entry entry status 2130 */ 2131 #define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */ 2132 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */ 2133 #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */ 2134 #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */ 2135 #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */ 2136 #define RF_BUSY BIT_1 /* Busy */ 2137 #define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \ 2138 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY) 2139 #define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \ 2140 RF_INV_E_TYPE) 2141 2142 /* 2143 * Status entry SCSI status bit definitions. 2144 */ 2145 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/ 2146 #define SS_RESIDUAL_UNDER BIT_11 2147 #define SS_RESIDUAL_OVER BIT_10 2148 #define SS_SENSE_LEN_VALID BIT_9 2149 #define SS_RESPONSE_INFO_LEN_VALID BIT_8 2150 #define SS_SCSI_STATUS_BYTE 0xff 2151 2152 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3) 2153 #define SS_BUSY_CONDITION BIT_3 2154 #define SS_CONDITION_MET BIT_2 2155 #define SS_CHECK_CONDITION BIT_1 2156 2157 /* 2158 * Status entry completion status 2159 */ 2160 #define CS_COMPLETE 0x0 /* No errors */ 2161 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */ 2162 #define CS_DMA 0x2 /* A DMA direction error. */ 2163 #define CS_TRANSPORT 0x3 /* Transport error. */ 2164 #define CS_RESET 0x4 /* SCSI bus reset occurred */ 2165 #define CS_ABORTED 0x5 /* System aborted command. */ 2166 #define CS_TIMEOUT 0x6 /* Timeout error. */ 2167 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */ 2168 #define CS_DIF_ERROR 0xC /* DIF error detected */ 2169 2170 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */ 2171 #define CS_QUEUE_FULL 0x1C /* Queue Full. */ 2172 #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */ 2173 /* (selection timeout) */ 2174 #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */ 2175 #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */ 2176 #define CS_PORT_BUSY 0x2B /* Port Busy */ 2177 #define CS_COMPLETE_CHKCOND 0x30 /* Error? */ 2178 #define CS_IOCB_ERROR 0x31 /* Generic error for IOCB request 2179 failure */ 2180 #define CS_REJECT_RECEIVED 0x4E /* Reject received */ 2181 #define CS_EDIF_AUTH_ERROR 0x63 /* decrypt error */ 2182 #define CS_EDIF_PAD_LEN_ERROR 0x65 /* pad > frame size, not 4byte align */ 2183 #define CS_EDIF_INV_REQ 0x66 /* invalid request */ 2184 #define CS_EDIF_SPI_ERROR 0x67 /* rx frame unable to locate sa */ 2185 #define CS_EDIF_HDR_ERROR 0x69 /* data frame != expected len */ 2186 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */ 2187 #define CS_UNKNOWN 0x81 /* Driver defined */ 2188 #define CS_RETRY 0x82 /* Driver defined */ 2189 #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */ 2190 2191 #define CS_BIDIR_RD_OVERRUN 0x700 2192 #define CS_BIDIR_RD_WR_OVERRUN 0x707 2193 #define CS_BIDIR_RD_OVERRUN_WR_UNDERRUN 0x715 2194 #define CS_BIDIR_RD_UNDERRUN 0x1500 2195 #define CS_BIDIR_RD_UNDERRUN_WR_OVERRUN 0x1507 2196 #define CS_BIDIR_RD_WR_UNDERRUN 0x1515 2197 #define CS_BIDIR_DMA 0x200 2198 /* 2199 * Status entry status flags 2200 */ 2201 #define SF_ABTS_TERMINATED BIT_10 2202 #define SF_LOGOUT_SENT BIT_13 2203 2204 /* 2205 * ISP queue - status continuation entry structure definition. 2206 */ 2207 #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */ 2208 typedef struct { 2209 uint8_t entry_type; /* Entry type. */ 2210 uint8_t entry_count; /* Entry count. */ 2211 uint8_t sys_define; /* System defined. */ 2212 uint8_t entry_status; /* Entry Status. */ 2213 uint8_t data[60]; /* data */ 2214 } sts_cont_entry_t; 2215 2216 /* 2217 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles) 2218 * structure definition. 2219 */ 2220 #define STATUS_TYPE_21 0x21 /* Status entry. */ 2221 typedef struct { 2222 uint8_t entry_type; /* Entry type. */ 2223 uint8_t entry_count; /* Entry count. */ 2224 uint8_t handle_count; /* Handle count. */ 2225 uint8_t entry_status; /* Entry Status. */ 2226 uint32_t handle[15]; /* System handles. */ 2227 } sts21_entry_t; 2228 2229 /* 2230 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles) 2231 * structure definition. 2232 */ 2233 #define STATUS_TYPE_22 0x22 /* Status entry. */ 2234 typedef struct { 2235 uint8_t entry_type; /* Entry type. */ 2236 uint8_t entry_count; /* Entry count. */ 2237 uint8_t handle_count; /* Handle count. */ 2238 uint8_t entry_status; /* Entry Status. */ 2239 uint16_t handle[30]; /* System handles. */ 2240 } sts22_entry_t; 2241 2242 /* 2243 * ISP queue - marker entry structure definition. 2244 */ 2245 #define MARKER_TYPE 0x04 /* Marker entry. */ 2246 typedef struct { 2247 uint8_t entry_type; /* Entry type. */ 2248 uint8_t entry_count; /* Entry count. */ 2249 uint8_t handle_count; /* Handle count. */ 2250 uint8_t entry_status; /* Entry Status. */ 2251 uint32_t sys_define_2; /* System defined. */ 2252 target_id_t target; /* SCSI ID */ 2253 uint8_t modifier; /* Modifier (7-0). */ 2254 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */ 2255 #define MK_SYNC_ID 1 /* Synchronize ID */ 2256 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */ 2257 #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */ 2258 /* clear port changed, */ 2259 /* use sequence number. */ 2260 uint8_t reserved_1; 2261 __le16 sequence_number; /* Sequence number of event */ 2262 __le16 lun; /* SCSI LUN */ 2263 uint8_t reserved_2[48]; 2264 } mrk_entry_t; 2265 2266 /* 2267 * ISP queue - Management Server entry structure definition. 2268 */ 2269 #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */ 2270 typedef struct { 2271 uint8_t entry_type; /* Entry type. */ 2272 uint8_t entry_count; /* Entry count. */ 2273 uint8_t handle_count; /* Handle count. */ 2274 uint8_t entry_status; /* Entry Status. */ 2275 uint32_t handle1; /* System handle. */ 2276 target_id_t loop_id; 2277 __le16 status; 2278 __le16 control_flags; /* Control flags. */ 2279 uint16_t reserved2; 2280 __le16 timeout; 2281 __le16 cmd_dsd_count; 2282 __le16 total_dsd_count; 2283 uint8_t type; 2284 uint8_t r_ctl; 2285 __le16 rx_id; 2286 uint16_t reserved3; 2287 uint32_t handle2; 2288 __le32 rsp_bytecount; 2289 __le32 req_bytecount; 2290 struct dsd64 req_dsd; 2291 struct dsd64 rsp_dsd; 2292 } ms_iocb_entry_t; 2293 2294 #define SCM_EDC_ACC_RECEIVED BIT_6 2295 #define SCM_RDF_ACC_RECEIVED BIT_7 2296 2297 /* 2298 * ISP queue - Mailbox Command entry structure definition. 2299 */ 2300 #define MBX_IOCB_TYPE 0x39 2301 struct mbx_entry { 2302 uint8_t entry_type; 2303 uint8_t entry_count; 2304 uint8_t sys_define1; 2305 /* Use sys_define1 for source type */ 2306 #define SOURCE_SCSI 0x00 2307 #define SOURCE_IP 0x01 2308 #define SOURCE_VI 0x02 2309 #define SOURCE_SCTP 0x03 2310 #define SOURCE_MP 0x04 2311 #define SOURCE_MPIOCTL 0x05 2312 #define SOURCE_ASYNC_IOCB 0x07 2313 2314 uint8_t entry_status; 2315 2316 uint32_t handle; 2317 target_id_t loop_id; 2318 2319 __le16 status; 2320 __le16 state_flags; 2321 __le16 status_flags; 2322 2323 uint32_t sys_define2[2]; 2324 2325 __le16 mb0; 2326 __le16 mb1; 2327 __le16 mb2; 2328 __le16 mb3; 2329 __le16 mb6; 2330 __le16 mb7; 2331 __le16 mb9; 2332 __le16 mb10; 2333 uint32_t reserved_2[2]; 2334 uint8_t node_name[WWN_SIZE]; 2335 uint8_t port_name[WWN_SIZE]; 2336 }; 2337 2338 #ifndef IMMED_NOTIFY_TYPE 2339 #define IMMED_NOTIFY_TYPE 0x0D /* Immediate notify entry. */ 2340 /* 2341 * ISP queue - immediate notify entry structure definition. 2342 * This is sent by the ISP to the Target driver. 2343 * This IOCB would have report of events sent by the 2344 * initiator, that needs to be handled by the target 2345 * driver immediately. 2346 */ 2347 struct imm_ntfy_from_isp { 2348 uint8_t entry_type; /* Entry type. */ 2349 uint8_t entry_count; /* Entry count. */ 2350 uint8_t sys_define; /* System defined. */ 2351 uint8_t entry_status; /* Entry Status. */ 2352 union { 2353 struct { 2354 __le32 sys_define_2; /* System defined. */ 2355 target_id_t target; 2356 __le16 lun; 2357 uint8_t target_id; 2358 uint8_t reserved_1; 2359 __le16 status_modifier; 2360 __le16 status; 2361 __le16 task_flags; 2362 __le16 seq_id; 2363 __le16 srr_rx_id; 2364 __le32 srr_rel_offs; 2365 __le16 srr_ui; 2366 #define SRR_IU_DATA_IN 0x1 2367 #define SRR_IU_DATA_OUT 0x5 2368 #define SRR_IU_STATUS 0x7 2369 __le16 srr_ox_id; 2370 uint8_t reserved_2[28]; 2371 } isp2x; 2372 struct { 2373 uint32_t reserved; 2374 __le16 nport_handle; 2375 uint16_t reserved_2; 2376 __le16 flags; 2377 #define NOTIFY24XX_FLAGS_FCSP BIT_5 2378 #define NOTIFY24XX_FLAGS_GLOBAL_TPRLO BIT_1 2379 #define NOTIFY24XX_FLAGS_PUREX_IOCB BIT_0 2380 __le16 srr_rx_id; 2381 __le16 status; 2382 uint8_t status_subcode; 2383 uint8_t fw_handle; 2384 __le32 exchange_address; 2385 __le32 srr_rel_offs; 2386 __le16 srr_ui; 2387 __le16 srr_ox_id; 2388 union { 2389 struct { 2390 uint8_t node_name[8]; 2391 } plogi; /* PLOGI/ADISC/PDISC */ 2392 struct { 2393 /* PRLI word 3 bit 0-15 */ 2394 __le16 wd3_lo; 2395 uint8_t resv0[6]; 2396 } prli; 2397 struct { 2398 uint8_t port_id[3]; 2399 uint8_t resv1; 2400 __le16 nport_handle; 2401 uint16_t resv2; 2402 } req_els; 2403 } u; 2404 uint8_t port_name[8]; 2405 uint8_t resv3[3]; 2406 uint8_t vp_index; 2407 uint32_t reserved_5; 2408 uint8_t port_id[3]; 2409 uint8_t reserved_6; 2410 } isp24; 2411 } u; 2412 uint16_t reserved_7; 2413 __le16 ox_id; 2414 } __packed; 2415 #endif 2416 2417 /* 2418 * ISP request and response queue entry sizes 2419 */ 2420 #define RESPONSE_ENTRY_SIZE (sizeof(response_t)) 2421 #define REQUEST_ENTRY_SIZE (sizeof(request_t)) 2422 2423 2424 2425 /* 2426 * Switch info gathering structure. 2427 */ 2428 typedef struct { 2429 port_id_t d_id; 2430 uint8_t node_name[WWN_SIZE]; 2431 uint8_t port_name[WWN_SIZE]; 2432 uint8_t fabric_port_name[WWN_SIZE]; 2433 uint16_t fp_speed; 2434 uint8_t fc4_type; 2435 uint8_t fc4_features; 2436 } sw_info_t; 2437 2438 /* FCP-4 types */ 2439 #define FC4_TYPE_FCP_SCSI 0x08 2440 #define FC4_TYPE_NVME 0x28 2441 #define FC4_TYPE_OTHER 0x0 2442 #define FC4_TYPE_UNKNOWN 0xff 2443 2444 /* mailbox command 4G & above */ 2445 struct mbx_24xx_entry { 2446 uint8_t entry_type; 2447 uint8_t entry_count; 2448 uint8_t sys_define1; 2449 uint8_t entry_status; 2450 uint32_t handle; 2451 uint16_t mb[28]; 2452 }; 2453 2454 #define IOCB_SIZE 64 2455 2456 /* 2457 * Fibre channel port type. 2458 */ 2459 typedef enum { 2460 FCT_UNKNOWN, 2461 FCT_BROADCAST = 0x01, 2462 FCT_INITIATOR = 0x02, 2463 FCT_TARGET = 0x04, 2464 FCT_NVME_INITIATOR = 0x10, 2465 FCT_NVME_TARGET = 0x20, 2466 FCT_NVME_DISCOVERY = 0x40, 2467 FCT_NVME = 0xf0, 2468 } fc_port_type_t; 2469 2470 enum qla_sess_deletion { 2471 QLA_SESS_DELETION_NONE = 0, 2472 QLA_SESS_DELETION_IN_PROGRESS, 2473 QLA_SESS_DELETED, 2474 }; 2475 2476 enum qlt_plogi_link_t { 2477 QLT_PLOGI_LINK_SAME_WWN, 2478 QLT_PLOGI_LINK_CONFLICT, 2479 QLT_PLOGI_LINK_MAX 2480 }; 2481 2482 struct qlt_plogi_ack_t { 2483 struct list_head list; 2484 struct imm_ntfy_from_isp iocb; 2485 port_id_t id; 2486 int ref_count; 2487 void *fcport; 2488 }; 2489 2490 struct ct_sns_desc { 2491 struct ct_sns_pkt *ct_sns; 2492 dma_addr_t ct_sns_dma; 2493 }; 2494 2495 enum discovery_state { 2496 DSC_DELETED, 2497 DSC_GNL, 2498 DSC_LOGIN_PEND, 2499 DSC_LOGIN_FAILED, 2500 DSC_GPDB, 2501 DSC_UPD_FCPORT, 2502 DSC_LOGIN_COMPLETE, 2503 DSC_ADISC, 2504 DSC_DELETE_PEND, 2505 DSC_LOGIN_AUTH_PEND, 2506 }; 2507 2508 enum login_state { /* FW control Target side */ 2509 DSC_LS_LLIOCB_SENT = 2, 2510 DSC_LS_PLOGI_PEND, 2511 DSC_LS_PLOGI_COMP, 2512 DSC_LS_PRLI_PEND, 2513 DSC_LS_PRLI_COMP, 2514 DSC_LS_PORT_UNAVAIL, 2515 DSC_LS_PRLO_PEND = 9, 2516 DSC_LS_LOGO_PEND, 2517 }; 2518 2519 enum rscn_addr_format { 2520 RSCN_PORT_ADDR, 2521 RSCN_AREA_ADDR, 2522 RSCN_DOM_ADDR, 2523 RSCN_FAB_ADDR, 2524 }; 2525 2526 /* 2527 * Fibre channel port structure. 2528 */ 2529 typedef struct fc_port { 2530 struct list_head list; 2531 struct scsi_qla_host *vha; 2532 2533 unsigned int conf_compl_supported:1; 2534 unsigned int deleted:2; 2535 unsigned int free_pending:1; 2536 unsigned int local:1; 2537 unsigned int logout_on_delete:1; 2538 unsigned int logo_ack_needed:1; 2539 unsigned int keep_nport_handle:1; 2540 unsigned int send_els_logo:1; 2541 unsigned int login_pause:1; 2542 unsigned int login_succ:1; 2543 unsigned int query:1; 2544 unsigned int id_changed:1; 2545 unsigned int scan_needed:1; 2546 unsigned int n2n_flag:1; 2547 unsigned int explicit_logout:1; 2548 unsigned int prli_pend_timer:1; 2549 unsigned int do_prli_nvme:1; 2550 2551 uint8_t nvme_flag; 2552 2553 uint8_t node_name[WWN_SIZE]; 2554 uint8_t port_name[WWN_SIZE]; 2555 port_id_t d_id; 2556 uint16_t loop_id; 2557 uint16_t old_loop_id; 2558 2559 struct completion nvme_del_done; 2560 uint32_t nvme_prli_service_param; 2561 #define NVME_PRLI_SP_PI_CTRL BIT_9 2562 #define NVME_PRLI_SP_SLER BIT_8 2563 #define NVME_PRLI_SP_CONF BIT_7 2564 #define NVME_PRLI_SP_INITIATOR BIT_5 2565 #define NVME_PRLI_SP_TARGET BIT_4 2566 #define NVME_PRLI_SP_DISCOVERY BIT_3 2567 #define NVME_PRLI_SP_FIRST_BURST BIT_0 2568 2569 uint32_t nvme_first_burst_size; 2570 #define NVME_FLAG_REGISTERED 4 2571 #define NVME_FLAG_DELETING 2 2572 #define NVME_FLAG_RESETTING 1 2573 2574 struct fc_port *conflict; 2575 unsigned char logout_completed; 2576 int generation; 2577 2578 struct se_session *se_sess; 2579 struct list_head sess_cmd_list; 2580 spinlock_t sess_cmd_lock; 2581 struct kref sess_kref; 2582 struct qla_tgt *tgt; 2583 unsigned long expires; 2584 struct list_head del_list_entry; 2585 struct work_struct free_work; 2586 struct work_struct reg_work; 2587 uint64_t jiffies_at_registration; 2588 unsigned long prli_expired; 2589 struct qlt_plogi_ack_t *plogi_link[QLT_PLOGI_LINK_MAX]; 2590 2591 uint16_t tgt_id; 2592 uint16_t old_tgt_id; 2593 uint16_t sec_since_registration; 2594 2595 uint8_t fcp_prio; 2596 2597 uint8_t fabric_port_name[WWN_SIZE]; 2598 uint16_t fp_speed; 2599 2600 fc_port_type_t port_type; 2601 2602 atomic_t state; 2603 uint32_t flags; 2604 2605 int login_retry; 2606 2607 struct fc_rport *rport; 2608 u32 supported_classes; 2609 2610 uint8_t fc4_type; 2611 uint8_t fc4_features; 2612 uint8_t scan_state; 2613 2614 unsigned long last_queue_full; 2615 unsigned long last_ramp_up; 2616 2617 uint16_t port_id; 2618 2619 struct nvme_fc_remote_port *nvme_remote_port; 2620 2621 unsigned long retry_delay_timestamp; 2622 struct qla_tgt_sess *tgt_session; 2623 struct ct_sns_desc ct_desc; 2624 enum discovery_state disc_state; 2625 atomic_t shadow_disc_state; 2626 enum discovery_state next_disc_state; 2627 enum login_state fw_login_state; 2628 unsigned long dm_login_expire; 2629 unsigned long plogi_nack_done_deadline; 2630 2631 u32 login_gen, last_login_gen; 2632 u32 rscn_gen, last_rscn_gen; 2633 u32 chip_reset; 2634 struct list_head gnl_entry; 2635 struct work_struct del_work; 2636 u8 iocb[IOCB_SIZE]; 2637 u8 current_login_state; 2638 u8 last_login_state; 2639 u16 n2n_link_reset_cnt; 2640 u16 n2n_chip_reset; 2641 2642 struct dentry *dfs_rport_dir; 2643 2644 u64 tgt_short_link_down_cnt; 2645 u64 tgt_link_down_time; 2646 u64 dev_loss_tmo; 2647 /* 2648 * EDIF parameters for encryption. 2649 */ 2650 struct { 2651 uint32_t enable:1; /* device is edif enabled/req'd */ 2652 uint32_t app_stop:2; 2653 uint32_t aes_gmac:1; 2654 uint32_t app_sess_online:1; 2655 uint32_t tx_sa_set:1; 2656 uint32_t rx_sa_set:1; 2657 uint32_t tx_sa_pending:1; 2658 uint32_t rx_sa_pending:1; 2659 uint32_t tx_rekey_cnt; 2660 uint32_t rx_rekey_cnt; 2661 uint64_t tx_bytes; 2662 uint64_t rx_bytes; 2663 uint8_t sess_down_acked; 2664 uint8_t auth_state; 2665 uint16_t authok:1; 2666 uint16_t rekey_cnt; 2667 struct list_head edif_indx_list; 2668 spinlock_t indx_list_lock; 2669 2670 struct list_head tx_sa_list; 2671 struct list_head rx_sa_list; 2672 spinlock_t sa_list_lock; 2673 } edif; 2674 } fc_port_t; 2675 2676 enum { 2677 FC4_PRIORITY_NVME = 1, 2678 FC4_PRIORITY_FCP = 2, 2679 }; 2680 2681 #define QLA_FCPORT_SCAN 1 2682 #define QLA_FCPORT_FOUND 2 2683 2684 struct event_arg { 2685 fc_port_t *fcport; 2686 srb_t *sp; 2687 port_id_t id; 2688 u16 data[2], rc; 2689 u8 port_name[WWN_SIZE]; 2690 u32 iop[2]; 2691 }; 2692 2693 #include "qla_mr.h" 2694 2695 /* 2696 * Fibre channel port/lun states. 2697 */ 2698 enum { 2699 FCS_UNKNOWN, 2700 FCS_UNCONFIGURED, 2701 FCS_DEVICE_DEAD, 2702 FCS_DEVICE_LOST, 2703 FCS_ONLINE, 2704 }; 2705 2706 extern const char *const port_state_str[5]; 2707 2708 static const char *const port_dstate_str[] = { 2709 [DSC_DELETED] = "DELETED", 2710 [DSC_GNL] = "GNL", 2711 [DSC_LOGIN_PEND] = "LOGIN_PEND", 2712 [DSC_LOGIN_FAILED] = "LOGIN_FAILED", 2713 [DSC_GPDB] = "GPDB", 2714 [DSC_UPD_FCPORT] = "UPD_FCPORT", 2715 [DSC_LOGIN_COMPLETE] = "LOGIN_COMPLETE", 2716 [DSC_ADISC] = "ADISC", 2717 [DSC_DELETE_PEND] = "DELETE_PEND", 2718 [DSC_LOGIN_AUTH_PEND] = "LOGIN_AUTH_PEND", 2719 }; 2720 2721 /* 2722 * FC port flags. 2723 */ 2724 #define FCF_FABRIC_DEVICE BIT_0 2725 #define FCF_LOGIN_NEEDED BIT_1 2726 #define FCF_FCP2_DEVICE BIT_2 2727 #define FCF_ASYNC_SENT BIT_3 2728 #define FCF_CONF_COMP_SUPPORTED BIT_4 2729 #define FCF_ASYNC_ACTIVE BIT_5 2730 #define FCF_FCSP_DEVICE BIT_6 2731 #define FCF_EDIF_DELETE BIT_7 2732 2733 /* No loop ID flag. */ 2734 #define FC_NO_LOOP_ID 0x1000 2735 2736 /* 2737 * FC-CT interface 2738 * 2739 * NOTE: All structures are big-endian in form. 2740 */ 2741 2742 #define CT_REJECT_RESPONSE 0x8001 2743 #define CT_ACCEPT_RESPONSE 0x8002 2744 #define CT_REASON_INVALID_COMMAND_CODE 0x01 2745 #define CT_REASON_CANNOT_PERFORM 0x09 2746 #define CT_REASON_COMMAND_UNSUPPORTED 0x0b 2747 #define CT_EXPL_ALREADY_REGISTERED 0x10 2748 #define CT_EXPL_HBA_ATTR_NOT_REGISTERED 0x11 2749 #define CT_EXPL_MULTIPLE_HBA_ATTR 0x12 2750 #define CT_EXPL_INVALID_HBA_BLOCK_LENGTH 0x13 2751 #define CT_EXPL_MISSING_REQ_HBA_ATTR 0x14 2752 #define CT_EXPL_PORT_NOT_REGISTERED_ 0x15 2753 #define CT_EXPL_MISSING_HBA_ID_PORT_LIST 0x16 2754 #define CT_EXPL_HBA_NOT_REGISTERED 0x17 2755 #define CT_EXPL_PORT_ATTR_NOT_REGISTERED 0x20 2756 #define CT_EXPL_PORT_NOT_REGISTERED 0x21 2757 #define CT_EXPL_MULTIPLE_PORT_ATTR 0x22 2758 #define CT_EXPL_INVALID_PORT_BLOCK_LENGTH 0x23 2759 2760 #define NS_N_PORT_TYPE 0x01 2761 #define NS_NL_PORT_TYPE 0x02 2762 #define NS_NX_PORT_TYPE 0x7F 2763 2764 #define GA_NXT_CMD 0x100 2765 #define GA_NXT_REQ_SIZE (16 + 4) 2766 #define GA_NXT_RSP_SIZE (16 + 620) 2767 2768 #define GPN_FT_CMD 0x172 2769 #define GPN_FT_REQ_SIZE (16 + 4) 2770 #define GNN_FT_CMD 0x173 2771 #define GNN_FT_REQ_SIZE (16 + 4) 2772 2773 #define GID_PT_CMD 0x1A1 2774 #define GID_PT_REQ_SIZE (16 + 4) 2775 2776 #define GPN_ID_CMD 0x112 2777 #define GPN_ID_REQ_SIZE (16 + 4) 2778 #define GPN_ID_RSP_SIZE (16 + 8) 2779 2780 #define GNN_ID_CMD 0x113 2781 #define GNN_ID_REQ_SIZE (16 + 4) 2782 #define GNN_ID_RSP_SIZE (16 + 8) 2783 2784 #define GFT_ID_CMD 0x117 2785 #define GFT_ID_REQ_SIZE (16 + 4) 2786 #define GFT_ID_RSP_SIZE (16 + 32) 2787 2788 #define GID_PN_CMD 0x121 2789 #define GID_PN_REQ_SIZE (16 + 8) 2790 #define GID_PN_RSP_SIZE (16 + 4) 2791 2792 #define RFT_ID_CMD 0x217 2793 #define RFT_ID_REQ_SIZE (16 + 4 + 32) 2794 #define RFT_ID_RSP_SIZE 16 2795 2796 #define RFF_ID_CMD 0x21F 2797 #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1) 2798 #define RFF_ID_RSP_SIZE 16 2799 2800 #define RNN_ID_CMD 0x213 2801 #define RNN_ID_REQ_SIZE (16 + 4 + 8) 2802 #define RNN_ID_RSP_SIZE 16 2803 2804 #define RSNN_NN_CMD 0x239 2805 #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255) 2806 #define RSNN_NN_RSP_SIZE 16 2807 2808 #define GFPN_ID_CMD 0x11C 2809 #define GFPN_ID_REQ_SIZE (16 + 4) 2810 #define GFPN_ID_RSP_SIZE (16 + 8) 2811 2812 #define GPSC_CMD 0x127 2813 #define GPSC_REQ_SIZE (16 + 8) 2814 #define GPSC_RSP_SIZE (16 + 2 + 2) 2815 2816 #define GFF_ID_CMD 0x011F 2817 #define GFF_ID_REQ_SIZE (16 + 4) 2818 #define GFF_ID_RSP_SIZE (16 + 128) 2819 2820 /* 2821 * FDMI HBA attribute types. 2822 */ 2823 #define FDMI1_HBA_ATTR_COUNT 10 2824 #define FDMI2_HBA_ATTR_COUNT 17 2825 2826 #define FDMI_HBA_NODE_NAME 0x1 2827 #define FDMI_HBA_MANUFACTURER 0x2 2828 #define FDMI_HBA_SERIAL_NUMBER 0x3 2829 #define FDMI_HBA_MODEL 0x4 2830 #define FDMI_HBA_MODEL_DESCRIPTION 0x5 2831 #define FDMI_HBA_HARDWARE_VERSION 0x6 2832 #define FDMI_HBA_DRIVER_VERSION 0x7 2833 #define FDMI_HBA_OPTION_ROM_VERSION 0x8 2834 #define FDMI_HBA_FIRMWARE_VERSION 0x9 2835 #define FDMI_HBA_OS_NAME_AND_VERSION 0xa 2836 #define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb 2837 2838 #define FDMI_HBA_NODE_SYMBOLIC_NAME 0xc 2839 #define FDMI_HBA_VENDOR_SPECIFIC_INFO 0xd 2840 #define FDMI_HBA_NUM_PORTS 0xe 2841 #define FDMI_HBA_FABRIC_NAME 0xf 2842 #define FDMI_HBA_BOOT_BIOS_NAME 0x10 2843 #define FDMI_HBA_VENDOR_IDENTIFIER 0xe0 2844 2845 struct ct_fdmi_hba_attr { 2846 __be16 type; 2847 __be16 len; 2848 union { 2849 uint8_t node_name[WWN_SIZE]; 2850 uint8_t manufacturer[64]; 2851 uint8_t serial_num[32]; 2852 uint8_t model[16+1]; 2853 uint8_t model_desc[80]; 2854 uint8_t hw_version[32]; 2855 uint8_t driver_version[32]; 2856 uint8_t orom_version[16]; 2857 uint8_t fw_version[32]; 2858 uint8_t os_version[128]; 2859 __be32 max_ct_len; 2860 2861 uint8_t sym_name[256]; 2862 __be32 vendor_specific_info; 2863 __be32 num_ports; 2864 uint8_t fabric_name[WWN_SIZE]; 2865 uint8_t bios_name[32]; 2866 uint8_t vendor_identifier[8]; 2867 } a; 2868 }; 2869 2870 struct ct_fdmi1_hba_attributes { 2871 __be32 count; 2872 struct ct_fdmi_hba_attr entry[FDMI1_HBA_ATTR_COUNT]; 2873 }; 2874 2875 struct ct_fdmi2_hba_attributes { 2876 __be32 count; 2877 struct ct_fdmi_hba_attr entry[FDMI2_HBA_ATTR_COUNT]; 2878 }; 2879 2880 /* 2881 * FDMI Port attribute types. 2882 */ 2883 #define FDMI1_PORT_ATTR_COUNT 6 2884 #define FDMI2_PORT_ATTR_COUNT 16 2885 #define FDMI2_SMARTSAN_PORT_ATTR_COUNT 23 2886 2887 #define FDMI_PORT_FC4_TYPES 0x1 2888 #define FDMI_PORT_SUPPORT_SPEED 0x2 2889 #define FDMI_PORT_CURRENT_SPEED 0x3 2890 #define FDMI_PORT_MAX_FRAME_SIZE 0x4 2891 #define FDMI_PORT_OS_DEVICE_NAME 0x5 2892 #define FDMI_PORT_HOST_NAME 0x6 2893 2894 #define FDMI_PORT_NODE_NAME 0x7 2895 #define FDMI_PORT_NAME 0x8 2896 #define FDMI_PORT_SYM_NAME 0x9 2897 #define FDMI_PORT_TYPE 0xa 2898 #define FDMI_PORT_SUPP_COS 0xb 2899 #define FDMI_PORT_FABRIC_NAME 0xc 2900 #define FDMI_PORT_FC4_TYPE 0xd 2901 #define FDMI_PORT_STATE 0x101 2902 #define FDMI_PORT_COUNT 0x102 2903 #define FDMI_PORT_IDENTIFIER 0x103 2904 2905 #define FDMI_SMARTSAN_SERVICE 0xF100 2906 #define FDMI_SMARTSAN_GUID 0xF101 2907 #define FDMI_SMARTSAN_VERSION 0xF102 2908 #define FDMI_SMARTSAN_PROD_NAME 0xF103 2909 #define FDMI_SMARTSAN_PORT_INFO 0xF104 2910 #define FDMI_SMARTSAN_QOS_SUPPORT 0xF105 2911 #define FDMI_SMARTSAN_SECURITY_SUPPORT 0xF106 2912 2913 #define FDMI_PORT_SPEED_1GB 0x1 2914 #define FDMI_PORT_SPEED_2GB 0x2 2915 #define FDMI_PORT_SPEED_10GB 0x4 2916 #define FDMI_PORT_SPEED_4GB 0x8 2917 #define FDMI_PORT_SPEED_8GB 0x10 2918 #define FDMI_PORT_SPEED_16GB 0x20 2919 #define FDMI_PORT_SPEED_32GB 0x40 2920 #define FDMI_PORT_SPEED_20GB 0x80 2921 #define FDMI_PORT_SPEED_40GB 0x100 2922 #define FDMI_PORT_SPEED_128GB 0x200 2923 #define FDMI_PORT_SPEED_64GB 0x400 2924 #define FDMI_PORT_SPEED_256GB 0x800 2925 #define FDMI_PORT_SPEED_UNKNOWN 0x8000 2926 2927 #define FC_CLASS_2 0x04 2928 #define FC_CLASS_3 0x08 2929 #define FC_CLASS_2_3 0x0C 2930 2931 struct ct_fdmi_port_attr { 2932 __be16 type; 2933 __be16 len; 2934 union { 2935 uint8_t fc4_types[32]; 2936 __be32 sup_speed; 2937 __be32 cur_speed; 2938 __be32 max_frame_size; 2939 uint8_t os_dev_name[32]; 2940 uint8_t host_name[256]; 2941 2942 uint8_t node_name[WWN_SIZE]; 2943 uint8_t port_name[WWN_SIZE]; 2944 uint8_t port_sym_name[128]; 2945 __be32 port_type; 2946 __be32 port_supported_cos; 2947 uint8_t fabric_name[WWN_SIZE]; 2948 uint8_t port_fc4_type[32]; 2949 __be32 port_state; 2950 __be32 num_ports; 2951 __be32 port_id; 2952 2953 uint8_t smartsan_service[24]; 2954 uint8_t smartsan_guid[16]; 2955 uint8_t smartsan_version[24]; 2956 uint8_t smartsan_prod_name[16]; 2957 __be32 smartsan_port_info; 2958 __be32 smartsan_qos_support; 2959 __be32 smartsan_security_support; 2960 } a; 2961 }; 2962 2963 struct ct_fdmi1_port_attributes { 2964 __be32 count; 2965 struct ct_fdmi_port_attr entry[FDMI1_PORT_ATTR_COUNT]; 2966 }; 2967 2968 struct ct_fdmi2_port_attributes { 2969 __be32 count; 2970 struct ct_fdmi_port_attr entry[FDMI2_PORT_ATTR_COUNT]; 2971 }; 2972 2973 #define FDMI_ATTR_TYPELEN(obj) \ 2974 (sizeof((obj)->type) + sizeof((obj)->len)) 2975 2976 #define FDMI_ATTR_ALIGNMENT(len) \ 2977 (4 - ((len) & 3)) 2978 2979 /* FDMI register call options */ 2980 #define CALLOPT_FDMI1 0 2981 #define CALLOPT_FDMI2 1 2982 #define CALLOPT_FDMI2_SMARTSAN 2 2983 2984 /* FDMI definitions. */ 2985 #define GRHL_CMD 0x100 2986 #define GHAT_CMD 0x101 2987 #define GRPL_CMD 0x102 2988 #define GPAT_CMD 0x110 2989 2990 #define RHBA_CMD 0x200 2991 #define RHBA_RSP_SIZE 16 2992 2993 #define RHAT_CMD 0x201 2994 2995 #define RPRT_CMD 0x210 2996 #define RPRT_RSP_SIZE 24 2997 2998 #define RPA_CMD 0x211 2999 #define RPA_RSP_SIZE 16 3000 #define SMARTSAN_RPA_RSP_SIZE 24 3001 3002 #define DHBA_CMD 0x300 3003 #define DHBA_REQ_SIZE (16 + 8) 3004 #define DHBA_RSP_SIZE 16 3005 3006 #define DHAT_CMD 0x301 3007 #define DPRT_CMD 0x310 3008 #define DPA_CMD 0x311 3009 3010 /* CT command header -- request/response common fields */ 3011 struct ct_cmd_hdr { 3012 uint8_t revision; 3013 uint8_t in_id[3]; 3014 uint8_t gs_type; 3015 uint8_t gs_subtype; 3016 uint8_t options; 3017 uint8_t reserved; 3018 }; 3019 3020 /* CT command request */ 3021 struct ct_sns_req { 3022 struct ct_cmd_hdr header; 3023 __be16 command; 3024 __be16 max_rsp_size; 3025 uint8_t fragment_id; 3026 uint8_t reserved[3]; 3027 3028 union { 3029 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */ 3030 struct { 3031 uint8_t reserved; 3032 be_id_t port_id; 3033 } port_id; 3034 3035 struct { 3036 uint8_t reserved; 3037 uint8_t domain; 3038 uint8_t area; 3039 uint8_t port_type; 3040 } gpn_ft; 3041 3042 struct { 3043 uint8_t port_type; 3044 uint8_t domain; 3045 uint8_t area; 3046 uint8_t reserved; 3047 } gid_pt; 3048 3049 struct { 3050 uint8_t reserved; 3051 be_id_t port_id; 3052 uint8_t fc4_types[32]; 3053 } rft_id; 3054 3055 struct { 3056 uint8_t reserved; 3057 be_id_t port_id; 3058 uint16_t reserved2; 3059 uint8_t fc4_feature; 3060 uint8_t fc4_type; 3061 } rff_id; 3062 3063 struct { 3064 uint8_t reserved; 3065 be_id_t port_id; 3066 uint8_t node_name[8]; 3067 } rnn_id; 3068 3069 struct { 3070 uint8_t node_name[8]; 3071 uint8_t name_len; 3072 uint8_t sym_node_name[255]; 3073 } rsnn_nn; 3074 3075 struct { 3076 uint8_t hba_identifier[8]; 3077 } ghat; 3078 3079 struct { 3080 uint8_t hba_identifier[8]; 3081 __be32 entry_count; 3082 uint8_t port_name[8]; 3083 struct ct_fdmi2_hba_attributes attrs; 3084 } rhba; 3085 3086 struct { 3087 uint8_t hba_identifier[8]; 3088 struct ct_fdmi1_hba_attributes attrs; 3089 } rhat; 3090 3091 struct { 3092 uint8_t port_name[8]; 3093 struct ct_fdmi2_port_attributes attrs; 3094 } rpa; 3095 3096 struct { 3097 uint8_t hba_identifier[8]; 3098 uint8_t port_name[8]; 3099 struct ct_fdmi2_port_attributes attrs; 3100 } rprt; 3101 3102 struct { 3103 uint8_t port_name[8]; 3104 } dhba; 3105 3106 struct { 3107 uint8_t port_name[8]; 3108 } dhat; 3109 3110 struct { 3111 uint8_t port_name[8]; 3112 } dprt; 3113 3114 struct { 3115 uint8_t port_name[8]; 3116 } dpa; 3117 3118 struct { 3119 uint8_t port_name[8]; 3120 } gpsc; 3121 3122 struct { 3123 uint8_t reserved; 3124 uint8_t port_id[3]; 3125 } gff_id; 3126 3127 struct { 3128 uint8_t port_name[8]; 3129 } gid_pn; 3130 } req; 3131 }; 3132 3133 /* CT command response header */ 3134 struct ct_rsp_hdr { 3135 struct ct_cmd_hdr header; 3136 __be16 response; 3137 uint16_t residual; 3138 uint8_t fragment_id; 3139 uint8_t reason_code; 3140 uint8_t explanation_code; 3141 uint8_t vendor_unique; 3142 }; 3143 3144 struct ct_sns_gid_pt_data { 3145 uint8_t control_byte; 3146 be_id_t port_id; 3147 }; 3148 3149 /* It's the same for both GPN_FT and GNN_FT */ 3150 struct ct_sns_gpnft_rsp { 3151 struct { 3152 struct ct_cmd_hdr header; 3153 uint16_t response; 3154 uint16_t residual; 3155 uint8_t fragment_id; 3156 uint8_t reason_code; 3157 uint8_t explanation_code; 3158 uint8_t vendor_unique; 3159 }; 3160 /* Assume the largest number of targets for the union */ 3161 struct ct_sns_gpn_ft_data { 3162 u8 control_byte; 3163 u8 port_id[3]; 3164 u32 reserved; 3165 u8 port_name[8]; 3166 } entries[1]; 3167 }; 3168 3169 /* CT command response */ 3170 struct ct_sns_rsp { 3171 struct ct_rsp_hdr header; 3172 3173 union { 3174 struct { 3175 uint8_t port_type; 3176 be_id_t port_id; 3177 uint8_t port_name[8]; 3178 uint8_t sym_port_name_len; 3179 uint8_t sym_port_name[255]; 3180 uint8_t node_name[8]; 3181 uint8_t sym_node_name_len; 3182 uint8_t sym_node_name[255]; 3183 uint8_t init_proc_assoc[8]; 3184 uint8_t node_ip_addr[16]; 3185 uint8_t class_of_service[4]; 3186 uint8_t fc4_types[32]; 3187 uint8_t ip_address[16]; 3188 uint8_t fabric_port_name[8]; 3189 uint8_t reserved; 3190 uint8_t hard_address[3]; 3191 } ga_nxt; 3192 3193 struct { 3194 /* Assume the largest number of targets for the union */ 3195 struct ct_sns_gid_pt_data 3196 entries[MAX_FIBRE_DEVICES_MAX]; 3197 } gid_pt; 3198 3199 struct { 3200 uint8_t port_name[8]; 3201 } gpn_id; 3202 3203 struct { 3204 uint8_t node_name[8]; 3205 } gnn_id; 3206 3207 struct { 3208 uint8_t fc4_types[32]; 3209 } gft_id; 3210 3211 struct { 3212 uint32_t entry_count; 3213 uint8_t port_name[8]; 3214 struct ct_fdmi1_hba_attributes attrs; 3215 } ghat; 3216 3217 struct { 3218 uint8_t port_name[8]; 3219 } gfpn_id; 3220 3221 struct { 3222 __be16 speeds; 3223 __be16 speed; 3224 } gpsc; 3225 3226 #define GFF_FCP_SCSI_OFFSET 7 3227 #define GFF_NVME_OFFSET 23 /* type = 28h */ 3228 struct { 3229 uint8_t fc4_features[128]; 3230 #define FC4_FF_TARGET BIT_0 3231 #define FC4_FF_INITIATOR BIT_1 3232 } gff_id; 3233 struct { 3234 uint8_t reserved; 3235 uint8_t port_id[3]; 3236 } gid_pn; 3237 } rsp; 3238 }; 3239 3240 struct ct_sns_pkt { 3241 union { 3242 struct ct_sns_req req; 3243 struct ct_sns_rsp rsp; 3244 } p; 3245 }; 3246 3247 struct ct_sns_gpnft_pkt { 3248 union { 3249 struct ct_sns_req req; 3250 struct ct_sns_gpnft_rsp rsp; 3251 } p; 3252 }; 3253 3254 enum scan_flags_t { 3255 SF_SCANNING = BIT_0, 3256 SF_QUEUED = BIT_1, 3257 }; 3258 3259 enum fc4type_t { 3260 FS_FC4TYPE_FCP = BIT_0, 3261 FS_FC4TYPE_NVME = BIT_1, 3262 FS_FCP_IS_N2N = BIT_7, 3263 }; 3264 3265 struct fab_scan_rp { 3266 port_id_t id; 3267 enum fc4type_t fc4type; 3268 u8 port_name[8]; 3269 u8 node_name[8]; 3270 }; 3271 3272 struct fab_scan { 3273 struct fab_scan_rp *l; 3274 u32 size; 3275 u16 scan_retry; 3276 #define MAX_SCAN_RETRIES 5 3277 enum scan_flags_t scan_flags; 3278 struct delayed_work scan_work; 3279 }; 3280 3281 /* 3282 * SNS command structures -- for 2200 compatibility. 3283 */ 3284 #define RFT_ID_SNS_SCMD_LEN 22 3285 #define RFT_ID_SNS_CMD_SIZE 60 3286 #define RFT_ID_SNS_DATA_SIZE 16 3287 3288 #define RNN_ID_SNS_SCMD_LEN 10 3289 #define RNN_ID_SNS_CMD_SIZE 36 3290 #define RNN_ID_SNS_DATA_SIZE 16 3291 3292 #define GA_NXT_SNS_SCMD_LEN 6 3293 #define GA_NXT_SNS_CMD_SIZE 28 3294 #define GA_NXT_SNS_DATA_SIZE (620 + 16) 3295 3296 #define GID_PT_SNS_SCMD_LEN 6 3297 #define GID_PT_SNS_CMD_SIZE 28 3298 /* 3299 * Assume MAX_FIBRE_DEVICES_2100 as these defines are only used with older 3300 * adapters. 3301 */ 3302 #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES_2100 * 4 + 16) 3303 3304 #define GPN_ID_SNS_SCMD_LEN 6 3305 #define GPN_ID_SNS_CMD_SIZE 28 3306 #define GPN_ID_SNS_DATA_SIZE (8 + 16) 3307 3308 #define GNN_ID_SNS_SCMD_LEN 6 3309 #define GNN_ID_SNS_CMD_SIZE 28 3310 #define GNN_ID_SNS_DATA_SIZE (8 + 16) 3311 3312 struct sns_cmd_pkt { 3313 union { 3314 struct { 3315 __le16 buffer_length; 3316 __le16 reserved_1; 3317 __le64 buffer_address __packed; 3318 __le16 subcommand_length; 3319 __le16 reserved_2; 3320 __le16 subcommand; 3321 __le16 size; 3322 uint32_t reserved_3; 3323 uint8_t param[36]; 3324 } cmd; 3325 3326 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE]; 3327 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE]; 3328 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE]; 3329 uint8_t gid_data[GID_PT_SNS_DATA_SIZE]; 3330 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE]; 3331 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE]; 3332 } p; 3333 }; 3334 3335 struct fw_blob { 3336 char *name; 3337 uint32_t segs[4]; 3338 const struct firmware *fw; 3339 }; 3340 3341 /* Return data from MBC_GET_ID_LIST call. */ 3342 struct gid_list_info { 3343 uint8_t al_pa; 3344 uint8_t area; 3345 uint8_t domain; 3346 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */ 3347 __le16 loop_id; /* ISP23XX -- 6 bytes. */ 3348 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */ 3349 }; 3350 3351 /* NPIV */ 3352 typedef struct vport_info { 3353 uint8_t port_name[WWN_SIZE]; 3354 uint8_t node_name[WWN_SIZE]; 3355 int vp_id; 3356 uint16_t loop_id; 3357 unsigned long host_no; 3358 uint8_t port_id[3]; 3359 int loop_state; 3360 } vport_info_t; 3361 3362 typedef struct vport_params { 3363 uint8_t port_name[WWN_SIZE]; 3364 uint8_t node_name[WWN_SIZE]; 3365 uint32_t options; 3366 #define VP_OPTS_RETRY_ENABLE BIT_0 3367 #define VP_OPTS_VP_DISABLE BIT_1 3368 } vport_params_t; 3369 3370 /* NPIV - return codes of VP create and modify */ 3371 #define VP_RET_CODE_OK 0 3372 #define VP_RET_CODE_FATAL 1 3373 #define VP_RET_CODE_WRONG_ID 2 3374 #define VP_RET_CODE_WWPN 3 3375 #define VP_RET_CODE_RESOURCES 4 3376 #define VP_RET_CODE_NO_MEM 5 3377 #define VP_RET_CODE_NOT_FOUND 6 3378 3379 struct qla_hw_data; 3380 struct rsp_que; 3381 /* 3382 * ISP operations 3383 */ 3384 struct isp_operations { 3385 3386 int (*pci_config) (struct scsi_qla_host *); 3387 int (*reset_chip)(struct scsi_qla_host *); 3388 int (*chip_diag) (struct scsi_qla_host *); 3389 void (*config_rings) (struct scsi_qla_host *); 3390 int (*reset_adapter)(struct scsi_qla_host *); 3391 int (*nvram_config) (struct scsi_qla_host *); 3392 void (*update_fw_options) (struct scsi_qla_host *); 3393 int (*load_risc) (struct scsi_qla_host *, uint32_t *); 3394 3395 char * (*pci_info_str)(struct scsi_qla_host *, char *, size_t); 3396 char * (*fw_version_str)(struct scsi_qla_host *, char *, size_t); 3397 3398 irq_handler_t intr_handler; 3399 void (*enable_intrs) (struct qla_hw_data *); 3400 void (*disable_intrs) (struct qla_hw_data *); 3401 3402 int (*abort_command) (srb_t *); 3403 int (*target_reset) (struct fc_port *, uint64_t, int); 3404 int (*lun_reset) (struct fc_port *, uint64_t, int); 3405 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t, 3406 uint8_t, uint8_t, uint16_t *, uint8_t); 3407 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t, 3408 uint8_t, uint8_t); 3409 3410 uint16_t (*calc_req_entries) (uint16_t); 3411 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t); 3412 void *(*prep_ms_iocb) (struct scsi_qla_host *, struct ct_arg *); 3413 void *(*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t, 3414 uint32_t); 3415 3416 uint8_t *(*read_nvram)(struct scsi_qla_host *, void *, 3417 uint32_t, uint32_t); 3418 int (*write_nvram)(struct scsi_qla_host *, void *, uint32_t, 3419 uint32_t); 3420 3421 void (*fw_dump)(struct scsi_qla_host *vha); 3422 void (*mpi_fw_dump)(struct scsi_qla_host *, int); 3423 3424 /* Context: task, might sleep */ 3425 int (*beacon_on) (struct scsi_qla_host *); 3426 int (*beacon_off) (struct scsi_qla_host *); 3427 3428 void (*beacon_blink) (struct scsi_qla_host *); 3429 3430 void *(*read_optrom)(struct scsi_qla_host *, void *, 3431 uint32_t, uint32_t); 3432 int (*write_optrom)(struct scsi_qla_host *, void *, uint32_t, 3433 uint32_t); 3434 3435 int (*get_flash_version) (struct scsi_qla_host *, void *); 3436 int (*start_scsi) (srb_t *); 3437 int (*start_scsi_mq) (srb_t *); 3438 3439 /* Context: task, might sleep */ 3440 int (*abort_isp) (struct scsi_qla_host *); 3441 3442 int (*iospace_config)(struct qla_hw_data *); 3443 int (*initialize_adapter)(struct scsi_qla_host *); 3444 }; 3445 3446 /* MSI-X Support *************************************************************/ 3447 3448 #define QLA_MSIX_CHIP_REV_24XX 3 3449 #define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7) 3450 #define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1) 3451 3452 #define QLA_BASE_VECTORS 2 /* default + RSP */ 3453 #define QLA_MSIX_RSP_Q 0x01 3454 #define QLA_ATIO_VECTOR 0x02 3455 #define QLA_MSIX_QPAIR_MULTIQ_RSP_Q 0x03 3456 #define QLA_MSIX_QPAIR_MULTIQ_RSP_Q_HS 0x04 3457 3458 #define QLA_MIDX_DEFAULT 0 3459 #define QLA_MIDX_RSP_Q 1 3460 #define QLA_PCI_MSIX_CONTROL 0xa2 3461 #define QLA_83XX_PCI_MSIX_CONTROL 0x92 3462 3463 struct scsi_qla_host; 3464 3465 3466 #define QLA83XX_RSPQ_MSIX_ENTRY_NUMBER 1 /* refer to qla83xx_msix_entries */ 3467 3468 struct qla_msix_entry { 3469 int have_irq; 3470 int in_use; 3471 uint32_t vector; 3472 uint32_t vector_base0; 3473 uint16_t entry; 3474 char name[30]; 3475 void *handle; 3476 int cpuid; 3477 }; 3478 3479 #define WATCH_INTERVAL 1 /* number of seconds */ 3480 3481 /* Work events. */ 3482 enum qla_work_type { 3483 QLA_EVT_AEN, 3484 QLA_EVT_IDC_ACK, 3485 QLA_EVT_ASYNC_LOGIN, 3486 QLA_EVT_ASYNC_LOGOUT, 3487 QLA_EVT_ASYNC_ADISC, 3488 QLA_EVT_UEVENT, 3489 QLA_EVT_AENFX, 3490 QLA_EVT_UNMAP, 3491 QLA_EVT_NEW_SESS, 3492 QLA_EVT_GPDB, 3493 QLA_EVT_PRLI, 3494 QLA_EVT_GPSC, 3495 QLA_EVT_GNL, 3496 QLA_EVT_NACK, 3497 QLA_EVT_RELOGIN, 3498 QLA_EVT_ASYNC_PRLO, 3499 QLA_EVT_ASYNC_PRLO_DONE, 3500 QLA_EVT_GPNFT, 3501 QLA_EVT_GPNFT_DONE, 3502 QLA_EVT_GNNFT_DONE, 3503 QLA_EVT_GFPNID, 3504 QLA_EVT_SP_RETRY, 3505 QLA_EVT_IIDMA, 3506 QLA_EVT_ELS_PLOGI, 3507 QLA_EVT_SA_REPLACE, 3508 }; 3509 3510 3511 struct qla_work_evt { 3512 struct list_head list; 3513 enum qla_work_type type; 3514 u32 flags; 3515 #define QLA_EVT_FLAG_FREE 0x1 3516 3517 union { 3518 struct { 3519 enum fc_host_event_code code; 3520 u32 data; 3521 } aen; 3522 struct { 3523 #define QLA_IDC_ACK_REGS 7 3524 uint16_t mb[QLA_IDC_ACK_REGS]; 3525 } idc_ack; 3526 struct { 3527 struct fc_port *fcport; 3528 #define QLA_LOGIO_LOGIN_RETRIED BIT_0 3529 u16 data[2]; 3530 } logio; 3531 struct { 3532 u32 code; 3533 #define QLA_UEVENT_CODE_FW_DUMP 0 3534 } uevent; 3535 struct { 3536 uint32_t evtcode; 3537 uint32_t mbx[8]; 3538 uint32_t count; 3539 } aenfx; 3540 struct { 3541 srb_t *sp; 3542 } iosb; 3543 struct { 3544 port_id_t id; 3545 u8 port_name[8]; 3546 u8 node_name[8]; 3547 void *pla; 3548 u8 fc4_type; 3549 } new_sess; 3550 struct { /*Get PDB, Get Speed, update fcport, gnl */ 3551 fc_port_t *fcport; 3552 u8 opt; 3553 } fcport; 3554 struct { 3555 fc_port_t *fcport; 3556 u8 iocb[IOCB_SIZE]; 3557 int type; 3558 } nack; 3559 struct { 3560 u8 fc4_type; 3561 srb_t *sp; 3562 } gpnft; 3563 struct { 3564 struct edif_sa_ctl *sa_ctl; 3565 fc_port_t *fcport; 3566 uint16_t nport_handle; 3567 } sa_update; 3568 } u; 3569 }; 3570 3571 struct qla_chip_state_84xx { 3572 struct list_head list; 3573 struct kref kref; 3574 3575 void *bus; 3576 spinlock_t access_lock; 3577 struct mutex fw_update_mutex; 3578 uint32_t fw_update; 3579 uint32_t op_fw_version; 3580 uint32_t op_fw_size; 3581 uint32_t op_fw_seq_size; 3582 uint32_t diag_fw_version; 3583 uint32_t gold_fw_version; 3584 }; 3585 3586 struct qla_dif_statistics { 3587 uint64_t dif_input_bytes; 3588 uint64_t dif_output_bytes; 3589 uint64_t dif_input_requests; 3590 uint64_t dif_output_requests; 3591 uint32_t dif_guard_err; 3592 uint32_t dif_ref_tag_err; 3593 uint32_t dif_app_tag_err; 3594 }; 3595 3596 struct qla_statistics { 3597 uint32_t total_isp_aborts; 3598 uint64_t input_bytes; 3599 uint64_t output_bytes; 3600 uint64_t input_requests; 3601 uint64_t output_requests; 3602 uint32_t control_requests; 3603 3604 uint64_t jiffies_at_last_reset; 3605 uint32_t stat_max_pend_cmds; 3606 uint32_t stat_max_qfull_cmds_alloc; 3607 uint32_t stat_max_qfull_cmds_dropped; 3608 3609 struct qla_dif_statistics qla_dif_stats; 3610 }; 3611 3612 struct bidi_statistics { 3613 unsigned long long io_count; 3614 unsigned long long transfer_bytes; 3615 }; 3616 3617 struct qla_tc_param { 3618 struct scsi_qla_host *vha; 3619 uint32_t blk_sz; 3620 uint32_t bufflen; 3621 struct scatterlist *sg; 3622 struct scatterlist *prot_sg; 3623 struct crc_context *ctx; 3624 uint8_t *ctx_dsd_alloced; 3625 }; 3626 3627 /* Multi queue support */ 3628 #define MBC_INITIALIZE_MULTIQ 0x1f 3629 #define QLA_QUE_PAGE 0X1000 3630 #define QLA_MQ_SIZE 32 3631 #define QLA_MAX_QUEUES 256 3632 #define ISP_QUE_REG(ha, id) \ 3633 ((ha->mqenable || IS_QLA83XX(ha) || \ 3634 IS_QLA27XX(ha) || IS_QLA28XX(ha)) ? \ 3635 ((void __iomem *)ha->mqiobase + (QLA_QUE_PAGE * id)) :\ 3636 ((void __iomem *)ha->iobase)) 3637 #define QLA_REQ_QUE_ID(tag) \ 3638 ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0) 3639 #define QLA_DEFAULT_QUE_QOS 5 3640 #define QLA_PRECONFIG_VPORTS 32 3641 #define QLA_MAX_VPORTS_QLA24XX 128 3642 #define QLA_MAX_VPORTS_QLA25XX 256 3643 3644 struct qla_tgt_counters { 3645 uint64_t qla_core_sbt_cmd; 3646 uint64_t core_qla_que_buf; 3647 uint64_t qla_core_ret_ctio; 3648 uint64_t core_qla_snd_status; 3649 uint64_t qla_core_ret_sta_ctio; 3650 uint64_t core_qla_free_cmd; 3651 uint64_t num_q_full_sent; 3652 uint64_t num_alloc_iocb_failed; 3653 uint64_t num_term_xchg_sent; 3654 }; 3655 3656 struct qla_counters { 3657 uint64_t input_bytes; 3658 uint64_t input_requests; 3659 uint64_t output_bytes; 3660 uint64_t output_requests; 3661 3662 }; 3663 3664 struct qla_qpair; 3665 3666 /* Response queue data structure */ 3667 struct rsp_que { 3668 dma_addr_t dma; 3669 response_t *ring; 3670 response_t *ring_ptr; 3671 __le32 __iomem *rsp_q_in; /* FWI2-capable only. */ 3672 __le32 __iomem *rsp_q_out; 3673 uint16_t ring_index; 3674 uint16_t out_ptr; 3675 uint16_t *in_ptr; /* queue shadow in index */ 3676 uint16_t length; 3677 uint16_t options; 3678 uint16_t rid; 3679 uint16_t id; 3680 uint16_t vp_idx; 3681 struct qla_hw_data *hw; 3682 struct qla_msix_entry *msix; 3683 struct req_que *req; 3684 srb_t *status_srb; /* status continuation entry */ 3685 struct qla_qpair *qpair; 3686 3687 dma_addr_t dma_fx00; 3688 response_t *ring_fx00; 3689 uint16_t length_fx00; 3690 uint8_t rsp_pkt[REQUEST_ENTRY_SIZE]; 3691 }; 3692 3693 /* Request queue data structure */ 3694 struct req_que { 3695 dma_addr_t dma; 3696 request_t *ring; 3697 request_t *ring_ptr; 3698 __le32 __iomem *req_q_in; /* FWI2-capable only. */ 3699 __le32 __iomem *req_q_out; 3700 uint16_t ring_index; 3701 uint16_t in_ptr; 3702 uint16_t *out_ptr; /* queue shadow out index */ 3703 uint16_t cnt; 3704 uint16_t length; 3705 uint16_t options; 3706 uint16_t rid; 3707 uint16_t id; 3708 uint16_t qos; 3709 uint16_t vp_idx; 3710 struct rsp_que *rsp; 3711 srb_t **outstanding_cmds; 3712 uint32_t current_outstanding_cmd; 3713 uint16_t num_outstanding_cmds; 3714 int max_q_depth; 3715 3716 dma_addr_t dma_fx00; 3717 request_t *ring_fx00; 3718 uint16_t length_fx00; 3719 uint8_t req_pkt[REQUEST_ENTRY_SIZE]; 3720 }; 3721 3722 struct qla_fw_resources { 3723 u16 iocbs_total; 3724 u16 iocbs_limit; 3725 u16 iocbs_qp_limit; 3726 u16 iocbs_used; 3727 u16 exch_total; 3728 u16 exch_limit; 3729 u16 exch_used; 3730 u16 pad; 3731 }; 3732 3733 #define QLA_IOCB_PCT_LIMIT 95 3734 3735 struct qla_buf_pool { 3736 u16 num_bufs; 3737 u16 num_active; 3738 u16 max_used; 3739 u16 num_alloc; 3740 u16 prev_max; 3741 u16 pad; 3742 uint32_t take_snapshot:1; 3743 unsigned long *buf_map; 3744 void **buf_array; 3745 dma_addr_t *dma_array; 3746 }; 3747 3748 /*Queue pair data structure */ 3749 struct qla_qpair { 3750 spinlock_t qp_lock; 3751 atomic_t ref_count; 3752 uint32_t lun_cnt; 3753 /* 3754 * For qpair 0, qp_lock_ptr will point at hardware_lock due to 3755 * legacy code. For other Qpair(s), it will point at qp_lock. 3756 */ 3757 spinlock_t *qp_lock_ptr; 3758 struct scsi_qla_host *vha; 3759 u32 chip_reset; 3760 3761 /* distill these fields down to 'online=0/1' 3762 * ha->flags.eeh_busy 3763 * ha->flags.pci_channel_io_perm_failure 3764 * base_vha->loop_state 3765 */ 3766 uint32_t online:1; 3767 /* move vha->flags.difdix_supported here */ 3768 uint32_t difdix_supported:1; 3769 uint32_t delete_in_progress:1; 3770 uint32_t fw_started:1; 3771 uint32_t enable_class_2:1; 3772 uint32_t enable_explicit_conf:1; 3773 uint32_t use_shadow_reg:1; 3774 uint32_t rcv_intr:1; 3775 3776 uint16_t id; /* qp number used with FW */ 3777 uint16_t vp_idx; /* vport ID */ 3778 mempool_t *srb_mempool; 3779 3780 struct pci_dev *pdev; 3781 void (*reqq_start_iocbs)(struct qla_qpair *); 3782 3783 /* to do: New driver: move queues to here instead of pointers */ 3784 struct req_que *req; 3785 struct rsp_que *rsp; 3786 struct atio_que *atio; 3787 struct qla_msix_entry *msix; /* point to &ha->msix_entries[x] */ 3788 struct qla_hw_data *hw; 3789 struct work_struct q_work; 3790 struct qla_counters counters; 3791 3792 struct list_head qp_list_elem; /* vha->qp_list */ 3793 struct list_head hints_list; 3794 3795 uint16_t retry_term_cnt; 3796 __le32 retry_term_exchg_addr; 3797 uint64_t retry_term_jiff; 3798 struct qla_tgt_counters tgt_counters; 3799 uint16_t cpuid; 3800 struct qla_fw_resources fwres ____cacheline_aligned; 3801 struct qla_buf_pool buf_pool; 3802 u32 cmd_cnt; 3803 u32 cmd_completion_cnt; 3804 u32 prev_completion_cnt; 3805 }; 3806 3807 /* Place holder for FW buffer parameters */ 3808 struct qlfc_fw { 3809 void *fw_buf; 3810 dma_addr_t fw_dma; 3811 uint32_t len; 3812 }; 3813 3814 struct rdp_req_payload { 3815 uint32_t els_request; 3816 uint32_t desc_list_len; 3817 3818 /* NPIV descriptor */ 3819 struct { 3820 uint32_t desc_tag; 3821 uint32_t desc_len; 3822 uint8_t reserved; 3823 uint8_t nport_id[3]; 3824 } npiv_desc; 3825 }; 3826 3827 struct rdp_rsp_payload { 3828 struct { 3829 __be32 cmd; 3830 __be32 len; 3831 } hdr; 3832 3833 /* LS Request Info descriptor */ 3834 struct { 3835 __be32 desc_tag; 3836 __be32 desc_len; 3837 __be32 req_payload_word_0; 3838 } ls_req_info_desc; 3839 3840 /* LS Request Info descriptor */ 3841 struct { 3842 __be32 desc_tag; 3843 __be32 desc_len; 3844 __be32 req_payload_word_0; 3845 } ls_req_info_desc2; 3846 3847 /* SFP diagnostic param descriptor */ 3848 struct { 3849 __be32 desc_tag; 3850 __be32 desc_len; 3851 __be16 temperature; 3852 __be16 vcc; 3853 __be16 tx_bias; 3854 __be16 tx_power; 3855 __be16 rx_power; 3856 __be16 sfp_flags; 3857 } sfp_diag_desc; 3858 3859 /* Port Speed Descriptor */ 3860 struct { 3861 __be32 desc_tag; 3862 __be32 desc_len; 3863 __be16 speed_capab; 3864 __be16 operating_speed; 3865 } port_speed_desc; 3866 3867 /* Link Error Status Descriptor */ 3868 struct { 3869 __be32 desc_tag; 3870 __be32 desc_len; 3871 __be32 link_fail_cnt; 3872 __be32 loss_sync_cnt; 3873 __be32 loss_sig_cnt; 3874 __be32 prim_seq_err_cnt; 3875 __be32 inval_xmit_word_cnt; 3876 __be32 inval_crc_cnt; 3877 uint8_t pn_port_phy_type; 3878 uint8_t reserved[3]; 3879 } ls_err_desc; 3880 3881 /* Port name description with diag param */ 3882 struct { 3883 __be32 desc_tag; 3884 __be32 desc_len; 3885 uint8_t WWNN[WWN_SIZE]; 3886 uint8_t WWPN[WWN_SIZE]; 3887 } port_name_diag_desc; 3888 3889 /* Port Name desc for Direct attached Fx_Port or Nx_Port */ 3890 struct { 3891 __be32 desc_tag; 3892 __be32 desc_len; 3893 uint8_t WWNN[WWN_SIZE]; 3894 uint8_t WWPN[WWN_SIZE]; 3895 } port_name_direct_desc; 3896 3897 /* Buffer Credit descriptor */ 3898 struct { 3899 __be32 desc_tag; 3900 __be32 desc_len; 3901 __be32 fcport_b2b; 3902 __be32 attached_fcport_b2b; 3903 __be32 fcport_rtt; 3904 } buffer_credit_desc; 3905 3906 /* Optical Element Data Descriptor */ 3907 struct { 3908 __be32 desc_tag; 3909 __be32 desc_len; 3910 __be16 high_alarm; 3911 __be16 low_alarm; 3912 __be16 high_warn; 3913 __be16 low_warn; 3914 __be32 element_flags; 3915 } optical_elmt_desc[5]; 3916 3917 /* Optical Product Data Descriptor */ 3918 struct { 3919 __be32 desc_tag; 3920 __be32 desc_len; 3921 uint8_t vendor_name[16]; 3922 uint8_t part_number[16]; 3923 uint8_t serial_number[16]; 3924 uint8_t revision[4]; 3925 uint8_t date[8]; 3926 } optical_prod_desc; 3927 }; 3928 3929 #define RDP_DESC_LEN(obj) \ 3930 (sizeof(obj) - sizeof((obj).desc_tag) - sizeof((obj).desc_len)) 3931 3932 #define RDP_PORT_SPEED_1GB BIT_15 3933 #define RDP_PORT_SPEED_2GB BIT_14 3934 #define RDP_PORT_SPEED_4GB BIT_13 3935 #define RDP_PORT_SPEED_10GB BIT_12 3936 #define RDP_PORT_SPEED_8GB BIT_11 3937 #define RDP_PORT_SPEED_16GB BIT_10 3938 #define RDP_PORT_SPEED_32GB BIT_9 3939 #define RDP_PORT_SPEED_64GB BIT_8 3940 #define RDP_PORT_SPEED_UNKNOWN BIT_0 3941 3942 struct scsi_qlt_host { 3943 void *target_lport_ptr; 3944 struct mutex tgt_mutex; 3945 struct mutex tgt_host_action_mutex; 3946 struct qla_tgt *qla_tgt; 3947 }; 3948 3949 struct qlt_hw_data { 3950 /* Protected by hw lock */ 3951 uint32_t node_name_set:1; 3952 3953 dma_addr_t atio_dma; /* Physical address. */ 3954 struct atio *atio_ring; /* Base virtual address */ 3955 struct atio *atio_ring_ptr; /* Current address. */ 3956 uint16_t atio_ring_index; /* Current index. */ 3957 uint16_t atio_q_length; 3958 __le32 __iomem *atio_q_in; 3959 __le32 __iomem *atio_q_out; 3960 3961 const struct qla_tgt_func_tmpl *tgt_ops; 3962 3963 int saved_set; 3964 __le16 saved_exchange_count; 3965 __le32 saved_firmware_options_1; 3966 __le32 saved_firmware_options_2; 3967 __le32 saved_firmware_options_3; 3968 uint8_t saved_firmware_options[2]; 3969 uint8_t saved_add_firmware_options[2]; 3970 3971 uint8_t tgt_node_name[WWN_SIZE]; 3972 3973 struct dentry *dfs_tgt_sess; 3974 struct dentry *dfs_tgt_port_database; 3975 struct dentry *dfs_naqp; 3976 3977 struct list_head q_full_list; 3978 uint32_t num_pend_cmds; 3979 uint32_t num_qfull_cmds_alloc; 3980 uint32_t num_qfull_cmds_dropped; 3981 spinlock_t q_full_lock; 3982 uint32_t leak_exchg_thresh_hold; 3983 spinlock_t sess_lock; 3984 int num_act_qpairs; 3985 #define DEFAULT_NAQP 2 3986 spinlock_t atio_lock ____cacheline_aligned; 3987 }; 3988 3989 #define MAX_QFULL_CMDS_ALLOC 8192 3990 #define Q_FULL_THRESH_HOLD_PERCENT 90 3991 #define Q_FULL_THRESH_HOLD(ha) \ 3992 ((ha->cur_fw_xcb_count/100) * Q_FULL_THRESH_HOLD_PERCENT) 3993 3994 #define LEAK_EXCHG_THRESH_HOLD_PERCENT 75 /* 75 percent */ 3995 3996 struct qla_hw_data_stat { 3997 u32 num_fw_dump; 3998 u32 num_mpi_reset; 3999 }; 4000 4001 /* refer to pcie_do_recovery reference */ 4002 typedef enum { 4003 QLA_PCI_RESUME, 4004 QLA_PCI_ERR_DETECTED, 4005 QLA_PCI_MMIO_ENABLED, 4006 QLA_PCI_SLOT_RESET, 4007 } pci_error_state_t; 4008 /* 4009 * Qlogic host adapter specific data structure. 4010 */ 4011 struct qla_hw_data { 4012 struct pci_dev *pdev; 4013 /* SRB cache. */ 4014 #define SRB_MIN_REQ 128 4015 mempool_t *srb_mempool; 4016 u8 port_name[WWN_SIZE]; 4017 4018 volatile struct { 4019 uint32_t mbox_int :1; 4020 uint32_t mbox_busy :1; 4021 uint32_t disable_risc_code_load :1; 4022 uint32_t enable_64bit_addressing :1; 4023 uint32_t enable_lip_reset :1; 4024 uint32_t enable_target_reset :1; 4025 uint32_t enable_lip_full_login :1; 4026 uint32_t enable_led_scheme :1; 4027 4028 uint32_t msi_enabled :1; 4029 uint32_t msix_enabled :1; 4030 uint32_t disable_serdes :1; 4031 uint32_t gpsc_supported :1; 4032 uint32_t npiv_supported :1; 4033 uint32_t pci_channel_io_perm_failure :1; 4034 uint32_t fce_enabled :1; 4035 uint32_t fac_supported :1; 4036 4037 uint32_t chip_reset_done :1; 4038 uint32_t running_gold_fw :1; 4039 uint32_t eeh_busy :1; 4040 uint32_t disable_msix_handshake :1; 4041 uint32_t fcp_prio_enabled :1; 4042 uint32_t isp82xx_fw_hung:1; 4043 uint32_t nic_core_hung:1; 4044 4045 uint32_t quiesce_owner:1; 4046 uint32_t nic_core_reset_hdlr_active:1; 4047 uint32_t nic_core_reset_owner:1; 4048 uint32_t isp82xx_no_md_cap:1; 4049 uint32_t host_shutting_down:1; 4050 uint32_t idc_compl_status:1; 4051 uint32_t mr_reset_hdlr_active:1; 4052 uint32_t mr_intr_valid:1; 4053 4054 uint32_t dport_enabled:1; 4055 uint32_t fawwpn_enabled:1; 4056 uint32_t exlogins_enabled:1; 4057 uint32_t exchoffld_enabled:1; 4058 4059 uint32_t lip_ae:1; 4060 uint32_t n2n_ae:1; 4061 uint32_t fw_started:1; 4062 uint32_t fw_init_done:1; 4063 4064 uint32_t lr_detected:1; 4065 4066 uint32_t rida_fmt2:1; 4067 uint32_t purge_mbox:1; 4068 uint32_t n2n_bigger:1; 4069 uint32_t secure_adapter:1; 4070 uint32_t secure_fw:1; 4071 /* Supported by Adapter */ 4072 uint32_t scm_supported_a:1; 4073 /* Supported by Firmware */ 4074 uint32_t scm_supported_f:1; 4075 /* Enabled in Driver */ 4076 uint32_t scm_enabled:1; 4077 uint32_t edif_hw:1; 4078 uint32_t edif_enabled:1; 4079 uint32_t n2n_fw_acc_sec:1; 4080 uint32_t plogi_template_valid:1; 4081 uint32_t port_isolated:1; 4082 uint32_t eeh_flush:2; 4083 #define EEH_FLUSH_RDY 1 4084 #define EEH_FLUSH_DONE 2 4085 } flags; 4086 4087 uint16_t max_exchg; 4088 uint16_t lr_distance; /* 32G & above */ 4089 #define LR_DISTANCE_5K 1 4090 #define LR_DISTANCE_10K 0 4091 4092 /* This spinlock is used to protect "io transactions", you must 4093 * acquire it before doing any IO to the card, eg with RD_REG*() and 4094 * WRT_REG*() for the duration of your entire commandtransaction. 4095 * 4096 * This spinlock is of lower priority than the io request lock. 4097 */ 4098 4099 spinlock_t hardware_lock ____cacheline_aligned; 4100 int bars; 4101 int mem_only; 4102 device_reg_t *iobase; /* Base I/O address */ 4103 resource_size_t pio_address; 4104 4105 #define MIN_IOBASE_LEN 0x100 4106 dma_addr_t bar0_hdl; 4107 4108 void __iomem *cregbase; 4109 dma_addr_t bar2_hdl; 4110 #define BAR0_LEN_FX00 (1024 * 1024) 4111 #define BAR2_LEN_FX00 (128 * 1024) 4112 4113 uint32_t rqstq_intr_code; 4114 uint32_t mbx_intr_code; 4115 uint32_t req_que_len; 4116 uint32_t rsp_que_len; 4117 uint32_t req_que_off; 4118 uint32_t rsp_que_off; 4119 unsigned long eeh_jif; 4120 4121 /* Multi queue data structs */ 4122 device_reg_t *mqiobase; 4123 device_reg_t *msixbase; 4124 uint16_t msix_count; 4125 uint8_t mqenable; 4126 struct req_que **req_q_map; 4127 struct rsp_que **rsp_q_map; 4128 struct qla_qpair **queue_pair_map; 4129 struct qla_qpair **qp_cpu_map; 4130 unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)]; 4131 unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)]; 4132 unsigned long qpair_qid_map[(QLA_MAX_QUEUES / 8) 4133 / sizeof(unsigned long)]; 4134 uint8_t max_req_queues; 4135 uint8_t max_rsp_queues; 4136 uint8_t max_qpairs; 4137 uint8_t num_qpairs; 4138 struct qla_qpair *base_qpair; 4139 struct qla_npiv_entry *npiv_info; 4140 uint16_t nvram_npiv_size; 4141 4142 uint16_t switch_cap; 4143 #define FLOGI_SEQ_DEL BIT_8 4144 #define FLOGI_MID_SUPPORT BIT_10 4145 #define FLOGI_VSAN_SUPPORT BIT_12 4146 #define FLOGI_SP_SUPPORT BIT_13 4147 4148 uint8_t port_no; /* Physical port of adapter */ 4149 uint8_t exch_starvation; 4150 4151 /* Timeout timers. */ 4152 uint8_t loop_down_abort_time; /* port down timer */ 4153 atomic_t loop_down_timer; /* loop down timer */ 4154 uint8_t link_down_timeout; /* link down timeout */ 4155 uint16_t max_loop_id; 4156 uint16_t max_fibre_devices; /* Maximum number of targets */ 4157 4158 uint16_t fb_rev; 4159 uint16_t min_external_loopid; /* First external loop Id */ 4160 4161 #define PORT_SPEED_UNKNOWN 0xFFFF 4162 #define PORT_SPEED_1GB 0x00 4163 #define PORT_SPEED_2GB 0x01 4164 #define PORT_SPEED_AUTO 0x02 4165 #define PORT_SPEED_4GB 0x03 4166 #define PORT_SPEED_8GB 0x04 4167 #define PORT_SPEED_16GB 0x05 4168 #define PORT_SPEED_32GB 0x06 4169 #define PORT_SPEED_64GB 0x07 4170 #define PORT_SPEED_10GB 0x13 4171 uint16_t link_data_rate; /* F/W operating speed */ 4172 uint16_t set_data_rate; /* Set by user */ 4173 4174 uint8_t current_topology; 4175 uint8_t prev_topology; 4176 #define ISP_CFG_NL 1 4177 #define ISP_CFG_N 2 4178 #define ISP_CFG_FL 4 4179 #define ISP_CFG_F 8 4180 4181 uint8_t operating_mode; /* F/W operating mode */ 4182 #define LOOP 0 4183 #define P2P 1 4184 #define LOOP_P2P 2 4185 #define P2P_LOOP 3 4186 uint8_t interrupts_on; 4187 uint32_t isp_abort_cnt; 4188 #define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532 4189 #define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432 4190 #define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001 4191 #define PCI_DEVICE_ID_QLOGIC_ISP8031 0x8031 4192 #define PCI_DEVICE_ID_QLOGIC_ISP2031 0x2031 4193 #define PCI_DEVICE_ID_QLOGIC_ISP2071 0x2071 4194 #define PCI_DEVICE_ID_QLOGIC_ISP2271 0x2271 4195 #define PCI_DEVICE_ID_QLOGIC_ISP2261 0x2261 4196 #define PCI_DEVICE_ID_QLOGIC_ISP2061 0x2061 4197 #define PCI_DEVICE_ID_QLOGIC_ISP2081 0x2081 4198 #define PCI_DEVICE_ID_QLOGIC_ISP2089 0x2089 4199 #define PCI_DEVICE_ID_QLOGIC_ISP2281 0x2281 4200 #define PCI_DEVICE_ID_QLOGIC_ISP2289 0x2289 4201 4202 uint32_t isp_type; 4203 #define DT_ISP2100 BIT_0 4204 #define DT_ISP2200 BIT_1 4205 #define DT_ISP2300 BIT_2 4206 #define DT_ISP2312 BIT_3 4207 #define DT_ISP2322 BIT_4 4208 #define DT_ISP6312 BIT_5 4209 #define DT_ISP6322 BIT_6 4210 #define DT_ISP2422 BIT_7 4211 #define DT_ISP2432 BIT_8 4212 #define DT_ISP5422 BIT_9 4213 #define DT_ISP5432 BIT_10 4214 #define DT_ISP2532 BIT_11 4215 #define DT_ISP8432 BIT_12 4216 #define DT_ISP8001 BIT_13 4217 #define DT_ISP8021 BIT_14 4218 #define DT_ISP2031 BIT_15 4219 #define DT_ISP8031 BIT_16 4220 #define DT_ISPFX00 BIT_17 4221 #define DT_ISP8044 BIT_18 4222 #define DT_ISP2071 BIT_19 4223 #define DT_ISP2271 BIT_20 4224 #define DT_ISP2261 BIT_21 4225 #define DT_ISP2061 BIT_22 4226 #define DT_ISP2081 BIT_23 4227 #define DT_ISP2089 BIT_24 4228 #define DT_ISP2281 BIT_25 4229 #define DT_ISP2289 BIT_26 4230 #define DT_ISP_LAST (DT_ISP2289 << 1) 4231 4232 uint32_t device_type; 4233 #define DT_T10_PI BIT_25 4234 #define DT_IIDMA BIT_26 4235 #define DT_FWI2 BIT_27 4236 #define DT_ZIO_SUPPORTED BIT_28 4237 #define DT_OEM_001 BIT_29 4238 #define DT_ISP2200A BIT_30 4239 #define DT_EXTENDED_IDS BIT_31 4240 4241 #define DT_MASK(ha) ((ha)->isp_type & (DT_ISP_LAST - 1)) 4242 #define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100) 4243 #define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200) 4244 #define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300) 4245 #define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312) 4246 #define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322) 4247 #define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312) 4248 #define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322) 4249 #define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422) 4250 #define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432) 4251 #define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422) 4252 #define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432) 4253 #define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532) 4254 #define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432) 4255 #define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001) 4256 #define IS_QLA81XX(ha) (IS_QLA8001(ha)) 4257 #define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021) 4258 #define IS_QLA8044(ha) (DT_MASK(ha) & DT_ISP8044) 4259 #define IS_QLA2031(ha) (DT_MASK(ha) & DT_ISP2031) 4260 #define IS_QLA8031(ha) (DT_MASK(ha) & DT_ISP8031) 4261 #define IS_QLAFX00(ha) (DT_MASK(ha) & DT_ISPFX00) 4262 #define IS_QLA2071(ha) (DT_MASK(ha) & DT_ISP2071) 4263 #define IS_QLA2271(ha) (DT_MASK(ha) & DT_ISP2271) 4264 #define IS_QLA2261(ha) (DT_MASK(ha) & DT_ISP2261) 4265 #define IS_QLA2081(ha) (DT_MASK(ha) & DT_ISP2081) 4266 #define IS_QLA2281(ha) (DT_MASK(ha) & DT_ISP2281) 4267 4268 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \ 4269 IS_QLA6312(ha) || IS_QLA6322(ha)) 4270 #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha)) 4271 #define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha)) 4272 #define IS_QLA25XX(ha) (IS_QLA2532(ha)) 4273 #define IS_QLA83XX(ha) (IS_QLA2031(ha) || IS_QLA8031(ha)) 4274 #define IS_QLA84XX(ha) (IS_QLA8432(ha)) 4275 #define IS_QLA27XX(ha) (IS_QLA2071(ha) || IS_QLA2271(ha) || IS_QLA2261(ha)) 4276 #define IS_QLA28XX(ha) (IS_QLA2081(ha) || IS_QLA2281(ha)) 4277 #define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \ 4278 IS_QLA84XX(ha)) 4279 #define IS_CNA_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha) || \ 4280 IS_QLA8031(ha) || IS_QLA8044(ha)) 4281 #define IS_P3P_TYPE(ha) (IS_QLA82XX(ha) || IS_QLA8044(ha)) 4282 #define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \ 4283 IS_QLA25XX(ha) || IS_QLA81XX(ha) || \ 4284 IS_QLA82XX(ha) || IS_QLA83XX(ha) || \ 4285 IS_QLA8044(ha) || IS_QLA27XX(ha) || \ 4286 IS_QLA28XX(ha)) 4287 #define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 4288 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4289 #define IS_NOPOLLING_TYPE(ha) (IS_QLA81XX(ha) && (ha)->flags.msix_enabled) 4290 #define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 4291 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4292 #define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 4293 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4294 #define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha)) 4295 4296 #define IS_T10_PI_CAPABLE(ha) ((ha)->device_type & DT_T10_PI) 4297 #define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA) 4298 #define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2) 4299 #define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED) 4300 #define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001) 4301 #define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS) 4302 #define IS_CT6_SUPPORTED(ha) ((ha)->device_type & DT_CT6_SUPPORTED) 4303 #define IS_MQUE_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \ 4304 IS_QLA28XX(ha)) 4305 #define IS_BIDI_CAPABLE(ha) \ 4306 (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4307 /* Bit 21 of fw_attributes decides the MCTP capabilities */ 4308 #define IS_MCTP_CAPABLE(ha) (IS_QLA2031(ha) && \ 4309 ((ha)->fw_attributes_ext[0] & BIT_0)) 4310 #define QLA_ABTS_FW_ENABLED(_ha) ((_ha)->fw_attributes_ext[0] & BIT_14) 4311 #define QLA_SRB_NVME_LS(_sp) ((_sp)->type == SRB_NVME_LS) 4312 #define QLA_SRB_NVME_CMD(_sp) ((_sp)->type == SRB_NVME_CMD) 4313 #define QLA_NVME_IOS(_sp) (QLA_SRB_NVME_CMD(_sp) || QLA_SRB_NVME_LS(_sp)) 4314 #define QLA_LS_ABTS_WAIT_ENABLED(_sp) \ 4315 (QLA_SRB_NVME_LS(_sp) && QLA_ABTS_FW_ENABLED(_sp->fcport->vha->hw)) 4316 #define QLA_CMD_ABTS_WAIT_ENABLED(_sp) \ 4317 (QLA_SRB_NVME_CMD(_sp) && QLA_ABTS_FW_ENABLED(_sp->fcport->vha->hw)) 4318 #define QLA_ABTS_WAIT_ENABLED(_sp) \ 4319 (QLA_NVME_IOS(_sp) && QLA_ABTS_FW_ENABLED(_sp->fcport->vha->hw)) 4320 4321 #define IS_PI_UNINIT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \ 4322 IS_QLA28XX(ha)) 4323 #define IS_PI_IPGUARD_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \ 4324 IS_QLA28XX(ha)) 4325 #define IS_PI_DIFB_DIX0_CAPABLE(ha) (0) 4326 #define IS_PI_SPLIT_DET_CAPABLE_HBA(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \ 4327 IS_QLA28XX(ha)) 4328 #define IS_PI_SPLIT_DET_CAPABLE(ha) (IS_PI_SPLIT_DET_CAPABLE_HBA(ha) && \ 4329 (((ha)->fw_attributes_h << 16 | (ha)->fw_attributes) & BIT_22)) 4330 #define IS_ATIO_MSIX_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \ 4331 IS_QLA28XX(ha)) 4332 #define IS_TGT_MODE_CAPABLE(ha) (ha->tgt.atio_q_length) 4333 #define IS_SHADOW_REG_CAPABLE(ha) (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4334 #define IS_DPORT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \ 4335 IS_QLA28XX(ha)) 4336 #define IS_FAWWN_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \ 4337 IS_QLA28XX(ha)) 4338 #define IS_EXCHG_OFFLD_CAPABLE(ha) \ 4339 (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4340 #define IS_EXLOGIN_OFFLD_CAPABLE(ha) \ 4341 (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 4342 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4343 #define USE_ASYNC_SCAN(ha) (IS_QLA25XX(ha) || IS_QLA81XX(ha) ||\ 4344 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4345 4346 #define IS_ZIO_THRESHOLD_CAPABLE(ha) \ 4347 ((IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) &&\ 4348 (ha->zio_mode == QLA_ZIO_MODE_6)) 4349 4350 /* HBA serial number */ 4351 uint8_t serial0; 4352 uint8_t serial1; 4353 uint8_t serial2; 4354 4355 /* NVRAM configuration data */ 4356 #define MAX_NVRAM_SIZE 4096 4357 #define VPD_OFFSET (MAX_NVRAM_SIZE / 2) 4358 uint16_t nvram_size; 4359 uint16_t nvram_base; 4360 void *nvram; 4361 uint16_t vpd_size; 4362 uint16_t vpd_base; 4363 void *vpd; 4364 4365 uint16_t loop_reset_delay; 4366 uint8_t retry_count; 4367 uint8_t login_timeout; 4368 uint16_t r_a_tov; 4369 int port_down_retry_count; 4370 uint8_t mbx_count; 4371 uint8_t aen_mbx_count; 4372 atomic_t num_pend_mbx_stage1; 4373 atomic_t num_pend_mbx_stage2; 4374 atomic_t num_pend_mbx_stage3; 4375 uint16_t frame_payload_size; 4376 4377 uint32_t login_retry_count; 4378 /* SNS command interfaces. */ 4379 ms_iocb_entry_t *ms_iocb; 4380 dma_addr_t ms_iocb_dma; 4381 struct ct_sns_pkt *ct_sns; 4382 dma_addr_t ct_sns_dma; 4383 /* SNS command interfaces for 2200. */ 4384 struct sns_cmd_pkt *sns_cmd; 4385 dma_addr_t sns_cmd_dma; 4386 4387 #define SFP_DEV_SIZE 512 4388 #define SFP_BLOCK_SIZE 64 4389 #define SFP_RTDI_LEN SFP_BLOCK_SIZE 4390 4391 void *sfp_data; 4392 dma_addr_t sfp_data_dma; 4393 4394 struct qla_flt_header *flt; 4395 dma_addr_t flt_dma; 4396 4397 #define XGMAC_DATA_SIZE 4096 4398 void *xgmac_data; 4399 dma_addr_t xgmac_data_dma; 4400 4401 #define DCBX_TLV_DATA_SIZE 4096 4402 void *dcbx_tlv; 4403 dma_addr_t dcbx_tlv_dma; 4404 4405 struct task_struct *dpc_thread; 4406 uint8_t dpc_active; /* DPC routine is active */ 4407 4408 dma_addr_t gid_list_dma; 4409 struct gid_list_info *gid_list; 4410 int gid_list_info_size; 4411 4412 /* Small DMA pool allocations -- maximum 256 bytes in length. */ 4413 #define DMA_POOL_SIZE 256 4414 struct dma_pool *s_dma_pool; 4415 4416 dma_addr_t init_cb_dma; 4417 init_cb_t *init_cb; 4418 int init_cb_size; 4419 dma_addr_t ex_init_cb_dma; 4420 struct ex_init_cb_81xx *ex_init_cb; 4421 dma_addr_t sf_init_cb_dma; 4422 struct init_sf_cb *sf_init_cb; 4423 4424 void *scm_fpin_els_buff; 4425 uint64_t scm_fpin_els_buff_size; 4426 bool scm_fpin_valid; 4427 bool scm_fpin_payload_size; 4428 4429 void *async_pd; 4430 dma_addr_t async_pd_dma; 4431 4432 #define ENABLE_EXTENDED_LOGIN BIT_7 4433 4434 /* Extended Logins */ 4435 void *exlogin_buf; 4436 dma_addr_t exlogin_buf_dma; 4437 uint32_t exlogin_size; 4438 4439 #define ENABLE_EXCHANGE_OFFLD BIT_2 4440 4441 /* Exchange Offload */ 4442 void *exchoffld_buf; 4443 dma_addr_t exchoffld_buf_dma; 4444 int exchoffld_size; 4445 int exchoffld_count; 4446 4447 /* n2n */ 4448 struct fc_els_flogi plogi_els_payld; 4449 #define LOGIN_TEMPLATE_SIZE (sizeof(struct fc_els_flogi) - 4) 4450 4451 void *swl; 4452 4453 /* These are used by mailbox operations. */ 4454 uint16_t mailbox_out[MAILBOX_REGISTER_COUNT]; 4455 uint32_t mailbox_out32[MAILBOX_REGISTER_COUNT]; 4456 uint32_t aenmb[AEN_MAILBOX_REGISTER_COUNT_FX00]; 4457 4458 mbx_cmd_t *mcp; 4459 struct mbx_cmd_32 *mcp32; 4460 4461 unsigned long mbx_cmd_flags; 4462 #define MBX_INTERRUPT 1 4463 #define MBX_INTR_WAIT 2 4464 #define MBX_UPDATE_FLASH_ACTIVE 3 4465 4466 struct mutex vport_lock; /* Virtual port synchronization */ 4467 spinlock_t vport_slock; /* order is hardware_lock, then vport_slock */ 4468 struct mutex mq_lock; /* multi-queue synchronization */ 4469 struct completion mbx_cmd_comp; /* Serialize mbx access */ 4470 struct completion mbx_intr_comp; /* Used for completion notification */ 4471 struct completion dcbx_comp; /* For set port config notification */ 4472 struct completion lb_portup_comp; /* Used to wait for link up during 4473 * loopback */ 4474 #define DCBX_COMP_TIMEOUT 20 4475 #define LB_PORTUP_COMP_TIMEOUT 10 4476 4477 int notify_dcbx_comp; 4478 int notify_lb_portup_comp; 4479 struct mutex selflogin_lock; 4480 4481 /* Basic firmware related information. */ 4482 uint16_t fw_major_version; 4483 uint16_t fw_minor_version; 4484 uint16_t fw_subminor_version; 4485 uint16_t fw_attributes; 4486 uint16_t fw_attributes_h; 4487 #define FW_ATTR_H_NVME_FBURST BIT_1 4488 #define FW_ATTR_H_NVME BIT_10 4489 #define FW_ATTR_H_NVME_UPDATED BIT_14 4490 4491 /* About firmware SCM support */ 4492 #define FW_ATTR_EXT0_SCM_SUPPORTED BIT_12 4493 /* Brocade fabric attached */ 4494 #define FW_ATTR_EXT0_SCM_BROCADE 0x00001000 4495 /* Cisco fabric attached */ 4496 #define FW_ATTR_EXT0_SCM_CISCO 0x00002000 4497 #define FW_ATTR_EXT0_NVME2 BIT_13 4498 #define FW_ATTR_EXT0_EDIF BIT_5 4499 uint16_t fw_attributes_ext[2]; 4500 uint32_t fw_memory_size; 4501 uint32_t fw_transfer_size; 4502 uint32_t fw_srisc_address; 4503 #define RISC_START_ADDRESS_2100 0x1000 4504 #define RISC_START_ADDRESS_2300 0x800 4505 #define RISC_START_ADDRESS_2400 0x100000 4506 4507 uint16_t orig_fw_tgt_xcb_count; 4508 uint16_t cur_fw_tgt_xcb_count; 4509 uint16_t orig_fw_xcb_count; 4510 uint16_t cur_fw_xcb_count; 4511 uint16_t orig_fw_iocb_count; 4512 uint16_t cur_fw_iocb_count; 4513 uint16_t fw_max_fcf_count; 4514 4515 uint32_t fw_shared_ram_start; 4516 uint32_t fw_shared_ram_end; 4517 uint32_t fw_ddr_ram_start; 4518 uint32_t fw_ddr_ram_end; 4519 4520 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */ 4521 uint8_t fw_seriallink_options[4]; 4522 __le16 fw_seriallink_options24[4]; 4523 4524 uint8_t serdes_version[3]; 4525 uint8_t mpi_version[3]; 4526 uint32_t mpi_capabilities; 4527 uint8_t phy_version[3]; 4528 uint8_t pep_version[3]; 4529 4530 /* Firmware dump template */ 4531 struct fwdt { 4532 void *template; 4533 ulong length; 4534 ulong dump_size; 4535 } fwdt[2]; 4536 struct qla2xxx_fw_dump *fw_dump; 4537 uint32_t fw_dump_len; 4538 u32 fw_dump_alloc_len; 4539 bool fw_dumped; 4540 unsigned long fw_dump_cap_flags; 4541 #define RISC_PAUSE_CMPL 0 4542 #define DMA_SHUTDOWN_CMPL 1 4543 #define ISP_RESET_CMPL 2 4544 #define RISC_RDY_AFT_RESET 3 4545 #define RISC_SRAM_DUMP_CMPL 4 4546 #define RISC_EXT_MEM_DUMP_CMPL 5 4547 #define ISP_MBX_RDY 6 4548 #define ISP_SOFT_RESET_CMPL 7 4549 int fw_dump_reading; 4550 void *mpi_fw_dump; 4551 u32 mpi_fw_dump_len; 4552 unsigned int mpi_fw_dump_reading:1; 4553 unsigned int mpi_fw_dumped:1; 4554 int prev_minidump_failed; 4555 dma_addr_t eft_dma; 4556 void *eft; 4557 /* Current size of mctp dump is 0x086064 bytes */ 4558 #define MCTP_DUMP_SIZE 0x086064 4559 dma_addr_t mctp_dump_dma; 4560 void *mctp_dump; 4561 int mctp_dumped; 4562 int mctp_dump_reading; 4563 uint32_t chain_offset; 4564 struct dentry *dfs_dir; 4565 struct dentry *dfs_fce; 4566 struct dentry *dfs_tgt_counters; 4567 struct dentry *dfs_fw_resource_cnt; 4568 4569 dma_addr_t fce_dma; 4570 void *fce; 4571 uint32_t fce_bufs; 4572 uint16_t fce_mb[8]; 4573 uint64_t fce_wr, fce_rd; 4574 struct mutex fce_mutex; 4575 4576 uint32_t pci_attr; 4577 uint16_t chip_revision; 4578 4579 uint16_t product_id[4]; 4580 4581 uint8_t model_number[16+1]; 4582 char model_desc[80]; 4583 uint8_t adapter_id[16+1]; 4584 4585 /* Option ROM information. */ 4586 char *optrom_buffer; 4587 uint32_t optrom_size; 4588 int optrom_state; 4589 #define QLA_SWAITING 0 4590 #define QLA_SREADING 1 4591 #define QLA_SWRITING 2 4592 uint32_t optrom_region_start; 4593 uint32_t optrom_region_size; 4594 struct mutex optrom_mutex; 4595 4596 /* PCI expansion ROM image information. */ 4597 #define ROM_CODE_TYPE_BIOS 0 4598 #define ROM_CODE_TYPE_FCODE 1 4599 #define ROM_CODE_TYPE_EFI 3 4600 uint8_t bios_revision[2]; 4601 uint8_t efi_revision[2]; 4602 uint8_t fcode_revision[16]; 4603 uint32_t fw_revision[4]; 4604 4605 uint32_t gold_fw_version[4]; 4606 4607 /* Offsets for flash/nvram access (set to ~0 if not used). */ 4608 uint32_t flash_conf_off; 4609 uint32_t flash_data_off; 4610 uint32_t nvram_conf_off; 4611 uint32_t nvram_data_off; 4612 4613 uint32_t fdt_wrt_disable; 4614 uint32_t fdt_wrt_enable; 4615 uint32_t fdt_erase_cmd; 4616 uint32_t fdt_block_size; 4617 uint32_t fdt_unprotect_sec_cmd; 4618 uint32_t fdt_protect_sec_cmd; 4619 uint32_t fdt_wrt_sts_reg_cmd; 4620 4621 struct { 4622 uint32_t flt_region_flt; 4623 uint32_t flt_region_fdt; 4624 uint32_t flt_region_boot; 4625 uint32_t flt_region_boot_sec; 4626 uint32_t flt_region_fw; 4627 uint32_t flt_region_fw_sec; 4628 uint32_t flt_region_vpd_nvram; 4629 uint32_t flt_region_vpd_nvram_sec; 4630 uint32_t flt_region_vpd; 4631 uint32_t flt_region_vpd_sec; 4632 uint32_t flt_region_nvram; 4633 uint32_t flt_region_nvram_sec; 4634 uint32_t flt_region_npiv_conf; 4635 uint32_t flt_region_gold_fw; 4636 uint32_t flt_region_fcp_prio; 4637 uint32_t flt_region_bootload; 4638 uint32_t flt_region_img_status_pri; 4639 uint32_t flt_region_img_status_sec; 4640 uint32_t flt_region_aux_img_status_pri; 4641 uint32_t flt_region_aux_img_status_sec; 4642 }; 4643 uint8_t active_image; 4644 4645 /* Needed for BEACON */ 4646 uint16_t beacon_blink_led; 4647 uint8_t beacon_color_state; 4648 #define QLA_LED_GRN_ON 0x01 4649 #define QLA_LED_YLW_ON 0x02 4650 #define QLA_LED_ABR_ON 0x04 4651 #define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */ 4652 /* ISP2322: red, green, amber. */ 4653 uint16_t zio_mode; 4654 uint16_t zio_timer; 4655 4656 struct qla_msix_entry *msix_entries; 4657 4658 struct list_head vp_list; /* list of VP */ 4659 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) / 4660 sizeof(unsigned long)]; 4661 uint16_t num_vhosts; /* number of vports created */ 4662 uint16_t num_vsans; /* number of vsan created */ 4663 uint16_t max_npiv_vports; /* 63 or 125 per topoloty */ 4664 int cur_vport_count; 4665 4666 struct qla_chip_state_84xx *cs84xx; 4667 struct isp_operations *isp_ops; 4668 struct workqueue_struct *wq; 4669 struct work_struct heartbeat_work; 4670 struct qlfc_fw fw_buf; 4671 unsigned long last_heartbeat_run_jiffies; 4672 4673 /* FCP_CMND priority support */ 4674 struct qla_fcp_prio_cfg *fcp_prio_cfg; 4675 4676 struct dma_pool *dl_dma_pool; 4677 #define DSD_LIST_DMA_POOL_SIZE 512 4678 4679 struct dma_pool *fcp_cmnd_dma_pool; 4680 mempool_t *ctx_mempool; 4681 #define FCP_CMND_DMA_POOL_SIZE 512 4682 4683 void __iomem *nx_pcibase; /* Base I/O address */ 4684 void __iomem *nxdb_rd_ptr; /* Doorbell read pointer */ 4685 void __iomem *nxdb_wr_ptr; /* Door bell write pointer */ 4686 4687 uint32_t crb_win; 4688 uint32_t curr_window; 4689 uint32_t ddr_mn_window; 4690 unsigned long mn_win_crb; 4691 unsigned long ms_win_crb; 4692 int qdr_sn_window; 4693 uint32_t fcoe_dev_init_timeout; 4694 uint32_t fcoe_reset_timeout; 4695 rwlock_t hw_lock; 4696 uint16_t portnum; /* port number */ 4697 int link_width; 4698 struct fw_blob *hablob; 4699 struct qla82xx_legacy_intr_set nx_legacy_intr; 4700 4701 uint16_t gbl_dsd_inuse; 4702 uint16_t gbl_dsd_avail; 4703 struct list_head gbl_dsd_list; 4704 #define NUM_DSD_CHAIN 4096 4705 4706 uint8_t fw_type; 4707 uint32_t file_prd_off; /* File firmware product offset */ 4708 4709 uint32_t md_template_size; 4710 void *md_tmplt_hdr; 4711 dma_addr_t md_tmplt_hdr_dma; 4712 void *md_dump; 4713 uint32_t md_dump_size; 4714 4715 void *loop_id_map; 4716 4717 /* QLA83XX IDC specific fields */ 4718 uint32_t idc_audit_ts; 4719 uint32_t idc_extend_tmo; 4720 4721 /* DPC low-priority workqueue */ 4722 struct workqueue_struct *dpc_lp_wq; 4723 struct work_struct idc_aen; 4724 /* DPC high-priority workqueue */ 4725 struct workqueue_struct *dpc_hp_wq; 4726 struct work_struct nic_core_reset; 4727 struct work_struct idc_state_handler; 4728 struct work_struct nic_core_unrecoverable; 4729 struct work_struct board_disable; 4730 4731 struct mr_data_fx00 mr; 4732 uint32_t chip_reset; 4733 4734 struct qlt_hw_data tgt; 4735 int allow_cna_fw_dump; 4736 uint32_t fw_ability_mask; 4737 uint16_t min_supported_speed; 4738 uint16_t max_supported_speed; 4739 4740 /* DMA pool for the DIF bundling buffers */ 4741 struct dma_pool *dif_bundl_pool; 4742 #define DIF_BUNDLING_DMA_POOL_SIZE 1024 4743 struct { 4744 struct { 4745 struct list_head head; 4746 uint count; 4747 } good; 4748 struct { 4749 struct list_head head; 4750 uint count; 4751 } unusable; 4752 } pool; 4753 4754 unsigned long long dif_bundle_crossed_pages; 4755 unsigned long long dif_bundle_reads; 4756 unsigned long long dif_bundle_writes; 4757 unsigned long long dif_bundle_kallocs; 4758 unsigned long long dif_bundle_dma_allocs; 4759 4760 atomic_t nvme_active_aen_cnt; 4761 uint16_t nvme_last_rptd_aen; /* Last recorded aen count */ 4762 4763 uint8_t fc4_type_priority; 4764 4765 atomic_t zio_threshold; 4766 uint16_t last_zio_threshold; 4767 4768 #define DEFAULT_ZIO_THRESHOLD 5 4769 4770 struct qla_hw_data_stat stat; 4771 pci_error_state_t pci_error_state; 4772 struct dma_pool *purex_dma_pool; 4773 struct btree_head32 host_map; 4774 4775 #define EDIF_NUM_SA_INDEX 512 4776 #define EDIF_TX_SA_INDEX_BASE EDIF_NUM_SA_INDEX 4777 void *edif_rx_sa_id_map; 4778 void *edif_tx_sa_id_map; 4779 spinlock_t sadb_fp_lock; 4780 4781 struct list_head sadb_tx_index_list; 4782 struct list_head sadb_rx_index_list; 4783 spinlock_t sadb_lock; /* protects list */ 4784 struct els_reject elsrej; 4785 u8 edif_post_stop_cnt_down; 4786 struct qla_vp_map *vp_map; 4787 }; 4788 4789 #define RX_ELS_SIZE (roundup(sizeof(struct enode) + ELS_MAX_PAYLOAD, SMP_CACHE_BYTES)) 4790 4791 struct active_regions { 4792 uint8_t global; 4793 struct { 4794 uint8_t board_config; 4795 uint8_t vpd_nvram; 4796 uint8_t npiv_config_0_1; 4797 uint8_t npiv_config_2_3; 4798 uint8_t nvme_params; 4799 } aux; 4800 }; 4801 4802 #define FW_ABILITY_MAX_SPEED_MASK 0xFUL 4803 #define FW_ABILITY_MAX_SPEED_16G 0x0 4804 #define FW_ABILITY_MAX_SPEED_32G 0x1 4805 #define FW_ABILITY_MAX_SPEED(ha) \ 4806 (ha->fw_ability_mask & FW_ABILITY_MAX_SPEED_MASK) 4807 4808 #define QLA_GET_DATA_RATE 0 4809 #define QLA_SET_DATA_RATE_NOLR 1 4810 #define QLA_SET_DATA_RATE_LR 2 /* Set speed and initiate LR */ 4811 4812 #define QLA_DEFAULT_PAYLOAD_SIZE 64 4813 /* 4814 * This item might be allocated with a size > sizeof(struct purex_item). 4815 * The "size" variable gives the size of the payload (which 4816 * is variable) starting at "iocb". 4817 */ 4818 struct purex_item { 4819 struct list_head list; 4820 struct scsi_qla_host *vha; 4821 void (*process_item)(struct scsi_qla_host *vha, 4822 struct purex_item *pkt); 4823 atomic_t in_use; 4824 uint16_t size; 4825 struct { 4826 uint8_t iocb[64]; 4827 } iocb; 4828 }; 4829 4830 #include "qla_edif.h" 4831 4832 #define SCM_FLAG_RDF_REJECT 0x00 4833 #define SCM_FLAG_RDF_COMPLETED 0x01 4834 4835 #define QLA_CON_PRIMITIVE_RECEIVED 0x1 4836 #define QLA_CONGESTION_ARB_WARNING 0x1 4837 #define QLA_CONGESTION_ARB_ALARM 0X2 4838 4839 /* 4840 * Qlogic scsi host structure 4841 */ 4842 typedef struct scsi_qla_host { 4843 struct list_head list; 4844 struct list_head vp_fcports; /* list of fcports */ 4845 struct list_head work_list; 4846 spinlock_t work_lock; 4847 struct work_struct iocb_work; 4848 4849 /* Commonly used flags and state information. */ 4850 struct Scsi_Host *host; 4851 unsigned long host_no; 4852 uint8_t host_str[16]; 4853 4854 volatile struct { 4855 uint32_t init_done :1; 4856 uint32_t online :1; 4857 uint32_t reset_active :1; 4858 4859 uint32_t management_server_logged_in :1; 4860 uint32_t process_response_queue :1; 4861 uint32_t difdix_supported:1; 4862 uint32_t delete_progress:1; 4863 4864 uint32_t fw_tgt_reported:1; 4865 uint32_t bbcr_enable:1; 4866 uint32_t qpairs_available:1; 4867 uint32_t qpairs_req_created:1; 4868 uint32_t qpairs_rsp_created:1; 4869 uint32_t nvme_enabled:1; 4870 uint32_t nvme_first_burst:1; 4871 uint32_t nvme2_enabled:1; 4872 } flags; 4873 4874 atomic_t loop_state; 4875 #define LOOP_TIMEOUT 1 4876 #define LOOP_DOWN 2 4877 #define LOOP_UP 3 4878 #define LOOP_UPDATE 4 4879 #define LOOP_READY 5 4880 #define LOOP_DEAD 6 4881 4882 unsigned long buf_expired; 4883 unsigned long relogin_jif; 4884 unsigned long dpc_flags; 4885 #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */ 4886 #define RESET_ACTIVE 1 4887 #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */ 4888 #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */ 4889 #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */ 4890 #define LOOP_RESYNC_ACTIVE 5 4891 #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */ 4892 #define RSCN_UPDATE 7 /* Perform an RSCN update. */ 4893 #define RELOGIN_NEEDED 8 4894 #define REGISTER_FC4_NEEDED 9 /* SNS FC4 registration required. */ 4895 #define ISP_ABORT_RETRY 10 /* ISP aborted. */ 4896 #define BEACON_BLINK_NEEDED 11 4897 #define REGISTER_FDMI_NEEDED 12 4898 #define VP_DPC_NEEDED 14 /* wake up for VP dpc handling */ 4899 #define UNLOADING 15 4900 #define NPIV_CONFIG_NEEDED 16 4901 #define ISP_UNRECOVERABLE 17 4902 #define FCOE_CTX_RESET_NEEDED 18 /* Initiate FCoE context reset */ 4903 #define MPI_RESET_NEEDED 19 /* Initiate MPI FW reset */ 4904 #define ISP_QUIESCE_NEEDED 20 /* Driver need some quiescence */ 4905 #define N2N_LINK_RESET 21 4906 #define PORT_UPDATE_NEEDED 22 4907 #define FX00_RESET_RECOVERY 23 4908 #define FX00_TARGET_SCAN 24 4909 #define FX00_CRITEMP_RECOVERY 25 4910 #define FX00_HOST_INFO_RESEND 26 4911 #define QPAIR_ONLINE_CHECK_NEEDED 27 4912 #define DO_EEH_RECOVERY 28 4913 #define DETECT_SFP_CHANGE 29 4914 #define N2N_LOGIN_NEEDED 30 4915 #define IOCB_WORK_ACTIVE 31 4916 #define SET_ZIO_THRESHOLD_NEEDED 32 4917 #define ISP_ABORT_TO_ROM 33 4918 #define VPORT_DELETE 34 4919 4920 #define PROCESS_PUREX_IOCB 63 4921 4922 unsigned long pci_flags; 4923 #define PFLG_DISCONNECTED 0 /* PCI device removed */ 4924 #define PFLG_DRIVER_REMOVING 1 /* PCI driver .remove */ 4925 #define PFLG_DRIVER_PROBING 2 /* PCI driver .probe */ 4926 4927 uint32_t device_flags; 4928 #define SWITCH_FOUND BIT_0 4929 #define DFLG_NO_CABLE BIT_1 4930 #define DFLG_DEV_FAILED BIT_5 4931 4932 /* ISP configuration data. */ 4933 uint16_t loop_id; /* Host adapter loop id */ 4934 uint16_t self_login_loop_id; /* host adapter loop id 4935 * get it on self login 4936 */ 4937 fc_port_t bidir_fcport; /* fcport used for bidir cmnds 4938 * no need of allocating it for 4939 * each command 4940 */ 4941 4942 port_id_t d_id; /* Host adapter port id */ 4943 uint8_t marker_needed; 4944 uint16_t mgmt_svr_loop_id; 4945 4946 4947 4948 /* Timeout timers. */ 4949 uint8_t loop_down_abort_time; /* port down timer */ 4950 atomic_t loop_down_timer; /* loop down timer */ 4951 uint8_t link_down_timeout; /* link down timeout */ 4952 4953 uint32_t timer_active; 4954 struct timer_list timer; 4955 4956 uint8_t node_name[WWN_SIZE]; 4957 uint8_t port_name[WWN_SIZE]; 4958 uint8_t fabric_node_name[WWN_SIZE]; 4959 uint8_t fabric_port_name[WWN_SIZE]; 4960 4961 struct nvme_fc_local_port *nvme_local_port; 4962 struct completion nvme_del_done; 4963 4964 uint16_t fcoe_vlan_id; 4965 uint16_t fcoe_fcf_idx; 4966 uint8_t fcoe_vn_port_mac[6]; 4967 4968 /* list of commands waiting on workqueue */ 4969 struct list_head qla_cmd_list; 4970 struct list_head unknown_atio_list; 4971 spinlock_t cmd_list_lock; 4972 struct delayed_work unknown_atio_work; 4973 4974 /* Counter to detect races between ELS and RSCN events */ 4975 atomic_t generation_tick; 4976 /* Time when global fcport update has been scheduled */ 4977 int total_fcport_update_gen; 4978 /* List of pending LOGOs, protected by tgt_mutex */ 4979 struct list_head logo_list; 4980 /* List of pending PLOGI acks, protected by hw lock */ 4981 struct list_head plogi_ack_list; 4982 4983 struct list_head qp_list; 4984 4985 uint32_t vp_abort_cnt; 4986 4987 struct fc_vport *fc_vport; /* holds fc_vport * for each vport */ 4988 uint16_t vp_idx; /* vport ID */ 4989 struct qla_qpair *qpair; /* base qpair */ 4990 4991 unsigned long vp_flags; 4992 #define VP_IDX_ACQUIRED 0 /* bit no 0 */ 4993 #define VP_CREATE_NEEDED 1 4994 #define VP_BIND_NEEDED 2 4995 #define VP_DELETE_NEEDED 3 4996 #define VP_SCR_NEEDED 4 /* State Change Request registration */ 4997 #define VP_CONFIG_OK 5 /* Flag to cfg VP, if FW is ready */ 4998 atomic_t vp_state; 4999 #define VP_OFFLINE 0 5000 #define VP_ACTIVE 1 5001 #define VP_FAILED 2 5002 // #define VP_DISABLE 3 5003 uint16_t vp_err_state; 5004 uint16_t vp_prev_err_state; 5005 #define VP_ERR_UNKWN 0 5006 #define VP_ERR_PORTDWN 1 5007 #define VP_ERR_FAB_UNSUPPORTED 2 5008 #define VP_ERR_FAB_NORESOURCES 3 5009 #define VP_ERR_FAB_LOGOUT 4 5010 #define VP_ERR_ADAP_NORESOURCES 5 5011 struct qla_hw_data *hw; 5012 struct scsi_qlt_host vha_tgt; 5013 struct req_que *req; 5014 int fw_heartbeat_counter; 5015 int seconds_since_last_heartbeat; 5016 struct fc_host_statistics fc_host_stat; 5017 struct qla_statistics qla_stats; 5018 struct bidi_statistics bidi_stats; 5019 atomic_t vref_count; 5020 struct qla8044_reset_template reset_tmplt; 5021 uint16_t bbcr; 5022 5023 uint16_t u_ql2xexchoffld; 5024 uint16_t u_ql2xiniexchg; 5025 uint16_t qlini_mode; 5026 uint16_t ql2xexchoffld; 5027 uint16_t ql2xiniexchg; 5028 5029 struct dentry *dfs_rport_root; 5030 5031 struct purex_list { 5032 struct list_head head; 5033 spinlock_t lock; 5034 } purex_list; 5035 struct purex_item default_item; 5036 5037 struct name_list_extended gnl; 5038 /* Count of active session/fcport */ 5039 int fcport_count; 5040 wait_queue_head_t fcport_waitQ; 5041 wait_queue_head_t vref_waitq; 5042 uint8_t min_supported_speed; 5043 uint8_t n2n_node_name[WWN_SIZE]; 5044 uint8_t n2n_port_name[WWN_SIZE]; 5045 uint16_t n2n_id; 5046 __le16 dport_data[4]; 5047 struct fab_scan scan; 5048 uint8_t scm_fabric_connection_flags; 5049 5050 unsigned int irq_offset; 5051 5052 u64 hw_err_cnt; 5053 u64 interface_err_cnt; 5054 u64 cmd_timeout_cnt; 5055 u64 reset_cmd_err_cnt; 5056 u64 link_down_time; 5057 u64 short_link_down_cnt; 5058 struct edif_dbell e_dbell; 5059 struct pur_core pur_cinfo; 5060 5061 #define DPORT_DIAG_IN_PROGRESS BIT_0 5062 #define DPORT_DIAG_CHIP_RESET_IN_PROGRESS BIT_1 5063 uint16_t dport_status; 5064 } scsi_qla_host_t; 5065 5066 struct qla27xx_image_status { 5067 uint8_t image_status_mask; 5068 __le16 generation; 5069 uint8_t ver_major; 5070 uint8_t ver_minor; 5071 uint8_t bitmap; /* 28xx only */ 5072 uint8_t reserved[2]; 5073 __le32 checksum; 5074 __le32 signature; 5075 } __packed; 5076 5077 /* 28xx aux image status bimap values */ 5078 #define QLA28XX_AUX_IMG_BOARD_CONFIG BIT_0 5079 #define QLA28XX_AUX_IMG_VPD_NVRAM BIT_1 5080 #define QLA28XX_AUX_IMG_NPIV_CONFIG_0_1 BIT_2 5081 #define QLA28XX_AUX_IMG_NPIV_CONFIG_2_3 BIT_3 5082 #define QLA28XX_AUX_IMG_NVME_PARAMS BIT_4 5083 5084 #define SET_VP_IDX 1 5085 #define SET_AL_PA 2 5086 #define RESET_VP_IDX 3 5087 #define RESET_AL_PA 4 5088 struct qla_vp_map { 5089 uint8_t idx; 5090 scsi_qla_host_t *vha; 5091 }; 5092 5093 struct qla2_sgx { 5094 dma_addr_t dma_addr; /* OUT */ 5095 uint32_t dma_len; /* OUT */ 5096 5097 uint32_t tot_bytes; /* IN */ 5098 struct scatterlist *cur_sg; /* IN */ 5099 5100 /* for book keeping, bzero on initial invocation */ 5101 uint32_t bytes_consumed; 5102 uint32_t num_bytes; 5103 uint32_t tot_partial; 5104 5105 /* for debugging */ 5106 uint32_t num_sg; 5107 srb_t *sp; 5108 }; 5109 5110 #define QLA_FW_STARTED(_ha) { \ 5111 int i; \ 5112 _ha->flags.fw_started = 1; \ 5113 _ha->base_qpair->fw_started = 1; \ 5114 for (i = 0; i < _ha->max_qpairs; i++) { \ 5115 if (_ha->queue_pair_map[i]) \ 5116 _ha->queue_pair_map[i]->fw_started = 1; \ 5117 } \ 5118 } 5119 5120 #define QLA_FW_STOPPED(_ha) { \ 5121 int i; \ 5122 _ha->flags.fw_started = 0; \ 5123 _ha->base_qpair->fw_started = 0; \ 5124 for (i = 0; i < _ha->max_qpairs; i++) { \ 5125 if (_ha->queue_pair_map[i]) \ 5126 _ha->queue_pair_map[i]->fw_started = 0; \ 5127 } \ 5128 } 5129 5130 5131 #define SFUB_CHECKSUM_SIZE 4 5132 5133 struct secure_flash_update_block { 5134 uint32_t block_info; 5135 uint32_t signature_lo; 5136 uint32_t signature_hi; 5137 uint32_t signature_upper[0x3e]; 5138 }; 5139 5140 struct secure_flash_update_block_pk { 5141 uint32_t block_info; 5142 uint32_t signature_lo; 5143 uint32_t signature_hi; 5144 uint32_t signature_upper[0x3e]; 5145 uint32_t public_key[0x41]; 5146 }; 5147 5148 /* 5149 * Macros to help code, maintain, etc. 5150 */ 5151 #define LOOP_TRANSITION(ha) \ 5152 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \ 5153 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \ 5154 atomic_read(&ha->loop_state) == LOOP_DOWN) 5155 5156 #define STATE_TRANSITION(ha) \ 5157 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \ 5158 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags)) 5159 5160 static inline bool qla_vha_mark_busy(scsi_qla_host_t *vha) 5161 { 5162 atomic_inc(&vha->vref_count); 5163 mb(); 5164 if (vha->flags.delete_progress) { 5165 atomic_dec(&vha->vref_count); 5166 wake_up(&vha->vref_waitq); 5167 return true; 5168 } 5169 return false; 5170 } 5171 5172 #define QLA_VHA_MARK_NOT_BUSY(__vha) do { \ 5173 atomic_dec(&__vha->vref_count); \ 5174 wake_up(&__vha->vref_waitq); \ 5175 } while (0) \ 5176 5177 #define QLA_QPAIR_MARK_BUSY(__qpair, __bail) do { \ 5178 atomic_inc(&__qpair->ref_count); \ 5179 mb(); \ 5180 if (__qpair->delete_in_progress) { \ 5181 atomic_dec(&__qpair->ref_count); \ 5182 __bail = 1; \ 5183 } else { \ 5184 __bail = 0; \ 5185 } \ 5186 } while (0) 5187 5188 #define QLA_QPAIR_MARK_NOT_BUSY(__qpair) \ 5189 atomic_dec(&__qpair->ref_count) 5190 5191 #define QLA_ENA_CONF(_ha) {\ 5192 int i;\ 5193 _ha->base_qpair->enable_explicit_conf = 1; \ 5194 for (i = 0; i < _ha->max_qpairs; i++) { \ 5195 if (_ha->queue_pair_map[i]) \ 5196 _ha->queue_pair_map[i]->enable_explicit_conf = 1; \ 5197 } \ 5198 } 5199 5200 #define QLA_DIS_CONF(_ha) {\ 5201 int i;\ 5202 _ha->base_qpair->enable_explicit_conf = 0; \ 5203 for (i = 0; i < _ha->max_qpairs; i++) { \ 5204 if (_ha->queue_pair_map[i]) \ 5205 _ha->queue_pair_map[i]->enable_explicit_conf = 0; \ 5206 } \ 5207 } 5208 5209 /* 5210 * qla2x00 local function return status codes 5211 */ 5212 #define MBS_MASK 0x3fff 5213 5214 #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK) 5215 #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK) 5216 #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK) 5217 #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK) 5218 #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK) 5219 #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK) 5220 #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK) 5221 #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK) 5222 #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK) 5223 #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK) 5224 5225 #define QLA_FUNCTION_TIMEOUT 0x100 5226 #define QLA_FUNCTION_PARAMETER_ERROR 0x101 5227 #define QLA_FUNCTION_FAILED 0x102 5228 #define QLA_MEMORY_ALLOC_FAILED 0x103 5229 #define QLA_LOCK_TIMEOUT 0x104 5230 #define QLA_ABORTED 0x105 5231 #define QLA_SUSPENDED 0x106 5232 #define QLA_BUSY 0x107 5233 #define QLA_ALREADY_REGISTERED 0x109 5234 #define QLA_OS_TIMER_EXPIRED 0x10a 5235 #define QLA_ERR_NO_QPAIR 0x10b 5236 #define QLA_ERR_NOT_FOUND 0x10c 5237 #define QLA_ERR_FROM_FW 0x10d 5238 5239 #define NVRAM_DELAY() udelay(10) 5240 5241 /* 5242 * Flash support definitions 5243 */ 5244 #define OPTROM_SIZE_2300 0x20000 5245 #define OPTROM_SIZE_2322 0x100000 5246 #define OPTROM_SIZE_24XX 0x100000 5247 #define OPTROM_SIZE_25XX 0x200000 5248 #define OPTROM_SIZE_81XX 0x400000 5249 #define OPTROM_SIZE_82XX 0x800000 5250 #define OPTROM_SIZE_83XX 0x1000000 5251 #define OPTROM_SIZE_28XX 0x2000000 5252 5253 #define OPTROM_BURST_SIZE 0x1000 5254 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4) 5255 5256 #define QLA_DSDS_PER_IOCB 37 5257 5258 #define QLA_SG_ALL 1024 5259 5260 enum nexus_wait_type { 5261 WAIT_HOST = 0, 5262 WAIT_TARGET, 5263 WAIT_LUN, 5264 }; 5265 5266 #define INVALID_EDIF_SA_INDEX 0xffff 5267 #define RX_DELETE_NO_EDIF_SA_INDEX 0xfffe 5268 5269 #define QLA_SKIP_HANDLE QLA_TGT_SKIP_HANDLE 5270 5271 /* edif hash element */ 5272 struct edif_list_entry { 5273 uint16_t handle; /* nport_handle */ 5274 uint32_t update_sa_index; 5275 uint32_t delete_sa_index; 5276 uint32_t count; /* counter for filtering sa_index */ 5277 #define EDIF_ENTRY_FLAGS_CLEANUP 0x01 /* this index is being cleaned up */ 5278 uint32_t flags; /* used by sadb cleanup code */ 5279 fc_port_t *fcport; /* needed by rx delay timer function */ 5280 struct timer_list timer; /* rx delay timer */ 5281 struct list_head next; 5282 }; 5283 5284 #define EDIF_TX_INDX_BASE 512 5285 #define EDIF_RX_INDX_BASE 0 5286 #define EDIF_RX_DELETE_FILTER_COUNT 3 /* delay queuing rx delete until this many */ 5287 5288 /* entry in the sa_index free pool */ 5289 5290 struct sa_index_pair { 5291 uint16_t sa_index; 5292 uint32_t spi; 5293 }; 5294 5295 /* edif sa_index data structure */ 5296 struct edif_sa_index_entry { 5297 struct sa_index_pair sa_pair[2]; 5298 fc_port_t *fcport; 5299 uint16_t handle; 5300 struct list_head next; 5301 }; 5302 5303 /* Refer to SNIA SFF 8247 */ 5304 struct sff_8247_a0 { 5305 u8 txid; /* transceiver id */ 5306 u8 ext_txid; 5307 u8 connector; 5308 /* compliance code */ 5309 u8 eth_infi_cc3; /* ethernet, inifiband */ 5310 u8 sonet_cc4[2]; 5311 u8 eth_cc6; 5312 /* link length */ 5313 #define FC_LL_VL BIT_7 /* very long */ 5314 #define FC_LL_S BIT_6 /* Short */ 5315 #define FC_LL_I BIT_5 /* Intermidiate*/ 5316 #define FC_LL_L BIT_4 /* Long */ 5317 #define FC_LL_M BIT_3 /* Medium */ 5318 #define FC_LL_SA BIT_2 /* ShortWave laser */ 5319 #define FC_LL_LC BIT_1 /* LongWave laser */ 5320 #define FC_LL_EL BIT_0 /* Electrical inter enclosure */ 5321 u8 fc_ll_cc7; 5322 /* FC technology */ 5323 #define FC_TEC_EL BIT_7 /* Electrical inter enclosure */ 5324 #define FC_TEC_SN BIT_6 /* short wave w/o OFC */ 5325 #define FC_TEC_SL BIT_5 /* short wave with OFC */ 5326 #define FC_TEC_LL BIT_4 /* Longwave Laser */ 5327 #define FC_TEC_ACT BIT_3 /* Active cable */ 5328 #define FC_TEC_PAS BIT_2 /* Passive cable */ 5329 u8 fc_tec_cc8; 5330 /* Transmission Media */ 5331 #define FC_MED_TW BIT_7 /* Twin Ax */ 5332 #define FC_MED_TP BIT_6 /* Twited Pair */ 5333 #define FC_MED_MI BIT_5 /* Min Coax */ 5334 #define FC_MED_TV BIT_4 /* Video Coax */ 5335 #define FC_MED_M6 BIT_3 /* Multimode, 62.5um */ 5336 #define FC_MED_M5 BIT_2 /* Multimode, 50um */ 5337 #define FC_MED_SM BIT_0 /* Single Mode */ 5338 u8 fc_med_cc9; 5339 /* speed FC_SP_12: 12*100M = 1200 MB/s */ 5340 #define FC_SP_12 BIT_7 5341 #define FC_SP_8 BIT_6 5342 #define FC_SP_16 BIT_5 5343 #define FC_SP_4 BIT_4 5344 #define FC_SP_32 BIT_3 5345 #define FC_SP_2 BIT_2 5346 #define FC_SP_1 BIT_0 5347 u8 fc_sp_cc10; 5348 u8 encode; 5349 u8 bitrate; 5350 u8 rate_id; 5351 u8 length_km; /* offset 14/eh */ 5352 u8 length_100m; 5353 u8 length_50um_10m; 5354 u8 length_62um_10m; 5355 u8 length_om4_10m; 5356 u8 length_om3_10m; 5357 #define SFF_VEN_NAME_LEN 16 5358 u8 vendor_name[SFF_VEN_NAME_LEN]; /* offset 20/14h */ 5359 u8 tx_compat; 5360 u8 vendor_oui[3]; 5361 #define SFF_PART_NAME_LEN 16 5362 u8 vendor_pn[SFF_PART_NAME_LEN]; /* part number */ 5363 u8 vendor_rev[4]; 5364 u8 wavelength[2]; 5365 u8 resv; 5366 u8 cc_base; 5367 u8 options[2]; /* offset 64 */ 5368 u8 br_max; 5369 u8 br_min; 5370 u8 vendor_sn[16]; 5371 u8 date_code[8]; 5372 u8 diag; 5373 u8 enh_options; 5374 u8 sff_revision; 5375 u8 cc_ext; 5376 u8 vendor_specific[32]; 5377 u8 resv2[128]; 5378 }; 5379 5380 /* BPM -- Buffer Plus Management support. */ 5381 #define IS_BPM_CAPABLE(ha) \ 5382 (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 5383 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 5384 #define IS_BPM_RANGE_CAPABLE(ha) \ 5385 (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 5386 #define IS_BPM_ENABLED(vha) \ 5387 (ql2xautodetectsfp && !vha->vp_idx && IS_BPM_CAPABLE(vha->hw)) 5388 5389 #define FLASH_SEMAPHORE_REGISTER_ADDR 0x00101016 5390 5391 #define USER_CTRL_IRQ(_ha) (ql2xuctrlirq && QLA_TGT_MODE_ENABLED() && \ 5392 (IS_QLA27XX(_ha) || IS_QLA28XX(_ha) || IS_QLA83XX(_ha))) 5393 5394 #define SAVE_TOPO(_ha) { \ 5395 if (_ha->current_topology) \ 5396 _ha->prev_topology = _ha->current_topology; \ 5397 } 5398 5399 #define N2N_TOPO(ha) \ 5400 ((ha->prev_topology == ISP_CFG_N && !ha->current_topology) || \ 5401 ha->current_topology == ISP_CFG_N || \ 5402 !ha->current_topology) 5403 5404 #define QLA_N2N_WAIT_TIME 5 /* 2 * ra_tov(n2n) + 1 */ 5405 5406 #define NVME_TYPE(fcport) \ 5407 (fcport->fc4_type & FS_FC4TYPE_NVME) \ 5408 5409 #define FCP_TYPE(fcport) \ 5410 (fcport->fc4_type & FS_FC4TYPE_FCP) \ 5411 5412 #define NVME_ONLY_TARGET(fcport) \ 5413 (NVME_TYPE(fcport) && !FCP_TYPE(fcport)) \ 5414 5415 #define NVME_FCP_TARGET(fcport) \ 5416 (FCP_TYPE(fcport) && NVME_TYPE(fcport)) \ 5417 5418 #define NVME_PRIORITY(ha, fcport) \ 5419 (NVME_FCP_TARGET(fcport) && \ 5420 (ha->fc4_type_priority == FC4_PRIORITY_NVME)) 5421 5422 #define NVME_TARGET(ha, fcport) \ 5423 (fcport->do_prli_nvme || \ 5424 NVME_ONLY_TARGET(fcport)) \ 5425 5426 #define PRLI_PHASE(_cls) \ 5427 ((_cls == DSC_LS_PRLI_PEND) || (_cls == DSC_LS_PRLI_COMP)) 5428 5429 enum ql_vnd_host_stat_action { 5430 QLA_STOP = 0, 5431 QLA_START, 5432 QLA_CLEAR, 5433 }; 5434 5435 struct ql_vnd_mng_host_stats_param { 5436 u32 stat_type; 5437 enum ql_vnd_host_stat_action action; 5438 } __packed; 5439 5440 struct ql_vnd_mng_host_stats_resp { 5441 u32 status; 5442 } __packed; 5443 5444 struct ql_vnd_stats_param { 5445 u32 stat_type; 5446 } __packed; 5447 5448 struct ql_vnd_tgt_stats_param { 5449 s32 tgt_id; 5450 u32 stat_type; 5451 } __packed; 5452 5453 enum ql_vnd_host_port_action { 5454 QLA_ENABLE = 0, 5455 QLA_DISABLE, 5456 }; 5457 5458 struct ql_vnd_mng_host_port_param { 5459 enum ql_vnd_host_port_action action; 5460 } __packed; 5461 5462 struct ql_vnd_mng_host_port_resp { 5463 u32 status; 5464 } __packed; 5465 5466 struct ql_vnd_stat_entry { 5467 u32 stat_type; /* Failure type */ 5468 u32 tgt_num; /* Target Num */ 5469 u64 cnt; /* Counter value */ 5470 } __packed; 5471 5472 struct ql_vnd_stats { 5473 u64 entry_count; /* Num of entries */ 5474 u64 rservd; 5475 struct ql_vnd_stat_entry entry[]; /* Place holder of entries */ 5476 } __packed; 5477 5478 struct ql_vnd_host_stats_resp { 5479 u32 status; 5480 struct ql_vnd_stats stats; 5481 } __packed; 5482 5483 struct ql_vnd_tgt_stats_resp { 5484 u32 status; 5485 struct ql_vnd_stats stats; 5486 } __packed; 5487 5488 #include "qla_target.h" 5489 #include "qla_gbl.h" 5490 #include "qla_dbg.h" 5491 #include "qla_inline.h" 5492 5493 #define IS_SESSION_DELETED(_fcport) (_fcport->disc_state == DSC_DELETE_PEND || \ 5494 _fcport->disc_state == DSC_DELETED) 5495 5496 #define DBG_FCPORT_PRFMT(_fp, _fmt, _args...) \ 5497 "%s: %8phC: " _fmt " (state=%d disc_state=%d scan_state=%d loopid=0x%x deleted=%d flags=0x%x)\n", \ 5498 __func__, _fp->port_name, ##_args, atomic_read(&_fp->state), \ 5499 _fp->disc_state, _fp->scan_state, _fp->loop_id, _fp->deleted, \ 5500 _fp->flags 5501 5502 #endif 5503