xref: /openbmc/linux/drivers/usb/chipidea/ci.h (revision 979ac5ef) 
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * ci.h - common structures, functions, and macros of the ChipIdea driver
4  *
5  * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
6  *
7  * Author: David Lopo
8  */
9 
10 #ifndef __DRIVERS_USB_CHIPIDEA_CI_H
11 #define __DRIVERS_USB_CHIPIDEA_CI_H
12 
13 #include <linux/list.h>
14 #include <linux/irqreturn.h>
15 #include <linux/usb.h>
16 #include <linux/usb/gadget.h>
17 #include <linux/usb/otg-fsm.h>
18 #include <linux/usb/otg.h>
19 #include <linux/usb/role.h>
20 #include <linux/ulpi/interface.h>
21 
22 /******************************************************************************
23  * DEFINE
24  *****************************************************************************/
25 #define TD_PAGE_COUNT      5
26 #define CI_HDRC_PAGE_SIZE  4096ul /* page size for TD's */
27 #define ENDPT_MAX          32
28 #define CI_MAX_BUF_SIZE	(TD_PAGE_COUNT * CI_HDRC_PAGE_SIZE)
29 
30 /******************************************************************************
31  * REGISTERS
32  *****************************************************************************/
33 /* Identification Registers */
34 #define ID_ID				0x0
35 #define ID_HWGENERAL			0x4
36 #define ID_HWHOST			0x8
37 #define ID_HWDEVICE			0xc
38 #define ID_HWTXBUF			0x10
39 #define ID_HWRXBUF			0x14
40 #define ID_SBUSCFG			0x90
41 
42 /* register indices */
43 enum ci_hw_regs {
44 	CAP_CAPLENGTH,
45 	CAP_HCCPARAMS,
46 	CAP_DCCPARAMS,
47 	CAP_TESTMODE,
48 	CAP_LAST = CAP_TESTMODE,
49 	OP_USBCMD,
50 	OP_USBSTS,
51 	OP_USBINTR,
52 	OP_FRINDEX,
53 	OP_DEVICEADDR,
54 	OP_ENDPTLISTADDR,
55 	OP_TTCTRL,
56 	OP_BURSTSIZE,
57 	OP_ULPI_VIEWPORT,
58 	OP_PORTSC,
59 	OP_DEVLC,
60 	OP_OTGSC,
61 	OP_USBMODE,
62 	OP_ENDPTSETUPSTAT,
63 	OP_ENDPTPRIME,
64 	OP_ENDPTFLUSH,
65 	OP_ENDPTSTAT,
66 	OP_ENDPTCOMPLETE,
67 	OP_ENDPTCTRL,
68 	/* endptctrl1..15 follow */
69 	OP_LAST = OP_ENDPTCTRL + ENDPT_MAX / 2,
70 };
71 
72 /******************************************************************************
73  * STRUCTURES
74  *****************************************************************************/
75 /**
76  * struct ci_hw_ep - endpoint representation
77  * @ep: endpoint structure for gadget drivers
78  * @dir: endpoint direction (TX/RX)
79  * @num: endpoint number
80  * @type: endpoint type
81  * @name: string description of the endpoint
82  * @qh: queue head for this endpoint
83  * @wedge: is the endpoint wedged
84  * @ci: pointer to the controller
85  * @lock: pointer to controller's spinlock
86  * @td_pool: pointer to controller's TD pool
87  */
88 struct ci_hw_ep {
89 	struct usb_ep				ep;
90 	u8					dir;
91 	u8					num;
92 	u8					type;
93 	char					name[16];
94 	struct {
95 		struct list_head	queue;
96 		struct ci_hw_qh		*ptr;
97 		dma_addr_t		dma;
98 	}					qh;
99 	int					wedge;
100 
101 	/* global resources */
102 	struct ci_hdrc				*ci;
103 	spinlock_t				*lock;
104 	struct dma_pool				*td_pool;
105 	struct td_node				*pending_td;
106 };
107 
108 enum ci_role {
109 	CI_ROLE_HOST = 0,
110 	CI_ROLE_GADGET,
111 	CI_ROLE_END,
112 };
113 
114 enum ci_revision {
115 	CI_REVISION_1X = 10,	/* Revision 1.x */
116 	CI_REVISION_20 = 20, /* Revision 2.0 */
117 	CI_REVISION_21, /* Revision 2.1 */
118 	CI_REVISION_22, /* Revision 2.2 */
119 	CI_REVISION_23, /* Revision 2.3 */
120 	CI_REVISION_24, /* Revision 2.4 */
121 	CI_REVISION_25, /* Revision 2.5 */
122 	CI_REVISION_25_PLUS, /* Revision above than 2.5 */
123 	CI_REVISION_UNKNOWN = 99, /* Unknown Revision */
124 };
125 
126 /**
127  * struct ci_role_driver - host/gadget role driver
128  * @start: start this role
129  * @stop: stop this role
130  * @suspend: system suspend handler for this role
131  * @resume: system resume handler for this role
132  * @irq: irq handler for this role
133  * @name: role name string (host/gadget)
134  */
135 struct ci_role_driver {
136 	int		(*start)(struct ci_hdrc *);
137 	void		(*stop)(struct ci_hdrc *);
138 	void		(*suspend)(struct ci_hdrc *ci);
139 	void		(*resume)(struct ci_hdrc *ci, bool power_lost);
140 	irqreturn_t	(*irq)(struct ci_hdrc *);
141 	const char	*name;
142 };
143 
144 /**
145  * struct hw_bank - hardware register mapping representation
146  * @lpm: set if the device is LPM capable
147  * @phys: physical address of the controller's registers
148  * @abs: absolute address of the beginning of register window
149  * @cap: capability registers
150  * @op: operational registers
151  * @size: size of the register window
152  * @regmap: register lookup table
153  */
154 struct hw_bank {
155 	unsigned	lpm;
156 	resource_size_t	phys;
157 	void __iomem	*abs;
158 	void __iomem	*cap;
159 	void __iomem	*op;
160 	size_t		size;
161 	void __iomem	*regmap[OP_LAST + 1];
162 };
163 
164 /**
165  * struct ci_hdrc - chipidea device representation
166  * @dev: pointer to parent device
167  * @lock: access synchronization
168  * @hw_bank: hardware register mapping
169  * @irq: IRQ number
170  * @roles: array of supported roles for this controller
171  * @role: current role
172  * @is_otg: if the device is otg-capable
173  * @fsm: otg finite state machine
174  * @otg_fsm_hrtimer: hrtimer for otg fsm timers
175  * @hr_timeouts: time out list for active otg fsm timers
176  * @enabled_otg_timer_bits: bits of enabled otg timers
177  * @next_otg_timer: next nearest enabled timer to be expired
178  * @work: work for role changing
179  * @wq: workqueue thread
180  * @qh_pool: allocation pool for queue heads
181  * @td_pool: allocation pool for transfer descriptors
182  * @gadget: device side representation for peripheral controller
183  * @driver: gadget driver
184  * @resume_state: save the state of gadget suspend from
185  * @hw_ep_max: total number of endpoints supported by hardware
186  * @ci_hw_ep: array of endpoints
187  * @ep0_dir: ep0 direction
188  * @ep0out: pointer to ep0 OUT endpoint
189  * @ep0in: pointer to ep0 IN endpoint
190  * @status: ep0 status request
191  * @setaddr: if we should set the address on status completion
192  * @address: usb address received from the host
193  * @remote_wakeup: host-enabled remote wakeup
194  * @suspended: suspended by host
195  * @test_mode: the selected test mode
196  * @platdata: platform specific information supplied by parent device
197  * @vbus_active: is VBUS active
198  * @ulpi: pointer to ULPI device, if any
199  * @ulpi_ops: ULPI read/write ops for this device
200  * @phy: pointer to PHY, if any
201  * @usb_phy: pointer to USB PHY, if any and if using the USB PHY framework
202  * @hcd: pointer to usb_hcd for ehci host driver
203  * @id_event: indicates there is an id event, and handled at ci_otg_work
204  * @b_sess_valid_event: indicates there is a vbus event, and handled
205  * at ci_otg_work
206  * @imx28_write_fix: Freescale imx28 needs swp instruction for writing
207  * @supports_runtime_pm: if runtime pm is supported
208  * @in_lpm: if the core in low power mode
209  * @wakeup_int: if wakeup interrupt occur
210  * @rev: The revision number for controller
211  */
212 struct ci_hdrc {
213 	struct device			*dev;
214 	spinlock_t			lock;
215 	struct hw_bank			hw_bank;
216 	int				irq;
217 	struct ci_role_driver		*roles[CI_ROLE_END];
218 	enum ci_role			role;
219 	bool				is_otg;
220 	struct usb_otg			otg;
221 	struct otg_fsm			fsm;
222 	struct hrtimer			otg_fsm_hrtimer;
223 	ktime_t				hr_timeouts[NUM_OTG_FSM_TIMERS];
224 	unsigned			enabled_otg_timer_bits;
225 	enum otg_fsm_timer		next_otg_timer;
226 	struct usb_role_switch		*role_switch;
227 	struct work_struct		work;
228 	struct workqueue_struct		*wq;
229 
230 	struct dma_pool			*qh_pool;
231 	struct dma_pool			*td_pool;
232 
233 	struct usb_gadget		gadget;
234 	struct usb_gadget_driver	*driver;
235 	enum usb_device_state		resume_state;
236 	unsigned			hw_ep_max;
237 	struct ci_hw_ep			ci_hw_ep[ENDPT_MAX];
238 	u32				ep0_dir;
239 	struct ci_hw_ep			*ep0out, *ep0in;
240 
241 	struct usb_request		*status;
242 	bool				setaddr;
243 	u8				address;
244 	u8				remote_wakeup;
245 	u8				suspended;
246 	u8				test_mode;
247 
248 	struct ci_hdrc_platform_data	*platdata;
249 	int				vbus_active;
250 	struct ulpi			*ulpi;
251 	struct ulpi_ops 		ulpi_ops;
252 	struct phy			*phy;
253 	/* old usb_phy interface */
254 	struct usb_phy			*usb_phy;
255 	struct usb_hcd			*hcd;
256 	bool				id_event;
257 	bool				b_sess_valid_event;
258 	bool				imx28_write_fix;
259 	bool				supports_runtime_pm;
260 	bool				in_lpm;
261 	bool				wakeup_int;
262 	enum ci_revision		rev;
263 };
264 
265 static inline struct ci_role_driver *ci_role(struct ci_hdrc *ci)
266 {
267 	BUG_ON(ci->role >= CI_ROLE_END || !ci->roles[ci->role]);
268 	return ci->roles[ci->role];
269 }
270 
271 static inline int ci_role_start(struct ci_hdrc *ci, enum ci_role role)
272 {
273 	int ret;
274 
275 	if (role >= CI_ROLE_END)
276 		return -EINVAL;
277 
278 	if (!ci->roles[role])
279 		return -ENXIO;
280 
281 	ret = ci->roles[role]->start(ci);
282 	if (!ret)
283 		ci->role = role;
284 	return ret;
285 }
286 
287 static inline void ci_role_stop(struct ci_hdrc *ci)
288 {
289 	enum ci_role role = ci->role;
290 
291 	if (role == CI_ROLE_END)
292 		return;
293 
294 	ci->role = CI_ROLE_END;
295 
296 	ci->roles[role]->stop(ci);
297 }
298 
299 static inline enum usb_role ci_role_to_usb_role(struct ci_hdrc *ci)
300 {
301 	if (ci->role == CI_ROLE_HOST)
302 		return USB_ROLE_HOST;
303 	else if (ci->role == CI_ROLE_GADGET && ci->vbus_active)
304 		return USB_ROLE_DEVICE;
305 	else
306 		return USB_ROLE_NONE;
307 }
308 
309 static inline enum ci_role usb_role_to_ci_role(enum usb_role role)
310 {
311 	if (role == USB_ROLE_HOST)
312 		return CI_ROLE_HOST;
313 	else if (role == USB_ROLE_DEVICE)
314 		return CI_ROLE_GADGET;
315 	else
316 		return CI_ROLE_END;
317 }
318 
319 /**
320  * hw_read_id_reg: reads from a identification register
321  * @ci: the controller
322  * @offset: offset from the beginning of identification registers region
323  * @mask: bitfield mask
324  *
325  * This function returns register contents
326  */
327 static inline u32 hw_read_id_reg(struct ci_hdrc *ci, u32 offset, u32 mask)
328 {
329 	return ioread32(ci->hw_bank.abs + offset) & mask;
330 }
331 
332 /**
333  * hw_write_id_reg: writes to a identification register
334  * @ci: the controller
335  * @offset: offset from the beginning of identification registers region
336  * @mask: bitfield mask
337  * @data: new value
338  */
339 static inline void hw_write_id_reg(struct ci_hdrc *ci, u32 offset,
340 			    u32 mask, u32 data)
341 {
342 	if (~mask)
343 		data = (ioread32(ci->hw_bank.abs + offset) & ~mask)
344 			| (data & mask);
345 
346 	iowrite32(data, ci->hw_bank.abs + offset);
347 }
348 
349 /**
350  * hw_read: reads from a hw register
351  * @ci: the controller
352  * @reg:  register index
353  * @mask: bitfield mask
354  *
355  * This function returns register contents
356  */
357 static inline u32 hw_read(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask)
358 {
359 	return ioread32(ci->hw_bank.regmap[reg]) & mask;
360 }
361 
362 #ifdef CONFIG_SOC_IMX28
363 static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
364 {
365 	__asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr));
366 }
367 #else
368 static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
369 {
370 }
371 #endif
372 
373 static inline void __hw_write(struct ci_hdrc *ci, u32 val,
374 		void __iomem *addr)
375 {
376 	if (ci->imx28_write_fix)
377 		imx28_ci_writel(val, addr);
378 	else
379 		iowrite32(val, addr);
380 }
381 
382 /**
383  * hw_write: writes to a hw register
384  * @ci: the controller
385  * @reg:  register index
386  * @mask: bitfield mask
387  * @data: new value
388  */
389 static inline void hw_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
390 			    u32 mask, u32 data)
391 {
392 	if (~mask)
393 		data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask)
394 			| (data & mask);
395 
396 	__hw_write(ci, data, ci->hw_bank.regmap[reg]);
397 }
398 
399 /**
400  * hw_test_and_clear: tests & clears a hw register
401  * @ci: the controller
402  * @reg:  register index
403  * @mask: bitfield mask
404  *
405  * This function returns register contents
406  */
407 static inline u32 hw_test_and_clear(struct ci_hdrc *ci, enum ci_hw_regs reg,
408 				    u32 mask)
409 {
410 	u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask;
411 
412 	__hw_write(ci, val, ci->hw_bank.regmap[reg]);
413 	return val;
414 }
415 
416 /**
417  * hw_test_and_write: tests & writes a hw register
418  * @ci: the controller
419  * @reg:  register index
420  * @mask: bitfield mask
421  * @data: new value
422  *
423  * This function returns register contents
424  */
425 static inline u32 hw_test_and_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
426 				    u32 mask, u32 data)
427 {
428 	u32 val = hw_read(ci, reg, ~0);
429 
430 	hw_write(ci, reg, mask, data);
431 	return (val & mask) >> __ffs(mask);
432 }
433 
434 /**
435  * ci_otg_is_fsm_mode: runtime check if otg controller
436  * is in otg fsm mode.
437  *
438  * @ci: chipidea device
439  */
440 static inline bool ci_otg_is_fsm_mode(struct ci_hdrc *ci)
441 {
442 #ifdef CONFIG_USB_OTG_FSM
443 	struct usb_otg_caps *otg_caps = &ci->platdata->ci_otg_caps;
444 
445 	return ci->is_otg && ci->roles[CI_ROLE_HOST] &&
446 		ci->roles[CI_ROLE_GADGET] && (otg_caps->srp_support ||
447 		otg_caps->hnp_support || otg_caps->adp_support);
448 #else
449 	return false;
450 #endif
451 }
452 
453 int ci_ulpi_init(struct ci_hdrc *ci);
454 void ci_ulpi_exit(struct ci_hdrc *ci);
455 int ci_ulpi_resume(struct ci_hdrc *ci);
456 
457 u32 hw_read_intr_enable(struct ci_hdrc *ci);
458 
459 u32 hw_read_intr_status(struct ci_hdrc *ci);
460 
461 int hw_device_reset(struct ci_hdrc *ci);
462 
463 int hw_port_test_set(struct ci_hdrc *ci, u8 mode);
464 
465 u8 hw_port_test_get(struct ci_hdrc *ci);
466 
467 void hw_phymode_configure(struct ci_hdrc *ci);
468 
469 void ci_platform_configure(struct ci_hdrc *ci);
470 
471 void dbg_create_files(struct ci_hdrc *ci);
472 
473 void dbg_remove_files(struct ci_hdrc *ci);
474 #endif	/* __DRIVERS_USB_CHIPIDEA_CI_H */
475