1// SPDX-License-Identifier: GPL-2.0 2 3#include <dt-bindings/clock/tegra234-clock.h> 4#include <dt-bindings/gpio/tegra234-gpio.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/mailbox/tegra186-hsp.h> 7#include <dt-bindings/memory/tegra234-mc.h> 8#include <dt-bindings/power/tegra234-powergate.h> 9#include <dt-bindings/reset/tegra234-reset.h> 10#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 11 12/ { 13 compatible = "nvidia,tegra234"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 bus@0 { 19 compatible = "simple-bus"; 20 #address-cells = <1>; 21 #size-cells = <1>; 22 23 ranges = <0x0 0x0 0x0 0x40000000>; 24 25 gpcdma: dma-controller@2600000 { 26 compatible = "nvidia,tegra234-gpcdma", 27 "nvidia,tegra186-gpcdma"; 28 reg = <0x2600000 0x210000>; 29 resets = <&bpmp TEGRA234_RESET_GPCDMA>; 30 reset-names = "gpcdma"; 31 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 34 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 35 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 36 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 37 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 41 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 42 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 43 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 44 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 45 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 46 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 47 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 48 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 49 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 50 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 51 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 52 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 53 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 54 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 55 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 56 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 57 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 58 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 59 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 61 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 62 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 63 #dma-cells = <1>; 64 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 65 dma-channel-mask = <0xfffffffe>; 66 dma-coherent; 67 }; 68 69 aconnect@2900000 { 70 compatible = "nvidia,tegra234-aconnect", 71 "nvidia,tegra210-aconnect"; 72 clocks = <&bpmp TEGRA234_CLK_APE>, 73 <&bpmp TEGRA234_CLK_APB2APE>; 74 clock-names = "ape", "apb2ape"; 75 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_AUD>; 76 #address-cells = <1>; 77 #size-cells = <1>; 78 ranges = <0x02900000 0x02900000 0x200000>; 79 status = "disabled"; 80 81 tegra_ahub: ahub@2900800 { 82 compatible = "nvidia,tegra234-ahub"; 83 reg = <0x02900800 0x800>; 84 clocks = <&bpmp TEGRA234_CLK_AHUB>; 85 clock-names = "ahub"; 86 assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>; 87 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 88 #address-cells = <1>; 89 #size-cells = <1>; 90 ranges = <0x02900800 0x02900800 0x11800>; 91 status = "disabled"; 92 93 tegra_i2s1: i2s@2901000 { 94 compatible = "nvidia,tegra234-i2s", 95 "nvidia,tegra210-i2s"; 96 reg = <0x2901000 0x100>; 97 clocks = <&bpmp TEGRA234_CLK_I2S1>, 98 <&bpmp TEGRA234_CLK_I2S1_SYNC_INPUT>; 99 clock-names = "i2s", "sync_input"; 100 assigned-clocks = <&bpmp TEGRA234_CLK_I2S1>; 101 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 102 assigned-clock-rates = <1536000>; 103 sound-name-prefix = "I2S1"; 104 status = "disabled"; 105 }; 106 107 tegra_i2s2: i2s@2901100 { 108 compatible = "nvidia,tegra234-i2s", 109 "nvidia,tegra210-i2s"; 110 reg = <0x2901100 0x100>; 111 clocks = <&bpmp TEGRA234_CLK_I2S2>, 112 <&bpmp TEGRA234_CLK_I2S2_SYNC_INPUT>; 113 clock-names = "i2s", "sync_input"; 114 assigned-clocks = <&bpmp TEGRA234_CLK_I2S2>; 115 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 116 assigned-clock-rates = <1536000>; 117 sound-name-prefix = "I2S2"; 118 status = "disabled"; 119 }; 120 121 tegra_i2s3: i2s@2901200 { 122 compatible = "nvidia,tegra234-i2s", 123 "nvidia,tegra210-i2s"; 124 reg = <0x2901200 0x100>; 125 clocks = <&bpmp TEGRA234_CLK_I2S3>, 126 <&bpmp TEGRA234_CLK_I2S3_SYNC_INPUT>; 127 clock-names = "i2s", "sync_input"; 128 assigned-clocks = <&bpmp TEGRA234_CLK_I2S3>; 129 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 130 assigned-clock-rates = <1536000>; 131 sound-name-prefix = "I2S3"; 132 status = "disabled"; 133 }; 134 135 tegra_i2s4: i2s@2901300 { 136 compatible = "nvidia,tegra234-i2s", 137 "nvidia,tegra210-i2s"; 138 reg = <0x2901300 0x100>; 139 clocks = <&bpmp TEGRA234_CLK_I2S4>, 140 <&bpmp TEGRA234_CLK_I2S4_SYNC_INPUT>; 141 clock-names = "i2s", "sync_input"; 142 assigned-clocks = <&bpmp TEGRA234_CLK_I2S4>; 143 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 144 assigned-clock-rates = <1536000>; 145 sound-name-prefix = "I2S4"; 146 status = "disabled"; 147 }; 148 149 tegra_i2s5: i2s@2901400 { 150 compatible = "nvidia,tegra234-i2s", 151 "nvidia,tegra210-i2s"; 152 reg = <0x2901400 0x100>; 153 clocks = <&bpmp TEGRA234_CLK_I2S5>, 154 <&bpmp TEGRA234_CLK_I2S5_SYNC_INPUT>; 155 clock-names = "i2s", "sync_input"; 156 assigned-clocks = <&bpmp TEGRA234_CLK_I2S5>; 157 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 158 assigned-clock-rates = <1536000>; 159 sound-name-prefix = "I2S5"; 160 status = "disabled"; 161 }; 162 163 tegra_i2s6: i2s@2901500 { 164 compatible = "nvidia,tegra234-i2s", 165 "nvidia,tegra210-i2s"; 166 reg = <0x2901500 0x100>; 167 clocks = <&bpmp TEGRA234_CLK_I2S6>, 168 <&bpmp TEGRA234_CLK_I2S6_SYNC_INPUT>; 169 clock-names = "i2s", "sync_input"; 170 assigned-clocks = <&bpmp TEGRA234_CLK_I2S6>; 171 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 172 assigned-clock-rates = <1536000>; 173 sound-name-prefix = "I2S6"; 174 status = "disabled"; 175 }; 176 177 tegra_sfc1: sfc@2902000 { 178 compatible = "nvidia,tegra234-sfc", 179 "nvidia,tegra210-sfc"; 180 reg = <0x2902000 0x200>; 181 sound-name-prefix = "SFC1"; 182 status = "disabled"; 183 }; 184 185 tegra_sfc2: sfc@2902200 { 186 compatible = "nvidia,tegra234-sfc", 187 "nvidia,tegra210-sfc"; 188 reg = <0x2902200 0x200>; 189 sound-name-prefix = "SFC2"; 190 status = "disabled"; 191 }; 192 193 tegra_sfc3: sfc@2902400 { 194 compatible = "nvidia,tegra234-sfc", 195 "nvidia,tegra210-sfc"; 196 reg = <0x2902400 0x200>; 197 sound-name-prefix = "SFC3"; 198 status = "disabled"; 199 }; 200 201 tegra_sfc4: sfc@2902600 { 202 compatible = "nvidia,tegra234-sfc", 203 "nvidia,tegra210-sfc"; 204 reg = <0x2902600 0x200>; 205 sound-name-prefix = "SFC4"; 206 status = "disabled"; 207 }; 208 209 tegra_amx1: amx@2903000 { 210 compatible = "nvidia,tegra234-amx", 211 "nvidia,tegra194-amx"; 212 reg = <0x2903000 0x100>; 213 sound-name-prefix = "AMX1"; 214 status = "disabled"; 215 }; 216 217 tegra_amx2: amx@2903100 { 218 compatible = "nvidia,tegra234-amx", 219 "nvidia,tegra194-amx"; 220 reg = <0x2903100 0x100>; 221 sound-name-prefix = "AMX2"; 222 status = "disabled"; 223 }; 224 225 tegra_amx3: amx@2903200 { 226 compatible = "nvidia,tegra234-amx", 227 "nvidia,tegra194-amx"; 228 reg = <0x2903200 0x100>; 229 sound-name-prefix = "AMX3"; 230 status = "disabled"; 231 }; 232 233 tegra_amx4: amx@2903300 { 234 compatible = "nvidia,tegra234-amx", 235 "nvidia,tegra194-amx"; 236 reg = <0x2903300 0x100>; 237 sound-name-prefix = "AMX4"; 238 status = "disabled"; 239 }; 240 241 tegra_adx1: adx@2903800 { 242 compatible = "nvidia,tegra234-adx", 243 "nvidia,tegra210-adx"; 244 reg = <0x2903800 0x100>; 245 sound-name-prefix = "ADX1"; 246 status = "disabled"; 247 }; 248 249 tegra_adx2: adx@2903900 { 250 compatible = "nvidia,tegra234-adx", 251 "nvidia,tegra210-adx"; 252 reg = <0x2903900 0x100>; 253 sound-name-prefix = "ADX2"; 254 status = "disabled"; 255 }; 256 257 tegra_adx3: adx@2903a00 { 258 compatible = "nvidia,tegra234-adx", 259 "nvidia,tegra210-adx"; 260 reg = <0x2903a00 0x100>; 261 sound-name-prefix = "ADX3"; 262 status = "disabled"; 263 }; 264 265 tegra_adx4: adx@2903b00 { 266 compatible = "nvidia,tegra234-adx", 267 "nvidia,tegra210-adx"; 268 reg = <0x2903b00 0x100>; 269 sound-name-prefix = "ADX4"; 270 status = "disabled"; 271 }; 272 273 274 tegra_dmic1: dmic@2904000 { 275 compatible = "nvidia,tegra234-dmic", 276 "nvidia,tegra210-dmic"; 277 reg = <0x2904000 0x100>; 278 clocks = <&bpmp TEGRA234_CLK_DMIC1>; 279 clock-names = "dmic"; 280 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC1>; 281 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 282 assigned-clock-rates = <3072000>; 283 sound-name-prefix = "DMIC1"; 284 status = "disabled"; 285 }; 286 287 tegra_dmic2: dmic@2904100 { 288 compatible = "nvidia,tegra234-dmic", 289 "nvidia,tegra210-dmic"; 290 reg = <0x2904100 0x100>; 291 clocks = <&bpmp TEGRA234_CLK_DMIC2>; 292 clock-names = "dmic"; 293 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC2>; 294 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 295 assigned-clock-rates = <3072000>; 296 sound-name-prefix = "DMIC2"; 297 status = "disabled"; 298 }; 299 300 tegra_dmic3: dmic@2904200 { 301 compatible = "nvidia,tegra234-dmic", 302 "nvidia,tegra210-dmic"; 303 reg = <0x2904200 0x100>; 304 clocks = <&bpmp TEGRA234_CLK_DMIC3>; 305 clock-names = "dmic"; 306 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC3>; 307 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 308 assigned-clock-rates = <3072000>; 309 sound-name-prefix = "DMIC3"; 310 status = "disabled"; 311 }; 312 313 tegra_dmic4: dmic@2904300 { 314 compatible = "nvidia,tegra234-dmic", 315 "nvidia,tegra210-dmic"; 316 reg = <0x2904300 0x100>; 317 clocks = <&bpmp TEGRA234_CLK_DMIC4>; 318 clock-names = "dmic"; 319 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC4>; 320 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 321 assigned-clock-rates = <3072000>; 322 sound-name-prefix = "DMIC4"; 323 status = "disabled"; 324 }; 325 326 tegra_dspk1: dspk@2905000 { 327 compatible = "nvidia,tegra234-dspk", 328 "nvidia,tegra186-dspk"; 329 reg = <0x2905000 0x100>; 330 clocks = <&bpmp TEGRA234_CLK_DSPK1>; 331 clock-names = "dspk"; 332 assigned-clocks = <&bpmp TEGRA234_CLK_DSPK1>; 333 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 334 assigned-clock-rates = <12288000>; 335 sound-name-prefix = "DSPK1"; 336 status = "disabled"; 337 }; 338 339 tegra_dspk2: dspk@2905100 { 340 compatible = "nvidia,tegra234-dspk", 341 "nvidia,tegra186-dspk"; 342 reg = <0x2905100 0x100>; 343 clocks = <&bpmp TEGRA234_CLK_DSPK2>; 344 clock-names = "dspk"; 345 assigned-clocks = <&bpmp TEGRA234_CLK_DSPK2>; 346 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 347 assigned-clock-rates = <12288000>; 348 sound-name-prefix = "DSPK2"; 349 status = "disabled"; 350 }; 351 352 tegra_ope1: processing-engine@2908000 { 353 compatible = "nvidia,tegra234-ope", 354 "nvidia,tegra210-ope"; 355 reg = <0x2908000 0x100>; 356 #address-cells = <1>; 357 #size-cells = <1>; 358 ranges; 359 sound-name-prefix = "OPE1"; 360 status = "disabled"; 361 362 equalizer@2908100 { 363 compatible = "nvidia,tegra234-peq", 364 "nvidia,tegra210-peq"; 365 reg = <0x2908100 0x100>; 366 }; 367 368 dynamic-range-compressor@2908200 { 369 compatible = "nvidia,tegra234-mbdrc", 370 "nvidia,tegra210-mbdrc"; 371 reg = <0x2908200 0x200>; 372 }; 373 }; 374 375 tegra_mvc1: mvc@290a000 { 376 compatible = "nvidia,tegra234-mvc", 377 "nvidia,tegra210-mvc"; 378 reg = <0x290a000 0x200>; 379 sound-name-prefix = "MVC1"; 380 status = "disabled"; 381 }; 382 383 tegra_mvc2: mvc@290a200 { 384 compatible = "nvidia,tegra234-mvc", 385 "nvidia,tegra210-mvc"; 386 reg = <0x290a200 0x200>; 387 sound-name-prefix = "MVC2"; 388 status = "disabled"; 389 }; 390 391 tegra_amixer: amixer@290bb00 { 392 compatible = "nvidia,tegra234-amixer", 393 "nvidia,tegra210-amixer"; 394 reg = <0x290bb00 0x800>; 395 sound-name-prefix = "MIXER1"; 396 status = "disabled"; 397 }; 398 399 tegra_admaif: admaif@290f000 { 400 compatible = "nvidia,tegra234-admaif", 401 "nvidia,tegra186-admaif"; 402 reg = <0x0290f000 0x1000>; 403 dmas = <&adma 1>, <&adma 1>, 404 <&adma 2>, <&adma 2>, 405 <&adma 3>, <&adma 3>, 406 <&adma 4>, <&adma 4>, 407 <&adma 5>, <&adma 5>, 408 <&adma 6>, <&adma 6>, 409 <&adma 7>, <&adma 7>, 410 <&adma 8>, <&adma 8>, 411 <&adma 9>, <&adma 9>, 412 <&adma 10>, <&adma 10>, 413 <&adma 11>, <&adma 11>, 414 <&adma 12>, <&adma 12>, 415 <&adma 13>, <&adma 13>, 416 <&adma 14>, <&adma 14>, 417 <&adma 15>, <&adma 15>, 418 <&adma 16>, <&adma 16>, 419 <&adma 17>, <&adma 17>, 420 <&adma 18>, <&adma 18>, 421 <&adma 19>, <&adma 19>, 422 <&adma 20>, <&adma 20>; 423 dma-names = "rx1", "tx1", 424 "rx2", "tx2", 425 "rx3", "tx3", 426 "rx4", "tx4", 427 "rx5", "tx5", 428 "rx6", "tx6", 429 "rx7", "tx7", 430 "rx8", "tx8", 431 "rx9", "tx9", 432 "rx10", "tx10", 433 "rx11", "tx11", 434 "rx12", "tx12", 435 "rx13", "tx13", 436 "rx14", "tx14", 437 "rx15", "tx15", 438 "rx16", "tx16", 439 "rx17", "tx17", 440 "rx18", "tx18", 441 "rx19", "tx19", 442 "rx20", "tx20"; 443 interconnects = <&mc TEGRA234_MEMORY_CLIENT_APEDMAR &emc>, 444 <&mc TEGRA234_MEMORY_CLIENT_APEDMAW &emc>; 445 interconnect-names = "dma-mem", "write"; 446 iommus = <&smmu_niso0 TEGRA234_SID_APE>; 447 status = "disabled"; 448 }; 449 450 tegra_asrc: asrc@2910000 { 451 compatible = "nvidia,tegra234-asrc", 452 "nvidia,tegra186-asrc"; 453 reg = <0x2910000 0x2000>; 454 sound-name-prefix = "ASRC1"; 455 status = "disabled"; 456 }; 457 }; 458 459 adma: dma-controller@2930000 { 460 compatible = "nvidia,tegra234-adma", 461 "nvidia,tegra186-adma"; 462 reg = <0x02930000 0x20000>; 463 interrupt-parent = <&agic>; 464 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 465 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 466 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 467 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 468 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 469 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 470 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 471 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 472 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 473 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 474 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 475 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 476 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 477 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 478 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 479 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 480 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 481 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 482 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 483 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 484 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 485 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 486 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 487 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 488 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 489 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 490 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 491 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 492 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 493 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 494 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 495 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 496 #dma-cells = <1>; 497 clocks = <&bpmp TEGRA234_CLK_AHUB>; 498 clock-names = "d_audio"; 499 status = "disabled"; 500 }; 501 502 agic: interrupt-controller@2a40000 { 503 compatible = "nvidia,tegra234-agic", 504 "nvidia,tegra210-agic"; 505 #interrupt-cells = <3>; 506 interrupt-controller; 507 reg = <0x02a41000 0x1000>, 508 <0x02a42000 0x2000>; 509 interrupts = <GIC_SPI 145 510 (GIC_CPU_MASK_SIMPLE(4) | 511 IRQ_TYPE_LEVEL_HIGH)>; 512 clocks = <&bpmp TEGRA234_CLK_APE>; 513 clock-names = "clk"; 514 status = "disabled"; 515 }; 516 }; 517 518 misc@100000 { 519 compatible = "nvidia,tegra234-misc"; 520 reg = <0x00100000 0xf000>, 521 <0x0010f000 0x1000>; 522 status = "okay"; 523 }; 524 525 timer@2080000 { 526 compatible = "nvidia,tegra234-timer"; 527 reg = <0x02080000 0x00121000>; 528 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 533 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 534 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 535 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 536 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 537 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 538 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 539 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 540 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 541 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 542 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 543 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 544 status = "okay"; 545 }; 546 547 host1x@13e00000 { 548 compatible = "nvidia,tegra234-host1x"; 549 reg = <0x13e00000 0x10000>, 550 <0x13e10000 0x10000>, 551 <0x13e40000 0x10000>; 552 reg-names = "common", "hypervisor", "vm"; 553 interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 554 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 555 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 556 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 557 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 558 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 559 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, 560 <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 562 interrupt-names = "syncpt0", "syncpt1", "syncpt2", "syncpt3", "syncpt4", 563 "syncpt5", "syncpt6", "syncpt7", "host1x"; 564 clocks = <&bpmp TEGRA234_CLK_HOST1X>; 565 clock-names = "host1x"; 566 567 #address-cells = <1>; 568 #size-cells = <1>; 569 570 ranges = <0x14800000 0x14800000 0x02000000>; 571 interconnects = <&mc TEGRA234_MEMORY_CLIENT_HOST1XDMAR &emc>; 572 interconnect-names = "dma-mem"; 573 iommus = <&smmu_niso1 TEGRA234_SID_HOST1X>; 574 575 /* Context isolation domains */ 576 iommu-map = <0 &smmu_niso0 TEGRA234_SID_HOST1X_CTX0 1>, 577 <1 &smmu_niso0 TEGRA234_SID_HOST1X_CTX1 1>, 578 <2 &smmu_niso0 TEGRA234_SID_HOST1X_CTX2 1>, 579 <3 &smmu_niso0 TEGRA234_SID_HOST1X_CTX3 1>, 580 <4 &smmu_niso0 TEGRA234_SID_HOST1X_CTX4 1>, 581 <5 &smmu_niso0 TEGRA234_SID_HOST1X_CTX5 1>, 582 <6 &smmu_niso0 TEGRA234_SID_HOST1X_CTX6 1>, 583 <7 &smmu_niso0 TEGRA234_SID_HOST1X_CTX7 1>, 584 <8 &smmu_niso1 TEGRA234_SID_HOST1X_CTX0 1>, 585 <9 &smmu_niso1 TEGRA234_SID_HOST1X_CTX1 1>, 586 <10 &smmu_niso1 TEGRA234_SID_HOST1X_CTX2 1>, 587 <11 &smmu_niso1 TEGRA234_SID_HOST1X_CTX3 1>, 588 <12 &smmu_niso1 TEGRA234_SID_HOST1X_CTX4 1>, 589 <13 &smmu_niso1 TEGRA234_SID_HOST1X_CTX5 1>, 590 <14 &smmu_niso1 TEGRA234_SID_HOST1X_CTX6 1>, 591 <15 &smmu_niso1 TEGRA234_SID_HOST1X_CTX7 1>; 592 593 vic@15340000 { 594 compatible = "nvidia,tegra234-vic"; 595 reg = <0x15340000 0x00040000>; 596 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 597 clocks = <&bpmp TEGRA234_CLK_VIC>; 598 clock-names = "vic"; 599 resets = <&bpmp TEGRA234_RESET_VIC>; 600 reset-names = "vic"; 601 602 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_VIC>; 603 interconnects = <&mc TEGRA234_MEMORY_CLIENT_VICSRD &emc>, 604 <&mc TEGRA234_MEMORY_CLIENT_VICSWR &emc>; 605 interconnect-names = "dma-mem", "write"; 606 iommus = <&smmu_niso1 TEGRA234_SID_VIC>; 607 dma-coherent; 608 }; 609 610 nvdec@15480000 { 611 compatible = "nvidia,tegra234-nvdec"; 612 reg = <0x15480000 0x00040000>; 613 clocks = <&bpmp TEGRA234_CLK_NVDEC>, 614 <&bpmp TEGRA234_CLK_FUSE>, 615 <&bpmp TEGRA234_CLK_TSEC_PKA>; 616 clock-names = "nvdec", "fuse", "tsec_pka"; 617 resets = <&bpmp TEGRA234_RESET_NVDEC>; 618 reset-names = "nvdec"; 619 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>; 620 interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDECSRD &emc>, 621 <&mc TEGRA234_MEMORY_CLIENT_NVDECSWR &emc>; 622 interconnect-names = "dma-mem", "write"; 623 iommus = <&smmu_niso1 TEGRA234_SID_NVDEC>; 624 dma-coherent; 625 626 nvidia,memory-controller = <&mc>; 627 628 /* 629 * Placeholder values that firmware needs to update with the real 630 * offsets parsed from the microcode headers. 631 */ 632 nvidia,bl-manifest-offset = <0>; 633 nvidia,bl-data-offset = <0>; 634 nvidia,bl-code-offset = <0>; 635 nvidia,os-manifest-offset = <0>; 636 nvidia,os-data-offset = <0>; 637 nvidia,os-code-offset = <0>; 638 639 /* 640 * Firmware needs to set this to "okay" once the above values have 641 * been updated. 642 */ 643 status = "disabled"; 644 }; 645 }; 646 647 gpio: gpio@2200000 { 648 compatible = "nvidia,tegra234-gpio"; 649 reg-names = "security", "gpio"; 650 reg = <0x02200000 0x10000>, 651 <0x02210000 0x10000>; 652 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 653 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 654 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 655 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 656 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 657 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 658 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 659 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 660 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 661 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 662 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 663 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 664 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 665 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 666 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 667 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 668 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 669 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 670 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 671 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 672 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 673 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 674 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 675 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 676 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 677 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 678 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 679 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 680 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 681 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 682 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 683 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 684 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 685 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 686 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 687 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 688 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 689 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 690 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 691 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 692 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 693 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 694 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 695 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 696 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 697 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 698 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 699 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 700 #interrupt-cells = <2>; 701 interrupt-controller; 702 #gpio-cells = <2>; 703 gpio-controller; 704 }; 705 706 mc: memory-controller@2c00000 { 707 compatible = "nvidia,tegra234-mc"; 708 reg = <0x02c00000 0x10000>, /* MC-SID */ 709 <0x02c10000 0x10000>, /* MC Broadcast*/ 710 <0x02c20000 0x10000>, /* MC0 */ 711 <0x02c30000 0x10000>, /* MC1 */ 712 <0x02c40000 0x10000>, /* MC2 */ 713 <0x02c50000 0x10000>, /* MC3 */ 714 <0x02b80000 0x10000>, /* MC4 */ 715 <0x02b90000 0x10000>, /* MC5 */ 716 <0x02ba0000 0x10000>, /* MC6 */ 717 <0x02bb0000 0x10000>, /* MC7 */ 718 <0x01700000 0x10000>, /* MC8 */ 719 <0x01710000 0x10000>, /* MC9 */ 720 <0x01720000 0x10000>, /* MC10 */ 721 <0x01730000 0x10000>, /* MC11 */ 722 <0x01740000 0x10000>, /* MC12 */ 723 <0x01750000 0x10000>, /* MC13 */ 724 <0x01760000 0x10000>, /* MC14 */ 725 <0x01770000 0x10000>; /* MC15 */ 726 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", 727 "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", 728 "ch11", "ch12", "ch13", "ch14", "ch15"; 729 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 730 #interconnect-cells = <1>; 731 status = "okay"; 732 733 #address-cells = <2>; 734 #size-cells = <2>; 735 736 ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 737 <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 738 <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 739 740 /* 741 * Bit 39 of addresses passing through the memory 742 * controller selects the XBAR format used when memory 743 * is accessed. This is used to transparently access 744 * memory in the XBAR format used by the discrete GPU 745 * (bit 39 set) or Tegra (bit 39 clear). 746 * 747 * As a consequence, the operating system must ensure 748 * that bit 39 is never used implicitly, for example 749 * via an I/O virtual address mapping of an IOMMU. If 750 * devices require access to the XBAR switch, their 751 * drivers must set this bit explicitly. 752 * 753 * Limit the DMA range for memory clients to [38:0]. 754 */ 755 dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 756 757 emc: external-memory-controller@2c60000 { 758 compatible = "nvidia,tegra234-emc"; 759 reg = <0x0 0x02c60000 0x0 0x90000>, 760 <0x0 0x01780000 0x0 0x80000>; 761 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 762 clocks = <&bpmp TEGRA234_CLK_EMC>; 763 clock-names = "emc"; 764 status = "okay"; 765 766 #interconnect-cells = <0>; 767 768 nvidia,bpmp = <&bpmp>; 769 }; 770 }; 771 772 uarta: serial@3100000 { 773 compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart"; 774 reg = <0x03100000 0x10000>; 775 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 776 clocks = <&bpmp TEGRA234_CLK_UARTA>; 777 clock-names = "serial"; 778 resets = <&bpmp TEGRA234_RESET_UARTA>; 779 reset-names = "serial"; 780 status = "disabled"; 781 }; 782 783 gen1_i2c: i2c@3160000 { 784 compatible = "nvidia,tegra194-i2c"; 785 reg = <0x3160000 0x100>; 786 status = "disabled"; 787 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 788 clock-frequency = <400000>; 789 clocks = <&bpmp TEGRA234_CLK_I2C1 790 &bpmp TEGRA234_CLK_PLLP_OUT0>; 791 assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>; 792 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 793 clock-names = "div-clk", "parent"; 794 resets = <&bpmp TEGRA234_RESET_I2C1>; 795 reset-names = "i2c"; 796 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 797 dma-coherent; 798 dmas = <&gpcdma 21>, <&gpcdma 21>; 799 dma-names = "rx", "tx"; 800 }; 801 802 cam_i2c: i2c@3180000 { 803 compatible = "nvidia,tegra194-i2c"; 804 reg = <0x3180000 0x100>; 805 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 806 status = "disabled"; 807 clock-frequency = <400000>; 808 clocks = <&bpmp TEGRA234_CLK_I2C3 809 &bpmp TEGRA234_CLK_PLLP_OUT0>; 810 assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>; 811 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 812 clock-names = "div-clk", "parent"; 813 resets = <&bpmp TEGRA234_RESET_I2C3>; 814 reset-names = "i2c"; 815 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 816 dma-coherent; 817 dmas = <&gpcdma 23>, <&gpcdma 23>; 818 dma-names = "rx", "tx"; 819 }; 820 821 dp_aux_ch1_i2c: i2c@3190000 { 822 compatible = "nvidia,tegra194-i2c"; 823 reg = <0x3190000 0x100>; 824 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 825 status = "disabled"; 826 clock-frequency = <100000>; 827 clocks = <&bpmp TEGRA234_CLK_I2C4 828 &bpmp TEGRA234_CLK_PLLP_OUT0>; 829 assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>; 830 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 831 clock-names = "div-clk", "parent"; 832 resets = <&bpmp TEGRA234_RESET_I2C4>; 833 reset-names = "i2c"; 834 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 835 dma-coherent; 836 dmas = <&gpcdma 26>, <&gpcdma 26>; 837 dma-names = "rx", "tx"; 838 }; 839 840 dp_aux_ch0_i2c: i2c@31b0000 { 841 compatible = "nvidia,tegra194-i2c"; 842 reg = <0x31b0000 0x100>; 843 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 844 status = "disabled"; 845 clock-frequency = <100000>; 846 clocks = <&bpmp TEGRA234_CLK_I2C6 847 &bpmp TEGRA234_CLK_PLLP_OUT0>; 848 assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>; 849 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 850 clock-names = "div-clk", "parent"; 851 resets = <&bpmp TEGRA234_RESET_I2C6>; 852 reset-names = "i2c"; 853 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 854 dma-coherent; 855 dmas = <&gpcdma 30>, <&gpcdma 30>; 856 dma-names = "rx", "tx"; 857 }; 858 859 dp_aux_ch2_i2c: i2c@31c0000 { 860 compatible = "nvidia,tegra194-i2c"; 861 reg = <0x31c0000 0x100>; 862 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 863 status = "disabled"; 864 clock-frequency = <100000>; 865 clocks = <&bpmp TEGRA234_CLK_I2C7 866 &bpmp TEGRA234_CLK_PLLP_OUT0>; 867 assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>; 868 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 869 clock-names = "div-clk", "parent"; 870 resets = <&bpmp TEGRA234_RESET_I2C7>; 871 reset-names = "i2c"; 872 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 873 dma-coherent; 874 dmas = <&gpcdma 27>, <&gpcdma 27>; 875 dma-names = "rx", "tx"; 876 }; 877 878 uarti: serial@31d0000 { 879 compatible = "arm,sbsa-uart"; 880 reg = <0x31d0000 0x10000>; 881 interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; 882 status = "disabled"; 883 }; 884 885 dp_aux_ch3_i2c: i2c@31e0000 { 886 compatible = "nvidia,tegra194-i2c"; 887 reg = <0x31e0000 0x100>; 888 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 889 status = "disabled"; 890 clock-frequency = <100000>; 891 clocks = <&bpmp TEGRA234_CLK_I2C9 892 &bpmp TEGRA234_CLK_PLLP_OUT0>; 893 assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>; 894 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 895 clock-names = "div-clk", "parent"; 896 resets = <&bpmp TEGRA234_RESET_I2C9>; 897 reset-names = "i2c"; 898 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 899 dma-coherent; 900 dmas = <&gpcdma 31>, <&gpcdma 31>; 901 dma-names = "rx", "tx"; 902 }; 903 904 spi@3270000 { 905 compatible = "nvidia,tegra234-qspi"; 906 reg = <0x3270000 0x1000>; 907 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 908 #address-cells = <1>; 909 #size-cells = <0>; 910 clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>, 911 <&bpmp TEGRA234_CLK_QSPI0_PM>; 912 clock-names = "qspi", "qspi_out"; 913 resets = <&bpmp TEGRA234_RESET_QSPI0>; 914 reset-names = "qspi"; 915 status = "disabled"; 916 }; 917 918 pwm1: pwm@3280000 { 919 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 920 reg = <0x3280000 0x10000>; 921 clocks = <&bpmp TEGRA234_CLK_PWM1>; 922 resets = <&bpmp TEGRA234_RESET_PWM1>; 923 reset-names = "pwm"; 924 status = "disabled"; 925 #pwm-cells = <2>; 926 }; 927 928 pwm2: pwm@3290000 { 929 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 930 reg = <0x3290000 0x10000>; 931 clocks = <&bpmp TEGRA234_CLK_PWM2>; 932 resets = <&bpmp TEGRA234_RESET_PWM2>; 933 reset-names = "pwm"; 934 status = "disabled"; 935 #pwm-cells = <2>; 936 }; 937 938 pwm3: pwm@32a0000 { 939 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 940 reg = <0x32a0000 0x10000>; 941 clocks = <&bpmp TEGRA234_CLK_PWM3>; 942 resets = <&bpmp TEGRA234_RESET_PWM3>; 943 reset-names = "pwm"; 944 status = "disabled"; 945 #pwm-cells = <2>; 946 }; 947 948 pwm5: pwm@32c0000 { 949 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 950 reg = <0x32c0000 0x10000>; 951 clocks = <&bpmp TEGRA234_CLK_PWM5>; 952 resets = <&bpmp TEGRA234_RESET_PWM5>; 953 reset-names = "pwm"; 954 status = "disabled"; 955 #pwm-cells = <2>; 956 }; 957 958 pwm6: pwm@32d0000 { 959 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 960 reg = <0x32d0000 0x10000>; 961 clocks = <&bpmp TEGRA234_CLK_PWM6>; 962 resets = <&bpmp TEGRA234_RESET_PWM6>; 963 reset-names = "pwm"; 964 status = "disabled"; 965 #pwm-cells = <2>; 966 }; 967 968 pwm7: pwm@32e0000 { 969 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 970 reg = <0x32e0000 0x10000>; 971 clocks = <&bpmp TEGRA234_CLK_PWM7>; 972 resets = <&bpmp TEGRA234_RESET_PWM7>; 973 reset-names = "pwm"; 974 status = "disabled"; 975 #pwm-cells = <2>; 976 }; 977 978 pwm8: pwm@32f0000 { 979 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 980 reg = <0x32f0000 0x10000>; 981 clocks = <&bpmp TEGRA234_CLK_PWM8>; 982 resets = <&bpmp TEGRA234_RESET_PWM8>; 983 reset-names = "pwm"; 984 status = "disabled"; 985 #pwm-cells = <2>; 986 }; 987 988 spi@3300000 { 989 compatible = "nvidia,tegra234-qspi"; 990 reg = <0x3300000 0x1000>; 991 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 992 #address-cells = <1>; 993 #size-cells = <0>; 994 clocks = <&bpmp TEGRA234_CLK_QSPI1_2X_PM>, 995 <&bpmp TEGRA234_CLK_QSPI1_PM>; 996 clock-names = "qspi", "qspi_out"; 997 resets = <&bpmp TEGRA234_RESET_QSPI1>; 998 reset-names = "qspi"; 999 status = "disabled"; 1000 }; 1001 1002 mmc@3400000 { 1003 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra234-sdhci"; 1004 reg = <0x03400000 0x20000>; 1005 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1006 clocks = <&bpmp TEGRA234_CLK_SDMMC1>, 1007 <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; 1008 clock-names = "sdhci", "tmclk"; 1009 assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC1>, 1010 <&bpmp TEGRA234_CLK_PLLC4_MUXED>; 1011 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4_MUXED>, 1012 <&bpmp TEGRA234_CLK_PLLC4_VCO_DIV2>; 1013 resets = <&bpmp TEGRA234_RESET_SDMMC1>; 1014 reset-names = "sdhci"; 1015 interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRA &emc>, 1016 <&mc TEGRA234_MEMORY_CLIENT_SDMMCWA &emc>; 1017 interconnect-names = "dma-mem", "write"; 1018 iommus = <&smmu_niso1 TEGRA234_SID_SDMMC1A>; 1019 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 1020 pinctrl-0 = <&sdmmc1_3v3>; 1021 pinctrl-1 = <&sdmmc1_1v8>; 1022 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 1023 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x07>; 1024 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 1025 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 1026 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 1027 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 1028 nvidia,default-tap = <14>; 1029 nvidia,default-trim = <0x8>; 1030 sd-uhs-sdr25; 1031 sd-uhs-sdr50; 1032 sd-uhs-ddr50; 1033 sd-uhs-sdr104; 1034 status = "disabled"; 1035 }; 1036 1037 mmc@3460000 { 1038 compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; 1039 reg = <0x03460000 0x20000>; 1040 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 1041 clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 1042 <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; 1043 clock-names = "sdhci", "tmclk"; 1044 assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 1045 <&bpmp TEGRA234_CLK_PLLC4>; 1046 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>; 1047 resets = <&bpmp TEGRA234_RESET_SDMMC4>; 1048 reset-names = "sdhci"; 1049 interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRAB &emc>, 1050 <&mc TEGRA234_MEMORY_CLIENT_SDMMCWAB &emc>; 1051 interconnect-names = "dma-mem", "write"; 1052 iommus = <&smmu_niso1 TEGRA234_SID_SDMMC4>; 1053 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 1054 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 1055 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 1056 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 1057 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 1058 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 1059 nvidia,default-tap = <0x8>; 1060 nvidia,default-trim = <0x14>; 1061 nvidia,dqs-trim = <40>; 1062 supports-cqe; 1063 status = "disabled"; 1064 }; 1065 1066 hda@3510000 { 1067 compatible = "nvidia,tegra234-hda", "nvidia,tegra30-hda"; 1068 reg = <0x3510000 0x10000>; 1069 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 1070 clocks = <&bpmp TEGRA234_CLK_AZA_BIT>, 1071 <&bpmp TEGRA234_CLK_AZA_2XBIT>; 1072 clock-names = "hda", "hda2codec_2x"; 1073 resets = <&bpmp TEGRA234_RESET_HDA>, 1074 <&bpmp TEGRA234_RESET_HDACODEC>; 1075 reset-names = "hda", "hda2codec_2x"; 1076 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DISP>; 1077 interconnects = <&mc TEGRA234_MEMORY_CLIENT_HDAR &emc>, 1078 <&mc TEGRA234_MEMORY_CLIENT_HDAW &emc>; 1079 interconnect-names = "dma-mem", "write"; 1080 iommus = <&smmu_niso0 TEGRA234_SID_HDA>; 1081 status = "disabled"; 1082 }; 1083 1084 fuse@3810000 { 1085 compatible = "nvidia,tegra234-efuse"; 1086 reg = <0x03810000 0x10000>; 1087 clocks = <&bpmp TEGRA234_CLK_FUSE>; 1088 clock-names = "fuse"; 1089 }; 1090 1091 hsp_top0: hsp@3c00000 { 1092 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 1093 reg = <0x03c00000 0xa0000>; 1094 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1095 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1096 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1097 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1098 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1099 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1100 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1101 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1102 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1103 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 1104 "shared3", "shared4", "shared5", "shared6", 1105 "shared7"; 1106 #mbox-cells = <2>; 1107 }; 1108 1109 p2u_hsio_0: phy@3e00000 { 1110 compatible = "nvidia,tegra234-p2u"; 1111 reg = <0x03e00000 0x10000>; 1112 reg-names = "ctl"; 1113 1114 #phy-cells = <0>; 1115 }; 1116 1117 p2u_hsio_1: phy@3e10000 { 1118 compatible = "nvidia,tegra234-p2u"; 1119 reg = <0x03e10000 0x10000>; 1120 reg-names = "ctl"; 1121 1122 #phy-cells = <0>; 1123 }; 1124 1125 p2u_hsio_2: phy@3e20000 { 1126 compatible = "nvidia,tegra234-p2u"; 1127 reg = <0x03e20000 0x10000>; 1128 reg-names = "ctl"; 1129 1130 #phy-cells = <0>; 1131 }; 1132 1133 p2u_hsio_3: phy@3e30000 { 1134 compatible = "nvidia,tegra234-p2u"; 1135 reg = <0x03e30000 0x10000>; 1136 reg-names = "ctl"; 1137 1138 #phy-cells = <0>; 1139 }; 1140 1141 p2u_hsio_4: phy@3e40000 { 1142 compatible = "nvidia,tegra234-p2u"; 1143 reg = <0x03e40000 0x10000>; 1144 reg-names = "ctl"; 1145 1146 #phy-cells = <0>; 1147 }; 1148 1149 p2u_hsio_5: phy@3e50000 { 1150 compatible = "nvidia,tegra234-p2u"; 1151 reg = <0x03e50000 0x10000>; 1152 reg-names = "ctl"; 1153 1154 #phy-cells = <0>; 1155 }; 1156 1157 p2u_hsio_6: phy@3e60000 { 1158 compatible = "nvidia,tegra234-p2u"; 1159 reg = <0x03e60000 0x10000>; 1160 reg-names = "ctl"; 1161 1162 #phy-cells = <0>; 1163 }; 1164 1165 p2u_hsio_7: phy@3e70000 { 1166 compatible = "nvidia,tegra234-p2u"; 1167 reg = <0x03e70000 0x10000>; 1168 reg-names = "ctl"; 1169 1170 #phy-cells = <0>; 1171 }; 1172 1173 p2u_nvhs_0: phy@3e90000 { 1174 compatible = "nvidia,tegra234-p2u"; 1175 reg = <0x03e90000 0x10000>; 1176 reg-names = "ctl"; 1177 1178 #phy-cells = <0>; 1179 }; 1180 1181 p2u_nvhs_1: phy@3ea0000 { 1182 compatible = "nvidia,tegra234-p2u"; 1183 reg = <0x03ea0000 0x10000>; 1184 reg-names = "ctl"; 1185 1186 #phy-cells = <0>; 1187 }; 1188 1189 p2u_nvhs_2: phy@3eb0000 { 1190 compatible = "nvidia,tegra234-p2u"; 1191 reg = <0x03eb0000 0x10000>; 1192 reg-names = "ctl"; 1193 1194 #phy-cells = <0>; 1195 }; 1196 1197 p2u_nvhs_3: phy@3ec0000 { 1198 compatible = "nvidia,tegra234-p2u"; 1199 reg = <0x03ec0000 0x10000>; 1200 reg-names = "ctl"; 1201 1202 #phy-cells = <0>; 1203 }; 1204 1205 p2u_nvhs_4: phy@3ed0000 { 1206 compatible = "nvidia,tegra234-p2u"; 1207 reg = <0x03ed0000 0x10000>; 1208 reg-names = "ctl"; 1209 1210 #phy-cells = <0>; 1211 }; 1212 1213 p2u_nvhs_5: phy@3ee0000 { 1214 compatible = "nvidia,tegra234-p2u"; 1215 reg = <0x03ee0000 0x10000>; 1216 reg-names = "ctl"; 1217 1218 #phy-cells = <0>; 1219 }; 1220 1221 p2u_nvhs_6: phy@3ef0000 { 1222 compatible = "nvidia,tegra234-p2u"; 1223 reg = <0x03ef0000 0x10000>; 1224 reg-names = "ctl"; 1225 1226 #phy-cells = <0>; 1227 }; 1228 1229 p2u_nvhs_7: phy@3f00000 { 1230 compatible = "nvidia,tegra234-p2u"; 1231 reg = <0x03f00000 0x10000>; 1232 reg-names = "ctl"; 1233 1234 #phy-cells = <0>; 1235 }; 1236 1237 p2u_gbe_0: phy@3f20000 { 1238 compatible = "nvidia,tegra234-p2u"; 1239 reg = <0x03f20000 0x10000>; 1240 reg-names = "ctl"; 1241 1242 #phy-cells = <0>; 1243 }; 1244 1245 p2u_gbe_1: phy@3f30000 { 1246 compatible = "nvidia,tegra234-p2u"; 1247 reg = <0x03f30000 0x10000>; 1248 reg-names = "ctl"; 1249 1250 #phy-cells = <0>; 1251 }; 1252 1253 p2u_gbe_2: phy@3f40000 { 1254 compatible = "nvidia,tegra234-p2u"; 1255 reg = <0x03f40000 0x10000>; 1256 reg-names = "ctl"; 1257 1258 #phy-cells = <0>; 1259 }; 1260 1261 p2u_gbe_3: phy@3f50000 { 1262 compatible = "nvidia,tegra234-p2u"; 1263 reg = <0x03f50000 0x10000>; 1264 reg-names = "ctl"; 1265 1266 #phy-cells = <0>; 1267 }; 1268 1269 p2u_gbe_4: phy@3f60000 { 1270 compatible = "nvidia,tegra234-p2u"; 1271 reg = <0x03f60000 0x10000>; 1272 reg-names = "ctl"; 1273 1274 #phy-cells = <0>; 1275 }; 1276 1277 p2u_gbe_5: phy@3f70000 { 1278 compatible = "nvidia,tegra234-p2u"; 1279 reg = <0x03f70000 0x10000>; 1280 reg-names = "ctl"; 1281 1282 #phy-cells = <0>; 1283 }; 1284 1285 p2u_gbe_6: phy@3f80000 { 1286 compatible = "nvidia,tegra234-p2u"; 1287 reg = <0x03f80000 0x10000>; 1288 reg-names = "ctl"; 1289 1290 #phy-cells = <0>; 1291 }; 1292 1293 p2u_gbe_7: phy@3f90000 { 1294 compatible = "nvidia,tegra234-p2u"; 1295 reg = <0x03f90000 0x10000>; 1296 reg-names = "ctl"; 1297 1298 #phy-cells = <0>; 1299 }; 1300 1301 ethernet@6800000 { 1302 compatible = "nvidia,tegra234-mgbe"; 1303 reg = <0x06800000 0x10000>, 1304 <0x06810000 0x10000>, 1305 <0x068a0000 0x10000>; 1306 reg-names = "hypervisor", "mac", "xpcs"; 1307 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; 1308 interrupt-names = "common"; 1309 clocks = <&bpmp TEGRA234_CLK_MGBE0_APP>, 1310 <&bpmp TEGRA234_CLK_MGBE0_MAC>, 1311 <&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>, 1312 <&bpmp TEGRA234_CLK_MGBE0_PTP_REF>, 1313 <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>, 1314 <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>, 1315 <&bpmp TEGRA234_CLK_MGBE0_TX>, 1316 <&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>, 1317 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>, 1318 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>, 1319 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS>, 1320 <&bpmp TEGRA234_CLK_MGBE0_TX_PCS>; 1321 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1322 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1323 "rx-pcs", "tx-pcs"; 1324 resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>, 1325 <&bpmp TEGRA234_RESET_MGBE0_PCS>; 1326 reset-names = "mac", "pcs"; 1327 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEARD &emc>, 1328 <&mc TEGRA234_MEMORY_CLIENT_MGBEAWR &emc>; 1329 interconnect-names = "dma-mem", "write"; 1330 iommus = <&smmu_niso0 TEGRA234_SID_MGBE>; 1331 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEA>; 1332 status = "disabled"; 1333 }; 1334 1335 ethernet@6900000 { 1336 compatible = "nvidia,tegra234-mgbe"; 1337 reg = <0x06900000 0x10000>, 1338 <0x06910000 0x10000>, 1339 <0x069a0000 0x10000>; 1340 reg-names = "hypervisor", "mac", "xpcs"; 1341 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>; 1342 interrupt-names = "common"; 1343 clocks = <&bpmp TEGRA234_CLK_MGBE1_APP>, 1344 <&bpmp TEGRA234_CLK_MGBE1_MAC>, 1345 <&bpmp TEGRA234_CLK_MGBE1_MAC_DIVIDER>, 1346 <&bpmp TEGRA234_CLK_MGBE1_PTP_REF>, 1347 <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT_M>, 1348 <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT>, 1349 <&bpmp TEGRA234_CLK_MGBE1_TX>, 1350 <&bpmp TEGRA234_CLK_MGBE1_EEE_PCS>, 1351 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_INPUT>, 1352 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_M>, 1353 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS>, 1354 <&bpmp TEGRA234_CLK_MGBE1_TX_PCS>; 1355 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1356 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1357 "rx-pcs", "tx-pcs"; 1358 resets = <&bpmp TEGRA234_RESET_MGBE1_MAC>, 1359 <&bpmp TEGRA234_RESET_MGBE1_PCS>; 1360 reset-names = "mac", "pcs"; 1361 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEBRD &emc>, 1362 <&mc TEGRA234_MEMORY_CLIENT_MGBEBWR &emc>; 1363 interconnect-names = "dma-mem", "write"; 1364 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF1>; 1365 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEB>; 1366 status = "disabled"; 1367 }; 1368 1369 ethernet@6a00000 { 1370 compatible = "nvidia,tegra234-mgbe"; 1371 reg = <0x06a00000 0x10000>, 1372 <0x06a10000 0x10000>, 1373 <0x06aa0000 0x10000>; 1374 reg-names = "hypervisor", "mac", "xpcs"; 1375 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>; 1376 interrupt-names = "common"; 1377 clocks = <&bpmp TEGRA234_CLK_MGBE2_APP>, 1378 <&bpmp TEGRA234_CLK_MGBE2_MAC>, 1379 <&bpmp TEGRA234_CLK_MGBE2_MAC_DIVIDER>, 1380 <&bpmp TEGRA234_CLK_MGBE2_PTP_REF>, 1381 <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT_M>, 1382 <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT>, 1383 <&bpmp TEGRA234_CLK_MGBE2_TX>, 1384 <&bpmp TEGRA234_CLK_MGBE2_EEE_PCS>, 1385 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_INPUT>, 1386 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_M>, 1387 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS>, 1388 <&bpmp TEGRA234_CLK_MGBE2_TX_PCS>; 1389 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1390 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1391 "rx-pcs", "tx-pcs"; 1392 resets = <&bpmp TEGRA234_RESET_MGBE2_MAC>, 1393 <&bpmp TEGRA234_RESET_MGBE2_PCS>; 1394 reset-names = "mac", "pcs"; 1395 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBECRD &emc>, 1396 <&mc TEGRA234_MEMORY_CLIENT_MGBECWR &emc>; 1397 interconnect-names = "dma-mem", "write"; 1398 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF2>; 1399 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEC>; 1400 status = "disabled"; 1401 }; 1402 1403 ethernet@6b00000 { 1404 compatible = "nvidia,tegra234-mgbe"; 1405 reg = <0x06b00000 0x10000>, 1406 <0x06b10000 0x10000>, 1407 <0x06ba0000 0x10000>; 1408 reg-names = "hypervisor", "mac", "xpcs"; 1409 interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 1410 interrupt-names = "common"; 1411 clocks = <&bpmp TEGRA234_CLK_MGBE3_APP>, 1412 <&bpmp TEGRA234_CLK_MGBE3_MAC>, 1413 <&bpmp TEGRA234_CLK_MGBE3_MAC_DIVIDER>, 1414 <&bpmp TEGRA234_CLK_MGBE3_PTP_REF>, 1415 <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT_M>, 1416 <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT>, 1417 <&bpmp TEGRA234_CLK_MGBE3_TX>, 1418 <&bpmp TEGRA234_CLK_MGBE3_EEE_PCS>, 1419 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_INPUT>, 1420 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_M>, 1421 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS>, 1422 <&bpmp TEGRA234_CLK_MGBE3_TX_PCS>; 1423 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1424 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1425 "rx-pcs", "tx-pcs"; 1426 resets = <&bpmp TEGRA234_RESET_MGBE3_MAC>, 1427 <&bpmp TEGRA234_RESET_MGBE3_PCS>; 1428 reset-names = "mac", "pcs"; 1429 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEDRD &emc>, 1430 <&mc TEGRA234_MEMORY_CLIENT_MGBEDWR &emc>; 1431 interconnect-names = "dma-mem", "write"; 1432 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF3>; 1433 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBED>; 1434 status = "disabled"; 1435 }; 1436 1437 smmu_niso1: iommu@8000000 { 1438 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 1439 reg = <0x8000000 0x1000000>, 1440 <0x7000000 0x1000000>; 1441 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1442 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 1443 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1444 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 1445 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1446 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1447 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1448 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1449 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1450 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1451 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1452 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1453 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1454 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1455 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1456 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1457 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1458 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1459 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1460 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1461 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1462 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1463 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1464 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1465 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1466 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1467 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1468 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1469 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1470 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1471 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1472 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1473 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1474 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1475 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1476 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1477 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1478 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1479 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1480 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1481 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1482 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1483 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1484 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1485 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1486 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1487 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1488 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1489 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1490 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1491 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1492 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1493 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1494 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1495 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1496 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1497 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1498 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1499 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1500 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1501 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1502 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1503 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1504 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1505 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1506 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1507 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1508 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1509 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1510 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1511 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1512 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1513 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1514 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1515 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1516 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1517 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1518 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1519 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1520 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1521 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1522 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1523 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1524 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1525 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1526 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1527 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1528 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1529 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1530 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1531 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1532 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1533 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1534 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1535 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1536 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1537 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1538 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1539 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1540 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1541 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1542 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1543 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1544 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1545 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1546 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1547 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1548 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1549 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1550 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1551 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1552 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1553 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1554 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1555 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1556 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1557 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1558 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1559 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1560 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1561 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1562 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1563 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1564 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1565 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1566 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1567 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1568 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1569 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1570 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1571 stream-match-mask = <0x7f80>; 1572 #global-interrupts = <2>; 1573 #iommu-cells = <1>; 1574 1575 nvidia,memory-controller = <&mc>; 1576 status = "okay"; 1577 }; 1578 1579 sce-fabric@b600000 { 1580 compatible = "nvidia,tegra234-sce-fabric"; 1581 reg = <0xb600000 0x40000>; 1582 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 1583 status = "okay"; 1584 }; 1585 1586 rce-fabric@be00000 { 1587 compatible = "nvidia,tegra234-rce-fabric"; 1588 reg = <0xbe00000 0x40000>; 1589 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1590 status = "okay"; 1591 }; 1592 1593 hsp_aon: hsp@c150000 { 1594 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 1595 reg = <0x0c150000 0x90000>; 1596 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1597 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1598 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1599 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1600 /* 1601 * Shared interrupt 0 is routed only to AON/SPE, so 1602 * we only have 4 shared interrupts for the CCPLEX. 1603 */ 1604 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 1605 #mbox-cells = <2>; 1606 }; 1607 1608 gen2_i2c: i2c@c240000 { 1609 compatible = "nvidia,tegra194-i2c"; 1610 reg = <0xc240000 0x100>; 1611 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1612 status = "disabled"; 1613 clock-frequency = <100000>; 1614 clocks = <&bpmp TEGRA234_CLK_I2C2 1615 &bpmp TEGRA234_CLK_PLLP_OUT0>; 1616 clock-names = "div-clk", "parent"; 1617 assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>; 1618 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 1619 resets = <&bpmp TEGRA234_RESET_I2C2>; 1620 reset-names = "i2c"; 1621 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 1622 dma-coherent; 1623 dmas = <&gpcdma 22>, <&gpcdma 22>; 1624 dma-names = "rx", "tx"; 1625 }; 1626 1627 gen8_i2c: i2c@c250000 { 1628 compatible = "nvidia,tegra194-i2c"; 1629 reg = <0xc250000 0x100>; 1630 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1631 status = "disabled"; 1632 clock-frequency = <400000>; 1633 clocks = <&bpmp TEGRA234_CLK_I2C8 1634 &bpmp TEGRA234_CLK_PLLP_OUT0>; 1635 clock-names = "div-clk", "parent"; 1636 assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>; 1637 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 1638 resets = <&bpmp TEGRA234_RESET_I2C8>; 1639 reset-names = "i2c"; 1640 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 1641 dma-coherent; 1642 dmas = <&gpcdma 0>, <&gpcdma 0>; 1643 dma-names = "rx", "tx"; 1644 }; 1645 1646 rtc@c2a0000 { 1647 compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc"; 1648 reg = <0x0c2a0000 0x10000>; 1649 interrupt-parent = <&pmc>; 1650 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1651 clocks = <&bpmp TEGRA234_CLK_CLK_32K>; 1652 clock-names = "rtc"; 1653 status = "disabled"; 1654 }; 1655 1656 gpio_aon: gpio@c2f0000 { 1657 compatible = "nvidia,tegra234-gpio-aon"; 1658 reg-names = "security", "gpio"; 1659 reg = <0x0c2f0000 0x1000>, 1660 <0x0c2f1000 0x1000>; 1661 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1662 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1663 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1664 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1665 #interrupt-cells = <2>; 1666 interrupt-controller; 1667 #gpio-cells = <2>; 1668 gpio-controller; 1669 }; 1670 1671 pwm4: pwm@c340000 { 1672 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 1673 reg = <0xc340000 0x10000>; 1674 clocks = <&bpmp TEGRA234_CLK_PWM4>; 1675 resets = <&bpmp TEGRA234_RESET_PWM4>; 1676 reset-names = "pwm"; 1677 status = "disabled"; 1678 #pwm-cells = <2>; 1679 }; 1680 1681 pmc: pmc@c360000 { 1682 compatible = "nvidia,tegra234-pmc"; 1683 reg = <0x0c360000 0x10000>, 1684 <0x0c370000 0x10000>, 1685 <0x0c380000 0x10000>, 1686 <0x0c390000 0x10000>, 1687 <0x0c3a0000 0x10000>; 1688 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 1689 1690 #interrupt-cells = <2>; 1691 interrupt-controller; 1692 1693 sdmmc1_3v3: sdmmc1-3v3 { 1694 pins = "sdmmc1-hv"; 1695 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1696 }; 1697 1698 sdmmc1_1v8: sdmmc1-1v8 { 1699 pins = "sdmmc1-hv"; 1700 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1701 }; 1702 1703 sdmmc3_3v3: sdmmc3-3v3 { 1704 pins = "sdmmc3-hv"; 1705 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1706 }; 1707 1708 sdmmc3_1v8: sdmmc3-1v8 { 1709 pins = "sdmmc3-hv"; 1710 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1711 }; 1712 }; 1713 1714 aon-fabric@c600000 { 1715 compatible = "nvidia,tegra234-aon-fabric"; 1716 reg = <0xc600000 0x40000>; 1717 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 1718 status = "okay"; 1719 }; 1720 1721 bpmp-fabric@d600000 { 1722 compatible = "nvidia,tegra234-bpmp-fabric"; 1723 reg = <0xd600000 0x40000>; 1724 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1725 status = "okay"; 1726 }; 1727 1728 dce-fabric@de00000 { 1729 compatible = "nvidia,tegra234-sce-fabric"; 1730 reg = <0xde00000 0x40000>; 1731 interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>; 1732 status = "okay"; 1733 }; 1734 1735 gic: interrupt-controller@f400000 { 1736 compatible = "arm,gic-v3"; 1737 reg = <0x0f400000 0x010000>, /* GICD */ 1738 <0x0f440000 0x200000>; /* GICR */ 1739 interrupt-parent = <&gic>; 1740 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1741 1742 #redistributor-regions = <1>; 1743 #interrupt-cells = <3>; 1744 interrupt-controller; 1745 }; 1746 1747 smmu_iso: iommu@10000000 { 1748 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 1749 reg = <0x10000000 0x1000000>; 1750 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1751 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1752 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1753 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1754 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1755 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1756 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1757 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1758 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1759 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1760 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1761 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1762 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1763 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1764 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1765 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1766 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1767 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1768 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1769 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1770 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1771 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1772 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1773 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1774 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1775 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1776 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1777 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1778 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1779 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1780 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1781 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1782 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1783 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1784 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1785 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1786 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1787 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1788 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1789 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1790 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1791 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1792 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1793 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1794 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1795 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1796 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1797 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1798 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1799 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1800 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1801 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1802 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1803 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1804 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1805 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1806 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1807 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1808 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1809 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1810 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1811 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1812 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1813 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1814 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1815 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1816 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1817 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1818 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1819 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1820 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1821 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1822 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1823 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1824 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1825 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1826 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1827 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1828 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1829 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1830 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1831 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1832 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1833 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1834 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1835 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1836 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1837 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1838 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1839 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1840 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1841 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1842 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1843 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1844 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1845 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1846 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1847 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1848 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1849 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1850 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1851 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1852 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1853 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1854 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1855 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1856 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1857 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1858 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1859 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1860 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1861 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1862 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1863 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1864 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1865 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1866 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1867 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1868 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1869 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1870 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1871 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1872 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1873 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1874 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1875 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1876 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1877 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1878 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1879 stream-match-mask = <0x7f80>; 1880 #global-interrupts = <1>; 1881 #iommu-cells = <1>; 1882 1883 nvidia,memory-controller = <&mc>; 1884 status = "okay"; 1885 }; 1886 1887 smmu_niso0: iommu@12000000 { 1888 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 1889 reg = <0x12000000 0x1000000>, 1890 <0x11000000 0x1000000>; 1891 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1892 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1893 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1894 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1895 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1896 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1897 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1898 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1899 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1900 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1901 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1902 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1903 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1904 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1905 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1906 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1907 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1908 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1909 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1910 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1911 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1912 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1913 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1914 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1915 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1916 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1917 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1918 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1919 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1920 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1921 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1922 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1923 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1924 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1925 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1926 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1927 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1928 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1929 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1930 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1931 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1932 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1933 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1934 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1935 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1936 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1937 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1938 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1939 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1940 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1941 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1942 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1943 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1944 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1945 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1946 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1947 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1948 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1949 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1950 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1951 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1952 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1953 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1954 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1955 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1956 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1957 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1958 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1959 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1960 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1961 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1962 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1963 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1964 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1965 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1966 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1967 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1968 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1969 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1970 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1971 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1972 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1973 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1974 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1975 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1976 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1977 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1978 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1979 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1980 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1981 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1982 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1983 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1984 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1985 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1986 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1987 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1988 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1989 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1990 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1991 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1992 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1993 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1994 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1995 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1996 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1997 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1998 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1999 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2000 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2001 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2002 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2003 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2004 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2005 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2006 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2007 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2008 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2009 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2010 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2011 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2012 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2013 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2014 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2015 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2016 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2017 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2018 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2019 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2020 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2021 stream-match-mask = <0x7f80>; 2022 #global-interrupts = <2>; 2023 #iommu-cells = <1>; 2024 2025 nvidia,memory-controller = <&mc>; 2026 status = "okay"; 2027 }; 2028 2029 cbb-fabric@13a00000 { 2030 compatible = "nvidia,tegra234-cbb-fabric"; 2031 reg = <0x13a00000 0x400000>; 2032 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 2033 status = "okay"; 2034 }; 2035 }; 2036 2037 ccplex@e000000 { 2038 compatible = "nvidia,tegra234-ccplex-cluster"; 2039 reg = <0x0 0x0e000000 0x0 0x5ffff>; 2040 nvidia,bpmp = <&bpmp>; 2041 status = "okay"; 2042 }; 2043 2044 pcie@140a0000 { 2045 compatible = "nvidia,tegra234-pcie"; 2046 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CA>; 2047 reg = <0x00 0x140a0000 0x0 0x00020000>, /* appl registers (128K) */ 2048 <0x00 0x2a000000 0x0 0x00040000>, /* configuration space (256K) */ 2049 <0x00 0x2a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2050 <0x00 0x2a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2051 <0x35 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2052 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2053 2054 #address-cells = <3>; 2055 #size-cells = <2>; 2056 device_type = "pci"; 2057 num-lanes = <4>; 2058 num-viewport = <8>; 2059 linux,pci-domain = <8>; 2060 2061 clocks = <&bpmp TEGRA234_CLK_PEX2_C8_CORE>; 2062 clock-names = "core"; 2063 2064 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_8_APB>, 2065 <&bpmp TEGRA234_RESET_PEX2_CORE_8>; 2066 reset-names = "apb", "core"; 2067 2068 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2069 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2070 interrupt-names = "intr", "msi"; 2071 2072 #interrupt-cells = <1>; 2073 interrupt-map-mask = <0 0 0 0>; 2074 interrupt-map = <0 0 0 0 &gic GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 2075 2076 nvidia,bpmp = <&bpmp 8>; 2077 2078 nvidia,aspm-cmrt-us = <60>; 2079 nvidia,aspm-pwr-on-t-us = <20>; 2080 nvidia,aspm-l0s-entrance-latency-us = <3>; 2081 2082 bus-range = <0x0 0xff>; 2083 2084 ranges = <0x43000000 0x32 0x40000000 0x32 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2085 <0x02000000 0x0 0x40000000 0x35 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2086 <0x01000000 0x0 0x2a100000 0x00 0x2a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2087 2088 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE8AR &emc>, 2089 <&mc TEGRA234_MEMORY_CLIENT_PCIE8AW &emc>; 2090 interconnect-names = "dma-mem", "write"; 2091 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE8 0x1000>; 2092 iommu-map-mask = <0x0>; 2093 dma-coherent; 2094 2095 status = "disabled"; 2096 }; 2097 2098 pcie@140c0000 { 2099 compatible = "nvidia,tegra234-pcie"; 2100 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CB>; 2101 reg = <0x00 0x140c0000 0x0 0x00020000>, /* appl registers (128K) */ 2102 <0x00 0x2c000000 0x0 0x00040000>, /* configuration space (256K) */ 2103 <0x00 0x2c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2104 <0x00 0x2c080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2105 <0x38 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2106 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2107 2108 #address-cells = <3>; 2109 #size-cells = <2>; 2110 device_type = "pci"; 2111 num-lanes = <4>; 2112 num-viewport = <8>; 2113 linux,pci-domain = <9>; 2114 2115 clocks = <&bpmp TEGRA234_CLK_PEX2_C9_CORE>; 2116 clock-names = "core"; 2117 2118 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_9_APB>, 2119 <&bpmp TEGRA234_RESET_PEX2_CORE_9>; 2120 reset-names = "apb", "core"; 2121 2122 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2123 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2124 interrupt-names = "intr", "msi"; 2125 2126 #interrupt-cells = <1>; 2127 interrupt-map-mask = <0 0 0 0>; 2128 interrupt-map = <0 0 0 0 &gic GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2129 2130 nvidia,bpmp = <&bpmp 9>; 2131 2132 nvidia,aspm-cmrt-us = <60>; 2133 nvidia,aspm-pwr-on-t-us = <20>; 2134 nvidia,aspm-l0s-entrance-latency-us = <3>; 2135 2136 bus-range = <0x0 0xff>; 2137 2138 ranges = <0x43000000 0x35 0x40000000 0x35 0x40000000 0x2 0xc0000000>, /* prefetchable memory (11264 MB) */ 2139 <0x02000000 0x0 0x40000000 0x38 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2140 <0x01000000 0x0 0x2c100000 0x00 0x2c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2141 2142 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE9AR &emc>, 2143 <&mc TEGRA234_MEMORY_CLIENT_PCIE9AW &emc>; 2144 interconnect-names = "dma-mem", "write"; 2145 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE9 0x1000>; 2146 iommu-map-mask = <0x0>; 2147 dma-coherent; 2148 2149 status = "disabled"; 2150 }; 2151 2152 pcie@140e0000 { 2153 compatible = "nvidia,tegra234-pcie"; 2154 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>; 2155 reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */ 2156 <0x00 0x2e000000 0x0 0x00040000>, /* configuration space (256K) */ 2157 <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2158 <0x00 0x2e080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2159 <0x3b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2160 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2161 2162 #address-cells = <3>; 2163 #size-cells = <2>; 2164 device_type = "pci"; 2165 num-lanes = <4>; 2166 num-viewport = <8>; 2167 linux,pci-domain = <10>; 2168 2169 clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>; 2170 clock-names = "core"; 2171 2172 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>, 2173 <&bpmp TEGRA234_RESET_PEX2_CORE_10>; 2174 reset-names = "apb", "core"; 2175 2176 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2177 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2178 interrupt-names = "intr", "msi"; 2179 2180 #interrupt-cells = <1>; 2181 interrupt-map-mask = <0 0 0 0>; 2182 interrupt-map = <0 0 0 0 &gic GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 2183 2184 nvidia,bpmp = <&bpmp 10>; 2185 2186 nvidia,aspm-cmrt-us = <60>; 2187 nvidia,aspm-pwr-on-t-us = <20>; 2188 nvidia,aspm-l0s-entrance-latency-us = <3>; 2189 2190 bus-range = <0x0 0xff>; 2191 2192 ranges = <0x43000000 0x38 0x40000000 0x38 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2193 <0x02000000 0x0 0x40000000 0x3b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2194 <0x01000000 0x0 0x2e100000 0x00 0x2e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2195 2196 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, 2197 <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; 2198 interconnect-names = "dma-mem", "write"; 2199 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>; 2200 iommu-map-mask = <0x0>; 2201 dma-coherent; 2202 2203 status = "disabled"; 2204 }; 2205 2206 pcie@14100000 { 2207 compatible = "nvidia,tegra234-pcie"; 2208 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 2209 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 2210 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 2211 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2212 <0x00 0x30080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2213 <0x20 0xb0000000 0x0 0x10000000>; /* ECAM (256MB) */ 2214 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2215 2216 #address-cells = <3>; 2217 #size-cells = <2>; 2218 device_type = "pci"; 2219 num-lanes = <1>; 2220 num-viewport = <8>; 2221 linux,pci-domain = <1>; 2222 2223 clocks = <&bpmp TEGRA234_CLK_PEX0_C1_CORE>; 2224 clock-names = "core"; 2225 2226 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_1_APB>, 2227 <&bpmp TEGRA234_RESET_PEX0_CORE_1>; 2228 reset-names = "apb", "core"; 2229 2230 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2231 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2232 interrupt-names = "intr", "msi"; 2233 2234 #interrupt-cells = <1>; 2235 interrupt-map-mask = <0 0 0 0>; 2236 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 2237 2238 nvidia,bpmp = <&bpmp 1>; 2239 2240 nvidia,aspm-cmrt-us = <60>; 2241 nvidia,aspm-pwr-on-t-us = <20>; 2242 nvidia,aspm-l0s-entrance-latency-us = <3>; 2243 2244 bus-range = <0x0 0xff>; 2245 2246 ranges = <0x43000000 0x20 0x80000000 0x20 0x80000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 2247 <0x02000000 0x0 0x40000000 0x20 0xa8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2248 <0x01000000 0x0 0x30100000 0x00 0x30100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2249 2250 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE1R &emc>, 2251 <&mc TEGRA234_MEMORY_CLIENT_PCIE1W &emc>; 2252 interconnect-names = "dma-mem", "write"; 2253 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE1 0x1000>; 2254 iommu-map-mask = <0x0>; 2255 dma-coherent; 2256 2257 status = "disabled"; 2258 }; 2259 2260 pcie@14120000 { 2261 compatible = "nvidia,tegra234-pcie"; 2262 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 2263 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 2264 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 2265 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2266 <0x00 0x32080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2267 <0x20 0xf0000000 0x0 0x10000000>; /* ECAM (256MB) */ 2268 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2269 2270 #address-cells = <3>; 2271 #size-cells = <2>; 2272 device_type = "pci"; 2273 num-lanes = <1>; 2274 num-viewport = <8>; 2275 linux,pci-domain = <2>; 2276 2277 clocks = <&bpmp TEGRA234_CLK_PEX0_C2_CORE>; 2278 clock-names = "core"; 2279 2280 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_2_APB>, 2281 <&bpmp TEGRA234_RESET_PEX0_CORE_2>; 2282 reset-names = "apb", "core"; 2283 2284 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2285 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2286 interrupt-names = "intr", "msi"; 2287 2288 #interrupt-cells = <1>; 2289 interrupt-map-mask = <0 0 0 0>; 2290 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 2291 2292 nvidia,bpmp = <&bpmp 2>; 2293 2294 nvidia,aspm-cmrt-us = <60>; 2295 nvidia,aspm-pwr-on-t-us = <20>; 2296 nvidia,aspm-l0s-entrance-latency-us = <3>; 2297 2298 bus-range = <0x0 0xff>; 2299 2300 ranges = <0x43000000 0x20 0xc0000000 0x20 0xc0000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 2301 <0x02000000 0x0 0x40000000 0x20 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2302 <0x01000000 0x0 0x32100000 0x00 0x32100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2303 2304 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE2AR &emc>, 2305 <&mc TEGRA234_MEMORY_CLIENT_PCIE2AW &emc>; 2306 interconnect-names = "dma-mem", "write"; 2307 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE2 0x1000>; 2308 iommu-map-mask = <0x0>; 2309 dma-coherent; 2310 2311 status = "disabled"; 2312 }; 2313 2314 pcie@14140000 { 2315 compatible = "nvidia,tegra234-pcie"; 2316 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 2317 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 2318 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 2319 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2320 <0x00 0x34080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2321 <0x21 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2322 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2323 2324 #address-cells = <3>; 2325 #size-cells = <2>; 2326 device_type = "pci"; 2327 num-lanes = <1>; 2328 num-viewport = <8>; 2329 linux,pci-domain = <3>; 2330 2331 clocks = <&bpmp TEGRA234_CLK_PEX0_C3_CORE>; 2332 clock-names = "core"; 2333 2334 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_3_APB>, 2335 <&bpmp TEGRA234_RESET_PEX0_CORE_3>; 2336 reset-names = "apb", "core"; 2337 2338 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2339 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2340 interrupt-names = "intr", "msi"; 2341 2342 #interrupt-cells = <1>; 2343 interrupt-map-mask = <0 0 0 0>; 2344 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 2345 2346 nvidia,bpmp = <&bpmp 3>; 2347 2348 nvidia,aspm-cmrt-us = <60>; 2349 nvidia,aspm-pwr-on-t-us = <20>; 2350 nvidia,aspm-l0s-entrance-latency-us = <3>; 2351 2352 bus-range = <0x0 0xff>; 2353 2354 ranges = <0x43000000 0x21 0x00000000 0x21 0x00000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 2355 <0x02000000 0x0 0x40000000 0x21 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2356 <0x01000000 0x0 0x34100000 0x00 0x34100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2357 2358 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE3R &emc>, 2359 <&mc TEGRA234_MEMORY_CLIENT_PCIE3W &emc>; 2360 interconnect-names = "dma-mem", "write"; 2361 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE3 0x1000>; 2362 iommu-map-mask = <0x0>; 2363 dma-coherent; 2364 2365 status = "disabled"; 2366 }; 2367 2368 pcie@14160000 { 2369 compatible = "nvidia,tegra234-pcie"; 2370 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>; 2371 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2372 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2373 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2374 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2375 <0x24 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2376 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2377 2378 #address-cells = <3>; 2379 #size-cells = <2>; 2380 device_type = "pci"; 2381 num-lanes = <4>; 2382 num-viewport = <8>; 2383 linux,pci-domain = <4>; 2384 2385 clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>; 2386 clock-names = "core"; 2387 2388 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>, 2389 <&bpmp TEGRA234_RESET_PEX0_CORE_4>; 2390 reset-names = "apb", "core"; 2391 2392 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2393 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2394 interrupt-names = "intr", "msi"; 2395 2396 #interrupt-cells = <1>; 2397 interrupt-map-mask = <0 0 0 0>; 2398 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 2399 2400 nvidia,bpmp = <&bpmp 4>; 2401 2402 nvidia,aspm-cmrt-us = <60>; 2403 nvidia,aspm-pwr-on-t-us = <20>; 2404 nvidia,aspm-l0s-entrance-latency-us = <3>; 2405 2406 bus-range = <0x0 0xff>; 2407 2408 ranges = <0x43000000 0x21 0x40000000 0x21 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2409 <0x02000000 0x0 0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2410 <0x01000000 0x0 0x36100000 0x00 0x36100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2411 2412 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE4R &emc>, 2413 <&mc TEGRA234_MEMORY_CLIENT_PCIE4W &emc>; 2414 interconnect-names = "dma-mem", "write"; 2415 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE4 0x1000>; 2416 iommu-map-mask = <0x0>; 2417 dma-coherent; 2418 2419 status = "disabled"; 2420 }; 2421 2422 pcie@14180000 { 2423 compatible = "nvidia,tegra234-pcie"; 2424 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BA>; 2425 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2426 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2427 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2428 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2429 <0x27 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2430 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2431 2432 #address-cells = <3>; 2433 #size-cells = <2>; 2434 device_type = "pci"; 2435 num-lanes = <4>; 2436 num-viewport = <8>; 2437 linux,pci-domain = <0>; 2438 2439 clocks = <&bpmp TEGRA234_CLK_PEX0_C0_CORE>; 2440 clock-names = "core"; 2441 2442 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_0_APB>, 2443 <&bpmp TEGRA234_RESET_PEX0_CORE_0>; 2444 reset-names = "apb", "core"; 2445 2446 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2447 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2448 interrupt-names = "intr", "msi"; 2449 2450 #interrupt-cells = <1>; 2451 interrupt-map-mask = <0 0 0 0>; 2452 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 2453 2454 nvidia,bpmp = <&bpmp 0>; 2455 2456 nvidia,aspm-cmrt-us = <60>; 2457 nvidia,aspm-pwr-on-t-us = <20>; 2458 nvidia,aspm-l0s-entrance-latency-us = <3>; 2459 2460 bus-range = <0x0 0xff>; 2461 2462 ranges = <0x43000000 0x24 0x40000000 0x24 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2463 <0x02000000 0x0 0x40000000 0x27 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2464 <0x01000000 0x0 0x38100000 0x00 0x38100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2465 2466 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE0R &emc>, 2467 <&mc TEGRA234_MEMORY_CLIENT_PCIE0W &emc>; 2468 interconnect-names = "dma-mem", "write"; 2469 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE0 0x1000>; 2470 iommu-map-mask = <0x0>; 2471 dma-coherent; 2472 2473 status = "disabled"; 2474 }; 2475 2476 pcie@141a0000 { 2477 compatible = "nvidia,tegra234-pcie"; 2478 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>; 2479 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2480 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2481 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2482 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2483 <0x2b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2484 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2485 2486 #address-cells = <3>; 2487 #size-cells = <2>; 2488 device_type = "pci"; 2489 num-lanes = <8>; 2490 num-viewport = <8>; 2491 linux,pci-domain = <5>; 2492 2493 clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>; 2494 clock-names = "core"; 2495 2496 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>, 2497 <&bpmp TEGRA234_RESET_PEX1_CORE_5>; 2498 reset-names = "apb", "core"; 2499 2500 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2501 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2502 interrupt-names = "intr", "msi"; 2503 2504 #interrupt-cells = <1>; 2505 interrupt-map-mask = <0 0 0 0>; 2506 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 2507 2508 nvidia,bpmp = <&bpmp 5>; 2509 2510 nvidia,aspm-cmrt-us = <60>; 2511 nvidia,aspm-pwr-on-t-us = <20>; 2512 nvidia,aspm-l0s-entrance-latency-us = <3>; 2513 2514 bus-range = <0x0 0xff>; 2515 2516 ranges = <0x43000000 0x28 0x00000000 0x28 0x00000000 0x3 0x28000000>, /* prefetchable memory (12928 MB) */ 2517 <0x02000000 0x0 0x40000000 0x2b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2518 <0x01000000 0x0 0x3a100000 0x00 0x3a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2519 2520 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, 2521 <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; 2522 interconnect-names = "dma-mem", "write"; 2523 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>; 2524 iommu-map-mask = <0x0>; 2525 dma-coherent; 2526 2527 status = "disabled"; 2528 }; 2529 2530 pcie@141c0000 { 2531 compatible = "nvidia,tegra234-pcie"; 2532 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>; 2533 reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */ 2534 <0x00 0x3c000000 0x0 0x00040000>, /* configuration space (256K) */ 2535 <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2536 <0x00 0x3c080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2537 <0x2e 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2538 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2539 2540 #address-cells = <3>; 2541 #size-cells = <2>; 2542 device_type = "pci"; 2543 num-lanes = <4>; 2544 num-viewport = <8>; 2545 linux,pci-domain = <6>; 2546 2547 clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>; 2548 clock-names = "core"; 2549 2550 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>, 2551 <&bpmp TEGRA234_RESET_PEX1_CORE_6>; 2552 reset-names = "apb", "core"; 2553 2554 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2555 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2556 interrupt-names = "intr", "msi"; 2557 2558 #interrupt-cells = <1>; 2559 interrupt-map-mask = <0 0 0 0>; 2560 interrupt-map = <0 0 0 0 &gic GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 2561 2562 nvidia,bpmp = <&bpmp 6>; 2563 2564 nvidia,aspm-cmrt-us = <60>; 2565 nvidia,aspm-pwr-on-t-us = <20>; 2566 nvidia,aspm-l0s-entrance-latency-us = <3>; 2567 2568 bus-range = <0x0 0xff>; 2569 2570 ranges = <0x43000000 0x2b 0x40000000 0x2b 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2571 <0x02000000 0x0 0x40000000 0x2e 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2572 <0x01000000 0x0 0x3c100000 0x00 0x3c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2573 2574 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, 2575 <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; 2576 interconnect-names = "dma-mem", "write"; 2577 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>; 2578 iommu-map-mask = <0x0>; 2579 dma-coherent; 2580 2581 status = "disabled"; 2582 }; 2583 2584 pcie@141e0000 { 2585 compatible = "nvidia,tegra234-pcie"; 2586 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>; 2587 reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */ 2588 <0x00 0x3e000000 0x0 0x00040000>, /* configuration space (256K) */ 2589 <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2590 <0x00 0x3e080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2591 <0x32 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2592 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2593 2594 #address-cells = <3>; 2595 #size-cells = <2>; 2596 device_type = "pci"; 2597 num-lanes = <8>; 2598 num-viewport = <8>; 2599 linux,pci-domain = <7>; 2600 2601 clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>; 2602 clock-names = "core"; 2603 2604 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>, 2605 <&bpmp TEGRA234_RESET_PEX2_CORE_7>; 2606 reset-names = "apb", "core"; 2607 2608 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2609 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2610 interrupt-names = "intr", "msi"; 2611 2612 #interrupt-cells = <1>; 2613 interrupt-map-mask = <0 0 0 0>; 2614 interrupt-map = <0 0 0 0 &gic GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 2615 2616 nvidia,bpmp = <&bpmp 7>; 2617 2618 nvidia,aspm-cmrt-us = <60>; 2619 nvidia,aspm-pwr-on-t-us = <20>; 2620 nvidia,aspm-l0s-entrance-latency-us = <3>; 2621 2622 bus-range = <0x0 0xff>; 2623 2624 ranges = <0x43000000 0x30 0x00000000 0x30 0x00000000 0x2 0x28000000>, /* prefetchable memory (8832 MB) */ 2625 <0x02000000 0x0 0x40000000 0x32 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2626 <0x01000000 0x0 0x3e100000 0x00 0x3e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2627 2628 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>, 2629 <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>; 2630 interconnect-names = "dma-mem", "write"; 2631 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>; 2632 iommu-map-mask = <0x0>; 2633 dma-coherent; 2634 2635 status = "disabled"; 2636 }; 2637 2638 pcie-ep@141a0000 { 2639 compatible = "nvidia,tegra234-pcie-ep"; 2640 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>; 2641 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2642 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2643 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2644 <0x27 0x40000000 0x4 0x00000000>; /* Address Space (16G) */ 2645 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2646 2647 num-lanes = <8>; 2648 2649 clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>; 2650 clock-names = "core"; 2651 2652 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>, 2653 <&bpmp TEGRA234_RESET_PEX1_CORE_5>; 2654 reset-names = "apb", "core"; 2655 2656 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2657 interrupt-names = "intr"; 2658 2659 nvidia,bpmp = <&bpmp 5>; 2660 2661 nvidia,enable-ext-refclk; 2662 nvidia,aspm-cmrt-us = <60>; 2663 nvidia,aspm-pwr-on-t-us = <20>; 2664 nvidia,aspm-l0s-entrance-latency-us = <3>; 2665 2666 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, 2667 <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; 2668 interconnect-names = "dma-mem", "write"; 2669 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>; 2670 iommu-map-mask = <0x0>; 2671 dma-coherent; 2672 2673 status = "disabled"; 2674 }; 2675 2676 pcie-ep@141c0000{ 2677 compatible = "nvidia,tegra234-pcie-ep"; 2678 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>; 2679 reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */ 2680 <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2681 <0x00 0x3c080000 0x0 0x00040000>, /* DBI space (256K) */ 2682 <0x2b 0x40000000 0x3 0x00000000>; /* Address Space (12G) */ 2683 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2684 2685 num-lanes = <4>; 2686 2687 clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>; 2688 clock-names = "core"; 2689 2690 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>, 2691 <&bpmp TEGRA234_RESET_PEX1_CORE_6>; 2692 reset-names = "apb", "core"; 2693 2694 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2695 interrupt-names = "intr"; 2696 2697 nvidia,bpmp = <&bpmp 6>; 2698 2699 nvidia,enable-ext-refclk; 2700 nvidia,aspm-cmrt-us = <60>; 2701 nvidia,aspm-pwr-on-t-us = <20>; 2702 nvidia,aspm-l0s-entrance-latency-us = <3>; 2703 2704 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, 2705 <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; 2706 interconnect-names = "dma-mem", "write"; 2707 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>; 2708 iommu-map-mask = <0x0>; 2709 dma-coherent; 2710 2711 status = "disabled"; 2712 }; 2713 2714 pcie-ep@141e0000{ 2715 compatible = "nvidia,tegra234-pcie-ep"; 2716 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>; 2717 reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */ 2718 <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2719 <0x00 0x3e080000 0x0 0x00040000>, /* DBI space (256K) */ 2720 <0x2e 0x40000000 0x4 0x00000000>; /* Address Space (16G) */ 2721 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2722 2723 num-lanes = <8>; 2724 2725 clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>; 2726 clock-names = "core"; 2727 2728 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>, 2729 <&bpmp TEGRA234_RESET_PEX2_CORE_7>; 2730 reset-names = "apb", "core"; 2731 2732 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2733 interrupt-names = "intr"; 2734 2735 nvidia,bpmp = <&bpmp 7>; 2736 2737 nvidia,enable-ext-refclk; 2738 nvidia,aspm-cmrt-us = <60>; 2739 nvidia,aspm-pwr-on-t-us = <20>; 2740 nvidia,aspm-l0s-entrance-latency-us = <3>; 2741 2742 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>, 2743 <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>; 2744 interconnect-names = "dma-mem", "write"; 2745 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>; 2746 iommu-map-mask = <0x0>; 2747 dma-coherent; 2748 2749 status = "disabled"; 2750 }; 2751 2752 pcie-ep@140e0000{ 2753 compatible = "nvidia,tegra234-pcie-ep"; 2754 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>; 2755 reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */ 2756 <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2757 <0x00 0x2e080000 0x0 0x00040000>, /* DBI space (256K) */ 2758 <0x38 0x40000000 0x3 0x00000000>; /* Address Space (12G) */ 2759 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2760 2761 num-lanes = <4>; 2762 2763 clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>; 2764 clock-names = "core"; 2765 2766 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>, 2767 <&bpmp TEGRA234_RESET_PEX2_CORE_10>; 2768 reset-names = "apb", "core"; 2769 2770 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2771 interrupt-names = "intr"; 2772 2773 nvidia,bpmp = <&bpmp 10>; 2774 2775 nvidia,enable-ext-refclk; 2776 nvidia,aspm-cmrt-us = <60>; 2777 nvidia,aspm-pwr-on-t-us = <20>; 2778 nvidia,aspm-l0s-entrance-latency-us = <3>; 2779 2780 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, 2781 <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; 2782 interconnect-names = "dma-mem", "write"; 2783 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>; 2784 iommu-map-mask = <0x0>; 2785 dma-coherent; 2786 2787 status = "disabled"; 2788 }; 2789 2790 sram@40000000 { 2791 compatible = "nvidia,tegra234-sysram", "mmio-sram"; 2792 reg = <0x0 0x40000000 0x0 0x80000>; 2793 #address-cells = <1>; 2794 #size-cells = <1>; 2795 ranges = <0x0 0x0 0x40000000 0x80000>; 2796 no-memory-wc; 2797 2798 cpu_bpmp_tx: sram@70000 { 2799 reg = <0x70000 0x1000>; 2800 label = "cpu-bpmp-tx"; 2801 pool; 2802 }; 2803 2804 cpu_bpmp_rx: sram@71000 { 2805 reg = <0x71000 0x1000>; 2806 label = "cpu-bpmp-rx"; 2807 pool; 2808 }; 2809 }; 2810 2811 bpmp: bpmp { 2812 compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp"; 2813 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 2814 TEGRA_HSP_DB_MASTER_BPMP>; 2815 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 2816 #clock-cells = <1>; 2817 #reset-cells = <1>; 2818 #power-domain-cells = <1>; 2819 interconnects = <&mc TEGRA234_MEMORY_CLIENT_BPMPR &emc>, 2820 <&mc TEGRA234_MEMORY_CLIENT_BPMPW &emc>, 2821 <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAR &emc>, 2822 <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAW &emc>; 2823 interconnect-names = "read", "write", "dma-mem", "dma-write"; 2824 iommus = <&smmu_niso1 TEGRA234_SID_BPMP>; 2825 2826 bpmp_i2c: i2c { 2827 compatible = "nvidia,tegra186-bpmp-i2c"; 2828 nvidia,bpmp-bus-id = <5>; 2829 #address-cells = <1>; 2830 #size-cells = <0>; 2831 }; 2832 }; 2833 2834 cpus { 2835 #address-cells = <1>; 2836 #size-cells = <0>; 2837 2838 cpu0_0: cpu@0 { 2839 compatible = "arm,cortex-a78"; 2840 device_type = "cpu"; 2841 reg = <0x00000>; 2842 2843 enable-method = "psci"; 2844 2845 i-cache-size = <65536>; 2846 i-cache-line-size = <64>; 2847 i-cache-sets = <256>; 2848 d-cache-size = <65536>; 2849 d-cache-line-size = <64>; 2850 d-cache-sets = <256>; 2851 next-level-cache = <&l2c0_0>; 2852 }; 2853 2854 cpu0_1: cpu@100 { 2855 compatible = "arm,cortex-a78"; 2856 device_type = "cpu"; 2857 reg = <0x00100>; 2858 2859 enable-method = "psci"; 2860 2861 i-cache-size = <65536>; 2862 i-cache-line-size = <64>; 2863 i-cache-sets = <256>; 2864 d-cache-size = <65536>; 2865 d-cache-line-size = <64>; 2866 d-cache-sets = <256>; 2867 next-level-cache = <&l2c0_1>; 2868 }; 2869 2870 cpu0_2: cpu@200 { 2871 compatible = "arm,cortex-a78"; 2872 device_type = "cpu"; 2873 reg = <0x00200>; 2874 2875 enable-method = "psci"; 2876 2877 i-cache-size = <65536>; 2878 i-cache-line-size = <64>; 2879 i-cache-sets = <256>; 2880 d-cache-size = <65536>; 2881 d-cache-line-size = <64>; 2882 d-cache-sets = <256>; 2883 next-level-cache = <&l2c0_2>; 2884 }; 2885 2886 cpu0_3: cpu@300 { 2887 compatible = "arm,cortex-a78"; 2888 device_type = "cpu"; 2889 reg = <0x00300>; 2890 2891 enable-method = "psci"; 2892 2893 i-cache-size = <65536>; 2894 i-cache-line-size = <64>; 2895 i-cache-sets = <256>; 2896 d-cache-size = <65536>; 2897 d-cache-line-size = <64>; 2898 d-cache-sets = <256>; 2899 next-level-cache = <&l2c0_3>; 2900 }; 2901 2902 cpu1_0: cpu@10000 { 2903 compatible = "arm,cortex-a78"; 2904 device_type = "cpu"; 2905 reg = <0x10000>; 2906 2907 enable-method = "psci"; 2908 2909 i-cache-size = <65536>; 2910 i-cache-line-size = <64>; 2911 i-cache-sets = <256>; 2912 d-cache-size = <65536>; 2913 d-cache-line-size = <64>; 2914 d-cache-sets = <256>; 2915 next-level-cache = <&l2c1_0>; 2916 }; 2917 2918 cpu1_1: cpu@10100 { 2919 compatible = "arm,cortex-a78"; 2920 device_type = "cpu"; 2921 reg = <0x10100>; 2922 2923 enable-method = "psci"; 2924 2925 i-cache-size = <65536>; 2926 i-cache-line-size = <64>; 2927 i-cache-sets = <256>; 2928 d-cache-size = <65536>; 2929 d-cache-line-size = <64>; 2930 d-cache-sets = <256>; 2931 next-level-cache = <&l2c1_1>; 2932 }; 2933 2934 cpu1_2: cpu@10200 { 2935 compatible = "arm,cortex-a78"; 2936 device_type = "cpu"; 2937 reg = <0x10200>; 2938 2939 enable-method = "psci"; 2940 2941 i-cache-size = <65536>; 2942 i-cache-line-size = <64>; 2943 i-cache-sets = <256>; 2944 d-cache-size = <65536>; 2945 d-cache-line-size = <64>; 2946 d-cache-sets = <256>; 2947 next-level-cache = <&l2c1_2>; 2948 }; 2949 2950 cpu1_3: cpu@10300 { 2951 compatible = "arm,cortex-a78"; 2952 device_type = "cpu"; 2953 reg = <0x10300>; 2954 2955 enable-method = "psci"; 2956 2957 i-cache-size = <65536>; 2958 i-cache-line-size = <64>; 2959 i-cache-sets = <256>; 2960 d-cache-size = <65536>; 2961 d-cache-line-size = <64>; 2962 d-cache-sets = <256>; 2963 next-level-cache = <&l2c1_3>; 2964 }; 2965 2966 cpu2_0: cpu@20000 { 2967 compatible = "arm,cortex-a78"; 2968 device_type = "cpu"; 2969 reg = <0x20000>; 2970 2971 enable-method = "psci"; 2972 2973 i-cache-size = <65536>; 2974 i-cache-line-size = <64>; 2975 i-cache-sets = <256>; 2976 d-cache-size = <65536>; 2977 d-cache-line-size = <64>; 2978 d-cache-sets = <256>; 2979 next-level-cache = <&l2c2_0>; 2980 }; 2981 2982 cpu2_1: cpu@20100 { 2983 compatible = "arm,cortex-a78"; 2984 device_type = "cpu"; 2985 reg = <0x20100>; 2986 2987 enable-method = "psci"; 2988 2989 i-cache-size = <65536>; 2990 i-cache-line-size = <64>; 2991 i-cache-sets = <256>; 2992 d-cache-size = <65536>; 2993 d-cache-line-size = <64>; 2994 d-cache-sets = <256>; 2995 next-level-cache = <&l2c2_1>; 2996 }; 2997 2998 cpu2_2: cpu@20200 { 2999 compatible = "arm,cortex-a78"; 3000 device_type = "cpu"; 3001 reg = <0x20200>; 3002 3003 enable-method = "psci"; 3004 3005 i-cache-size = <65536>; 3006 i-cache-line-size = <64>; 3007 i-cache-sets = <256>; 3008 d-cache-size = <65536>; 3009 d-cache-line-size = <64>; 3010 d-cache-sets = <256>; 3011 next-level-cache = <&l2c2_2>; 3012 }; 3013 3014 cpu2_3: cpu@20300 { 3015 compatible = "arm,cortex-a78"; 3016 device_type = "cpu"; 3017 reg = <0x20300>; 3018 3019 enable-method = "psci"; 3020 3021 i-cache-size = <65536>; 3022 i-cache-line-size = <64>; 3023 i-cache-sets = <256>; 3024 d-cache-size = <65536>; 3025 d-cache-line-size = <64>; 3026 d-cache-sets = <256>; 3027 next-level-cache = <&l2c2_3>; 3028 }; 3029 3030 cpu-map { 3031 cluster0 { 3032 core0 { 3033 cpu = <&cpu0_0>; 3034 }; 3035 3036 core1 { 3037 cpu = <&cpu0_1>; 3038 }; 3039 3040 core2 { 3041 cpu = <&cpu0_2>; 3042 }; 3043 3044 core3 { 3045 cpu = <&cpu0_3>; 3046 }; 3047 }; 3048 3049 cluster1 { 3050 core0 { 3051 cpu = <&cpu1_0>; 3052 }; 3053 3054 core1 { 3055 cpu = <&cpu1_1>; 3056 }; 3057 3058 core2 { 3059 cpu = <&cpu1_2>; 3060 }; 3061 3062 core3 { 3063 cpu = <&cpu1_3>; 3064 }; 3065 }; 3066 3067 cluster2 { 3068 core0 { 3069 cpu = <&cpu2_0>; 3070 }; 3071 3072 core1 { 3073 cpu = <&cpu2_1>; 3074 }; 3075 3076 core2 { 3077 cpu = <&cpu2_2>; 3078 }; 3079 3080 core3 { 3081 cpu = <&cpu2_3>; 3082 }; 3083 }; 3084 }; 3085 3086 l2c0_0: l2-cache00 { 3087 compatible = "cache"; 3088 cache-size = <262144>; 3089 cache-line-size = <64>; 3090 cache-sets = <512>; 3091 cache-unified; 3092 cache-level = <2>; 3093 next-level-cache = <&l3c0>; 3094 }; 3095 3096 l2c0_1: l2-cache01 { 3097 compatible = "cache"; 3098 cache-size = <262144>; 3099 cache-line-size = <64>; 3100 cache-sets = <512>; 3101 cache-unified; 3102 cache-level = <2>; 3103 next-level-cache = <&l3c0>; 3104 }; 3105 3106 l2c0_2: l2-cache02 { 3107 compatible = "cache"; 3108 cache-size = <262144>; 3109 cache-line-size = <64>; 3110 cache-sets = <512>; 3111 cache-unified; 3112 cache-level = <2>; 3113 next-level-cache = <&l3c0>; 3114 }; 3115 3116 l2c0_3: l2-cache03 { 3117 compatible = "cache"; 3118 cache-size = <262144>; 3119 cache-line-size = <64>; 3120 cache-sets = <512>; 3121 cache-unified; 3122 cache-level = <2>; 3123 next-level-cache = <&l3c0>; 3124 }; 3125 3126 l2c1_0: l2-cache10 { 3127 compatible = "cache"; 3128 cache-size = <262144>; 3129 cache-line-size = <64>; 3130 cache-sets = <512>; 3131 cache-unified; 3132 cache-level = <2>; 3133 next-level-cache = <&l3c1>; 3134 }; 3135 3136 l2c1_1: l2-cache11 { 3137 compatible = "cache"; 3138 cache-size = <262144>; 3139 cache-line-size = <64>; 3140 cache-sets = <512>; 3141 cache-unified; 3142 cache-level = <2>; 3143 next-level-cache = <&l3c1>; 3144 }; 3145 3146 l2c1_2: l2-cache12 { 3147 compatible = "cache"; 3148 cache-size = <262144>; 3149 cache-line-size = <64>; 3150 cache-sets = <512>; 3151 cache-unified; 3152 cache-level = <2>; 3153 next-level-cache = <&l3c1>; 3154 }; 3155 3156 l2c1_3: l2-cache13 { 3157 compatible = "cache"; 3158 cache-size = <262144>; 3159 cache-line-size = <64>; 3160 cache-sets = <512>; 3161 cache-unified; 3162 cache-level = <2>; 3163 next-level-cache = <&l3c1>; 3164 }; 3165 3166 l2c2_0: l2-cache20 { 3167 compatible = "cache"; 3168 cache-size = <262144>; 3169 cache-line-size = <64>; 3170 cache-sets = <512>; 3171 cache-unified; 3172 cache-level = <2>; 3173 next-level-cache = <&l3c2>; 3174 }; 3175 3176 l2c2_1: l2-cache21 { 3177 compatible = "cache"; 3178 cache-size = <262144>; 3179 cache-line-size = <64>; 3180 cache-sets = <512>; 3181 cache-unified; 3182 cache-level = <2>; 3183 next-level-cache = <&l3c2>; 3184 }; 3185 3186 l2c2_2: l2-cache22 { 3187 compatible = "cache"; 3188 cache-size = <262144>; 3189 cache-line-size = <64>; 3190 cache-sets = <512>; 3191 cache-unified; 3192 cache-level = <2>; 3193 next-level-cache = <&l3c2>; 3194 }; 3195 3196 l2c2_3: l2-cache23 { 3197 compatible = "cache"; 3198 cache-size = <262144>; 3199 cache-line-size = <64>; 3200 cache-sets = <512>; 3201 cache-unified; 3202 cache-level = <2>; 3203 next-level-cache = <&l3c2>; 3204 }; 3205 3206 l3c0: l3-cache0 { 3207 compatible = "cache"; 3208 cache-unified; 3209 cache-size = <2097152>; 3210 cache-line-size = <64>; 3211 cache-sets = <2048>; 3212 cache-level = <3>; 3213 }; 3214 3215 l3c1: l3-cache1 { 3216 compatible = "cache"; 3217 cache-unified; 3218 cache-size = <2097152>; 3219 cache-line-size = <64>; 3220 cache-sets = <2048>; 3221 cache-level = <3>; 3222 }; 3223 3224 l3c2: l3-cache2 { 3225 compatible = "cache"; 3226 cache-unified; 3227 cache-size = <2097152>; 3228 cache-line-size = <64>; 3229 cache-sets = <2048>; 3230 cache-level = <3>; 3231 }; 3232 }; 3233 3234 pmu { 3235 compatible = "arm,cortex-a78-pmu"; 3236 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 3237 status = "okay"; 3238 }; 3239 3240 psci { 3241 compatible = "arm,psci-1.0"; 3242 status = "okay"; 3243 method = "smc"; 3244 }; 3245 3246 tcu: serial { 3247 compatible = "nvidia,tegra234-tcu", "nvidia,tegra194-tcu"; 3248 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 3249 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 3250 mbox-names = "rx", "tx"; 3251 status = "disabled"; 3252 }; 3253 3254 sound { 3255 status = "disabled"; 3256 3257 clocks = <&bpmp TEGRA234_CLK_PLLA>, 3258 <&bpmp TEGRA234_CLK_PLLA_OUT0>; 3259 clock-names = "pll_a", "plla_out0"; 3260 assigned-clocks = <&bpmp TEGRA234_CLK_PLLA>, 3261 <&bpmp TEGRA234_CLK_PLLA_OUT0>, 3262 <&bpmp TEGRA234_CLK_AUD_MCLK>; 3263 assigned-clock-parents = <0>, 3264 <&bpmp TEGRA234_CLK_PLLA>, 3265 <&bpmp TEGRA234_CLK_PLLA_OUT0>; 3266 }; 3267 3268 timer { 3269 compatible = "arm,armv8-timer"; 3270 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3271 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3272 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3273 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 3274 interrupt-parent = <&gic>; 3275 always-on; 3276 }; 3277}; 3278