1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include <linux/kernel.h> 8 #include <linux/export.h> 9 #include <linux/clk-provider.h> 10 #include <linux/regmap.h> 11 #include <linux/delay.h> 12 13 #include "clk-alpha-pll.h" 14 #include "common.h" 15 16 #define PLL_MODE(p) ((p)->offset + 0x0) 17 # define PLL_OUTCTRL BIT(0) 18 # define PLL_BYPASSNL BIT(1) 19 # define PLL_RESET_N BIT(2) 20 # define PLL_OFFLINE_REQ BIT(7) 21 # define PLL_LOCK_COUNT_SHIFT 8 22 # define PLL_LOCK_COUNT_MASK 0x3f 23 # define PLL_BIAS_COUNT_SHIFT 14 24 # define PLL_BIAS_COUNT_MASK 0x3f 25 # define PLL_VOTE_FSM_ENA BIT(20) 26 # define PLL_FSM_ENA BIT(20) 27 # define PLL_VOTE_FSM_RESET BIT(21) 28 # define PLL_UPDATE BIT(22) 29 # define PLL_UPDATE_BYPASS BIT(23) 30 # define PLL_FSM_LEGACY_MODE BIT(24) 31 # define PLL_OFFLINE_ACK BIT(28) 32 # define ALPHA_PLL_ACK_LATCH BIT(29) 33 # define PLL_ACTIVE_FLAG BIT(30) 34 # define PLL_LOCK_DET BIT(31) 35 36 #define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL]) 37 #define PLL_CAL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_CAL_L_VAL]) 38 #define PLL_ALPHA_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL]) 39 #define PLL_ALPHA_VAL_U(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U]) 40 41 #define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL]) 42 # define PLL_POST_DIV_SHIFT 8 43 # define PLL_POST_DIV_MASK(p) GENMASK((p)->width, 0) 44 # define PLL_ALPHA_EN BIT(24) 45 # define PLL_ALPHA_MODE BIT(25) 46 # define PLL_VCO_SHIFT 20 47 # define PLL_VCO_MASK 0x3 48 49 #define PLL_USER_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U]) 50 #define PLL_USER_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U1]) 51 52 #define PLL_CONFIG_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL]) 53 #define PLL_CONFIG_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U]) 54 #define PLL_CONFIG_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U1]) 55 #define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL]) 56 #define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U]) 57 #define PLL_TEST_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U1]) 58 #define PLL_STATUS(p) ((p)->offset + (p)->regs[PLL_OFF_STATUS]) 59 #define PLL_OPMODE(p) ((p)->offset + (p)->regs[PLL_OFF_OPMODE]) 60 #define PLL_FRAC(p) ((p)->offset + (p)->regs[PLL_OFF_FRAC]) 61 62 const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { 63 [CLK_ALPHA_PLL_TYPE_DEFAULT] = { 64 [PLL_OFF_L_VAL] = 0x04, 65 [PLL_OFF_ALPHA_VAL] = 0x08, 66 [PLL_OFF_ALPHA_VAL_U] = 0x0c, 67 [PLL_OFF_USER_CTL] = 0x10, 68 [PLL_OFF_USER_CTL_U] = 0x14, 69 [PLL_OFF_CONFIG_CTL] = 0x18, 70 [PLL_OFF_TEST_CTL] = 0x1c, 71 [PLL_OFF_TEST_CTL_U] = 0x20, 72 [PLL_OFF_STATUS] = 0x24, 73 }, 74 [CLK_ALPHA_PLL_TYPE_HUAYRA] = { 75 [PLL_OFF_L_VAL] = 0x04, 76 [PLL_OFF_ALPHA_VAL] = 0x08, 77 [PLL_OFF_USER_CTL] = 0x10, 78 [PLL_OFF_CONFIG_CTL] = 0x14, 79 [PLL_OFF_CONFIG_CTL_U] = 0x18, 80 [PLL_OFF_TEST_CTL] = 0x1c, 81 [PLL_OFF_TEST_CTL_U] = 0x20, 82 [PLL_OFF_STATUS] = 0x24, 83 }, 84 [CLK_ALPHA_PLL_TYPE_BRAMMO] = { 85 [PLL_OFF_L_VAL] = 0x04, 86 [PLL_OFF_ALPHA_VAL] = 0x08, 87 [PLL_OFF_ALPHA_VAL_U] = 0x0c, 88 [PLL_OFF_USER_CTL] = 0x10, 89 [PLL_OFF_CONFIG_CTL] = 0x18, 90 [PLL_OFF_TEST_CTL] = 0x1c, 91 [PLL_OFF_STATUS] = 0x24, 92 }, 93 [CLK_ALPHA_PLL_TYPE_FABIA] = { 94 [PLL_OFF_L_VAL] = 0x04, 95 [PLL_OFF_USER_CTL] = 0x0c, 96 [PLL_OFF_USER_CTL_U] = 0x10, 97 [PLL_OFF_CONFIG_CTL] = 0x14, 98 [PLL_OFF_CONFIG_CTL_U] = 0x18, 99 [PLL_OFF_TEST_CTL] = 0x1c, 100 [PLL_OFF_TEST_CTL_U] = 0x20, 101 [PLL_OFF_STATUS] = 0x24, 102 [PLL_OFF_OPMODE] = 0x2c, 103 [PLL_OFF_FRAC] = 0x38, 104 }, 105 [CLK_ALPHA_PLL_TYPE_TRION] = { 106 [PLL_OFF_L_VAL] = 0x04, 107 [PLL_OFF_CAL_L_VAL] = 0x08, 108 [PLL_OFF_USER_CTL] = 0x0c, 109 [PLL_OFF_USER_CTL_U] = 0x10, 110 [PLL_OFF_USER_CTL_U1] = 0x14, 111 [PLL_OFF_CONFIG_CTL] = 0x18, 112 [PLL_OFF_CONFIG_CTL_U] = 0x1c, 113 [PLL_OFF_CONFIG_CTL_U1] = 0x20, 114 [PLL_OFF_TEST_CTL] = 0x24, 115 [PLL_OFF_TEST_CTL_U] = 0x28, 116 [PLL_OFF_TEST_CTL_U1] = 0x2c, 117 [PLL_OFF_STATUS] = 0x30, 118 [PLL_OFF_OPMODE] = 0x38, 119 [PLL_OFF_ALPHA_VAL] = 0x40, 120 }, 121 [CLK_ALPHA_PLL_TYPE_AGERA] = { 122 [PLL_OFF_L_VAL] = 0x04, 123 [PLL_OFF_ALPHA_VAL] = 0x08, 124 [PLL_OFF_USER_CTL] = 0x0c, 125 [PLL_OFF_CONFIG_CTL] = 0x10, 126 [PLL_OFF_CONFIG_CTL_U] = 0x14, 127 [PLL_OFF_TEST_CTL] = 0x18, 128 [PLL_OFF_TEST_CTL_U] = 0x1c, 129 [PLL_OFF_STATUS] = 0x2c, 130 }, 131 [CLK_ALPHA_PLL_TYPE_ZONDA] = { 132 [PLL_OFF_L_VAL] = 0x04, 133 [PLL_OFF_ALPHA_VAL] = 0x08, 134 [PLL_OFF_USER_CTL] = 0x0c, 135 [PLL_OFF_CONFIG_CTL] = 0x10, 136 [PLL_OFF_CONFIG_CTL_U] = 0x14, 137 [PLL_OFF_CONFIG_CTL_U1] = 0x18, 138 [PLL_OFF_TEST_CTL] = 0x1c, 139 [PLL_OFF_TEST_CTL_U] = 0x20, 140 [PLL_OFF_TEST_CTL_U1] = 0x24, 141 [PLL_OFF_OPMODE] = 0x28, 142 [PLL_OFF_STATUS] = 0x38, 143 }, 144 [CLK_ALPHA_PLL_TYPE_LUCID_EVO] = { 145 [PLL_OFF_OPMODE] = 0x04, 146 [PLL_OFF_STATUS] = 0x0c, 147 [PLL_OFF_L_VAL] = 0x10, 148 [PLL_OFF_ALPHA_VAL] = 0x14, 149 [PLL_OFF_USER_CTL] = 0x18, 150 [PLL_OFF_USER_CTL_U] = 0x1c, 151 [PLL_OFF_CONFIG_CTL] = 0x20, 152 [PLL_OFF_CONFIG_CTL_U] = 0x24, 153 [PLL_OFF_CONFIG_CTL_U1] = 0x28, 154 [PLL_OFF_TEST_CTL] = 0x2c, 155 [PLL_OFF_TEST_CTL_U] = 0x30, 156 [PLL_OFF_TEST_CTL_U1] = 0x34, 157 }, 158 [CLK_ALPHA_PLL_TYPE_LUCID_OLE] = { 159 [PLL_OFF_OPMODE] = 0x04, 160 [PLL_OFF_STATE] = 0x08, 161 [PLL_OFF_STATUS] = 0x0c, 162 [PLL_OFF_L_VAL] = 0x10, 163 [PLL_OFF_ALPHA_VAL] = 0x14, 164 [PLL_OFF_USER_CTL] = 0x18, 165 [PLL_OFF_USER_CTL_U] = 0x1c, 166 [PLL_OFF_CONFIG_CTL] = 0x20, 167 [PLL_OFF_CONFIG_CTL_U] = 0x24, 168 [PLL_OFF_CONFIG_CTL_U1] = 0x28, 169 [PLL_OFF_TEST_CTL] = 0x2c, 170 [PLL_OFF_TEST_CTL_U] = 0x30, 171 [PLL_OFF_TEST_CTL_U1] = 0x34, 172 [PLL_OFF_TEST_CTL_U2] = 0x38, 173 }, 174 [CLK_ALPHA_PLL_TYPE_RIVIAN_EVO] = { 175 [PLL_OFF_OPMODE] = 0x04, 176 [PLL_OFF_STATUS] = 0x0c, 177 [PLL_OFF_L_VAL] = 0x10, 178 [PLL_OFF_USER_CTL] = 0x14, 179 [PLL_OFF_USER_CTL_U] = 0x18, 180 [PLL_OFF_CONFIG_CTL] = 0x1c, 181 [PLL_OFF_CONFIG_CTL_U] = 0x20, 182 [PLL_OFF_CONFIG_CTL_U1] = 0x24, 183 [PLL_OFF_TEST_CTL] = 0x28, 184 [PLL_OFF_TEST_CTL_U] = 0x2c, 185 }, 186 [CLK_ALPHA_PLL_TYPE_DEFAULT_EVO] = { 187 [PLL_OFF_L_VAL] = 0x04, 188 [PLL_OFF_ALPHA_VAL] = 0x08, 189 [PLL_OFF_ALPHA_VAL_U] = 0x0c, 190 [PLL_OFF_TEST_CTL] = 0x10, 191 [PLL_OFF_TEST_CTL_U] = 0x14, 192 [PLL_OFF_USER_CTL] = 0x18, 193 [PLL_OFF_USER_CTL_U] = 0x1c, 194 [PLL_OFF_CONFIG_CTL] = 0x20, 195 [PLL_OFF_STATUS] = 0x24, 196 }, 197 [CLK_ALPHA_PLL_TYPE_BRAMMO_EVO] = { 198 [PLL_OFF_L_VAL] = 0x04, 199 [PLL_OFF_ALPHA_VAL] = 0x08, 200 [PLL_OFF_ALPHA_VAL_U] = 0x0c, 201 [PLL_OFF_TEST_CTL] = 0x10, 202 [PLL_OFF_TEST_CTL_U] = 0x14, 203 [PLL_OFF_USER_CTL] = 0x18, 204 [PLL_OFF_CONFIG_CTL] = 0x1C, 205 [PLL_OFF_STATUS] = 0x20, 206 }, 207 }; 208 EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); 209 210 /* 211 * Even though 40 bits are present, use only 32 for ease of calculation. 212 */ 213 #define ALPHA_REG_BITWIDTH 40 214 #define ALPHA_REG_16BIT_WIDTH 16 215 #define ALPHA_BITWIDTH 32U 216 #define ALPHA_SHIFT(w) min(w, ALPHA_BITWIDTH) 217 218 #define PLL_HUAYRA_M_WIDTH 8 219 #define PLL_HUAYRA_M_SHIFT 8 220 #define PLL_HUAYRA_M_MASK 0xff 221 #define PLL_HUAYRA_N_SHIFT 0 222 #define PLL_HUAYRA_N_MASK 0xff 223 #define PLL_HUAYRA_ALPHA_WIDTH 16 224 225 #define PLL_STANDBY 0x0 226 #define PLL_RUN 0x1 227 #define PLL_OUT_MASK 0x7 228 #define PLL_RATE_MARGIN 500 229 230 /* TRION PLL specific settings and offsets */ 231 #define TRION_PLL_CAL_VAL 0x44 232 #define TRION_PCAL_DONE BIT(26) 233 234 /* LUCID PLL specific settings and offsets */ 235 #define LUCID_PCAL_DONE BIT(27) 236 237 /* LUCID 5LPE PLL specific settings and offsets */ 238 #define LUCID_5LPE_PCAL_DONE BIT(11) 239 #define LUCID_5LPE_ALPHA_PLL_ACK_LATCH BIT(13) 240 #define LUCID_5LPE_PLL_LATCH_INPUT BIT(14) 241 #define LUCID_5LPE_ENABLE_VOTE_RUN BIT(21) 242 243 /* LUCID EVO PLL specific settings and offsets */ 244 #define LUCID_EVO_PCAL_NOT_DONE BIT(8) 245 #define LUCID_EVO_ENABLE_VOTE_RUN BIT(25) 246 #define LUCID_EVO_PLL_L_VAL_MASK GENMASK(15, 0) 247 #define LUCID_EVO_PLL_CAL_L_VAL_SHIFT 16 248 249 /* ZONDA PLL specific */ 250 #define ZONDA_PLL_OUT_MASK 0xf 251 #define ZONDA_STAY_IN_CFA BIT(16) 252 #define ZONDA_PLL_FREQ_LOCK_DET BIT(29) 253 254 #define pll_alpha_width(p) \ 255 ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \ 256 ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH) 257 258 #define pll_has_64bit_config(p) ((PLL_CONFIG_CTL_U(p) - PLL_CONFIG_CTL(p)) == 4) 259 260 #define to_clk_alpha_pll(_hw) container_of(to_clk_regmap(_hw), \ 261 struct clk_alpha_pll, clkr) 262 263 #define to_clk_alpha_pll_postdiv(_hw) container_of(to_clk_regmap(_hw), \ 264 struct clk_alpha_pll_postdiv, clkr) 265 266 static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse, 267 const char *action) 268 { 269 u32 val; 270 int count; 271 int ret; 272 const char *name = clk_hw_get_name(&pll->clkr.hw); 273 274 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 275 if (ret) 276 return ret; 277 278 for (count = 200; count > 0; count--) { 279 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 280 if (ret) 281 return ret; 282 if (inverse && !(val & mask)) 283 return 0; 284 else if ((val & mask) == mask) 285 return 0; 286 287 udelay(1); 288 } 289 290 WARN(1, "%s failed to %s!\n", name, action); 291 return -ETIMEDOUT; 292 } 293 294 #define wait_for_pll_enable_active(pll) \ 295 wait_for_pll(pll, PLL_ACTIVE_FLAG, 0, "enable") 296 297 #define wait_for_pll_enable_lock(pll) \ 298 wait_for_pll(pll, PLL_LOCK_DET, 0, "enable") 299 300 #define wait_for_zonda_pll_freq_lock(pll) \ 301 wait_for_pll(pll, ZONDA_PLL_FREQ_LOCK_DET, 0, "freq enable") 302 303 #define wait_for_pll_disable(pll) \ 304 wait_for_pll(pll, PLL_ACTIVE_FLAG, 1, "disable") 305 306 #define wait_for_pll_offline(pll) \ 307 wait_for_pll(pll, PLL_OFFLINE_ACK, 0, "offline") 308 309 #define wait_for_pll_update(pll) \ 310 wait_for_pll(pll, PLL_UPDATE, 1, "update") 311 312 #define wait_for_pll_update_ack_set(pll) \ 313 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 0, "update_ack_set") 314 315 #define wait_for_pll_update_ack_clear(pll) \ 316 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 1, "update_ack_clear") 317 318 static void clk_alpha_pll_write_config(struct regmap *regmap, unsigned int reg, 319 unsigned int val) 320 { 321 if (val) 322 regmap_write(regmap, reg, val); 323 } 324 325 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 326 const struct alpha_pll_config *config) 327 { 328 u32 val, mask; 329 330 regmap_write(regmap, PLL_L_VAL(pll), config->l); 331 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha); 332 regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 333 334 if (pll_has_64bit_config(pll)) 335 regmap_write(regmap, PLL_CONFIG_CTL_U(pll), 336 config->config_ctl_hi_val); 337 338 if (pll_alpha_width(pll) > 32) 339 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi); 340 341 val = config->main_output_mask; 342 val |= config->aux_output_mask; 343 val |= config->aux2_output_mask; 344 val |= config->early_output_mask; 345 val |= config->pre_div_val; 346 val |= config->post_div_val; 347 val |= config->vco_val; 348 val |= config->alpha_en_mask; 349 val |= config->alpha_mode_mask; 350 351 mask = config->main_output_mask; 352 mask |= config->aux_output_mask; 353 mask |= config->aux2_output_mask; 354 mask |= config->early_output_mask; 355 mask |= config->pre_div_mask; 356 mask |= config->post_div_mask; 357 mask |= config->vco_mask; 358 359 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); 360 361 if (pll->flags & SUPPORTS_FSM_MODE) 362 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0); 363 } 364 EXPORT_SYMBOL_GPL(clk_alpha_pll_configure); 365 366 static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw) 367 { 368 int ret; 369 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 370 u32 val; 371 372 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 373 if (ret) 374 return ret; 375 376 val |= PLL_FSM_ENA; 377 378 if (pll->flags & SUPPORTS_OFFLINE_REQ) 379 val &= ~PLL_OFFLINE_REQ; 380 381 ret = regmap_write(pll->clkr.regmap, PLL_MODE(pll), val); 382 if (ret) 383 return ret; 384 385 /* Make sure enable request goes through before waiting for update */ 386 mb(); 387 388 return wait_for_pll_enable_active(pll); 389 } 390 391 static void clk_alpha_pll_hwfsm_disable(struct clk_hw *hw) 392 { 393 int ret; 394 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 395 u32 val; 396 397 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 398 if (ret) 399 return; 400 401 if (pll->flags & SUPPORTS_OFFLINE_REQ) { 402 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 403 PLL_OFFLINE_REQ, PLL_OFFLINE_REQ); 404 if (ret) 405 return; 406 407 ret = wait_for_pll_offline(pll); 408 if (ret) 409 return; 410 } 411 412 /* Disable hwfsm */ 413 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 414 PLL_FSM_ENA, 0); 415 if (ret) 416 return; 417 418 wait_for_pll_disable(pll); 419 } 420 421 static int pll_is_enabled(struct clk_hw *hw, u32 mask) 422 { 423 int ret; 424 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 425 u32 val; 426 427 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 428 if (ret) 429 return ret; 430 431 return !!(val & mask); 432 } 433 434 static int clk_alpha_pll_hwfsm_is_enabled(struct clk_hw *hw) 435 { 436 return pll_is_enabled(hw, PLL_ACTIVE_FLAG); 437 } 438 439 static int clk_alpha_pll_is_enabled(struct clk_hw *hw) 440 { 441 return pll_is_enabled(hw, PLL_LOCK_DET); 442 } 443 444 static int clk_alpha_pll_enable(struct clk_hw *hw) 445 { 446 int ret; 447 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 448 u32 val, mask; 449 450 mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL; 451 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 452 if (ret) 453 return ret; 454 455 /* If in FSM mode, just vote for it */ 456 if (val & PLL_VOTE_FSM_ENA) { 457 ret = clk_enable_regmap(hw); 458 if (ret) 459 return ret; 460 return wait_for_pll_enable_active(pll); 461 } 462 463 /* Skip if already enabled */ 464 if ((val & mask) == mask) 465 return 0; 466 467 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 468 PLL_BYPASSNL, PLL_BYPASSNL); 469 if (ret) 470 return ret; 471 472 /* 473 * H/W requires a 5us delay between disabling the bypass and 474 * de-asserting the reset. 475 */ 476 mb(); 477 udelay(5); 478 479 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 480 PLL_RESET_N, PLL_RESET_N); 481 if (ret) 482 return ret; 483 484 ret = wait_for_pll_enable_lock(pll); 485 if (ret) 486 return ret; 487 488 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 489 PLL_OUTCTRL, PLL_OUTCTRL); 490 491 /* Ensure that the write above goes through before returning. */ 492 mb(); 493 return ret; 494 } 495 496 static void clk_alpha_pll_disable(struct clk_hw *hw) 497 { 498 int ret; 499 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 500 u32 val, mask; 501 502 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 503 if (ret) 504 return; 505 506 /* If in FSM mode, just unvote it */ 507 if (val & PLL_VOTE_FSM_ENA) { 508 clk_disable_regmap(hw); 509 return; 510 } 511 512 mask = PLL_OUTCTRL; 513 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0); 514 515 /* Delay of 2 output clock ticks required until output is disabled */ 516 mb(); 517 udelay(1); 518 519 mask = PLL_RESET_N | PLL_BYPASSNL; 520 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0); 521 } 522 523 static unsigned long 524 alpha_pll_calc_rate(u64 prate, u32 l, u32 a, u32 alpha_width) 525 { 526 return (prate * l) + ((prate * a) >> ALPHA_SHIFT(alpha_width)); 527 } 528 529 static unsigned long 530 alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a, 531 u32 alpha_width) 532 { 533 u64 remainder; 534 u64 quotient; 535 536 quotient = rate; 537 remainder = do_div(quotient, prate); 538 *l = quotient; 539 540 if (!remainder) { 541 *a = 0; 542 return rate; 543 } 544 545 /* Upper ALPHA_BITWIDTH bits of Alpha */ 546 quotient = remainder << ALPHA_SHIFT(alpha_width); 547 548 remainder = do_div(quotient, prate); 549 550 if (remainder) 551 quotient++; 552 553 *a = quotient; 554 return alpha_pll_calc_rate(prate, *l, *a, alpha_width); 555 } 556 557 static const struct pll_vco * 558 alpha_pll_find_vco(const struct clk_alpha_pll *pll, unsigned long rate) 559 { 560 const struct pll_vco *v = pll->vco_table; 561 const struct pll_vco *end = v + pll->num_vco; 562 563 for (; v < end; v++) 564 if (rate >= v->min_freq && rate <= v->max_freq) 565 return v; 566 567 return NULL; 568 } 569 570 static unsigned long 571 clk_alpha_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 572 { 573 u32 l, low, high, ctl; 574 u64 a = 0, prate = parent_rate; 575 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 576 u32 alpha_width = pll_alpha_width(pll); 577 578 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); 579 580 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 581 if (ctl & PLL_ALPHA_EN) { 582 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &low); 583 if (alpha_width > 32) { 584 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), 585 &high); 586 a = (u64)high << 32 | low; 587 } else { 588 a = low & GENMASK(alpha_width - 1, 0); 589 } 590 591 if (alpha_width > ALPHA_BITWIDTH) 592 a >>= alpha_width - ALPHA_BITWIDTH; 593 } 594 595 return alpha_pll_calc_rate(prate, l, a, alpha_width); 596 } 597 598 599 static int __clk_alpha_pll_update_latch(struct clk_alpha_pll *pll) 600 { 601 int ret; 602 u32 mode; 603 604 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &mode); 605 606 /* Latch the input to the PLL */ 607 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 608 PLL_UPDATE); 609 610 /* Wait for 2 reference cycle before checking ACK bit */ 611 udelay(1); 612 613 /* 614 * PLL will latch the new L, Alpha and freq control word. 615 * PLL will respond by raising PLL_ACK_LATCH output when new programming 616 * has been latched in and PLL is being updated. When 617 * UPDATE_LOGIC_BYPASS bit is not set, PLL_UPDATE will be cleared 618 * automatically by hardware when PLL_ACK_LATCH is asserted by PLL. 619 */ 620 if (mode & PLL_UPDATE_BYPASS) { 621 ret = wait_for_pll_update_ack_set(pll); 622 if (ret) 623 return ret; 624 625 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 0); 626 } else { 627 ret = wait_for_pll_update(pll); 628 if (ret) 629 return ret; 630 } 631 632 ret = wait_for_pll_update_ack_clear(pll); 633 if (ret) 634 return ret; 635 636 /* Wait for PLL output to stabilize */ 637 udelay(10); 638 639 return 0; 640 } 641 642 static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll, 643 int (*is_enabled)(struct clk_hw *)) 644 { 645 if (!is_enabled(&pll->clkr.hw) || 646 !(pll->flags & SUPPORTS_DYNAMIC_UPDATE)) 647 return 0; 648 649 return __clk_alpha_pll_update_latch(pll); 650 } 651 652 static int __clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate, 653 unsigned long prate, 654 int (*is_enabled)(struct clk_hw *)) 655 { 656 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 657 const struct pll_vco *vco; 658 u32 l, alpha_width = pll_alpha_width(pll); 659 u64 a; 660 661 rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 662 vco = alpha_pll_find_vco(pll, rate); 663 if (pll->vco_table && !vco) { 664 pr_err("%s: alpha pll not in a valid vco range\n", 665 clk_hw_get_name(hw)); 666 return -EINVAL; 667 } 668 669 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 670 671 if (alpha_width > ALPHA_BITWIDTH) 672 a <<= alpha_width - ALPHA_BITWIDTH; 673 674 if (alpha_width > 32) 675 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), a >> 32); 676 677 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 678 679 if (vco) { 680 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 681 PLL_VCO_MASK << PLL_VCO_SHIFT, 682 vco->val << PLL_VCO_SHIFT); 683 } 684 685 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 686 PLL_ALPHA_EN, PLL_ALPHA_EN); 687 688 return clk_alpha_pll_update_latch(pll, is_enabled); 689 } 690 691 static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate, 692 unsigned long prate) 693 { 694 return __clk_alpha_pll_set_rate(hw, rate, prate, 695 clk_alpha_pll_is_enabled); 696 } 697 698 static int clk_alpha_pll_hwfsm_set_rate(struct clk_hw *hw, unsigned long rate, 699 unsigned long prate) 700 { 701 return __clk_alpha_pll_set_rate(hw, rate, prate, 702 clk_alpha_pll_hwfsm_is_enabled); 703 } 704 705 static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate, 706 unsigned long *prate) 707 { 708 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 709 u32 l, alpha_width = pll_alpha_width(pll); 710 u64 a; 711 unsigned long min_freq, max_freq; 712 713 rate = alpha_pll_round_rate(rate, *prate, &l, &a, alpha_width); 714 if (!pll->vco_table || alpha_pll_find_vco(pll, rate)) 715 return rate; 716 717 min_freq = pll->vco_table[0].min_freq; 718 max_freq = pll->vco_table[pll->num_vco - 1].max_freq; 719 720 return clamp(rate, min_freq, max_freq); 721 } 722 723 static unsigned long 724 alpha_huayra_pll_calc_rate(u64 prate, u32 l, u32 a) 725 { 726 /* 727 * a contains 16 bit alpha_val in two’s complement number in the range 728 * of [-0.5, 0.5). 729 */ 730 if (a >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1)) 731 l -= 1; 732 733 return (prate * l) + (prate * a >> PLL_HUAYRA_ALPHA_WIDTH); 734 } 735 736 static unsigned long 737 alpha_huayra_pll_round_rate(unsigned long rate, unsigned long prate, 738 u32 *l, u32 *a) 739 { 740 u64 remainder; 741 u64 quotient; 742 743 quotient = rate; 744 remainder = do_div(quotient, prate); 745 *l = quotient; 746 747 if (!remainder) { 748 *a = 0; 749 return rate; 750 } 751 752 quotient = remainder << PLL_HUAYRA_ALPHA_WIDTH; 753 remainder = do_div(quotient, prate); 754 755 if (remainder) 756 quotient++; 757 758 /* 759 * alpha_val should be in two’s complement number in the range 760 * of [-0.5, 0.5) so if quotient >= 0.5 then increment the l value 761 * since alpha value will be subtracted in this case. 762 */ 763 if (quotient >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1)) 764 *l += 1; 765 766 *a = quotient; 767 return alpha_huayra_pll_calc_rate(prate, *l, *a); 768 } 769 770 static unsigned long 771 alpha_pll_huayra_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 772 { 773 u64 rate = parent_rate, tmp; 774 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 775 u32 l, alpha = 0, ctl, alpha_m, alpha_n; 776 777 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); 778 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 779 780 if (ctl & PLL_ALPHA_EN) { 781 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &alpha); 782 /* 783 * Depending upon alpha_mode, it can be treated as M/N value or 784 * as a two’s complement number. When alpha_mode=1, 785 * pll_alpha_val<15:8>=M and pll_apla_val<7:0>=N 786 * 787 * Fout=FIN*(L+(M/N)) 788 * 789 * M is a signed number (-128 to 127) and N is unsigned 790 * (0 to 255). M/N has to be within +/-0.5. 791 * 792 * When alpha_mode=0, it is a two’s complement number in the 793 * range [-0.5, 0.5). 794 * 795 * Fout=FIN*(L+(alpha_val)/2^16) 796 * 797 * where alpha_val is two’s complement number. 798 */ 799 if (!(ctl & PLL_ALPHA_MODE)) 800 return alpha_huayra_pll_calc_rate(rate, l, alpha); 801 802 alpha_m = alpha >> PLL_HUAYRA_M_SHIFT & PLL_HUAYRA_M_MASK; 803 alpha_n = alpha >> PLL_HUAYRA_N_SHIFT & PLL_HUAYRA_N_MASK; 804 805 rate *= l; 806 tmp = parent_rate; 807 if (alpha_m >= BIT(PLL_HUAYRA_M_WIDTH - 1)) { 808 alpha_m = BIT(PLL_HUAYRA_M_WIDTH) - alpha_m; 809 tmp *= alpha_m; 810 do_div(tmp, alpha_n); 811 rate -= tmp; 812 } else { 813 tmp *= alpha_m; 814 do_div(tmp, alpha_n); 815 rate += tmp; 816 } 817 818 return rate; 819 } 820 821 return alpha_huayra_pll_calc_rate(rate, l, alpha); 822 } 823 824 static int alpha_pll_huayra_set_rate(struct clk_hw *hw, unsigned long rate, 825 unsigned long prate) 826 { 827 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 828 u32 l, a, ctl, cur_alpha = 0; 829 830 rate = alpha_huayra_pll_round_rate(rate, prate, &l, &a); 831 832 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 833 834 if (ctl & PLL_ALPHA_EN) 835 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &cur_alpha); 836 837 /* 838 * Huayra PLL supports PLL dynamic programming. User can change L_VAL, 839 * without having to go through the power on sequence. 840 */ 841 if (clk_alpha_pll_is_enabled(hw)) { 842 if (cur_alpha != a) { 843 pr_err("%s: clock needs to be gated\n", 844 clk_hw_get_name(hw)); 845 return -EBUSY; 846 } 847 848 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 849 /* Ensure that the write above goes to detect L val change. */ 850 mb(); 851 return wait_for_pll_enable_lock(pll); 852 } 853 854 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 855 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 856 857 if (a == 0) 858 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 859 PLL_ALPHA_EN, 0x0); 860 else 861 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 862 PLL_ALPHA_EN | PLL_ALPHA_MODE, PLL_ALPHA_EN); 863 864 return 0; 865 } 866 867 static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate, 868 unsigned long *prate) 869 { 870 u32 l, a; 871 872 return alpha_huayra_pll_round_rate(rate, *prate, &l, &a); 873 } 874 875 static int trion_pll_is_enabled(struct clk_alpha_pll *pll, 876 struct regmap *regmap) 877 { 878 u32 mode_val, opmode_val; 879 int ret; 880 881 ret = regmap_read(regmap, PLL_MODE(pll), &mode_val); 882 ret |= regmap_read(regmap, PLL_OPMODE(pll), &opmode_val); 883 if (ret) 884 return 0; 885 886 return ((opmode_val & PLL_RUN) && (mode_val & PLL_OUTCTRL)); 887 } 888 889 static int clk_trion_pll_is_enabled(struct clk_hw *hw) 890 { 891 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 892 893 return trion_pll_is_enabled(pll, pll->clkr.regmap); 894 } 895 896 static int clk_trion_pll_enable(struct clk_hw *hw) 897 { 898 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 899 struct regmap *regmap = pll->clkr.regmap; 900 u32 val; 901 int ret; 902 903 ret = regmap_read(regmap, PLL_MODE(pll), &val); 904 if (ret) 905 return ret; 906 907 /* If in FSM mode, just vote for it */ 908 if (val & PLL_VOTE_FSM_ENA) { 909 ret = clk_enable_regmap(hw); 910 if (ret) 911 return ret; 912 return wait_for_pll_enable_active(pll); 913 } 914 915 /* Set operation mode to RUN */ 916 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); 917 918 ret = wait_for_pll_enable_lock(pll); 919 if (ret) 920 return ret; 921 922 /* Enable the PLL outputs */ 923 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), 924 PLL_OUT_MASK, PLL_OUT_MASK); 925 if (ret) 926 return ret; 927 928 /* Enable the global PLL outputs */ 929 return regmap_update_bits(regmap, PLL_MODE(pll), 930 PLL_OUTCTRL, PLL_OUTCTRL); 931 } 932 933 static void clk_trion_pll_disable(struct clk_hw *hw) 934 { 935 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 936 struct regmap *regmap = pll->clkr.regmap; 937 u32 val; 938 int ret; 939 940 ret = regmap_read(regmap, PLL_MODE(pll), &val); 941 if (ret) 942 return; 943 944 /* If in FSM mode, just unvote it */ 945 if (val & PLL_VOTE_FSM_ENA) { 946 clk_disable_regmap(hw); 947 return; 948 } 949 950 /* Disable the global PLL output */ 951 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 952 if (ret) 953 return; 954 955 /* Disable the PLL outputs */ 956 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), 957 PLL_OUT_MASK, 0); 958 if (ret) 959 return; 960 961 /* Place the PLL mode in STANDBY */ 962 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 963 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 964 } 965 966 static unsigned long 967 clk_trion_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 968 { 969 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 970 u32 l, frac, alpha_width = pll_alpha_width(pll); 971 972 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); 973 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac); 974 975 return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width); 976 } 977 978 const struct clk_ops clk_alpha_pll_fixed_ops = { 979 .enable = clk_alpha_pll_enable, 980 .disable = clk_alpha_pll_disable, 981 .is_enabled = clk_alpha_pll_is_enabled, 982 .recalc_rate = clk_alpha_pll_recalc_rate, 983 }; 984 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_ops); 985 986 const struct clk_ops clk_alpha_pll_ops = { 987 .enable = clk_alpha_pll_enable, 988 .disable = clk_alpha_pll_disable, 989 .is_enabled = clk_alpha_pll_is_enabled, 990 .recalc_rate = clk_alpha_pll_recalc_rate, 991 .round_rate = clk_alpha_pll_round_rate, 992 .set_rate = clk_alpha_pll_set_rate, 993 }; 994 EXPORT_SYMBOL_GPL(clk_alpha_pll_ops); 995 996 const struct clk_ops clk_alpha_pll_huayra_ops = { 997 .enable = clk_alpha_pll_enable, 998 .disable = clk_alpha_pll_disable, 999 .is_enabled = clk_alpha_pll_is_enabled, 1000 .recalc_rate = alpha_pll_huayra_recalc_rate, 1001 .round_rate = alpha_pll_huayra_round_rate, 1002 .set_rate = alpha_pll_huayra_set_rate, 1003 }; 1004 EXPORT_SYMBOL_GPL(clk_alpha_pll_huayra_ops); 1005 1006 const struct clk_ops clk_alpha_pll_hwfsm_ops = { 1007 .enable = clk_alpha_pll_hwfsm_enable, 1008 .disable = clk_alpha_pll_hwfsm_disable, 1009 .is_enabled = clk_alpha_pll_hwfsm_is_enabled, 1010 .recalc_rate = clk_alpha_pll_recalc_rate, 1011 .round_rate = clk_alpha_pll_round_rate, 1012 .set_rate = clk_alpha_pll_hwfsm_set_rate, 1013 }; 1014 EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops); 1015 1016 const struct clk_ops clk_alpha_pll_fixed_trion_ops = { 1017 .enable = clk_trion_pll_enable, 1018 .disable = clk_trion_pll_disable, 1019 .is_enabled = clk_trion_pll_is_enabled, 1020 .recalc_rate = clk_trion_pll_recalc_rate, 1021 .round_rate = clk_alpha_pll_round_rate, 1022 }; 1023 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_trion_ops); 1024 1025 static unsigned long 1026 clk_alpha_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 1027 { 1028 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1029 u32 ctl; 1030 1031 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 1032 1033 ctl >>= PLL_POST_DIV_SHIFT; 1034 ctl &= PLL_POST_DIV_MASK(pll); 1035 1036 return parent_rate >> fls(ctl); 1037 } 1038 1039 static const struct clk_div_table clk_alpha_div_table[] = { 1040 { 0x0, 1 }, 1041 { 0x1, 2 }, 1042 { 0x3, 4 }, 1043 { 0x7, 8 }, 1044 { 0xf, 16 }, 1045 { } 1046 }; 1047 1048 static const struct clk_div_table clk_alpha_2bit_div_table[] = { 1049 { 0x0, 1 }, 1050 { 0x1, 2 }, 1051 { 0x3, 4 }, 1052 { } 1053 }; 1054 1055 static long 1056 clk_alpha_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate, 1057 unsigned long *prate) 1058 { 1059 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1060 const struct clk_div_table *table; 1061 1062 if (pll->width == 2) 1063 table = clk_alpha_2bit_div_table; 1064 else 1065 table = clk_alpha_div_table; 1066 1067 return divider_round_rate(hw, rate, prate, table, 1068 pll->width, CLK_DIVIDER_POWER_OF_TWO); 1069 } 1070 1071 static long 1072 clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw *hw, unsigned long rate, 1073 unsigned long *prate) 1074 { 1075 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1076 u32 ctl, div; 1077 1078 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 1079 1080 ctl >>= PLL_POST_DIV_SHIFT; 1081 ctl &= BIT(pll->width) - 1; 1082 div = 1 << fls(ctl); 1083 1084 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) 1085 *prate = clk_hw_round_rate(clk_hw_get_parent(hw), div * rate); 1086 1087 return DIV_ROUND_UP_ULL((u64)*prate, div); 1088 } 1089 1090 static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 1091 unsigned long parent_rate) 1092 { 1093 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1094 int div; 1095 1096 /* 16 -> 0xf, 8 -> 0x7, 4 -> 0x3, 2 -> 0x1, 1 -> 0x0 */ 1097 div = DIV_ROUND_UP_ULL(parent_rate, rate) - 1; 1098 1099 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 1100 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT, 1101 div << PLL_POST_DIV_SHIFT); 1102 } 1103 1104 const struct clk_ops clk_alpha_pll_postdiv_ops = { 1105 .recalc_rate = clk_alpha_pll_postdiv_recalc_rate, 1106 .round_rate = clk_alpha_pll_postdiv_round_rate, 1107 .set_rate = clk_alpha_pll_postdiv_set_rate, 1108 }; 1109 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ops); 1110 1111 const struct clk_ops clk_alpha_pll_postdiv_ro_ops = { 1112 .round_rate = clk_alpha_pll_postdiv_round_ro_rate, 1113 .recalc_rate = clk_alpha_pll_postdiv_recalc_rate, 1114 }; 1115 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ro_ops); 1116 1117 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 1118 const struct alpha_pll_config *config) 1119 { 1120 u32 val, mask; 1121 1122 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 1123 clk_alpha_pll_write_config(regmap, PLL_FRAC(pll), config->alpha); 1124 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), 1125 config->config_ctl_val); 1126 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), 1127 config->config_ctl_hi_val); 1128 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), 1129 config->user_ctl_val); 1130 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), 1131 config->user_ctl_hi_val); 1132 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), 1133 config->test_ctl_val); 1134 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), 1135 config->test_ctl_hi_val); 1136 1137 if (config->post_div_mask) { 1138 mask = config->post_div_mask; 1139 val = config->post_div_val; 1140 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); 1141 } 1142 1143 if (pll->flags & SUPPORTS_FSM_LEGACY_MODE) 1144 regmap_update_bits(regmap, PLL_MODE(pll), PLL_FSM_LEGACY_MODE, 1145 PLL_FSM_LEGACY_MODE); 1146 1147 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS, 1148 PLL_UPDATE_BYPASS); 1149 1150 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1151 } 1152 EXPORT_SYMBOL_GPL(clk_fabia_pll_configure); 1153 1154 static int alpha_pll_fabia_enable(struct clk_hw *hw) 1155 { 1156 int ret; 1157 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1158 u32 val, opmode_val; 1159 struct regmap *regmap = pll->clkr.regmap; 1160 1161 ret = regmap_read(regmap, PLL_MODE(pll), &val); 1162 if (ret) 1163 return ret; 1164 1165 /* If in FSM mode, just vote for it */ 1166 if (val & PLL_VOTE_FSM_ENA) { 1167 ret = clk_enable_regmap(hw); 1168 if (ret) 1169 return ret; 1170 return wait_for_pll_enable_active(pll); 1171 } 1172 1173 ret = regmap_read(regmap, PLL_OPMODE(pll), &opmode_val); 1174 if (ret) 1175 return ret; 1176 1177 /* Skip If PLL is already running */ 1178 if ((opmode_val & PLL_RUN) && (val & PLL_OUTCTRL)) 1179 return 0; 1180 1181 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1182 if (ret) 1183 return ret; 1184 1185 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 1186 if (ret) 1187 return ret; 1188 1189 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, 1190 PLL_RESET_N); 1191 if (ret) 1192 return ret; 1193 1194 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); 1195 if (ret) 1196 return ret; 1197 1198 ret = wait_for_pll_enable_lock(pll); 1199 if (ret) 1200 return ret; 1201 1202 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), 1203 PLL_OUT_MASK, PLL_OUT_MASK); 1204 if (ret) 1205 return ret; 1206 1207 return regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 1208 PLL_OUTCTRL); 1209 } 1210 1211 static void alpha_pll_fabia_disable(struct clk_hw *hw) 1212 { 1213 int ret; 1214 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1215 u32 val; 1216 struct regmap *regmap = pll->clkr.regmap; 1217 1218 ret = regmap_read(regmap, PLL_MODE(pll), &val); 1219 if (ret) 1220 return; 1221 1222 /* If in FSM mode, just unvote it */ 1223 if (val & PLL_FSM_ENA) { 1224 clk_disable_regmap(hw); 1225 return; 1226 } 1227 1228 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1229 if (ret) 1230 return; 1231 1232 /* Disable main outputs */ 1233 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); 1234 if (ret) 1235 return; 1236 1237 /* Place the PLL in STANDBY */ 1238 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 1239 } 1240 1241 static unsigned long alpha_pll_fabia_recalc_rate(struct clk_hw *hw, 1242 unsigned long parent_rate) 1243 { 1244 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1245 u32 l, frac, alpha_width = pll_alpha_width(pll); 1246 1247 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); 1248 regmap_read(pll->clkr.regmap, PLL_FRAC(pll), &frac); 1249 1250 return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width); 1251 } 1252 1253 /* 1254 * Due to limited number of bits for fractional rate programming, the 1255 * rounded up rate could be marginally higher than the requested rate. 1256 */ 1257 static int alpha_pll_check_rate_margin(struct clk_hw *hw, 1258 unsigned long rrate, unsigned long rate) 1259 { 1260 unsigned long rate_margin = rate + PLL_RATE_MARGIN; 1261 1262 if (rrate > rate_margin || rrate < rate) { 1263 pr_err("%s: Rounded rate %lu not within range [%lu, %lu)\n", 1264 clk_hw_get_name(hw), rrate, rate, rate_margin); 1265 return -EINVAL; 1266 } 1267 1268 return 0; 1269 } 1270 1271 static int alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate, 1272 unsigned long prate) 1273 { 1274 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1275 u32 l, alpha_width = pll_alpha_width(pll); 1276 unsigned long rrate; 1277 int ret; 1278 u64 a; 1279 1280 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 1281 1282 ret = alpha_pll_check_rate_margin(hw, rrate, rate); 1283 if (ret < 0) 1284 return ret; 1285 1286 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 1287 regmap_write(pll->clkr.regmap, PLL_FRAC(pll), a); 1288 1289 return __clk_alpha_pll_update_latch(pll); 1290 } 1291 1292 static int alpha_pll_fabia_prepare(struct clk_hw *hw) 1293 { 1294 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1295 const struct pll_vco *vco; 1296 struct clk_hw *parent_hw; 1297 unsigned long cal_freq, rrate; 1298 u32 cal_l, val, alpha_width = pll_alpha_width(pll); 1299 const char *name = clk_hw_get_name(hw); 1300 u64 a; 1301 int ret; 1302 1303 /* Check if calibration needs to be done i.e. PLL is in reset */ 1304 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 1305 if (ret) 1306 return ret; 1307 1308 /* Return early if calibration is not needed. */ 1309 if (val & PLL_RESET_N) 1310 return 0; 1311 1312 vco = alpha_pll_find_vco(pll, clk_hw_get_rate(hw)); 1313 if (!vco) { 1314 pr_err("%s: alpha pll not in a valid vco range\n", name); 1315 return -EINVAL; 1316 } 1317 1318 cal_freq = DIV_ROUND_CLOSEST((pll->vco_table[0].min_freq + 1319 pll->vco_table[0].max_freq) * 54, 100); 1320 1321 parent_hw = clk_hw_get_parent(hw); 1322 if (!parent_hw) 1323 return -EINVAL; 1324 1325 rrate = alpha_pll_round_rate(cal_freq, clk_hw_get_rate(parent_hw), 1326 &cal_l, &a, alpha_width); 1327 1328 ret = alpha_pll_check_rate_margin(hw, rrate, cal_freq); 1329 if (ret < 0) 1330 return ret; 1331 1332 /* Setup PLL for calibration frequency */ 1333 regmap_write(pll->clkr.regmap, PLL_CAL_L_VAL(pll), cal_l); 1334 1335 /* Bringup the PLL at calibration frequency */ 1336 ret = clk_alpha_pll_enable(hw); 1337 if (ret) { 1338 pr_err("%s: alpha pll calibration failed\n", name); 1339 return ret; 1340 } 1341 1342 clk_alpha_pll_disable(hw); 1343 1344 return 0; 1345 } 1346 1347 const struct clk_ops clk_alpha_pll_fabia_ops = { 1348 .prepare = alpha_pll_fabia_prepare, 1349 .enable = alpha_pll_fabia_enable, 1350 .disable = alpha_pll_fabia_disable, 1351 .is_enabled = clk_alpha_pll_is_enabled, 1352 .set_rate = alpha_pll_fabia_set_rate, 1353 .recalc_rate = alpha_pll_fabia_recalc_rate, 1354 .round_rate = clk_alpha_pll_round_rate, 1355 }; 1356 EXPORT_SYMBOL_GPL(clk_alpha_pll_fabia_ops); 1357 1358 const struct clk_ops clk_alpha_pll_fixed_fabia_ops = { 1359 .enable = alpha_pll_fabia_enable, 1360 .disable = alpha_pll_fabia_disable, 1361 .is_enabled = clk_alpha_pll_is_enabled, 1362 .recalc_rate = alpha_pll_fabia_recalc_rate, 1363 .round_rate = clk_alpha_pll_round_rate, 1364 }; 1365 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_fabia_ops); 1366 1367 static unsigned long clk_alpha_pll_postdiv_fabia_recalc_rate(struct clk_hw *hw, 1368 unsigned long parent_rate) 1369 { 1370 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1371 u32 i, div = 1, val; 1372 int ret; 1373 1374 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); 1375 if (ret) 1376 return ret; 1377 1378 val >>= pll->post_div_shift; 1379 val &= BIT(pll->width) - 1; 1380 1381 for (i = 0; i < pll->num_post_div; i++) { 1382 if (pll->post_div_table[i].val == val) { 1383 div = pll->post_div_table[i].div; 1384 break; 1385 } 1386 } 1387 1388 return (parent_rate / div); 1389 } 1390 1391 static unsigned long 1392 clk_trion_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 1393 { 1394 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1395 struct regmap *regmap = pll->clkr.regmap; 1396 u32 i, div = 1, val; 1397 1398 regmap_read(regmap, PLL_USER_CTL(pll), &val); 1399 1400 val >>= pll->post_div_shift; 1401 val &= PLL_POST_DIV_MASK(pll); 1402 1403 for (i = 0; i < pll->num_post_div; i++) { 1404 if (pll->post_div_table[i].val == val) { 1405 div = pll->post_div_table[i].div; 1406 break; 1407 } 1408 } 1409 1410 return (parent_rate / div); 1411 } 1412 1413 static long 1414 clk_trion_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate, 1415 unsigned long *prate) 1416 { 1417 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1418 1419 return divider_round_rate(hw, rate, prate, pll->post_div_table, 1420 pll->width, CLK_DIVIDER_ROUND_CLOSEST); 1421 }; 1422 1423 static int 1424 clk_trion_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 1425 unsigned long parent_rate) 1426 { 1427 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1428 struct regmap *regmap = pll->clkr.regmap; 1429 int i, val = 0, div; 1430 1431 div = DIV_ROUND_UP_ULL(parent_rate, rate); 1432 for (i = 0; i < pll->num_post_div; i++) { 1433 if (pll->post_div_table[i].div == div) { 1434 val = pll->post_div_table[i].val; 1435 break; 1436 } 1437 } 1438 1439 return regmap_update_bits(regmap, PLL_USER_CTL(pll), 1440 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT, 1441 val << PLL_POST_DIV_SHIFT); 1442 } 1443 1444 const struct clk_ops clk_alpha_pll_postdiv_trion_ops = { 1445 .recalc_rate = clk_trion_pll_postdiv_recalc_rate, 1446 .round_rate = clk_trion_pll_postdiv_round_rate, 1447 .set_rate = clk_trion_pll_postdiv_set_rate, 1448 }; 1449 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_trion_ops); 1450 1451 static long clk_alpha_pll_postdiv_fabia_round_rate(struct clk_hw *hw, 1452 unsigned long rate, unsigned long *prate) 1453 { 1454 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1455 1456 return divider_round_rate(hw, rate, prate, pll->post_div_table, 1457 pll->width, CLK_DIVIDER_ROUND_CLOSEST); 1458 } 1459 1460 static int clk_alpha_pll_postdiv_fabia_set_rate(struct clk_hw *hw, 1461 unsigned long rate, unsigned long parent_rate) 1462 { 1463 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1464 int i, val = 0, div, ret; 1465 1466 /* 1467 * If the PLL is in FSM mode, then treat set_rate callback as a 1468 * no-operation. 1469 */ 1470 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 1471 if (ret) 1472 return ret; 1473 1474 if (val & PLL_VOTE_FSM_ENA) 1475 return 0; 1476 1477 div = DIV_ROUND_UP_ULL(parent_rate, rate); 1478 for (i = 0; i < pll->num_post_div; i++) { 1479 if (pll->post_div_table[i].div == div) { 1480 val = pll->post_div_table[i].val; 1481 break; 1482 } 1483 } 1484 1485 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 1486 (BIT(pll->width) - 1) << pll->post_div_shift, 1487 val << pll->post_div_shift); 1488 } 1489 1490 const struct clk_ops clk_alpha_pll_postdiv_fabia_ops = { 1491 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, 1492 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate, 1493 .set_rate = clk_alpha_pll_postdiv_fabia_set_rate, 1494 }; 1495 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops); 1496 1497 /** 1498 * clk_trion_pll_configure - configure the trion pll 1499 * 1500 * @pll: clk alpha pll 1501 * @regmap: register map 1502 * @config: configuration to apply for pll 1503 */ 1504 void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 1505 const struct alpha_pll_config *config) 1506 { 1507 /* 1508 * If the bootloader left the PLL enabled it's likely that there are 1509 * RCGs that will lock up if we disable the PLL below. 1510 */ 1511 if (trion_pll_is_enabled(pll, regmap)) { 1512 pr_debug("Trion PLL is already enabled, skipping configuration\n"); 1513 return; 1514 } 1515 1516 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 1517 regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL); 1518 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 1519 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), 1520 config->config_ctl_val); 1521 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), 1522 config->config_ctl_hi_val); 1523 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), 1524 config->config_ctl_hi1_val); 1525 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), 1526 config->user_ctl_val); 1527 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), 1528 config->user_ctl_hi_val); 1529 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), 1530 config->user_ctl_hi1_val); 1531 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), 1532 config->test_ctl_val); 1533 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), 1534 config->test_ctl_hi_val); 1535 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), 1536 config->test_ctl_hi1_val); 1537 1538 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS, 1539 PLL_UPDATE_BYPASS); 1540 1541 /* Disable PLL output */ 1542 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1543 1544 /* Set operation mode to OFF */ 1545 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 1546 1547 /* Place the PLL in STANDBY mode */ 1548 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1549 } 1550 EXPORT_SYMBOL_GPL(clk_trion_pll_configure); 1551 1552 /* 1553 * The TRION PLL requires a power-on self-calibration which happens when the 1554 * PLL comes out of reset. Calibrate in case it is not completed. 1555 */ 1556 static int __alpha_pll_trion_prepare(struct clk_hw *hw, u32 pcal_done) 1557 { 1558 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1559 u32 val; 1560 int ret; 1561 1562 /* Return early if calibration is not needed. */ 1563 regmap_read(pll->clkr.regmap, PLL_STATUS(pll), &val); 1564 if (val & pcal_done) 1565 return 0; 1566 1567 /* On/off to calibrate */ 1568 ret = clk_trion_pll_enable(hw); 1569 if (!ret) 1570 clk_trion_pll_disable(hw); 1571 1572 return ret; 1573 } 1574 1575 static int alpha_pll_trion_prepare(struct clk_hw *hw) 1576 { 1577 return __alpha_pll_trion_prepare(hw, TRION_PCAL_DONE); 1578 } 1579 1580 static int alpha_pll_lucid_prepare(struct clk_hw *hw) 1581 { 1582 return __alpha_pll_trion_prepare(hw, LUCID_PCAL_DONE); 1583 } 1584 1585 static int __alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate, 1586 unsigned long prate, u32 latch_bit, u32 latch_ack) 1587 { 1588 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1589 unsigned long rrate; 1590 u32 val, l, alpha_width = pll_alpha_width(pll); 1591 u64 a; 1592 int ret; 1593 1594 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 1595 1596 ret = alpha_pll_check_rate_margin(hw, rrate, rate); 1597 if (ret < 0) 1598 return ret; 1599 1600 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 1601 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 1602 1603 /* Latch the PLL input */ 1604 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, latch_bit); 1605 if (ret) 1606 return ret; 1607 1608 /* Wait for 2 reference cycles before checking the ACK bit. */ 1609 udelay(1); 1610 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 1611 if (!(val & latch_ack)) { 1612 pr_err("Lucid PLL latch failed. Output may be unstable!\n"); 1613 return -EINVAL; 1614 } 1615 1616 /* Return the latch input to 0 */ 1617 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, 0); 1618 if (ret) 1619 return ret; 1620 1621 if (clk_hw_is_enabled(hw)) { 1622 ret = wait_for_pll_enable_lock(pll); 1623 if (ret) 1624 return ret; 1625 } 1626 1627 /* Wait for PLL output to stabilize */ 1628 udelay(100); 1629 return 0; 1630 } 1631 1632 static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate, 1633 unsigned long prate) 1634 { 1635 return __alpha_pll_trion_set_rate(hw, rate, prate, PLL_UPDATE, ALPHA_PLL_ACK_LATCH); 1636 } 1637 1638 const struct clk_ops clk_alpha_pll_trion_ops = { 1639 .prepare = alpha_pll_trion_prepare, 1640 .enable = clk_trion_pll_enable, 1641 .disable = clk_trion_pll_disable, 1642 .is_enabled = clk_trion_pll_is_enabled, 1643 .recalc_rate = clk_trion_pll_recalc_rate, 1644 .round_rate = clk_alpha_pll_round_rate, 1645 .set_rate = alpha_pll_trion_set_rate, 1646 }; 1647 EXPORT_SYMBOL_GPL(clk_alpha_pll_trion_ops); 1648 1649 const struct clk_ops clk_alpha_pll_lucid_ops = { 1650 .prepare = alpha_pll_lucid_prepare, 1651 .enable = clk_trion_pll_enable, 1652 .disable = clk_trion_pll_disable, 1653 .is_enabled = clk_trion_pll_is_enabled, 1654 .recalc_rate = clk_trion_pll_recalc_rate, 1655 .round_rate = clk_alpha_pll_round_rate, 1656 .set_rate = alpha_pll_trion_set_rate, 1657 }; 1658 EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_ops); 1659 1660 const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = { 1661 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, 1662 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate, 1663 .set_rate = clk_alpha_pll_postdiv_fabia_set_rate, 1664 }; 1665 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_ops); 1666 1667 void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 1668 const struct alpha_pll_config *config) 1669 { 1670 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 1671 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 1672 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), 1673 config->user_ctl_val); 1674 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), 1675 config->config_ctl_val); 1676 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), 1677 config->config_ctl_hi_val); 1678 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), 1679 config->test_ctl_val); 1680 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), 1681 config->test_ctl_hi_val); 1682 } 1683 EXPORT_SYMBOL_GPL(clk_agera_pll_configure); 1684 1685 static int clk_alpha_pll_agera_set_rate(struct clk_hw *hw, unsigned long rate, 1686 unsigned long prate) 1687 { 1688 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1689 u32 l, alpha_width = pll_alpha_width(pll); 1690 int ret; 1691 unsigned long rrate; 1692 u64 a; 1693 1694 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 1695 ret = alpha_pll_check_rate_margin(hw, rrate, rate); 1696 if (ret < 0) 1697 return ret; 1698 1699 /* change L_VAL without having to go through the power on sequence */ 1700 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 1701 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 1702 1703 if (clk_hw_is_enabled(hw)) 1704 return wait_for_pll_enable_lock(pll); 1705 1706 return 0; 1707 } 1708 1709 const struct clk_ops clk_alpha_pll_agera_ops = { 1710 .enable = clk_alpha_pll_enable, 1711 .disable = clk_alpha_pll_disable, 1712 .is_enabled = clk_alpha_pll_is_enabled, 1713 .recalc_rate = alpha_pll_fabia_recalc_rate, 1714 .round_rate = clk_alpha_pll_round_rate, 1715 .set_rate = clk_alpha_pll_agera_set_rate, 1716 }; 1717 EXPORT_SYMBOL_GPL(clk_alpha_pll_agera_ops); 1718 1719 static int alpha_pll_lucid_5lpe_enable(struct clk_hw *hw) 1720 { 1721 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1722 u32 val; 1723 int ret; 1724 1725 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); 1726 if (ret) 1727 return ret; 1728 1729 /* If in FSM mode, just vote for it */ 1730 if (val & LUCID_5LPE_ENABLE_VOTE_RUN) { 1731 ret = clk_enable_regmap(hw); 1732 if (ret) 1733 return ret; 1734 return wait_for_pll_enable_lock(pll); 1735 } 1736 1737 /* Check if PLL is already enabled, return if enabled */ 1738 ret = trion_pll_is_enabled(pll, pll->clkr.regmap); 1739 if (ret < 0) 1740 return ret; 1741 1742 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1743 if (ret) 1744 return ret; 1745 1746 regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_RUN); 1747 1748 ret = wait_for_pll_enable_lock(pll); 1749 if (ret) 1750 return ret; 1751 1752 /* Enable the PLL outputs */ 1753 ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK); 1754 if (ret) 1755 return ret; 1756 1757 /* Enable the global PLL outputs */ 1758 return regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); 1759 } 1760 1761 static void alpha_pll_lucid_5lpe_disable(struct clk_hw *hw) 1762 { 1763 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1764 u32 val; 1765 int ret; 1766 1767 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); 1768 if (ret) 1769 return; 1770 1771 /* If in FSM mode, just unvote it */ 1772 if (val & LUCID_5LPE_ENABLE_VOTE_RUN) { 1773 clk_disable_regmap(hw); 1774 return; 1775 } 1776 1777 /* Disable the global PLL output */ 1778 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1779 if (ret) 1780 return; 1781 1782 /* Disable the PLL outputs */ 1783 ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); 1784 if (ret) 1785 return; 1786 1787 /* Place the PLL mode in STANDBY */ 1788 regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_STANDBY); 1789 } 1790 1791 /* 1792 * The Lucid 5LPE PLL requires a power-on self-calibration which happens 1793 * when the PLL comes out of reset. Calibrate in case it is not completed. 1794 */ 1795 static int alpha_pll_lucid_5lpe_prepare(struct clk_hw *hw) 1796 { 1797 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1798 struct clk_hw *p; 1799 u32 val = 0; 1800 int ret; 1801 1802 /* Return early if calibration is not needed. */ 1803 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 1804 if (val & LUCID_5LPE_PCAL_DONE) 1805 return 0; 1806 1807 p = clk_hw_get_parent(hw); 1808 if (!p) 1809 return -EINVAL; 1810 1811 ret = alpha_pll_lucid_5lpe_enable(hw); 1812 if (ret) 1813 return ret; 1814 1815 alpha_pll_lucid_5lpe_disable(hw); 1816 1817 return 0; 1818 } 1819 1820 static int alpha_pll_lucid_5lpe_set_rate(struct clk_hw *hw, unsigned long rate, 1821 unsigned long prate) 1822 { 1823 return __alpha_pll_trion_set_rate(hw, rate, prate, 1824 LUCID_5LPE_PLL_LATCH_INPUT, 1825 LUCID_5LPE_ALPHA_PLL_ACK_LATCH); 1826 } 1827 1828 static int __clk_lucid_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 1829 unsigned long parent_rate, 1830 unsigned long enable_vote_run) 1831 { 1832 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1833 struct regmap *regmap = pll->clkr.regmap; 1834 int i, val, div, ret; 1835 u32 mask; 1836 1837 /* 1838 * If the PLL is in FSM mode, then treat set_rate callback as a 1839 * no-operation. 1840 */ 1841 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); 1842 if (ret) 1843 return ret; 1844 1845 if (val & enable_vote_run) 1846 return 0; 1847 1848 if (!pll->post_div_table) { 1849 pr_err("Missing the post_div_table for the %s PLL\n", 1850 clk_hw_get_name(&pll->clkr.hw)); 1851 return -EINVAL; 1852 } 1853 1854 div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); 1855 for (i = 0; i < pll->num_post_div; i++) { 1856 if (pll->post_div_table[i].div == div) { 1857 val = pll->post_div_table[i].val; 1858 break; 1859 } 1860 } 1861 1862 mask = GENMASK(pll->width + pll->post_div_shift - 1, pll->post_div_shift); 1863 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 1864 mask, val << pll->post_div_shift); 1865 } 1866 1867 static int clk_lucid_5lpe_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 1868 unsigned long parent_rate) 1869 { 1870 return __clk_lucid_pll_postdiv_set_rate(hw, rate, parent_rate, LUCID_5LPE_ENABLE_VOTE_RUN); 1871 } 1872 1873 const struct clk_ops clk_alpha_pll_lucid_5lpe_ops = { 1874 .prepare = alpha_pll_lucid_5lpe_prepare, 1875 .enable = alpha_pll_lucid_5lpe_enable, 1876 .disable = alpha_pll_lucid_5lpe_disable, 1877 .is_enabled = clk_trion_pll_is_enabled, 1878 .recalc_rate = clk_trion_pll_recalc_rate, 1879 .round_rate = clk_alpha_pll_round_rate, 1880 .set_rate = alpha_pll_lucid_5lpe_set_rate, 1881 }; 1882 EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_5lpe_ops); 1883 1884 const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops = { 1885 .enable = alpha_pll_lucid_5lpe_enable, 1886 .disable = alpha_pll_lucid_5lpe_disable, 1887 .is_enabled = clk_trion_pll_is_enabled, 1888 .recalc_rate = clk_trion_pll_recalc_rate, 1889 .round_rate = clk_alpha_pll_round_rate, 1890 }; 1891 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_5lpe_ops); 1892 1893 const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops = { 1894 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, 1895 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate, 1896 .set_rate = clk_lucid_5lpe_pll_postdiv_set_rate, 1897 }; 1898 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_5lpe_ops); 1899 1900 void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 1901 const struct alpha_pll_config *config) 1902 { 1903 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 1904 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 1905 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 1906 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); 1907 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); 1908 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); 1909 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); 1910 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), config->user_ctl_hi1_val); 1911 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 1912 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 1913 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); 1914 1915 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, 0); 1916 1917 /* Disable PLL output */ 1918 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1919 1920 /* Set operation mode to OFF */ 1921 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 1922 1923 /* Place the PLL in STANDBY mode */ 1924 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1925 } 1926 EXPORT_SYMBOL_GPL(clk_zonda_pll_configure); 1927 1928 static int clk_zonda_pll_enable(struct clk_hw *hw) 1929 { 1930 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1931 struct regmap *regmap = pll->clkr.regmap; 1932 u32 val; 1933 int ret; 1934 1935 regmap_read(regmap, PLL_MODE(pll), &val); 1936 1937 /* If in FSM mode, just vote for it */ 1938 if (val & PLL_VOTE_FSM_ENA) { 1939 ret = clk_enable_regmap(hw); 1940 if (ret) 1941 return ret; 1942 return wait_for_pll_enable_active(pll); 1943 } 1944 1945 /* Get the PLL out of bypass mode */ 1946 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL); 1947 1948 /* 1949 * H/W requires a 1us delay between disabling the bypass and 1950 * de-asserting the reset. 1951 */ 1952 udelay(1); 1953 1954 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1955 1956 /* Set operation mode to RUN */ 1957 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); 1958 1959 regmap_read(regmap, PLL_TEST_CTL(pll), &val); 1960 1961 /* If cfa mode then poll for freq lock */ 1962 if (val & ZONDA_STAY_IN_CFA) 1963 ret = wait_for_zonda_pll_freq_lock(pll); 1964 else 1965 ret = wait_for_pll_enable_lock(pll); 1966 if (ret) 1967 return ret; 1968 1969 /* Enable the PLL outputs */ 1970 regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, ZONDA_PLL_OUT_MASK); 1971 1972 /* Enable the global PLL outputs */ 1973 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); 1974 1975 return 0; 1976 } 1977 1978 static void clk_zonda_pll_disable(struct clk_hw *hw) 1979 { 1980 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1981 struct regmap *regmap = pll->clkr.regmap; 1982 u32 val; 1983 1984 regmap_read(regmap, PLL_MODE(pll), &val); 1985 1986 /* If in FSM mode, just unvote it */ 1987 if (val & PLL_VOTE_FSM_ENA) { 1988 clk_disable_regmap(hw); 1989 return; 1990 } 1991 1992 /* Disable the global PLL output */ 1993 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1994 1995 /* Disable the PLL outputs */ 1996 regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, 0); 1997 1998 /* Put the PLL in bypass and reset */ 1999 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N | PLL_BYPASSNL, 0); 2000 2001 /* Place the PLL mode in OFF state */ 2002 regmap_write(regmap, PLL_OPMODE(pll), 0x0); 2003 } 2004 2005 static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate, 2006 unsigned long prate) 2007 { 2008 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2009 unsigned long rrate; 2010 u32 test_ctl_val; 2011 u32 l, alpha_width = pll_alpha_width(pll); 2012 u64 a; 2013 int ret; 2014 2015 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 2016 2017 ret = alpha_pll_check_rate_margin(hw, rrate, rate); 2018 if (ret < 0) 2019 return ret; 2020 2021 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 2022 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 2023 2024 /* Wait before polling for the frequency latch */ 2025 udelay(5); 2026 2027 /* Read stay in cfa mode */ 2028 regmap_read(pll->clkr.regmap, PLL_TEST_CTL(pll), &test_ctl_val); 2029 2030 /* If cfa mode then poll for freq lock */ 2031 if (test_ctl_val & ZONDA_STAY_IN_CFA) 2032 ret = wait_for_zonda_pll_freq_lock(pll); 2033 else 2034 ret = wait_for_pll_enable_lock(pll); 2035 if (ret) 2036 return ret; 2037 2038 /* Wait for PLL output to stabilize */ 2039 udelay(100); 2040 return 0; 2041 } 2042 2043 const struct clk_ops clk_alpha_pll_zonda_ops = { 2044 .enable = clk_zonda_pll_enable, 2045 .disable = clk_zonda_pll_disable, 2046 .is_enabled = clk_trion_pll_is_enabled, 2047 .recalc_rate = clk_trion_pll_recalc_rate, 2048 .round_rate = clk_alpha_pll_round_rate, 2049 .set_rate = clk_zonda_pll_set_rate, 2050 }; 2051 EXPORT_SYMBOL_GPL(clk_alpha_pll_zonda_ops); 2052 2053 void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 2054 const struct alpha_pll_config *config) 2055 { 2056 u32 lval = config->l; 2057 2058 lval |= TRION_PLL_CAL_VAL << LUCID_EVO_PLL_CAL_L_VAL_SHIFT; 2059 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval); 2060 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 2061 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 2062 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); 2063 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); 2064 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); 2065 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); 2066 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 2067 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 2068 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); 2069 2070 /* Disable PLL output */ 2071 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2072 2073 /* Set operation mode to STANDBY and de-assert the reset */ 2074 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2075 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 2076 } 2077 EXPORT_SYMBOL_GPL(clk_lucid_evo_pll_configure); 2078 2079 static int alpha_pll_lucid_evo_enable(struct clk_hw *hw) 2080 { 2081 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2082 struct regmap *regmap = pll->clkr.regmap; 2083 u32 val; 2084 int ret; 2085 2086 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); 2087 if (ret) 2088 return ret; 2089 2090 /* If in FSM mode, just vote for it */ 2091 if (val & LUCID_EVO_ENABLE_VOTE_RUN) { 2092 ret = clk_enable_regmap(hw); 2093 if (ret) 2094 return ret; 2095 return wait_for_pll_enable_lock(pll); 2096 } 2097 2098 /* Check if PLL is already enabled */ 2099 ret = trion_pll_is_enabled(pll, regmap); 2100 if (ret < 0) { 2101 return ret; 2102 } else if (ret) { 2103 pr_warn("%s PLL is already enabled\n", clk_hw_get_name(&pll->clkr.hw)); 2104 return 0; 2105 } 2106 2107 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 2108 if (ret) 2109 return ret; 2110 2111 /* Set operation mode to RUN */ 2112 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); 2113 2114 ret = wait_for_pll_enable_lock(pll); 2115 if (ret) 2116 return ret; 2117 2118 /* Enable the PLL outputs */ 2119 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK); 2120 if (ret) 2121 return ret; 2122 2123 /* Enable the global PLL outputs */ 2124 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); 2125 if (ret) 2126 return ret; 2127 2128 /* Ensure that the write above goes through before returning. */ 2129 mb(); 2130 return ret; 2131 } 2132 2133 static void _alpha_pll_lucid_evo_disable(struct clk_hw *hw, bool reset) 2134 { 2135 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2136 struct regmap *regmap = pll->clkr.regmap; 2137 u32 val; 2138 int ret; 2139 2140 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); 2141 if (ret) 2142 return; 2143 2144 /* If in FSM mode, just unvote it */ 2145 if (val & LUCID_EVO_ENABLE_VOTE_RUN) { 2146 clk_disable_regmap(hw); 2147 return; 2148 } 2149 2150 /* Disable the global PLL output */ 2151 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2152 if (ret) 2153 return; 2154 2155 /* Disable the PLL outputs */ 2156 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); 2157 if (ret) 2158 return; 2159 2160 /* Place the PLL mode in STANDBY */ 2161 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2162 2163 if (reset) 2164 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, 0); 2165 } 2166 2167 static int _alpha_pll_lucid_evo_prepare(struct clk_hw *hw, bool reset) 2168 { 2169 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2170 struct clk_hw *p; 2171 u32 val = 0; 2172 int ret; 2173 2174 /* Return early if calibration is not needed. */ 2175 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 2176 if (!(val & LUCID_EVO_PCAL_NOT_DONE)) 2177 return 0; 2178 2179 p = clk_hw_get_parent(hw); 2180 if (!p) 2181 return -EINVAL; 2182 2183 ret = alpha_pll_lucid_evo_enable(hw); 2184 if (ret) 2185 return ret; 2186 2187 _alpha_pll_lucid_evo_disable(hw, reset); 2188 2189 return 0; 2190 } 2191 2192 static void alpha_pll_lucid_evo_disable(struct clk_hw *hw) 2193 { 2194 _alpha_pll_lucid_evo_disable(hw, false); 2195 } 2196 2197 static int alpha_pll_lucid_evo_prepare(struct clk_hw *hw) 2198 { 2199 return _alpha_pll_lucid_evo_prepare(hw, false); 2200 } 2201 2202 static void alpha_pll_reset_lucid_evo_disable(struct clk_hw *hw) 2203 { 2204 _alpha_pll_lucid_evo_disable(hw, true); 2205 } 2206 2207 static int alpha_pll_reset_lucid_evo_prepare(struct clk_hw *hw) 2208 { 2209 return _alpha_pll_lucid_evo_prepare(hw, true); 2210 } 2211 2212 static unsigned long alpha_pll_lucid_evo_recalc_rate(struct clk_hw *hw, 2213 unsigned long parent_rate) 2214 { 2215 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2216 struct regmap *regmap = pll->clkr.regmap; 2217 u32 l, frac; 2218 2219 regmap_read(regmap, PLL_L_VAL(pll), &l); 2220 l &= LUCID_EVO_PLL_L_VAL_MASK; 2221 regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac); 2222 2223 return alpha_pll_calc_rate(parent_rate, l, frac, pll_alpha_width(pll)); 2224 } 2225 2226 static int clk_lucid_evo_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 2227 unsigned long parent_rate) 2228 { 2229 return __clk_lucid_pll_postdiv_set_rate(hw, rate, parent_rate, LUCID_EVO_ENABLE_VOTE_RUN); 2230 } 2231 2232 const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops = { 2233 .enable = alpha_pll_lucid_evo_enable, 2234 .disable = alpha_pll_lucid_evo_disable, 2235 .is_enabled = clk_trion_pll_is_enabled, 2236 .recalc_rate = alpha_pll_lucid_evo_recalc_rate, 2237 .round_rate = clk_alpha_pll_round_rate, 2238 }; 2239 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_evo_ops); 2240 2241 const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops = { 2242 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, 2243 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate, 2244 .set_rate = clk_lucid_evo_pll_postdiv_set_rate, 2245 }; 2246 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_evo_ops); 2247 2248 const struct clk_ops clk_alpha_pll_lucid_evo_ops = { 2249 .prepare = alpha_pll_lucid_evo_prepare, 2250 .enable = alpha_pll_lucid_evo_enable, 2251 .disable = alpha_pll_lucid_evo_disable, 2252 .is_enabled = clk_trion_pll_is_enabled, 2253 .recalc_rate = alpha_pll_lucid_evo_recalc_rate, 2254 .round_rate = clk_alpha_pll_round_rate, 2255 .set_rate = alpha_pll_lucid_5lpe_set_rate, 2256 }; 2257 EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_evo_ops); 2258 2259 const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops = { 2260 .prepare = alpha_pll_reset_lucid_evo_prepare, 2261 .enable = alpha_pll_lucid_evo_enable, 2262 .disable = alpha_pll_reset_lucid_evo_disable, 2263 .is_enabled = clk_trion_pll_is_enabled, 2264 .recalc_rate = alpha_pll_lucid_evo_recalc_rate, 2265 .round_rate = clk_alpha_pll_round_rate, 2266 .set_rate = alpha_pll_lucid_5lpe_set_rate, 2267 }; 2268 EXPORT_SYMBOL_GPL(clk_alpha_pll_reset_lucid_evo_ops); 2269 2270 void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 2271 const struct alpha_pll_config *config) 2272 { 2273 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 2274 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); 2275 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); 2276 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 2277 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 2278 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 2279 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); 2280 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); 2281 2282 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2283 2284 regmap_update_bits(regmap, PLL_MODE(pll), 2285 PLL_RESET_N | PLL_BYPASSNL | PLL_OUTCTRL, 2286 PLL_RESET_N | PLL_BYPASSNL); 2287 } 2288 EXPORT_SYMBOL_GPL(clk_rivian_evo_pll_configure); 2289 2290 static unsigned long clk_rivian_evo_pll_recalc_rate(struct clk_hw *hw, 2291 unsigned long parent_rate) 2292 { 2293 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2294 u32 l; 2295 2296 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); 2297 2298 return parent_rate * l; 2299 } 2300 2301 static long clk_rivian_evo_pll_round_rate(struct clk_hw *hw, unsigned long rate, 2302 unsigned long *prate) 2303 { 2304 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2305 unsigned long min_freq, max_freq; 2306 u32 l; 2307 u64 a; 2308 2309 rate = alpha_pll_round_rate(rate, *prate, &l, &a, 0); 2310 if (!pll->vco_table || alpha_pll_find_vco(pll, rate)) 2311 return rate; 2312 2313 min_freq = pll->vco_table[0].min_freq; 2314 max_freq = pll->vco_table[pll->num_vco - 1].max_freq; 2315 2316 return clamp(rate, min_freq, max_freq); 2317 } 2318 2319 const struct clk_ops clk_alpha_pll_rivian_evo_ops = { 2320 .enable = alpha_pll_lucid_5lpe_enable, 2321 .disable = alpha_pll_lucid_5lpe_disable, 2322 .is_enabled = clk_trion_pll_is_enabled, 2323 .recalc_rate = clk_rivian_evo_pll_recalc_rate, 2324 .round_rate = clk_rivian_evo_pll_round_rate, 2325 }; 2326 EXPORT_SYMBOL_GPL(clk_alpha_pll_rivian_evo_ops); 2327