1 // SPDX-License-Identifier: GPL-2.0-only 2 /* cpu_feature_enabled() cannot be used this early */ 3 #define USE_EARLY_PGTABLE_L5 4 5 #include <linux/memblock.h> 6 #include <linux/linkage.h> 7 #include <linux/bitops.h> 8 #include <linux/kernel.h> 9 #include <linux/export.h> 10 #include <linux/percpu.h> 11 #include <linux/string.h> 12 #include <linux/ctype.h> 13 #include <linux/delay.h> 14 #include <linux/sched/mm.h> 15 #include <linux/sched/clock.h> 16 #include <linux/sched/task.h> 17 #include <linux/sched/smt.h> 18 #include <linux/init.h> 19 #include <linux/kprobes.h> 20 #include <linux/kgdb.h> 21 #include <linux/smp.h> 22 #include <linux/io.h> 23 #include <linux/syscore_ops.h> 24 #include <linux/pgtable.h> 25 #include <linux/stackprotector.h> 26 27 #include <asm/cmdline.h> 28 #include <asm/perf_event.h> 29 #include <asm/mmu_context.h> 30 #include <asm/doublefault.h> 31 #include <asm/archrandom.h> 32 #include <asm/hypervisor.h> 33 #include <asm/processor.h> 34 #include <asm/tlbflush.h> 35 #include <asm/debugreg.h> 36 #include <asm/sections.h> 37 #include <asm/vsyscall.h> 38 #include <linux/topology.h> 39 #include <linux/cpumask.h> 40 #include <linux/atomic.h> 41 #include <asm/proto.h> 42 #include <asm/setup.h> 43 #include <asm/apic.h> 44 #include <asm/desc.h> 45 #include <asm/fpu/api.h> 46 #include <asm/mtrr.h> 47 #include <asm/hwcap2.h> 48 #include <linux/numa.h> 49 #include <asm/numa.h> 50 #include <asm/asm.h> 51 #include <asm/bugs.h> 52 #include <asm/cpu.h> 53 #include <asm/mce.h> 54 #include <asm/msr.h> 55 #include <asm/cacheinfo.h> 56 #include <asm/memtype.h> 57 #include <asm/microcode.h> 58 #include <asm/microcode_intel.h> 59 #include <asm/intel-family.h> 60 #include <asm/cpu_device_id.h> 61 #include <asm/uv/uv.h> 62 #include <asm/sigframe.h> 63 #include <asm/traps.h> 64 #include <asm/sev.h> 65 66 #include "cpu.h" 67 68 u32 elf_hwcap2 __read_mostly; 69 70 /* all of these masks are initialized in setup_cpu_local_masks() */ 71 cpumask_var_t cpu_initialized_mask; 72 cpumask_var_t cpu_callout_mask; 73 cpumask_var_t cpu_callin_mask; 74 75 /* representing cpus for which sibling maps can be computed */ 76 cpumask_var_t cpu_sibling_setup_mask; 77 78 /* Number of siblings per CPU package */ 79 int smp_num_siblings = 1; 80 EXPORT_SYMBOL(smp_num_siblings); 81 82 /* Last level cache ID of each logical CPU */ 83 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; 84 85 u16 get_llc_id(unsigned int cpu) 86 { 87 return per_cpu(cpu_llc_id, cpu); 88 } 89 EXPORT_SYMBOL_GPL(get_llc_id); 90 91 /* L2 cache ID of each logical CPU */ 92 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_l2c_id) = BAD_APICID; 93 94 static struct ppin_info { 95 int feature; 96 int msr_ppin_ctl; 97 int msr_ppin; 98 } ppin_info[] = { 99 [X86_VENDOR_INTEL] = { 100 .feature = X86_FEATURE_INTEL_PPIN, 101 .msr_ppin_ctl = MSR_PPIN_CTL, 102 .msr_ppin = MSR_PPIN 103 }, 104 [X86_VENDOR_AMD] = { 105 .feature = X86_FEATURE_AMD_PPIN, 106 .msr_ppin_ctl = MSR_AMD_PPIN_CTL, 107 .msr_ppin = MSR_AMD_PPIN 108 }, 109 }; 110 111 static const struct x86_cpu_id ppin_cpuids[] = { 112 X86_MATCH_FEATURE(X86_FEATURE_AMD_PPIN, &ppin_info[X86_VENDOR_AMD]), 113 X86_MATCH_FEATURE(X86_FEATURE_INTEL_PPIN, &ppin_info[X86_VENDOR_INTEL]), 114 115 /* Legacy models without CPUID enumeration */ 116 X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE_X, &ppin_info[X86_VENDOR_INTEL]), 117 X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, &ppin_info[X86_VENDOR_INTEL]), 118 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_D, &ppin_info[X86_VENDOR_INTEL]), 119 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, &ppin_info[X86_VENDOR_INTEL]), 120 X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X, &ppin_info[X86_VENDOR_INTEL]), 121 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, &ppin_info[X86_VENDOR_INTEL]), 122 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, &ppin_info[X86_VENDOR_INTEL]), 123 X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, &ppin_info[X86_VENDOR_INTEL]), 124 X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNL, &ppin_info[X86_VENDOR_INTEL]), 125 X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNM, &ppin_info[X86_VENDOR_INTEL]), 126 127 {} 128 }; 129 130 static void ppin_init(struct cpuinfo_x86 *c) 131 { 132 const struct x86_cpu_id *id; 133 unsigned long long val; 134 struct ppin_info *info; 135 136 id = x86_match_cpu(ppin_cpuids); 137 if (!id) 138 return; 139 140 /* 141 * Testing the presence of the MSR is not enough. Need to check 142 * that the PPIN_CTL allows reading of the PPIN. 143 */ 144 info = (struct ppin_info *)id->driver_data; 145 146 if (rdmsrl_safe(info->msr_ppin_ctl, &val)) 147 goto clear_ppin; 148 149 if ((val & 3UL) == 1UL) { 150 /* PPIN locked in disabled mode */ 151 goto clear_ppin; 152 } 153 154 /* If PPIN is disabled, try to enable */ 155 if (!(val & 2UL)) { 156 wrmsrl_safe(info->msr_ppin_ctl, val | 2UL); 157 rdmsrl_safe(info->msr_ppin_ctl, &val); 158 } 159 160 /* Is the enable bit set? */ 161 if (val & 2UL) { 162 c->ppin = __rdmsr(info->msr_ppin); 163 set_cpu_cap(c, info->feature); 164 return; 165 } 166 167 clear_ppin: 168 clear_cpu_cap(c, info->feature); 169 } 170 171 /* correctly size the local cpu masks */ 172 void __init setup_cpu_local_masks(void) 173 { 174 alloc_bootmem_cpumask_var(&cpu_initialized_mask); 175 alloc_bootmem_cpumask_var(&cpu_callin_mask); 176 alloc_bootmem_cpumask_var(&cpu_callout_mask); 177 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); 178 } 179 180 static void default_init(struct cpuinfo_x86 *c) 181 { 182 #ifdef CONFIG_X86_64 183 cpu_detect_cache_sizes(c); 184 #else 185 /* Not much we can do here... */ 186 /* Check if at least it has cpuid */ 187 if (c->cpuid_level == -1) { 188 /* No cpuid. It must be an ancient CPU */ 189 if (c->x86 == 4) 190 strcpy(c->x86_model_id, "486"); 191 else if (c->x86 == 3) 192 strcpy(c->x86_model_id, "386"); 193 } 194 #endif 195 } 196 197 static const struct cpu_dev default_cpu = { 198 .c_init = default_init, 199 .c_vendor = "Unknown", 200 .c_x86_vendor = X86_VENDOR_UNKNOWN, 201 }; 202 203 static const struct cpu_dev *this_cpu = &default_cpu; 204 205 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { 206 #ifdef CONFIG_X86_64 207 /* 208 * We need valid kernel segments for data and code in long mode too 209 * IRET will check the segment types kkeil 2000/10/28 210 * Also sysret mandates a special GDT layout 211 * 212 * TLS descriptors are currently at a different place compared to i386. 213 * Hopefully nobody expects them at a fixed place (Wine?) 214 */ 215 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), 216 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), 217 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), 218 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), 219 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), 220 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), 221 #else 222 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), 223 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 224 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), 225 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), 226 /* 227 * Segments used for calling PnP BIOS have byte granularity. 228 * They code segments and data segments have fixed 64k limits, 229 * the transfer segment sizes are set at run time. 230 */ 231 /* 32-bit code */ 232 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 233 /* 16-bit code */ 234 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 235 /* 16-bit data */ 236 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), 237 /* 16-bit data */ 238 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), 239 /* 16-bit data */ 240 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), 241 /* 242 * The APM segments have byte granularity and their bases 243 * are set at run time. All have 64k limits. 244 */ 245 /* 32-bit code */ 246 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 247 /* 16-bit code */ 248 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 249 /* data */ 250 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), 251 252 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 253 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 254 #endif 255 } }; 256 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); 257 258 #ifdef CONFIG_X86_64 259 static int __init x86_nopcid_setup(char *s) 260 { 261 /* nopcid doesn't accept parameters */ 262 if (s) 263 return -EINVAL; 264 265 /* do not emit a message if the feature is not present */ 266 if (!boot_cpu_has(X86_FEATURE_PCID)) 267 return 0; 268 269 setup_clear_cpu_cap(X86_FEATURE_PCID); 270 pr_info("nopcid: PCID feature disabled\n"); 271 return 0; 272 } 273 early_param("nopcid", x86_nopcid_setup); 274 #endif 275 276 static int __init x86_noinvpcid_setup(char *s) 277 { 278 /* noinvpcid doesn't accept parameters */ 279 if (s) 280 return -EINVAL; 281 282 /* do not emit a message if the feature is not present */ 283 if (!boot_cpu_has(X86_FEATURE_INVPCID)) 284 return 0; 285 286 setup_clear_cpu_cap(X86_FEATURE_INVPCID); 287 pr_info("noinvpcid: INVPCID feature disabled\n"); 288 return 0; 289 } 290 early_param("noinvpcid", x86_noinvpcid_setup); 291 292 #ifdef CONFIG_X86_32 293 static int cachesize_override = -1; 294 static int disable_x86_serial_nr = 1; 295 296 static int __init cachesize_setup(char *str) 297 { 298 get_option(&str, &cachesize_override); 299 return 1; 300 } 301 __setup("cachesize=", cachesize_setup); 302 303 /* Standard macro to see if a specific flag is changeable */ 304 static inline int flag_is_changeable_p(u32 flag) 305 { 306 u32 f1, f2; 307 308 /* 309 * Cyrix and IDT cpus allow disabling of CPUID 310 * so the code below may return different results 311 * when it is executed before and after enabling 312 * the CPUID. Add "volatile" to not allow gcc to 313 * optimize the subsequent calls to this function. 314 */ 315 asm volatile ("pushfl \n\t" 316 "pushfl \n\t" 317 "popl %0 \n\t" 318 "movl %0, %1 \n\t" 319 "xorl %2, %0 \n\t" 320 "pushl %0 \n\t" 321 "popfl \n\t" 322 "pushfl \n\t" 323 "popl %0 \n\t" 324 "popfl \n\t" 325 326 : "=&r" (f1), "=&r" (f2) 327 : "ir" (flag)); 328 329 return ((f1^f2) & flag) != 0; 330 } 331 332 /* Probe for the CPUID instruction */ 333 int have_cpuid_p(void) 334 { 335 return flag_is_changeable_p(X86_EFLAGS_ID); 336 } 337 338 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 339 { 340 unsigned long lo, hi; 341 342 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) 343 return; 344 345 /* Disable processor serial number: */ 346 347 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 348 lo |= 0x200000; 349 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 350 351 pr_notice("CPU serial number disabled.\n"); 352 clear_cpu_cap(c, X86_FEATURE_PN); 353 354 /* Disabling the serial number may affect the cpuid level */ 355 c->cpuid_level = cpuid_eax(0); 356 } 357 358 static int __init x86_serial_nr_setup(char *s) 359 { 360 disable_x86_serial_nr = 0; 361 return 1; 362 } 363 __setup("serialnumber", x86_serial_nr_setup); 364 #else 365 static inline int flag_is_changeable_p(u32 flag) 366 { 367 return 1; 368 } 369 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 370 { 371 } 372 #endif 373 374 static __always_inline void setup_smep(struct cpuinfo_x86 *c) 375 { 376 if (cpu_has(c, X86_FEATURE_SMEP)) 377 cr4_set_bits(X86_CR4_SMEP); 378 } 379 380 static __always_inline void setup_smap(struct cpuinfo_x86 *c) 381 { 382 unsigned long eflags = native_save_fl(); 383 384 /* This should have been cleared long ago */ 385 BUG_ON(eflags & X86_EFLAGS_AC); 386 387 if (cpu_has(c, X86_FEATURE_SMAP)) 388 cr4_set_bits(X86_CR4_SMAP); 389 } 390 391 static __always_inline void setup_umip(struct cpuinfo_x86 *c) 392 { 393 /* Check the boot processor, plus build option for UMIP. */ 394 if (!cpu_feature_enabled(X86_FEATURE_UMIP)) 395 goto out; 396 397 /* Check the current processor's cpuid bits. */ 398 if (!cpu_has(c, X86_FEATURE_UMIP)) 399 goto out; 400 401 cr4_set_bits(X86_CR4_UMIP); 402 403 pr_info_once("x86/cpu: User Mode Instruction Prevention (UMIP) activated\n"); 404 405 return; 406 407 out: 408 /* 409 * Make sure UMIP is disabled in case it was enabled in a 410 * previous boot (e.g., via kexec). 411 */ 412 cr4_clear_bits(X86_CR4_UMIP); 413 } 414 415 /* These bits should not change their value after CPU init is finished. */ 416 static const unsigned long cr4_pinned_mask = 417 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP | 418 X86_CR4_FSGSBASE | X86_CR4_CET; 419 static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning); 420 static unsigned long cr4_pinned_bits __ro_after_init; 421 422 void native_write_cr0(unsigned long val) 423 { 424 unsigned long bits_missing = 0; 425 426 set_register: 427 asm volatile("mov %0,%%cr0": "+r" (val) : : "memory"); 428 429 if (static_branch_likely(&cr_pinning)) { 430 if (unlikely((val & X86_CR0_WP) != X86_CR0_WP)) { 431 bits_missing = X86_CR0_WP; 432 val |= bits_missing; 433 goto set_register; 434 } 435 /* Warn after we've set the missing bits. */ 436 WARN_ONCE(bits_missing, "CR0 WP bit went missing!?\n"); 437 } 438 } 439 EXPORT_SYMBOL(native_write_cr0); 440 441 void __no_profile native_write_cr4(unsigned long val) 442 { 443 unsigned long bits_changed = 0; 444 445 set_register: 446 asm volatile("mov %0,%%cr4": "+r" (val) : : "memory"); 447 448 if (static_branch_likely(&cr_pinning)) { 449 if (unlikely((val & cr4_pinned_mask) != cr4_pinned_bits)) { 450 bits_changed = (val & cr4_pinned_mask) ^ cr4_pinned_bits; 451 val = (val & ~cr4_pinned_mask) | cr4_pinned_bits; 452 goto set_register; 453 } 454 /* Warn after we've corrected the changed bits. */ 455 WARN_ONCE(bits_changed, "pinned CR4 bits changed: 0x%lx!?\n", 456 bits_changed); 457 } 458 } 459 #if IS_MODULE(CONFIG_LKDTM) 460 EXPORT_SYMBOL_GPL(native_write_cr4); 461 #endif 462 463 void cr4_update_irqsoff(unsigned long set, unsigned long clear) 464 { 465 unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4); 466 467 lockdep_assert_irqs_disabled(); 468 469 newval = (cr4 & ~clear) | set; 470 if (newval != cr4) { 471 this_cpu_write(cpu_tlbstate.cr4, newval); 472 __write_cr4(newval); 473 } 474 } 475 EXPORT_SYMBOL(cr4_update_irqsoff); 476 477 /* Read the CR4 shadow. */ 478 unsigned long cr4_read_shadow(void) 479 { 480 return this_cpu_read(cpu_tlbstate.cr4); 481 } 482 EXPORT_SYMBOL_GPL(cr4_read_shadow); 483 484 void cr4_init(void) 485 { 486 unsigned long cr4 = __read_cr4(); 487 488 if (boot_cpu_has(X86_FEATURE_PCID)) 489 cr4 |= X86_CR4_PCIDE; 490 if (static_branch_likely(&cr_pinning)) 491 cr4 = (cr4 & ~cr4_pinned_mask) | cr4_pinned_bits; 492 493 __write_cr4(cr4); 494 495 /* Initialize cr4 shadow for this CPU. */ 496 this_cpu_write(cpu_tlbstate.cr4, cr4); 497 } 498 499 /* 500 * Once CPU feature detection is finished (and boot params have been 501 * parsed), record any of the sensitive CR bits that are set, and 502 * enable CR pinning. 503 */ 504 static void __init setup_cr_pinning(void) 505 { 506 cr4_pinned_bits = this_cpu_read(cpu_tlbstate.cr4) & cr4_pinned_mask; 507 static_key_enable(&cr_pinning.key); 508 } 509 510 static __init int x86_nofsgsbase_setup(char *arg) 511 { 512 /* Require an exact match without trailing characters. */ 513 if (strlen(arg)) 514 return 0; 515 516 /* Do not emit a message if the feature is not present. */ 517 if (!boot_cpu_has(X86_FEATURE_FSGSBASE)) 518 return 1; 519 520 setup_clear_cpu_cap(X86_FEATURE_FSGSBASE); 521 pr_info("FSGSBASE disabled via kernel command line\n"); 522 return 1; 523 } 524 __setup("nofsgsbase", x86_nofsgsbase_setup); 525 526 /* 527 * Protection Keys are not available in 32-bit mode. 528 */ 529 static bool pku_disabled; 530 531 static __always_inline void setup_pku(struct cpuinfo_x86 *c) 532 { 533 if (c == &boot_cpu_data) { 534 if (pku_disabled || !cpu_feature_enabled(X86_FEATURE_PKU)) 535 return; 536 /* 537 * Setting CR4.PKE will cause the X86_FEATURE_OSPKE cpuid 538 * bit to be set. Enforce it. 539 */ 540 setup_force_cpu_cap(X86_FEATURE_OSPKE); 541 542 } else if (!cpu_feature_enabled(X86_FEATURE_OSPKE)) { 543 return; 544 } 545 546 cr4_set_bits(X86_CR4_PKE); 547 /* Load the default PKRU value */ 548 pkru_write_default(); 549 } 550 551 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS 552 static __init int setup_disable_pku(char *arg) 553 { 554 /* 555 * Do not clear the X86_FEATURE_PKU bit. All of the 556 * runtime checks are against OSPKE so clearing the 557 * bit does nothing. 558 * 559 * This way, we will see "pku" in cpuinfo, but not 560 * "ospke", which is exactly what we want. It shows 561 * that the CPU has PKU, but the OS has not enabled it. 562 * This happens to be exactly how a system would look 563 * if we disabled the config option. 564 */ 565 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n"); 566 pku_disabled = true; 567 return 1; 568 } 569 __setup("nopku", setup_disable_pku); 570 #endif 571 572 #ifdef CONFIG_X86_KERNEL_IBT 573 574 __noendbr u64 ibt_save(bool disable) 575 { 576 u64 msr = 0; 577 578 if (cpu_feature_enabled(X86_FEATURE_IBT)) { 579 rdmsrl(MSR_IA32_S_CET, msr); 580 if (disable) 581 wrmsrl(MSR_IA32_S_CET, msr & ~CET_ENDBR_EN); 582 } 583 584 return msr; 585 } 586 587 __noendbr void ibt_restore(u64 save) 588 { 589 u64 msr; 590 591 if (cpu_feature_enabled(X86_FEATURE_IBT)) { 592 rdmsrl(MSR_IA32_S_CET, msr); 593 msr &= ~CET_ENDBR_EN; 594 msr |= (save & CET_ENDBR_EN); 595 wrmsrl(MSR_IA32_S_CET, msr); 596 } 597 } 598 599 #endif 600 601 static __always_inline void setup_cet(struct cpuinfo_x86 *c) 602 { 603 u64 msr = CET_ENDBR_EN; 604 605 if (!HAS_KERNEL_IBT || 606 !cpu_feature_enabled(X86_FEATURE_IBT)) 607 return; 608 609 wrmsrl(MSR_IA32_S_CET, msr); 610 cr4_set_bits(X86_CR4_CET); 611 612 if (!ibt_selftest()) { 613 pr_err("IBT selftest: Failed!\n"); 614 wrmsrl(MSR_IA32_S_CET, 0); 615 setup_clear_cpu_cap(X86_FEATURE_IBT); 616 return; 617 } 618 } 619 620 __noendbr void cet_disable(void) 621 { 622 if (cpu_feature_enabled(X86_FEATURE_IBT)) 623 wrmsrl(MSR_IA32_S_CET, 0); 624 } 625 626 /* 627 * Some CPU features depend on higher CPUID levels, which may not always 628 * be available due to CPUID level capping or broken virtualization 629 * software. Add those features to this table to auto-disable them. 630 */ 631 struct cpuid_dependent_feature { 632 u32 feature; 633 u32 level; 634 }; 635 636 static const struct cpuid_dependent_feature 637 cpuid_dependent_features[] = { 638 { X86_FEATURE_MWAIT, 0x00000005 }, 639 { X86_FEATURE_DCA, 0x00000009 }, 640 { X86_FEATURE_XSAVE, 0x0000000d }, 641 { 0, 0 } 642 }; 643 644 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) 645 { 646 const struct cpuid_dependent_feature *df; 647 648 for (df = cpuid_dependent_features; df->feature; df++) { 649 650 if (!cpu_has(c, df->feature)) 651 continue; 652 /* 653 * Note: cpuid_level is set to -1 if unavailable, but 654 * extended_extended_level is set to 0 if unavailable 655 * and the legitimate extended levels are all negative 656 * when signed; hence the weird messing around with 657 * signs here... 658 */ 659 if (!((s32)df->level < 0 ? 660 (u32)df->level > (u32)c->extended_cpuid_level : 661 (s32)df->level > (s32)c->cpuid_level)) 662 continue; 663 664 clear_cpu_cap(c, df->feature); 665 if (!warn) 666 continue; 667 668 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n", 669 x86_cap_flag(df->feature), df->level); 670 } 671 } 672 673 /* 674 * Naming convention should be: <Name> [(<Codename>)] 675 * This table only is used unless init_<vendor>() below doesn't set it; 676 * in particular, if CPUID levels 0x80000002..4 are supported, this 677 * isn't used 678 */ 679 680 /* Look up CPU names by table lookup. */ 681 static const char *table_lookup_model(struct cpuinfo_x86 *c) 682 { 683 #ifdef CONFIG_X86_32 684 const struct legacy_cpu_model_info *info; 685 686 if (c->x86_model >= 16) 687 return NULL; /* Range check */ 688 689 if (!this_cpu) 690 return NULL; 691 692 info = this_cpu->legacy_models; 693 694 while (info->family) { 695 if (info->family == c->x86) 696 return info->model_names[c->x86_model]; 697 info++; 698 } 699 #endif 700 return NULL; /* Not found */ 701 } 702 703 /* Aligned to unsigned long to avoid split lock in atomic bitmap ops */ 704 __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); 705 __u32 cpu_caps_set[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); 706 707 #ifdef CONFIG_X86_32 708 /* The 32-bit entry code needs to find cpu_entry_area. */ 709 DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area); 710 #endif 711 712 /* Load the original GDT from the per-cpu structure */ 713 void load_direct_gdt(int cpu) 714 { 715 struct desc_ptr gdt_descr; 716 717 gdt_descr.address = (long)get_cpu_gdt_rw(cpu); 718 gdt_descr.size = GDT_SIZE - 1; 719 load_gdt(&gdt_descr); 720 } 721 EXPORT_SYMBOL_GPL(load_direct_gdt); 722 723 /* Load a fixmap remapping of the per-cpu GDT */ 724 void load_fixmap_gdt(int cpu) 725 { 726 struct desc_ptr gdt_descr; 727 728 gdt_descr.address = (long)get_cpu_gdt_ro(cpu); 729 gdt_descr.size = GDT_SIZE - 1; 730 load_gdt(&gdt_descr); 731 } 732 EXPORT_SYMBOL_GPL(load_fixmap_gdt); 733 734 /** 735 * switch_gdt_and_percpu_base - Switch to direct GDT and runtime per CPU base 736 * @cpu: The CPU number for which this is invoked 737 * 738 * Invoked during early boot to switch from early GDT and early per CPU to 739 * the direct GDT and the runtime per CPU area. On 32-bit the percpu base 740 * switch is implicit by loading the direct GDT. On 64bit this requires 741 * to update GSBASE. 742 */ 743 void __init switch_gdt_and_percpu_base(int cpu) 744 { 745 load_direct_gdt(cpu); 746 747 #ifdef CONFIG_X86_64 748 /* 749 * No need to load %gs. It is already correct. 750 * 751 * Writing %gs on 64bit would zero GSBASE which would make any per 752 * CPU operation up to the point of the wrmsrl() fault. 753 * 754 * Set GSBASE to the new offset. Until the wrmsrl() happens the 755 * early mapping is still valid. That means the GSBASE update will 756 * lose any prior per CPU data which was not copied over in 757 * setup_per_cpu_areas(). 758 * 759 * This works even with stackprotector enabled because the 760 * per CPU stack canary is 0 in both per CPU areas. 761 */ 762 wrmsrl(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu)); 763 #else 764 /* 765 * %fs is already set to __KERNEL_PERCPU, but after switching GDT 766 * it is required to load FS again so that the 'hidden' part is 767 * updated from the new GDT. Up to this point the early per CPU 768 * translation is active. Any content of the early per CPU data 769 * which was not copied over in setup_per_cpu_areas() is lost. 770 */ 771 loadsegment(fs, __KERNEL_PERCPU); 772 #endif 773 } 774 775 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; 776 777 static void get_model_name(struct cpuinfo_x86 *c) 778 { 779 unsigned int *v; 780 char *p, *q, *s; 781 782 if (c->extended_cpuid_level < 0x80000004) 783 return; 784 785 v = (unsigned int *)c->x86_model_id; 786 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); 787 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); 788 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); 789 c->x86_model_id[48] = 0; 790 791 /* Trim whitespace */ 792 p = q = s = &c->x86_model_id[0]; 793 794 while (*p == ' ') 795 p++; 796 797 while (*p) { 798 /* Note the last non-whitespace index */ 799 if (!isspace(*p)) 800 s = q; 801 802 *q++ = *p++; 803 } 804 805 *(s + 1) = '\0'; 806 } 807 808 void detect_num_cpu_cores(struct cpuinfo_x86 *c) 809 { 810 unsigned int eax, ebx, ecx, edx; 811 812 c->x86_max_cores = 1; 813 if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4) 814 return; 815 816 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx); 817 if (eax & 0x1f) 818 c->x86_max_cores = (eax >> 26) + 1; 819 } 820 821 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) 822 { 823 unsigned int n, dummy, ebx, ecx, edx, l2size; 824 825 n = c->extended_cpuid_level; 826 827 if (n >= 0x80000005) { 828 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); 829 c->x86_cache_size = (ecx>>24) + (edx>>24); 830 #ifdef CONFIG_X86_64 831 /* On K8 L1 TLB is inclusive, so don't count it */ 832 c->x86_tlbsize = 0; 833 #endif 834 } 835 836 if (n < 0x80000006) /* Some chips just has a large L1. */ 837 return; 838 839 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); 840 l2size = ecx >> 16; 841 842 #ifdef CONFIG_X86_64 843 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); 844 #else 845 /* do processor-specific cache resizing */ 846 if (this_cpu->legacy_cache_size) 847 l2size = this_cpu->legacy_cache_size(c, l2size); 848 849 /* Allow user to override all this if necessary. */ 850 if (cachesize_override != -1) 851 l2size = cachesize_override; 852 853 if (l2size == 0) 854 return; /* Again, no L2 cache is possible */ 855 #endif 856 857 c->x86_cache_size = l2size; 858 } 859 860 u16 __read_mostly tlb_lli_4k[NR_INFO]; 861 u16 __read_mostly tlb_lli_2m[NR_INFO]; 862 u16 __read_mostly tlb_lli_4m[NR_INFO]; 863 u16 __read_mostly tlb_lld_4k[NR_INFO]; 864 u16 __read_mostly tlb_lld_2m[NR_INFO]; 865 u16 __read_mostly tlb_lld_4m[NR_INFO]; 866 u16 __read_mostly tlb_lld_1g[NR_INFO]; 867 868 static void cpu_detect_tlb(struct cpuinfo_x86 *c) 869 { 870 if (this_cpu->c_detect_tlb) 871 this_cpu->c_detect_tlb(c); 872 873 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n", 874 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], 875 tlb_lli_4m[ENTRIES]); 876 877 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", 878 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES], 879 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]); 880 } 881 882 int detect_ht_early(struct cpuinfo_x86 *c) 883 { 884 #ifdef CONFIG_SMP 885 u32 eax, ebx, ecx, edx; 886 887 if (!cpu_has(c, X86_FEATURE_HT)) 888 return -1; 889 890 if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) 891 return -1; 892 893 if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) 894 return -1; 895 896 cpuid(1, &eax, &ebx, &ecx, &edx); 897 898 smp_num_siblings = (ebx & 0xff0000) >> 16; 899 if (smp_num_siblings == 1) 900 pr_info_once("CPU0: Hyper-Threading is disabled\n"); 901 #endif 902 return 0; 903 } 904 905 void detect_ht(struct cpuinfo_x86 *c) 906 { 907 #ifdef CONFIG_SMP 908 int index_msb, core_bits; 909 910 if (detect_ht_early(c) < 0) 911 return; 912 913 index_msb = get_count_order(smp_num_siblings); 914 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); 915 916 smp_num_siblings = smp_num_siblings / c->x86_max_cores; 917 918 index_msb = get_count_order(smp_num_siblings); 919 920 core_bits = get_count_order(c->x86_max_cores); 921 922 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & 923 ((1 << core_bits) - 1); 924 #endif 925 } 926 927 static void get_cpu_vendor(struct cpuinfo_x86 *c) 928 { 929 char *v = c->x86_vendor_id; 930 int i; 931 932 for (i = 0; i < X86_VENDOR_NUM; i++) { 933 if (!cpu_devs[i]) 934 break; 935 936 if (!strcmp(v, cpu_devs[i]->c_ident[0]) || 937 (cpu_devs[i]->c_ident[1] && 938 !strcmp(v, cpu_devs[i]->c_ident[1]))) { 939 940 this_cpu = cpu_devs[i]; 941 c->x86_vendor = this_cpu->c_x86_vendor; 942 return; 943 } 944 } 945 946 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \ 947 "CPU: Your system may be unstable.\n", v); 948 949 c->x86_vendor = X86_VENDOR_UNKNOWN; 950 this_cpu = &default_cpu; 951 } 952 953 void cpu_detect(struct cpuinfo_x86 *c) 954 { 955 /* Get vendor name */ 956 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 957 (unsigned int *)&c->x86_vendor_id[0], 958 (unsigned int *)&c->x86_vendor_id[8], 959 (unsigned int *)&c->x86_vendor_id[4]); 960 961 c->x86 = 4; 962 /* Intel-defined flags: level 0x00000001 */ 963 if (c->cpuid_level >= 0x00000001) { 964 u32 junk, tfms, cap0, misc; 965 966 cpuid(0x00000001, &tfms, &misc, &junk, &cap0); 967 c->x86 = x86_family(tfms); 968 c->x86_model = x86_model(tfms); 969 c->x86_stepping = x86_stepping(tfms); 970 971 if (cap0 & (1<<19)) { 972 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; 973 c->x86_cache_alignment = c->x86_clflush_size; 974 } 975 } 976 } 977 978 static void apply_forced_caps(struct cpuinfo_x86 *c) 979 { 980 int i; 981 982 for (i = 0; i < NCAPINTS + NBUGINTS; i++) { 983 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 984 c->x86_capability[i] |= cpu_caps_set[i]; 985 } 986 } 987 988 static void init_speculation_control(struct cpuinfo_x86 *c) 989 { 990 /* 991 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support, 992 * and they also have a different bit for STIBP support. Also, 993 * a hypervisor might have set the individual AMD bits even on 994 * Intel CPUs, for finer-grained selection of what's available. 995 */ 996 if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) { 997 set_cpu_cap(c, X86_FEATURE_IBRS); 998 set_cpu_cap(c, X86_FEATURE_IBPB); 999 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 1000 } 1001 1002 if (cpu_has(c, X86_FEATURE_INTEL_STIBP)) 1003 set_cpu_cap(c, X86_FEATURE_STIBP); 1004 1005 if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) || 1006 cpu_has(c, X86_FEATURE_VIRT_SSBD)) 1007 set_cpu_cap(c, X86_FEATURE_SSBD); 1008 1009 if (cpu_has(c, X86_FEATURE_AMD_IBRS)) { 1010 set_cpu_cap(c, X86_FEATURE_IBRS); 1011 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 1012 } 1013 1014 if (cpu_has(c, X86_FEATURE_AMD_IBPB)) 1015 set_cpu_cap(c, X86_FEATURE_IBPB); 1016 1017 if (cpu_has(c, X86_FEATURE_AMD_STIBP)) { 1018 set_cpu_cap(c, X86_FEATURE_STIBP); 1019 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 1020 } 1021 1022 if (cpu_has(c, X86_FEATURE_AMD_SSBD)) { 1023 set_cpu_cap(c, X86_FEATURE_SSBD); 1024 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 1025 clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD); 1026 } 1027 } 1028 1029 void get_cpu_cap(struct cpuinfo_x86 *c) 1030 { 1031 u32 eax, ebx, ecx, edx; 1032 1033 /* Intel-defined flags: level 0x00000001 */ 1034 if (c->cpuid_level >= 0x00000001) { 1035 cpuid(0x00000001, &eax, &ebx, &ecx, &edx); 1036 1037 c->x86_capability[CPUID_1_ECX] = ecx; 1038 c->x86_capability[CPUID_1_EDX] = edx; 1039 } 1040 1041 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */ 1042 if (c->cpuid_level >= 0x00000006) 1043 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006); 1044 1045 /* Additional Intel-defined flags: level 0x00000007 */ 1046 if (c->cpuid_level >= 0x00000007) { 1047 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); 1048 c->x86_capability[CPUID_7_0_EBX] = ebx; 1049 c->x86_capability[CPUID_7_ECX] = ecx; 1050 c->x86_capability[CPUID_7_EDX] = edx; 1051 1052 /* Check valid sub-leaf index before accessing it */ 1053 if (eax >= 1) { 1054 cpuid_count(0x00000007, 1, &eax, &ebx, &ecx, &edx); 1055 c->x86_capability[CPUID_7_1_EAX] = eax; 1056 } 1057 } 1058 1059 /* Extended state features: level 0x0000000d */ 1060 if (c->cpuid_level >= 0x0000000d) { 1061 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); 1062 1063 c->x86_capability[CPUID_D_1_EAX] = eax; 1064 } 1065 1066 /* AMD-defined flags: level 0x80000001 */ 1067 eax = cpuid_eax(0x80000000); 1068 c->extended_cpuid_level = eax; 1069 1070 if ((eax & 0xffff0000) == 0x80000000) { 1071 if (eax >= 0x80000001) { 1072 cpuid(0x80000001, &eax, &ebx, &ecx, &edx); 1073 1074 c->x86_capability[CPUID_8000_0001_ECX] = ecx; 1075 c->x86_capability[CPUID_8000_0001_EDX] = edx; 1076 } 1077 } 1078 1079 if (c->extended_cpuid_level >= 0x80000007) { 1080 cpuid(0x80000007, &eax, &ebx, &ecx, &edx); 1081 1082 c->x86_capability[CPUID_8000_0007_EBX] = ebx; 1083 c->x86_power = edx; 1084 } 1085 1086 if (c->extended_cpuid_level >= 0x80000008) { 1087 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 1088 c->x86_capability[CPUID_8000_0008_EBX] = ebx; 1089 } 1090 1091 if (c->extended_cpuid_level >= 0x8000000a) 1092 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a); 1093 1094 if (c->extended_cpuid_level >= 0x8000001f) 1095 c->x86_capability[CPUID_8000_001F_EAX] = cpuid_eax(0x8000001f); 1096 1097 if (c->extended_cpuid_level >= 0x80000021) 1098 c->x86_capability[CPUID_8000_0021_EAX] = cpuid_eax(0x80000021); 1099 1100 init_scattered_cpuid_features(c); 1101 init_speculation_control(c); 1102 1103 /* 1104 * Clear/Set all flags overridden by options, after probe. 1105 * This needs to happen each time we re-probe, which may happen 1106 * several times during CPU initialization. 1107 */ 1108 apply_forced_caps(c); 1109 } 1110 1111 void get_cpu_address_sizes(struct cpuinfo_x86 *c) 1112 { 1113 u32 eax, ebx, ecx, edx; 1114 1115 if (c->extended_cpuid_level >= 0x80000008) { 1116 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 1117 1118 c->x86_virt_bits = (eax >> 8) & 0xff; 1119 c->x86_phys_bits = eax & 0xff; 1120 } 1121 #ifdef CONFIG_X86_32 1122 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) 1123 c->x86_phys_bits = 36; 1124 #endif 1125 c->x86_cache_bits = c->x86_phys_bits; 1126 } 1127 1128 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) 1129 { 1130 #ifdef CONFIG_X86_32 1131 int i; 1132 1133 /* 1134 * First of all, decide if this is a 486 or higher 1135 * It's a 486 if we can modify the AC flag 1136 */ 1137 if (flag_is_changeable_p(X86_EFLAGS_AC)) 1138 c->x86 = 4; 1139 else 1140 c->x86 = 3; 1141 1142 for (i = 0; i < X86_VENDOR_NUM; i++) 1143 if (cpu_devs[i] && cpu_devs[i]->c_identify) { 1144 c->x86_vendor_id[0] = 0; 1145 cpu_devs[i]->c_identify(c); 1146 if (c->x86_vendor_id[0]) { 1147 get_cpu_vendor(c); 1148 break; 1149 } 1150 } 1151 #endif 1152 } 1153 1154 #define NO_SPECULATION BIT(0) 1155 #define NO_MELTDOWN BIT(1) 1156 #define NO_SSB BIT(2) 1157 #define NO_L1TF BIT(3) 1158 #define NO_MDS BIT(4) 1159 #define MSBDS_ONLY BIT(5) 1160 #define NO_SWAPGS BIT(6) 1161 #define NO_ITLB_MULTIHIT BIT(7) 1162 #define NO_SPECTRE_V2 BIT(8) 1163 #define NO_MMIO BIT(9) 1164 #define NO_EIBRS_PBRSB BIT(10) 1165 1166 #define VULNWL(vendor, family, model, whitelist) \ 1167 X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, whitelist) 1168 1169 #define VULNWL_INTEL(model, whitelist) \ 1170 VULNWL(INTEL, 6, INTEL_FAM6_##model, whitelist) 1171 1172 #define VULNWL_AMD(family, whitelist) \ 1173 VULNWL(AMD, family, X86_MODEL_ANY, whitelist) 1174 1175 #define VULNWL_HYGON(family, whitelist) \ 1176 VULNWL(HYGON, family, X86_MODEL_ANY, whitelist) 1177 1178 static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = { 1179 VULNWL(ANY, 4, X86_MODEL_ANY, NO_SPECULATION), 1180 VULNWL(CENTAUR, 5, X86_MODEL_ANY, NO_SPECULATION), 1181 VULNWL(INTEL, 5, X86_MODEL_ANY, NO_SPECULATION), 1182 VULNWL(NSC, 5, X86_MODEL_ANY, NO_SPECULATION), 1183 VULNWL(VORTEX, 5, X86_MODEL_ANY, NO_SPECULATION), 1184 VULNWL(VORTEX, 6, X86_MODEL_ANY, NO_SPECULATION), 1185 1186 /* Intel Family 6 */ 1187 VULNWL_INTEL(TIGERLAKE, NO_MMIO), 1188 VULNWL_INTEL(TIGERLAKE_L, NO_MMIO), 1189 VULNWL_INTEL(ALDERLAKE, NO_MMIO), 1190 VULNWL_INTEL(ALDERLAKE_L, NO_MMIO), 1191 1192 VULNWL_INTEL(ATOM_SALTWELL, NO_SPECULATION | NO_ITLB_MULTIHIT), 1193 VULNWL_INTEL(ATOM_SALTWELL_TABLET, NO_SPECULATION | NO_ITLB_MULTIHIT), 1194 VULNWL_INTEL(ATOM_SALTWELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), 1195 VULNWL_INTEL(ATOM_BONNELL, NO_SPECULATION | NO_ITLB_MULTIHIT), 1196 VULNWL_INTEL(ATOM_BONNELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), 1197 1198 VULNWL_INTEL(ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1199 VULNWL_INTEL(ATOM_SILVERMONT_D, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1200 VULNWL_INTEL(ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1201 VULNWL_INTEL(ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1202 VULNWL_INTEL(XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1203 VULNWL_INTEL(XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1204 1205 VULNWL_INTEL(CORE_YONAH, NO_SSB), 1206 1207 VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1208 VULNWL_INTEL(ATOM_AIRMONT_NP, NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), 1209 1210 VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), 1211 VULNWL_INTEL(ATOM_GOLDMONT_D, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), 1212 VULNWL_INTEL(ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB), 1213 1214 /* 1215 * Technically, swapgs isn't serializing on AMD (despite it previously 1216 * being documented as such in the APM). But according to AMD, %gs is 1217 * updated non-speculatively, and the issuing of %gs-relative memory 1218 * operands will be blocked until the %gs update completes, which is 1219 * good enough for our purposes. 1220 */ 1221 1222 VULNWL_INTEL(ATOM_TREMONT, NO_EIBRS_PBRSB), 1223 VULNWL_INTEL(ATOM_TREMONT_L, NO_EIBRS_PBRSB), 1224 VULNWL_INTEL(ATOM_TREMONT_D, NO_ITLB_MULTIHIT | NO_EIBRS_PBRSB), 1225 1226 /* AMD Family 0xf - 0x12 */ 1227 VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), 1228 VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), 1229 VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), 1230 VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), 1231 1232 /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */ 1233 VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB), 1234 VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB), 1235 1236 /* Zhaoxin Family 7 */ 1237 VULNWL(CENTAUR, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS | NO_MMIO), 1238 VULNWL(ZHAOXIN, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS | NO_MMIO), 1239 {} 1240 }; 1241 1242 #define VULNBL(vendor, family, model, blacklist) \ 1243 X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, blacklist) 1244 1245 #define VULNBL_INTEL_STEPPINGS(model, steppings, issues) \ 1246 X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE(INTEL, 6, \ 1247 INTEL_FAM6_##model, steppings, \ 1248 X86_FEATURE_ANY, issues) 1249 1250 #define VULNBL_AMD(family, blacklist) \ 1251 VULNBL(AMD, family, X86_MODEL_ANY, blacklist) 1252 1253 #define VULNBL_HYGON(family, blacklist) \ 1254 VULNBL(HYGON, family, X86_MODEL_ANY, blacklist) 1255 1256 #define SRBDS BIT(0) 1257 /* CPU is affected by X86_BUG_MMIO_STALE_DATA */ 1258 #define MMIO BIT(1) 1259 /* CPU is affected by Shared Buffers Data Sampling (SBDS), a variant of X86_BUG_MMIO_STALE_DATA */ 1260 #define MMIO_SBDS BIT(2) 1261 /* CPU is affected by RETbleed, speculating where you would not expect it */ 1262 #define RETBLEED BIT(3) 1263 /* CPU is affected by SMT (cross-thread) return predictions */ 1264 #define SMT_RSB BIT(4) 1265 1266 static const struct x86_cpu_id cpu_vuln_blacklist[] __initconst = { 1267 VULNBL_INTEL_STEPPINGS(IVYBRIDGE, X86_STEPPING_ANY, SRBDS), 1268 VULNBL_INTEL_STEPPINGS(HASWELL, X86_STEPPING_ANY, SRBDS), 1269 VULNBL_INTEL_STEPPINGS(HASWELL_L, X86_STEPPING_ANY, SRBDS), 1270 VULNBL_INTEL_STEPPINGS(HASWELL_G, X86_STEPPING_ANY, SRBDS), 1271 VULNBL_INTEL_STEPPINGS(HASWELL_X, X86_STEPPING_ANY, MMIO), 1272 VULNBL_INTEL_STEPPINGS(BROADWELL_D, X86_STEPPING_ANY, MMIO), 1273 VULNBL_INTEL_STEPPINGS(BROADWELL_G, X86_STEPPING_ANY, SRBDS), 1274 VULNBL_INTEL_STEPPINGS(BROADWELL_X, X86_STEPPING_ANY, MMIO), 1275 VULNBL_INTEL_STEPPINGS(BROADWELL, X86_STEPPING_ANY, SRBDS), 1276 VULNBL_INTEL_STEPPINGS(SKYLAKE_L, X86_STEPPING_ANY, SRBDS | MMIO | RETBLEED), 1277 VULNBL_INTEL_STEPPINGS(SKYLAKE_X, X86_STEPPING_ANY, MMIO | RETBLEED), 1278 VULNBL_INTEL_STEPPINGS(SKYLAKE, X86_STEPPING_ANY, SRBDS | MMIO | RETBLEED), 1279 VULNBL_INTEL_STEPPINGS(KABYLAKE_L, X86_STEPPING_ANY, SRBDS | MMIO | RETBLEED), 1280 VULNBL_INTEL_STEPPINGS(KABYLAKE, X86_STEPPING_ANY, SRBDS | MMIO | RETBLEED), 1281 VULNBL_INTEL_STEPPINGS(CANNONLAKE_L, X86_STEPPING_ANY, RETBLEED), 1282 VULNBL_INTEL_STEPPINGS(ICELAKE_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED), 1283 VULNBL_INTEL_STEPPINGS(ICELAKE_D, X86_STEPPING_ANY, MMIO), 1284 VULNBL_INTEL_STEPPINGS(ICELAKE_X, X86_STEPPING_ANY, MMIO), 1285 VULNBL_INTEL_STEPPINGS(COMETLAKE, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED), 1286 VULNBL_INTEL_STEPPINGS(COMETLAKE_L, X86_STEPPINGS(0x0, 0x0), MMIO | RETBLEED), 1287 VULNBL_INTEL_STEPPINGS(COMETLAKE_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED), 1288 VULNBL_INTEL_STEPPINGS(LAKEFIELD, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED), 1289 VULNBL_INTEL_STEPPINGS(ROCKETLAKE, X86_STEPPING_ANY, MMIO | RETBLEED), 1290 VULNBL_INTEL_STEPPINGS(ATOM_TREMONT, X86_STEPPING_ANY, MMIO | MMIO_SBDS), 1291 VULNBL_INTEL_STEPPINGS(ATOM_TREMONT_D, X86_STEPPING_ANY, MMIO), 1292 VULNBL_INTEL_STEPPINGS(ATOM_TREMONT_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS), 1293 1294 VULNBL_AMD(0x15, RETBLEED), 1295 VULNBL_AMD(0x16, RETBLEED), 1296 VULNBL_AMD(0x17, RETBLEED | SMT_RSB), 1297 VULNBL_HYGON(0x18, RETBLEED | SMT_RSB), 1298 {} 1299 }; 1300 1301 static bool __init cpu_matches(const struct x86_cpu_id *table, unsigned long which) 1302 { 1303 const struct x86_cpu_id *m = x86_match_cpu(table); 1304 1305 return m && !!(m->driver_data & which); 1306 } 1307 1308 u64 x86_read_arch_cap_msr(void) 1309 { 1310 u64 ia32_cap = 0; 1311 1312 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) 1313 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap); 1314 1315 return ia32_cap; 1316 } 1317 1318 static bool arch_cap_mmio_immune(u64 ia32_cap) 1319 { 1320 return (ia32_cap & ARCH_CAP_FBSDP_NO && 1321 ia32_cap & ARCH_CAP_PSDP_NO && 1322 ia32_cap & ARCH_CAP_SBDR_SSDP_NO); 1323 } 1324 1325 static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) 1326 { 1327 u64 ia32_cap = x86_read_arch_cap_msr(); 1328 1329 /* Set ITLB_MULTIHIT bug if cpu is not in the whitelist and not mitigated */ 1330 if (!cpu_matches(cpu_vuln_whitelist, NO_ITLB_MULTIHIT) && 1331 !(ia32_cap & ARCH_CAP_PSCHANGE_MC_NO)) 1332 setup_force_cpu_bug(X86_BUG_ITLB_MULTIHIT); 1333 1334 if (cpu_matches(cpu_vuln_whitelist, NO_SPECULATION)) 1335 return; 1336 1337 setup_force_cpu_bug(X86_BUG_SPECTRE_V1); 1338 1339 if (!cpu_matches(cpu_vuln_whitelist, NO_SPECTRE_V2)) 1340 setup_force_cpu_bug(X86_BUG_SPECTRE_V2); 1341 1342 if (!cpu_matches(cpu_vuln_whitelist, NO_SSB) && 1343 !(ia32_cap & ARCH_CAP_SSB_NO) && 1344 !cpu_has(c, X86_FEATURE_AMD_SSB_NO)) 1345 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS); 1346 1347 /* 1348 * AMD's AutoIBRS is equivalent to Intel's eIBRS - use the Intel feature 1349 * flag and protect from vendor-specific bugs via the whitelist. 1350 */ 1351 if ((ia32_cap & ARCH_CAP_IBRS_ALL) || cpu_has(c, X86_FEATURE_AUTOIBRS)) { 1352 setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED); 1353 if (!cpu_matches(cpu_vuln_whitelist, NO_EIBRS_PBRSB) && 1354 !(ia32_cap & ARCH_CAP_PBRSB_NO)) 1355 setup_force_cpu_bug(X86_BUG_EIBRS_PBRSB); 1356 } 1357 1358 if (!cpu_matches(cpu_vuln_whitelist, NO_MDS) && 1359 !(ia32_cap & ARCH_CAP_MDS_NO)) { 1360 setup_force_cpu_bug(X86_BUG_MDS); 1361 if (cpu_matches(cpu_vuln_whitelist, MSBDS_ONLY)) 1362 setup_force_cpu_bug(X86_BUG_MSBDS_ONLY); 1363 } 1364 1365 if (!cpu_matches(cpu_vuln_whitelist, NO_SWAPGS)) 1366 setup_force_cpu_bug(X86_BUG_SWAPGS); 1367 1368 /* 1369 * When the CPU is not mitigated for TAA (TAA_NO=0) set TAA bug when: 1370 * - TSX is supported or 1371 * - TSX_CTRL is present 1372 * 1373 * TSX_CTRL check is needed for cases when TSX could be disabled before 1374 * the kernel boot e.g. kexec. 1375 * TSX_CTRL check alone is not sufficient for cases when the microcode 1376 * update is not present or running as guest that don't get TSX_CTRL. 1377 */ 1378 if (!(ia32_cap & ARCH_CAP_TAA_NO) && 1379 (cpu_has(c, X86_FEATURE_RTM) || 1380 (ia32_cap & ARCH_CAP_TSX_CTRL_MSR))) 1381 setup_force_cpu_bug(X86_BUG_TAA); 1382 1383 /* 1384 * SRBDS affects CPUs which support RDRAND or RDSEED and are listed 1385 * in the vulnerability blacklist. 1386 * 1387 * Some of the implications and mitigation of Shared Buffers Data 1388 * Sampling (SBDS) are similar to SRBDS. Give SBDS same treatment as 1389 * SRBDS. 1390 */ 1391 if ((cpu_has(c, X86_FEATURE_RDRAND) || 1392 cpu_has(c, X86_FEATURE_RDSEED)) && 1393 cpu_matches(cpu_vuln_blacklist, SRBDS | MMIO_SBDS)) 1394 setup_force_cpu_bug(X86_BUG_SRBDS); 1395 1396 /* 1397 * Processor MMIO Stale Data bug enumeration 1398 * 1399 * Affected CPU list is generally enough to enumerate the vulnerability, 1400 * but for virtualization case check for ARCH_CAP MSR bits also, VMM may 1401 * not want the guest to enumerate the bug. 1402 * 1403 * Set X86_BUG_MMIO_UNKNOWN for CPUs that are neither in the blacklist, 1404 * nor in the whitelist and also don't enumerate MSR ARCH_CAP MMIO bits. 1405 */ 1406 if (!arch_cap_mmio_immune(ia32_cap)) { 1407 if (cpu_matches(cpu_vuln_blacklist, MMIO)) 1408 setup_force_cpu_bug(X86_BUG_MMIO_STALE_DATA); 1409 else if (!cpu_matches(cpu_vuln_whitelist, NO_MMIO)) 1410 setup_force_cpu_bug(X86_BUG_MMIO_UNKNOWN); 1411 } 1412 1413 if (!cpu_has(c, X86_FEATURE_BTC_NO)) { 1414 if (cpu_matches(cpu_vuln_blacklist, RETBLEED) || (ia32_cap & ARCH_CAP_RSBA)) 1415 setup_force_cpu_bug(X86_BUG_RETBLEED); 1416 } 1417 1418 if (cpu_matches(cpu_vuln_blacklist, SMT_RSB)) 1419 setup_force_cpu_bug(X86_BUG_SMT_RSB); 1420 1421 if (cpu_matches(cpu_vuln_whitelist, NO_MELTDOWN)) 1422 return; 1423 1424 /* Rogue Data Cache Load? No! */ 1425 if (ia32_cap & ARCH_CAP_RDCL_NO) 1426 return; 1427 1428 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN); 1429 1430 if (cpu_matches(cpu_vuln_whitelist, NO_L1TF)) 1431 return; 1432 1433 setup_force_cpu_bug(X86_BUG_L1TF); 1434 } 1435 1436 /* 1437 * The NOPL instruction is supposed to exist on all CPUs of family >= 6; 1438 * unfortunately, that's not true in practice because of early VIA 1439 * chips and (more importantly) broken virtualizers that are not easy 1440 * to detect. In the latter case it doesn't even *fail* reliably, so 1441 * probing for it doesn't even work. Disable it completely on 32-bit 1442 * unless we can find a reliable way to detect all the broken cases. 1443 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). 1444 */ 1445 static void detect_nopl(void) 1446 { 1447 #ifdef CONFIG_X86_32 1448 setup_clear_cpu_cap(X86_FEATURE_NOPL); 1449 #else 1450 setup_force_cpu_cap(X86_FEATURE_NOPL); 1451 #endif 1452 } 1453 1454 /* 1455 * We parse cpu parameters early because fpu__init_system() is executed 1456 * before parse_early_param(). 1457 */ 1458 static void __init cpu_parse_early_param(void) 1459 { 1460 char arg[128]; 1461 char *argptr = arg, *opt; 1462 int arglen, taint = 0; 1463 1464 #ifdef CONFIG_X86_32 1465 if (cmdline_find_option_bool(boot_command_line, "no387")) 1466 #ifdef CONFIG_MATH_EMULATION 1467 setup_clear_cpu_cap(X86_FEATURE_FPU); 1468 #else 1469 pr_err("Option 'no387' required CONFIG_MATH_EMULATION enabled.\n"); 1470 #endif 1471 1472 if (cmdline_find_option_bool(boot_command_line, "nofxsr")) 1473 setup_clear_cpu_cap(X86_FEATURE_FXSR); 1474 #endif 1475 1476 if (cmdline_find_option_bool(boot_command_line, "noxsave")) 1477 setup_clear_cpu_cap(X86_FEATURE_XSAVE); 1478 1479 if (cmdline_find_option_bool(boot_command_line, "noxsaveopt")) 1480 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); 1481 1482 if (cmdline_find_option_bool(boot_command_line, "noxsaves")) 1483 setup_clear_cpu_cap(X86_FEATURE_XSAVES); 1484 1485 arglen = cmdline_find_option(boot_command_line, "clearcpuid", arg, sizeof(arg)); 1486 if (arglen <= 0) 1487 return; 1488 1489 pr_info("Clearing CPUID bits:"); 1490 1491 while (argptr) { 1492 bool found __maybe_unused = false; 1493 unsigned int bit; 1494 1495 opt = strsep(&argptr, ","); 1496 1497 /* 1498 * Handle naked numbers first for feature flags which don't 1499 * have names. 1500 */ 1501 if (!kstrtouint(opt, 10, &bit)) { 1502 if (bit < NCAPINTS * 32) { 1503 1504 #ifdef CONFIG_X86_FEATURE_NAMES 1505 /* empty-string, i.e., ""-defined feature flags */ 1506 if (!x86_cap_flags[bit]) 1507 pr_cont(" " X86_CAP_FMT_NUM, x86_cap_flag_num(bit)); 1508 else 1509 #endif 1510 pr_cont(" " X86_CAP_FMT, x86_cap_flag(bit)); 1511 1512 setup_clear_cpu_cap(bit); 1513 taint++; 1514 } 1515 /* 1516 * The assumption is that there are no feature names with only 1517 * numbers in the name thus go to the next argument. 1518 */ 1519 continue; 1520 } 1521 1522 #ifdef CONFIG_X86_FEATURE_NAMES 1523 for (bit = 0; bit < 32 * NCAPINTS; bit++) { 1524 if (!x86_cap_flag(bit)) 1525 continue; 1526 1527 if (strcmp(x86_cap_flag(bit), opt)) 1528 continue; 1529 1530 pr_cont(" %s", opt); 1531 setup_clear_cpu_cap(bit); 1532 taint++; 1533 found = true; 1534 break; 1535 } 1536 1537 if (!found) 1538 pr_cont(" (unknown: %s)", opt); 1539 #endif 1540 } 1541 pr_cont("\n"); 1542 1543 if (taint) 1544 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1545 } 1546 1547 /* 1548 * Do minimum CPU detection early. 1549 * Fields really needed: vendor, cpuid_level, family, model, mask, 1550 * cache alignment. 1551 * The others are not touched to avoid unwanted side effects. 1552 * 1553 * WARNING: this function is only called on the boot CPU. Don't add code 1554 * here that is supposed to run on all CPUs. 1555 */ 1556 static void __init early_identify_cpu(struct cpuinfo_x86 *c) 1557 { 1558 #ifdef CONFIG_X86_64 1559 c->x86_clflush_size = 64; 1560 c->x86_phys_bits = 36; 1561 c->x86_virt_bits = 48; 1562 #else 1563 c->x86_clflush_size = 32; 1564 c->x86_phys_bits = 32; 1565 c->x86_virt_bits = 32; 1566 #endif 1567 c->x86_cache_alignment = c->x86_clflush_size; 1568 1569 memset(&c->x86_capability, 0, sizeof(c->x86_capability)); 1570 c->extended_cpuid_level = 0; 1571 1572 if (!have_cpuid_p()) 1573 identify_cpu_without_cpuid(c); 1574 1575 /* cyrix could have cpuid enabled via c_identify()*/ 1576 if (have_cpuid_p()) { 1577 cpu_detect(c); 1578 get_cpu_vendor(c); 1579 get_cpu_cap(c); 1580 get_cpu_address_sizes(c); 1581 setup_force_cpu_cap(X86_FEATURE_CPUID); 1582 cpu_parse_early_param(); 1583 1584 if (this_cpu->c_early_init) 1585 this_cpu->c_early_init(c); 1586 1587 c->cpu_index = 0; 1588 filter_cpuid_features(c, false); 1589 1590 if (this_cpu->c_bsp_init) 1591 this_cpu->c_bsp_init(c); 1592 } else { 1593 setup_clear_cpu_cap(X86_FEATURE_CPUID); 1594 } 1595 1596 setup_force_cpu_cap(X86_FEATURE_ALWAYS); 1597 1598 cpu_set_bug_bits(c); 1599 1600 sld_setup(c); 1601 1602 fpu__init_system(c); 1603 1604 init_sigframe_size(); 1605 1606 #ifdef CONFIG_X86_32 1607 /* 1608 * Regardless of whether PCID is enumerated, the SDM says 1609 * that it can't be enabled in 32-bit mode. 1610 */ 1611 setup_clear_cpu_cap(X86_FEATURE_PCID); 1612 #endif 1613 1614 /* 1615 * Later in the boot process pgtable_l5_enabled() relies on 1616 * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not 1617 * enabled by this point we need to clear the feature bit to avoid 1618 * false-positives at the later stage. 1619 * 1620 * pgtable_l5_enabled() can be false here for several reasons: 1621 * - 5-level paging is disabled compile-time; 1622 * - it's 32-bit kernel; 1623 * - machine doesn't support 5-level paging; 1624 * - user specified 'no5lvl' in kernel command line. 1625 */ 1626 if (!pgtable_l5_enabled()) 1627 setup_clear_cpu_cap(X86_FEATURE_LA57); 1628 1629 detect_nopl(); 1630 } 1631 1632 void __init early_cpu_init(void) 1633 { 1634 const struct cpu_dev *const *cdev; 1635 int count = 0; 1636 1637 #ifdef CONFIG_PROCESSOR_SELECT 1638 pr_info("KERNEL supported cpus:\n"); 1639 #endif 1640 1641 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { 1642 const struct cpu_dev *cpudev = *cdev; 1643 1644 if (count >= X86_VENDOR_NUM) 1645 break; 1646 cpu_devs[count] = cpudev; 1647 count++; 1648 1649 #ifdef CONFIG_PROCESSOR_SELECT 1650 { 1651 unsigned int j; 1652 1653 for (j = 0; j < 2; j++) { 1654 if (!cpudev->c_ident[j]) 1655 continue; 1656 pr_info(" %s %s\n", cpudev->c_vendor, 1657 cpudev->c_ident[j]); 1658 } 1659 } 1660 #endif 1661 } 1662 early_identify_cpu(&boot_cpu_data); 1663 } 1664 1665 static bool detect_null_seg_behavior(void) 1666 { 1667 /* 1668 * Empirically, writing zero to a segment selector on AMD does 1669 * not clear the base, whereas writing zero to a segment 1670 * selector on Intel does clear the base. Intel's behavior 1671 * allows slightly faster context switches in the common case 1672 * where GS is unused by the prev and next threads. 1673 * 1674 * Since neither vendor documents this anywhere that I can see, 1675 * detect it directly instead of hard-coding the choice by 1676 * vendor. 1677 * 1678 * I've designated AMD's behavior as the "bug" because it's 1679 * counterintuitive and less friendly. 1680 */ 1681 1682 unsigned long old_base, tmp; 1683 rdmsrl(MSR_FS_BASE, old_base); 1684 wrmsrl(MSR_FS_BASE, 1); 1685 loadsegment(fs, 0); 1686 rdmsrl(MSR_FS_BASE, tmp); 1687 wrmsrl(MSR_FS_BASE, old_base); 1688 return tmp == 0; 1689 } 1690 1691 void check_null_seg_clears_base(struct cpuinfo_x86 *c) 1692 { 1693 /* BUG_NULL_SEG is only relevant with 64bit userspace */ 1694 if (!IS_ENABLED(CONFIG_X86_64)) 1695 return; 1696 1697 if (cpu_has(c, X86_FEATURE_NULL_SEL_CLR_BASE)) 1698 return; 1699 1700 /* 1701 * CPUID bit above wasn't set. If this kernel is still running 1702 * as a HV guest, then the HV has decided not to advertize 1703 * that CPUID bit for whatever reason. For example, one 1704 * member of the migration pool might be vulnerable. Which 1705 * means, the bug is present: set the BUG flag and return. 1706 */ 1707 if (cpu_has(c, X86_FEATURE_HYPERVISOR)) { 1708 set_cpu_bug(c, X86_BUG_NULL_SEG); 1709 return; 1710 } 1711 1712 /* 1713 * Zen2 CPUs also have this behaviour, but no CPUID bit. 1714 * 0x18 is the respective family for Hygon. 1715 */ 1716 if ((c->x86 == 0x17 || c->x86 == 0x18) && 1717 detect_null_seg_behavior()) 1718 return; 1719 1720 /* All the remaining ones are affected */ 1721 set_cpu_bug(c, X86_BUG_NULL_SEG); 1722 } 1723 1724 static void generic_identify(struct cpuinfo_x86 *c) 1725 { 1726 c->extended_cpuid_level = 0; 1727 1728 if (!have_cpuid_p()) 1729 identify_cpu_without_cpuid(c); 1730 1731 /* cyrix could have cpuid enabled via c_identify()*/ 1732 if (!have_cpuid_p()) 1733 return; 1734 1735 cpu_detect(c); 1736 1737 get_cpu_vendor(c); 1738 1739 get_cpu_cap(c); 1740 1741 get_cpu_address_sizes(c); 1742 1743 if (c->cpuid_level >= 0x00000001) { 1744 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; 1745 #ifdef CONFIG_X86_32 1746 # ifdef CONFIG_SMP 1747 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 1748 # else 1749 c->apicid = c->initial_apicid; 1750 # endif 1751 #endif 1752 c->phys_proc_id = c->initial_apicid; 1753 } 1754 1755 get_model_name(c); /* Default name */ 1756 1757 /* 1758 * ESPFIX is a strange bug. All real CPUs have it. Paravirt 1759 * systems that run Linux at CPL > 0 may or may not have the 1760 * issue, but, even if they have the issue, there's absolutely 1761 * nothing we can do about it because we can't use the real IRET 1762 * instruction. 1763 * 1764 * NB: For the time being, only 32-bit kernels support 1765 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose 1766 * whether to apply espfix using paravirt hooks. If any 1767 * non-paravirt system ever shows up that does *not* have the 1768 * ESPFIX issue, we can change this. 1769 */ 1770 #ifdef CONFIG_X86_32 1771 set_cpu_bug(c, X86_BUG_ESPFIX); 1772 #endif 1773 } 1774 1775 /* 1776 * Validate that ACPI/mptables have the same information about the 1777 * effective APIC id and update the package map. 1778 */ 1779 static void validate_apic_and_package_id(struct cpuinfo_x86 *c) 1780 { 1781 #ifdef CONFIG_SMP 1782 unsigned int apicid, cpu = smp_processor_id(); 1783 1784 apicid = apic->cpu_present_to_apicid(cpu); 1785 1786 if (apicid != c->apicid) { 1787 pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n", 1788 cpu, apicid, c->initial_apicid); 1789 } 1790 BUG_ON(topology_update_package_map(c->phys_proc_id, cpu)); 1791 BUG_ON(topology_update_die_map(c->cpu_die_id, cpu)); 1792 #else 1793 c->logical_proc_id = 0; 1794 #endif 1795 } 1796 1797 /* 1798 * This does the hard work of actually picking apart the CPU stuff... 1799 */ 1800 static void identify_cpu(struct cpuinfo_x86 *c) 1801 { 1802 int i; 1803 1804 c->loops_per_jiffy = loops_per_jiffy; 1805 c->x86_cache_size = 0; 1806 c->x86_vendor = X86_VENDOR_UNKNOWN; 1807 c->x86_model = c->x86_stepping = 0; /* So far unknown... */ 1808 c->x86_vendor_id[0] = '\0'; /* Unset */ 1809 c->x86_model_id[0] = '\0'; /* Unset */ 1810 c->x86_max_cores = 1; 1811 c->x86_coreid_bits = 0; 1812 c->cu_id = 0xff; 1813 #ifdef CONFIG_X86_64 1814 c->x86_clflush_size = 64; 1815 c->x86_phys_bits = 36; 1816 c->x86_virt_bits = 48; 1817 #else 1818 c->cpuid_level = -1; /* CPUID not detected */ 1819 c->x86_clflush_size = 32; 1820 c->x86_phys_bits = 32; 1821 c->x86_virt_bits = 32; 1822 #endif 1823 c->x86_cache_alignment = c->x86_clflush_size; 1824 memset(&c->x86_capability, 0, sizeof(c->x86_capability)); 1825 #ifdef CONFIG_X86_VMX_FEATURE_NAMES 1826 memset(&c->vmx_capability, 0, sizeof(c->vmx_capability)); 1827 #endif 1828 1829 generic_identify(c); 1830 1831 if (this_cpu->c_identify) 1832 this_cpu->c_identify(c); 1833 1834 /* Clear/Set all flags overridden by options, after probe */ 1835 apply_forced_caps(c); 1836 1837 #ifdef CONFIG_X86_64 1838 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 1839 #endif 1840 1841 /* 1842 * Vendor-specific initialization. In this section we 1843 * canonicalize the feature flags, meaning if there are 1844 * features a certain CPU supports which CPUID doesn't 1845 * tell us, CPUID claiming incorrect flags, or other bugs, 1846 * we handle them here. 1847 * 1848 * At the end of this section, c->x86_capability better 1849 * indicate the features this CPU genuinely supports! 1850 */ 1851 if (this_cpu->c_init) 1852 this_cpu->c_init(c); 1853 1854 /* Disable the PN if appropriate */ 1855 squash_the_stupid_serial_number(c); 1856 1857 /* Set up SMEP/SMAP/UMIP */ 1858 setup_smep(c); 1859 setup_smap(c); 1860 setup_umip(c); 1861 1862 /* Enable FSGSBASE instructions if available. */ 1863 if (cpu_has(c, X86_FEATURE_FSGSBASE)) { 1864 cr4_set_bits(X86_CR4_FSGSBASE); 1865 elf_hwcap2 |= HWCAP2_FSGSBASE; 1866 } 1867 1868 /* 1869 * The vendor-specific functions might have changed features. 1870 * Now we do "generic changes." 1871 */ 1872 1873 /* Filter out anything that depends on CPUID levels we don't have */ 1874 filter_cpuid_features(c, true); 1875 1876 /* If the model name is still unset, do table lookup. */ 1877 if (!c->x86_model_id[0]) { 1878 const char *p; 1879 p = table_lookup_model(c); 1880 if (p) 1881 strcpy(c->x86_model_id, p); 1882 else 1883 /* Last resort... */ 1884 sprintf(c->x86_model_id, "%02x/%02x", 1885 c->x86, c->x86_model); 1886 } 1887 1888 #ifdef CONFIG_X86_64 1889 detect_ht(c); 1890 #endif 1891 1892 x86_init_rdrand(c); 1893 setup_pku(c); 1894 setup_cet(c); 1895 1896 /* 1897 * Clear/Set all flags overridden by options, need do it 1898 * before following smp all cpus cap AND. 1899 */ 1900 apply_forced_caps(c); 1901 1902 /* 1903 * On SMP, boot_cpu_data holds the common feature set between 1904 * all CPUs; so make sure that we indicate which features are 1905 * common between the CPUs. The first time this routine gets 1906 * executed, c == &boot_cpu_data. 1907 */ 1908 if (c != &boot_cpu_data) { 1909 /* AND the already accumulated flags with these */ 1910 for (i = 0; i < NCAPINTS; i++) 1911 boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; 1912 1913 /* OR, i.e. replicate the bug flags */ 1914 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) 1915 c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; 1916 } 1917 1918 ppin_init(c); 1919 1920 /* Init Machine Check Exception if available. */ 1921 mcheck_cpu_init(c); 1922 1923 select_idle_routine(c); 1924 1925 #ifdef CONFIG_NUMA 1926 numa_add_cpu(smp_processor_id()); 1927 #endif 1928 } 1929 1930 /* 1931 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions 1932 * on 32-bit kernels: 1933 */ 1934 #ifdef CONFIG_X86_32 1935 void enable_sep_cpu(void) 1936 { 1937 struct tss_struct *tss; 1938 int cpu; 1939 1940 if (!boot_cpu_has(X86_FEATURE_SEP)) 1941 return; 1942 1943 cpu = get_cpu(); 1944 tss = &per_cpu(cpu_tss_rw, cpu); 1945 1946 /* 1947 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field -- 1948 * see the big comment in struct x86_hw_tss's definition. 1949 */ 1950 1951 tss->x86_tss.ss1 = __KERNEL_CS; 1952 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0); 1953 wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0); 1954 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0); 1955 1956 put_cpu(); 1957 } 1958 #endif 1959 1960 void __init identify_boot_cpu(void) 1961 { 1962 identify_cpu(&boot_cpu_data); 1963 if (HAS_KERNEL_IBT && cpu_feature_enabled(X86_FEATURE_IBT)) 1964 pr_info("CET detected: Indirect Branch Tracking enabled\n"); 1965 #ifdef CONFIG_X86_32 1966 enable_sep_cpu(); 1967 #endif 1968 cpu_detect_tlb(&boot_cpu_data); 1969 setup_cr_pinning(); 1970 1971 tsx_init(); 1972 lkgs_init(); 1973 } 1974 1975 void identify_secondary_cpu(struct cpuinfo_x86 *c) 1976 { 1977 BUG_ON(c == &boot_cpu_data); 1978 identify_cpu(c); 1979 #ifdef CONFIG_X86_32 1980 enable_sep_cpu(); 1981 #endif 1982 validate_apic_and_package_id(c); 1983 x86_spec_ctrl_setup_ap(); 1984 update_srbds_msr(); 1985 1986 tsx_ap_init(); 1987 } 1988 1989 void print_cpu_info(struct cpuinfo_x86 *c) 1990 { 1991 const char *vendor = NULL; 1992 1993 if (c->x86_vendor < X86_VENDOR_NUM) { 1994 vendor = this_cpu->c_vendor; 1995 } else { 1996 if (c->cpuid_level >= 0) 1997 vendor = c->x86_vendor_id; 1998 } 1999 2000 if (vendor && !strstr(c->x86_model_id, vendor)) 2001 pr_cont("%s ", vendor); 2002 2003 if (c->x86_model_id[0]) 2004 pr_cont("%s", c->x86_model_id); 2005 else 2006 pr_cont("%d86", c->x86); 2007 2008 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model); 2009 2010 if (c->x86_stepping || c->cpuid_level >= 0) 2011 pr_cont(", stepping: 0x%x)\n", c->x86_stepping); 2012 else 2013 pr_cont(")\n"); 2014 } 2015 2016 /* 2017 * clearcpuid= was already parsed in cpu_parse_early_param(). This dummy 2018 * function prevents it from becoming an environment variable for init. 2019 */ 2020 static __init int setup_clearcpuid(char *arg) 2021 { 2022 return 1; 2023 } 2024 __setup("clearcpuid=", setup_clearcpuid); 2025 2026 DEFINE_PER_CPU_ALIGNED(struct pcpu_hot, pcpu_hot) = { 2027 .current_task = &init_task, 2028 .preempt_count = INIT_PREEMPT_COUNT, 2029 .top_of_stack = TOP_OF_INIT_STACK, 2030 }; 2031 EXPORT_PER_CPU_SYMBOL(pcpu_hot); 2032 2033 #ifdef CONFIG_X86_64 2034 DEFINE_PER_CPU_FIRST(struct fixed_percpu_data, 2035 fixed_percpu_data) __aligned(PAGE_SIZE) __visible; 2036 EXPORT_PER_CPU_SYMBOL_GPL(fixed_percpu_data); 2037 2038 static void wrmsrl_cstar(unsigned long val) 2039 { 2040 /* 2041 * Intel CPUs do not support 32-bit SYSCALL. Writing to MSR_CSTAR 2042 * is so far ignored by the CPU, but raises a #VE trap in a TDX 2043 * guest. Avoid the pointless write on all Intel CPUs. 2044 */ 2045 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) 2046 wrmsrl(MSR_CSTAR, val); 2047 } 2048 2049 /* May not be marked __init: used by software suspend */ 2050 void syscall_init(void) 2051 { 2052 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS); 2053 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); 2054 2055 #ifdef CONFIG_IA32_EMULATION 2056 wrmsrl_cstar((unsigned long)entry_SYSCALL_compat); 2057 /* 2058 * This only works on Intel CPUs. 2059 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. 2060 * This does not cause SYSENTER to jump to the wrong location, because 2061 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). 2062 */ 2063 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); 2064 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 2065 (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1)); 2066 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); 2067 #else 2068 wrmsrl_cstar((unsigned long)ignore_sysret); 2069 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); 2070 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); 2071 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); 2072 #endif 2073 2074 /* 2075 * Flags to clear on syscall; clear as much as possible 2076 * to minimize user space-kernel interference. 2077 */ 2078 wrmsrl(MSR_SYSCALL_MASK, 2079 X86_EFLAGS_CF|X86_EFLAGS_PF|X86_EFLAGS_AF| 2080 X86_EFLAGS_ZF|X86_EFLAGS_SF|X86_EFLAGS_TF| 2081 X86_EFLAGS_IF|X86_EFLAGS_DF|X86_EFLAGS_OF| 2082 X86_EFLAGS_IOPL|X86_EFLAGS_NT|X86_EFLAGS_RF| 2083 X86_EFLAGS_AC|X86_EFLAGS_ID); 2084 } 2085 2086 #else /* CONFIG_X86_64 */ 2087 2088 #ifdef CONFIG_STACKPROTECTOR 2089 DEFINE_PER_CPU(unsigned long, __stack_chk_guard); 2090 EXPORT_PER_CPU_SYMBOL(__stack_chk_guard); 2091 #endif 2092 2093 #endif /* CONFIG_X86_64 */ 2094 2095 /* 2096 * Clear all 6 debug registers: 2097 */ 2098 static void clear_all_debug_regs(void) 2099 { 2100 int i; 2101 2102 for (i = 0; i < 8; i++) { 2103 /* Ignore db4, db5 */ 2104 if ((i == 4) || (i == 5)) 2105 continue; 2106 2107 set_debugreg(0, i); 2108 } 2109 } 2110 2111 #ifdef CONFIG_KGDB 2112 /* 2113 * Restore debug regs if using kgdbwait and you have a kernel debugger 2114 * connection established. 2115 */ 2116 static void dbg_restore_debug_regs(void) 2117 { 2118 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) 2119 arch_kgdb_ops.correct_hw_break(); 2120 } 2121 #else /* ! CONFIG_KGDB */ 2122 #define dbg_restore_debug_regs() 2123 #endif /* ! CONFIG_KGDB */ 2124 2125 static void wait_for_master_cpu(int cpu) 2126 { 2127 #ifdef CONFIG_SMP 2128 /* 2129 * wait for ACK from master CPU before continuing 2130 * with AP initialization 2131 */ 2132 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)); 2133 while (!cpumask_test_cpu(cpu, cpu_callout_mask)) 2134 cpu_relax(); 2135 #endif 2136 } 2137 2138 static inline void setup_getcpu(int cpu) 2139 { 2140 unsigned long cpudata = vdso_encode_cpunode(cpu, early_cpu_to_node(cpu)); 2141 struct desc_struct d = { }; 2142 2143 if (boot_cpu_has(X86_FEATURE_RDTSCP) || boot_cpu_has(X86_FEATURE_RDPID)) 2144 wrmsr(MSR_TSC_AUX, cpudata, 0); 2145 2146 /* Store CPU and node number in limit. */ 2147 d.limit0 = cpudata; 2148 d.limit1 = cpudata >> 16; 2149 2150 d.type = 5; /* RO data, expand down, accessed */ 2151 d.dpl = 3; /* Visible to user code */ 2152 d.s = 1; /* Not a system segment */ 2153 d.p = 1; /* Present */ 2154 d.d = 1; /* 32-bit */ 2155 2156 write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_CPUNODE, &d, DESCTYPE_S); 2157 } 2158 2159 #ifdef CONFIG_X86_64 2160 static inline void ucode_cpu_init(int cpu) 2161 { 2162 if (cpu) 2163 load_ucode_ap(); 2164 } 2165 2166 static inline void tss_setup_ist(struct tss_struct *tss) 2167 { 2168 /* Set up the per-CPU TSS IST stacks */ 2169 tss->x86_tss.ist[IST_INDEX_DF] = __this_cpu_ist_top_va(DF); 2170 tss->x86_tss.ist[IST_INDEX_NMI] = __this_cpu_ist_top_va(NMI); 2171 tss->x86_tss.ist[IST_INDEX_DB] = __this_cpu_ist_top_va(DB); 2172 tss->x86_tss.ist[IST_INDEX_MCE] = __this_cpu_ist_top_va(MCE); 2173 /* Only mapped when SEV-ES is active */ 2174 tss->x86_tss.ist[IST_INDEX_VC] = __this_cpu_ist_top_va(VC); 2175 } 2176 2177 #else /* CONFIG_X86_64 */ 2178 2179 static inline void ucode_cpu_init(int cpu) 2180 { 2181 show_ucode_info_early(); 2182 } 2183 2184 static inline void tss_setup_ist(struct tss_struct *tss) { } 2185 2186 #endif /* !CONFIG_X86_64 */ 2187 2188 static inline void tss_setup_io_bitmap(struct tss_struct *tss) 2189 { 2190 tss->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET_INVALID; 2191 2192 #ifdef CONFIG_X86_IOPL_IOPERM 2193 tss->io_bitmap.prev_max = 0; 2194 tss->io_bitmap.prev_sequence = 0; 2195 memset(tss->io_bitmap.bitmap, 0xff, sizeof(tss->io_bitmap.bitmap)); 2196 /* 2197 * Invalidate the extra array entry past the end of the all 2198 * permission bitmap as required by the hardware. 2199 */ 2200 tss->io_bitmap.mapall[IO_BITMAP_LONGS] = ~0UL; 2201 #endif 2202 } 2203 2204 /* 2205 * Setup everything needed to handle exceptions from the IDT, including the IST 2206 * exceptions which use paranoid_entry(). 2207 */ 2208 void cpu_init_exception_handling(void) 2209 { 2210 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw); 2211 int cpu = raw_smp_processor_id(); 2212 2213 /* paranoid_entry() gets the CPU number from the GDT */ 2214 setup_getcpu(cpu); 2215 2216 /* IST vectors need TSS to be set up. */ 2217 tss_setup_ist(tss); 2218 tss_setup_io_bitmap(tss); 2219 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); 2220 2221 load_TR_desc(); 2222 2223 /* GHCB needs to be setup to handle #VC. */ 2224 setup_ghcb(); 2225 2226 /* Finally load the IDT */ 2227 load_current_idt(); 2228 } 2229 2230 /* 2231 * cpu_init() initializes state that is per-CPU. Some data is already 2232 * initialized (naturally) in the bootstrap process, such as the GDT. We 2233 * reload it nevertheless, this function acts as a 'CPU state barrier', 2234 * nothing should get across. 2235 */ 2236 void cpu_init(void) 2237 { 2238 struct task_struct *cur = current; 2239 int cpu = raw_smp_processor_id(); 2240 2241 wait_for_master_cpu(cpu); 2242 2243 ucode_cpu_init(cpu); 2244 2245 #ifdef CONFIG_NUMA 2246 if (this_cpu_read(numa_node) == 0 && 2247 early_cpu_to_node(cpu) != NUMA_NO_NODE) 2248 set_numa_node(early_cpu_to_node(cpu)); 2249 #endif 2250 pr_debug("Initializing CPU#%d\n", cpu); 2251 2252 if (IS_ENABLED(CONFIG_X86_64) || cpu_feature_enabled(X86_FEATURE_VME) || 2253 boot_cpu_has(X86_FEATURE_TSC) || boot_cpu_has(X86_FEATURE_DE)) 2254 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 2255 2256 if (IS_ENABLED(CONFIG_X86_64)) { 2257 loadsegment(fs, 0); 2258 memset(cur->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); 2259 syscall_init(); 2260 2261 wrmsrl(MSR_FS_BASE, 0); 2262 wrmsrl(MSR_KERNEL_GS_BASE, 0); 2263 barrier(); 2264 2265 x2apic_setup(); 2266 } 2267 2268 mmgrab(&init_mm); 2269 cur->active_mm = &init_mm; 2270 BUG_ON(cur->mm); 2271 initialize_tlbstate_and_flush(); 2272 enter_lazy_tlb(&init_mm, cur); 2273 2274 /* 2275 * sp0 points to the entry trampoline stack regardless of what task 2276 * is running. 2277 */ 2278 load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1)); 2279 2280 load_mm_ldt(&init_mm); 2281 2282 clear_all_debug_regs(); 2283 dbg_restore_debug_regs(); 2284 2285 doublefault_init_cpu_tss(); 2286 2287 fpu__init_cpu(); 2288 2289 if (is_uv_system()) 2290 uv_cpu_init(); 2291 2292 load_fixmap_gdt(cpu); 2293 } 2294 2295 #ifdef CONFIG_SMP 2296 void cpu_init_secondary(void) 2297 { 2298 /* 2299 * Relies on the BP having set-up the IDT tables, which are loaded 2300 * on this CPU in cpu_init_exception_handling(). 2301 */ 2302 cpu_init_exception_handling(); 2303 cpu_init(); 2304 } 2305 #endif 2306 2307 #ifdef CONFIG_MICROCODE_LATE_LOADING 2308 /** 2309 * store_cpu_caps() - Store a snapshot of CPU capabilities 2310 * @curr_info: Pointer where to store it 2311 * 2312 * Returns: None 2313 */ 2314 void store_cpu_caps(struct cpuinfo_x86 *curr_info) 2315 { 2316 /* Reload CPUID max function as it might've changed. */ 2317 curr_info->cpuid_level = cpuid_eax(0); 2318 2319 /* Copy all capability leafs and pick up the synthetic ones. */ 2320 memcpy(&curr_info->x86_capability, &boot_cpu_data.x86_capability, 2321 sizeof(curr_info->x86_capability)); 2322 2323 /* Get the hardware CPUID leafs */ 2324 get_cpu_cap(curr_info); 2325 } 2326 2327 /** 2328 * microcode_check() - Check if any CPU capabilities changed after an update. 2329 * @prev_info: CPU capabilities stored before an update. 2330 * 2331 * The microcode loader calls this upon late microcode load to recheck features, 2332 * only when microcode has been updated. Caller holds microcode_mutex and CPU 2333 * hotplug lock. 2334 * 2335 * Return: None 2336 */ 2337 void microcode_check(struct cpuinfo_x86 *prev_info) 2338 { 2339 struct cpuinfo_x86 curr_info; 2340 2341 perf_check_microcode(); 2342 2343 store_cpu_caps(&curr_info); 2344 2345 if (!memcmp(&prev_info->x86_capability, &curr_info.x86_capability, 2346 sizeof(prev_info->x86_capability))) 2347 return; 2348 2349 pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n"); 2350 pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n"); 2351 } 2352 #endif 2353 2354 /* 2355 * Invoked from core CPU hotplug code after hotplug operations 2356 */ 2357 void arch_smt_update(void) 2358 { 2359 /* Handle the speculative execution misfeatures */ 2360 cpu_bugs_smt_update(); 2361 /* Check whether IPI broadcasting can be enabled */ 2362 apic_smt_update(); 2363 } 2364