1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 */ 5 6 #include "i915_reg.h" 7 #include "intel_de.h" 8 #include "intel_display_types.h" 9 #include "intel_fb.h" 10 #include "skl_scaler.h" 11 #include "skl_universal_plane.h" 12 13 /* 14 * The hardware phase 0.0 refers to the center of the pixel. 15 * We want to start from the top/left edge which is phase 16 * -0.5. That matches how the hardware calculates the scaling 17 * factors (from top-left of the first pixel to bottom-right 18 * of the last pixel, as opposed to the pixel centers). 19 * 20 * For 4:2:0 subsampled chroma planes we obviously have to 21 * adjust that so that the chroma sample position lands in 22 * the right spot. 23 * 24 * Note that for packed YCbCr 4:2:2 formats there is no way to 25 * control chroma siting. The hardware simply replicates the 26 * chroma samples for both of the luma samples, and thus we don't 27 * actually get the expected MPEG2 chroma siting convention :( 28 * The same behaviour is observed on pre-SKL platforms as well. 29 * 30 * Theory behind the formula (note that we ignore sub-pixel 31 * source coordinates): 32 * s = source sample position 33 * d = destination sample position 34 * 35 * Downscaling 4:1: 36 * -0.5 37 * | 0.0 38 * | | 1.5 (initial phase) 39 * | | | 40 * v v v 41 * | s | s | s | s | 42 * | d | 43 * 44 * Upscaling 1:4: 45 * -0.5 46 * | -0.375 (initial phase) 47 * | | 0.0 48 * | | | 49 * v v v 50 * | s | 51 * | d | d | d | d | 52 */ 53 static u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited) 54 { 55 int phase = -0x8000; 56 u16 trip = 0; 57 58 if (chroma_cosited) 59 phase += (sub - 1) * 0x8000 / sub; 60 61 phase += scale / (2 * sub); 62 63 /* 64 * Hardware initial phase limited to [-0.5:1.5]. 65 * Since the max hardware scale factor is 3.0, we 66 * should never actually excdeed 1.0 here. 67 */ 68 WARN_ON(phase < -0x8000 || phase > 0x18000); 69 70 if (phase < 0) 71 phase = 0x10000 + phase; 72 else 73 trip = PS_PHASE_TRIP; 74 75 return ((phase >> 2) & PS_PHASE_MASK) | trip; 76 } 77 78 #define SKL_MIN_SRC_W 8 79 #define SKL_MAX_SRC_W 4096 80 #define SKL_MIN_SRC_H 8 81 #define SKL_MAX_SRC_H 4096 82 #define SKL_MIN_DST_W 8 83 #define SKL_MAX_DST_W 4096 84 #define SKL_MIN_DST_H 8 85 #define SKL_MAX_DST_H 4096 86 #define ICL_MAX_SRC_W 5120 87 #define ICL_MAX_SRC_H 4096 88 #define ICL_MAX_DST_W 5120 89 #define ICL_MAX_DST_H 4096 90 #define SKL_MIN_YUV_420_SRC_W 16 91 #define SKL_MIN_YUV_420_SRC_H 16 92 93 static int 94 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, 95 unsigned int scaler_user, int *scaler_id, 96 int src_w, int src_h, int dst_w, int dst_h, 97 const struct drm_format_info *format, 98 u64 modifier, bool need_scaler) 99 { 100 struct intel_crtc_scaler_state *scaler_state = 101 &crtc_state->scaler_state; 102 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 103 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 104 const struct drm_display_mode *adjusted_mode = 105 &crtc_state->hw.adjusted_mode; 106 107 /* 108 * Src coordinates are already rotated by 270 degrees for 109 * the 90/270 degree plane rotation cases (to match the 110 * GTT mapping), hence no need to account for rotation here. 111 */ 112 if (src_w != dst_w || src_h != dst_h) 113 need_scaler = true; 114 115 /* 116 * Scaling/fitting not supported in IF-ID mode in GEN9+ 117 * TODO: Interlace fetch mode doesn't support YUV420 planar formats. 118 * Once NV12 is enabled, handle it here while allocating scaler 119 * for NV12. 120 */ 121 if (DISPLAY_VER(dev_priv) >= 9 && crtc_state->hw.enable && 122 need_scaler && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 123 drm_dbg_kms(&dev_priv->drm, 124 "Pipe/Plane scaling not supported with IF-ID mode\n"); 125 return -EINVAL; 126 } 127 128 /* 129 * if plane is being disabled or scaler is no more required or force detach 130 * - free scaler binded to this plane/crtc 131 * - in order to do this, update crtc->scaler_usage 132 * 133 * Here scaler state in crtc_state is set free so that 134 * scaler can be assigned to other user. Actual register 135 * update to free the scaler is done in plane/panel-fit programming. 136 * For this purpose crtc/plane_state->scaler_id isn't reset here. 137 */ 138 if (force_detach || !need_scaler) { 139 if (*scaler_id >= 0) { 140 scaler_state->scaler_users &= ~(1 << scaler_user); 141 scaler_state->scalers[*scaler_id].in_use = 0; 142 143 drm_dbg_kms(&dev_priv->drm, 144 "scaler_user index %u.%u: " 145 "Staged freeing scaler id %d scaler_users = 0x%x\n", 146 crtc->pipe, scaler_user, *scaler_id, 147 scaler_state->scaler_users); 148 *scaler_id = -1; 149 } 150 return 0; 151 } 152 153 if (format && intel_format_info_is_yuv_semiplanar(format, modifier) && 154 (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) { 155 drm_dbg_kms(&dev_priv->drm, 156 "Planar YUV: src dimensions not met\n"); 157 return -EINVAL; 158 } 159 160 /* range checks */ 161 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || 162 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || 163 (DISPLAY_VER(dev_priv) >= 11 && 164 (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H || 165 dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) || 166 (DISPLAY_VER(dev_priv) < 11 && 167 (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || 168 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H))) { 169 drm_dbg_kms(&dev_priv->drm, 170 "scaler_user index %u.%u: src %ux%u dst %ux%u " 171 "size is out of scaler range\n", 172 crtc->pipe, scaler_user, src_w, src_h, 173 dst_w, dst_h); 174 return -EINVAL; 175 } 176 177 /* mark this plane as a scaler user in crtc_state */ 178 scaler_state->scaler_users |= (1 << scaler_user); 179 drm_dbg_kms(&dev_priv->drm, "scaler_user index %u.%u: " 180 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", 181 crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, 182 scaler_state->scaler_users); 183 184 return 0; 185 } 186 187 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state) 188 { 189 const struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 190 int width, height; 191 192 if (crtc_state->pch_pfit.enabled) { 193 width = drm_rect_width(&crtc_state->pch_pfit.dst); 194 height = drm_rect_height(&crtc_state->pch_pfit.dst); 195 } else { 196 width = pipe_mode->crtc_hdisplay; 197 height = pipe_mode->crtc_vdisplay; 198 } 199 return skl_update_scaler(crtc_state, !crtc_state->hw.active, 200 SKL_CRTC_INDEX, 201 &crtc_state->scaler_state.scaler_id, 202 drm_rect_width(&crtc_state->pipe_src), 203 drm_rect_height(&crtc_state->pipe_src), 204 width, height, NULL, 0, 205 crtc_state->pch_pfit.enabled); 206 } 207 208 /** 209 * skl_update_scaler_plane - Stages update to scaler state for a given plane. 210 * @crtc_state: crtc's scaler state 211 * @plane_state: atomic plane state to update 212 * 213 * Return 214 * 0 - scaler_usage updated successfully 215 * error - requested scaling cannot be supported or other error condition 216 */ 217 int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, 218 struct intel_plane_state *plane_state) 219 { 220 struct intel_plane *intel_plane = 221 to_intel_plane(plane_state->uapi.plane); 222 struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev); 223 struct drm_framebuffer *fb = plane_state->hw.fb; 224 int ret; 225 bool force_detach = !fb || !plane_state->uapi.visible; 226 bool need_scaler = false; 227 228 /* Pre-gen11 and SDR planes always need a scaler for planar formats. */ 229 if (!icl_is_hdr_plane(dev_priv, intel_plane->id) && 230 fb && intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) 231 need_scaler = true; 232 233 ret = skl_update_scaler(crtc_state, force_detach, 234 drm_plane_index(&intel_plane->base), 235 &plane_state->scaler_id, 236 drm_rect_width(&plane_state->uapi.src) >> 16, 237 drm_rect_height(&plane_state->uapi.src) >> 16, 238 drm_rect_width(&plane_state->uapi.dst), 239 drm_rect_height(&plane_state->uapi.dst), 240 fb ? fb->format : NULL, 241 fb ? fb->modifier : 0, 242 need_scaler); 243 244 if (ret || plane_state->scaler_id < 0) 245 return ret; 246 247 /* check colorkey */ 248 if (plane_state->ckey.flags) { 249 drm_dbg_kms(&dev_priv->drm, 250 "[PLANE:%d:%s] scaling with color key not allowed", 251 intel_plane->base.base.id, 252 intel_plane->base.name); 253 return -EINVAL; 254 } 255 256 /* Check src format */ 257 switch (fb->format->format) { 258 case DRM_FORMAT_RGB565: 259 case DRM_FORMAT_XBGR8888: 260 case DRM_FORMAT_XRGB8888: 261 case DRM_FORMAT_ABGR8888: 262 case DRM_FORMAT_ARGB8888: 263 case DRM_FORMAT_XRGB2101010: 264 case DRM_FORMAT_XBGR2101010: 265 case DRM_FORMAT_ARGB2101010: 266 case DRM_FORMAT_ABGR2101010: 267 case DRM_FORMAT_YUYV: 268 case DRM_FORMAT_YVYU: 269 case DRM_FORMAT_UYVY: 270 case DRM_FORMAT_VYUY: 271 case DRM_FORMAT_NV12: 272 case DRM_FORMAT_XYUV8888: 273 case DRM_FORMAT_P010: 274 case DRM_FORMAT_P012: 275 case DRM_FORMAT_P016: 276 case DRM_FORMAT_Y210: 277 case DRM_FORMAT_Y212: 278 case DRM_FORMAT_Y216: 279 case DRM_FORMAT_XVYU2101010: 280 case DRM_FORMAT_XVYU12_16161616: 281 case DRM_FORMAT_XVYU16161616: 282 break; 283 case DRM_FORMAT_XBGR16161616F: 284 case DRM_FORMAT_ABGR16161616F: 285 case DRM_FORMAT_XRGB16161616F: 286 case DRM_FORMAT_ARGB16161616F: 287 if (DISPLAY_VER(dev_priv) >= 11) 288 break; 289 fallthrough; 290 default: 291 drm_dbg_kms(&dev_priv->drm, 292 "[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n", 293 intel_plane->base.base.id, intel_plane->base.name, 294 fb->base.id, fb->format->format); 295 return -EINVAL; 296 } 297 298 return 0; 299 } 300 301 static int glk_coef_tap(int i) 302 { 303 return i % 7; 304 } 305 306 static u16 glk_nearest_filter_coef(int t) 307 { 308 return t == 3 ? 0x0800 : 0x3000; 309 } 310 311 /* 312 * Theory behind setting nearest-neighbor integer scaling: 313 * 314 * 17 phase of 7 taps requires 119 coefficients in 60 dwords per set. 315 * The letter represents the filter tap (D is the center tap) and the number 316 * represents the coefficient set for a phase (0-16). 317 * 318 * +------------+------------------------+------------------------+ 319 * |Index value | Data value coeffient 1 | Data value coeffient 2 | 320 * +------------+------------------------+------------------------+ 321 * | 00h | B0 | A0 | 322 * +------------+------------------------+------------------------+ 323 * | 01h | D0 | C0 | 324 * +------------+------------------------+------------------------+ 325 * | 02h | F0 | E0 | 326 * +------------+------------------------+------------------------+ 327 * | 03h | A1 | G0 | 328 * +------------+------------------------+------------------------+ 329 * | 04h | C1 | B1 | 330 * +------------+------------------------+------------------------+ 331 * | ... | ... | ... | 332 * +------------+------------------------+------------------------+ 333 * | 38h | B16 | A16 | 334 * +------------+------------------------+------------------------+ 335 * | 39h | D16 | C16 | 336 * +------------+------------------------+------------------------+ 337 * | 3Ah | F16 | C16 | 338 * +------------+------------------------+------------------------+ 339 * | 3Bh | Reserved | G16 | 340 * +------------+------------------------+------------------------+ 341 * 342 * To enable nearest-neighbor scaling: program scaler coefficents with 343 * the center tap (Dxx) values set to 1 and all other values set to 0 as per 344 * SCALER_COEFFICIENT_FORMAT 345 * 346 */ 347 348 static void glk_program_nearest_filter_coefs(struct drm_i915_private *dev_priv, 349 enum pipe pipe, int id, int set) 350 { 351 int i; 352 353 intel_de_write_fw(dev_priv, GLK_PS_COEF_INDEX_SET(pipe, id, set), 354 PS_COEE_INDEX_AUTO_INC); 355 356 for (i = 0; i < 17 * 7; i += 2) { 357 u32 tmp; 358 int t; 359 360 t = glk_coef_tap(i); 361 tmp = glk_nearest_filter_coef(t); 362 363 t = glk_coef_tap(i + 1); 364 tmp |= glk_nearest_filter_coef(t) << 16; 365 366 intel_de_write_fw(dev_priv, GLK_PS_COEF_DATA_SET(pipe, id, set), 367 tmp); 368 } 369 370 intel_de_write_fw(dev_priv, GLK_PS_COEF_INDEX_SET(pipe, id, set), 0); 371 } 372 373 static u32 skl_scaler_get_filter_select(enum drm_scaling_filter filter, int set) 374 { 375 if (filter == DRM_SCALING_FILTER_NEAREST_NEIGHBOR) { 376 return (PS_FILTER_PROGRAMMED | 377 PS_Y_VERT_FILTER_SELECT(set) | 378 PS_Y_HORZ_FILTER_SELECT(set) | 379 PS_UV_VERT_FILTER_SELECT(set) | 380 PS_UV_HORZ_FILTER_SELECT(set)); 381 } 382 383 return PS_FILTER_MEDIUM; 384 } 385 386 static void skl_scaler_setup_filter(struct drm_i915_private *dev_priv, enum pipe pipe, 387 int id, int set, enum drm_scaling_filter filter) 388 { 389 switch (filter) { 390 case DRM_SCALING_FILTER_DEFAULT: 391 break; 392 case DRM_SCALING_FILTER_NEAREST_NEIGHBOR: 393 glk_program_nearest_filter_coefs(dev_priv, pipe, id, set); 394 break; 395 default: 396 MISSING_CASE(filter); 397 } 398 } 399 400 void skl_pfit_enable(const struct intel_crtc_state *crtc_state) 401 { 402 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 403 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 404 const struct intel_crtc_scaler_state *scaler_state = 405 &crtc_state->scaler_state; 406 const struct drm_rect *dst = &crtc_state->pch_pfit.dst; 407 u16 uv_rgb_hphase, uv_rgb_vphase; 408 enum pipe pipe = crtc->pipe; 409 int width = drm_rect_width(dst); 410 int height = drm_rect_height(dst); 411 int x = dst->x1; 412 int y = dst->y1; 413 int hscale, vscale; 414 struct drm_rect src; 415 int id; 416 u32 ps_ctrl; 417 418 if (!crtc_state->pch_pfit.enabled) 419 return; 420 421 if (drm_WARN_ON(&dev_priv->drm, 422 crtc_state->scaler_state.scaler_id < 0)) 423 return; 424 425 drm_rect_init(&src, 0, 0, 426 drm_rect_width(&crtc_state->pipe_src) << 16, 427 drm_rect_height(&crtc_state->pipe_src) << 16); 428 429 hscale = drm_rect_calc_hscale(&src, dst, 0, INT_MAX); 430 vscale = drm_rect_calc_vscale(&src, dst, 0, INT_MAX); 431 432 uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false); 433 uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false); 434 435 id = scaler_state->scaler_id; 436 437 ps_ctrl = skl_scaler_get_filter_select(crtc_state->hw.scaling_filter, 0); 438 ps_ctrl |= PS_SCALER_EN | scaler_state->scalers[id].mode; 439 440 skl_scaler_setup_filter(dev_priv, pipe, id, 0, 441 crtc_state->hw.scaling_filter); 442 443 intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, id), ps_ctrl); 444 445 intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, id), 446 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase)); 447 intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, id), 448 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase)); 449 intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, id), 450 x << 16 | y); 451 intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, id), 452 width << 16 | height); 453 } 454 455 void 456 skl_program_plane_scaler(struct intel_plane *plane, 457 const struct intel_crtc_state *crtc_state, 458 const struct intel_plane_state *plane_state) 459 { 460 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 461 const struct drm_framebuffer *fb = plane_state->hw.fb; 462 enum pipe pipe = plane->pipe; 463 int scaler_id = plane_state->scaler_id; 464 const struct intel_scaler *scaler = 465 &crtc_state->scaler_state.scalers[scaler_id]; 466 int crtc_x = plane_state->uapi.dst.x1; 467 int crtc_y = plane_state->uapi.dst.y1; 468 u32 crtc_w = drm_rect_width(&plane_state->uapi.dst); 469 u32 crtc_h = drm_rect_height(&plane_state->uapi.dst); 470 u16 y_hphase, uv_rgb_hphase; 471 u16 y_vphase, uv_rgb_vphase; 472 int hscale, vscale; 473 u32 ps_ctrl; 474 475 hscale = drm_rect_calc_hscale(&plane_state->uapi.src, 476 &plane_state->uapi.dst, 477 0, INT_MAX); 478 vscale = drm_rect_calc_vscale(&plane_state->uapi.src, 479 &plane_state->uapi.dst, 480 0, INT_MAX); 481 482 /* TODO: handle sub-pixel coordinates */ 483 if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) && 484 !icl_is_hdr_plane(dev_priv, plane->id)) { 485 y_hphase = skl_scaler_calc_phase(1, hscale, false); 486 y_vphase = skl_scaler_calc_phase(1, vscale, false); 487 488 /* MPEG2 chroma siting convention */ 489 uv_rgb_hphase = skl_scaler_calc_phase(2, hscale, true); 490 uv_rgb_vphase = skl_scaler_calc_phase(2, vscale, false); 491 } else { 492 /* not used */ 493 y_hphase = 0; 494 y_vphase = 0; 495 496 uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false); 497 uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false); 498 } 499 500 ps_ctrl = skl_scaler_get_filter_select(plane_state->hw.scaling_filter, 0); 501 ps_ctrl |= PS_SCALER_EN | PS_PLANE_SEL(plane->id) | scaler->mode; 502 503 skl_scaler_setup_filter(dev_priv, pipe, scaler_id, 0, 504 plane_state->hw.scaling_filter); 505 506 intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); 507 intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, scaler_id), 508 PS_Y_PHASE(y_vphase) | PS_UV_RGB_PHASE(uv_rgb_vphase)); 509 intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, scaler_id), 510 PS_Y_PHASE(y_hphase) | PS_UV_RGB_PHASE(uv_rgb_hphase)); 511 intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, scaler_id), 512 (crtc_x << 16) | crtc_y); 513 intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, scaler_id), 514 (crtc_w << 16) | crtc_h); 515 } 516 517 static void skl_detach_scaler(struct intel_crtc *crtc, int id) 518 { 519 struct drm_device *dev = crtc->base.dev; 520 struct drm_i915_private *dev_priv = to_i915(dev); 521 522 intel_de_write_fw(dev_priv, SKL_PS_CTRL(crtc->pipe, id), 0); 523 intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(crtc->pipe, id), 0); 524 intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, id), 0); 525 } 526 527 /* 528 * This function detaches (aka. unbinds) unused scalers in hardware 529 */ 530 void skl_detach_scalers(const struct intel_crtc_state *crtc_state) 531 { 532 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 533 const struct intel_crtc_scaler_state *scaler_state = 534 &crtc_state->scaler_state; 535 int i; 536 537 /* loop through and disable scalers that aren't in use */ 538 for (i = 0; i < crtc->num_scalers; i++) { 539 if (!scaler_state->scalers[i].in_use) 540 skl_detach_scaler(crtc, i); 541 } 542 } 543 544 void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state) 545 { 546 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 547 int i; 548 549 for (i = 0; i < crtc->num_scalers; i++) 550 skl_detach_scaler(crtc, i); 551 } 552