1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2020 Unisoc Inc. 4 */ 5 6 #include <linux/component.h> 7 #include <linux/module.h> 8 #include <linux/of_address.h> 9 #include <linux/of_device.h> 10 #include <linux/of_irq.h> 11 #include <linux/of_graph.h> 12 #include <video/mipi_display.h> 13 14 #include <drm/drm_atomic_helper.h> 15 #include <drm/drm_bridge.h> 16 #include <drm/drm_of.h> 17 #include <drm/drm_probe_helper.h> 18 19 #include "sprd_drm.h" 20 #include "sprd_dpu.h" 21 #include "sprd_dsi.h" 22 23 #define SOFT_RESET 0x04 24 #define MASK_PROTOCOL_INT 0x0C 25 #define MASK_INTERNAL_INT 0x14 26 #define DSI_MODE_CFG 0x18 27 28 #define VIRTUAL_CHANNEL_ID 0x1C 29 #define GEN_RX_VCID GENMASK(1, 0) 30 #define VIDEO_PKT_VCID GENMASK(3, 2) 31 32 #define DPI_VIDEO_FORMAT 0x20 33 #define DPI_VIDEO_MODE_FORMAT GENMASK(5, 0) 34 #define LOOSELY18_EN BIT(6) 35 36 #define VIDEO_PKT_CONFIG 0x24 37 #define VIDEO_PKT_SIZE GENMASK(15, 0) 38 #define VIDEO_LINE_CHUNK_NUM GENMASK(31, 16) 39 40 #define VIDEO_LINE_HBLK_TIME 0x28 41 #define VIDEO_LINE_HBP_TIME GENMASK(15, 0) 42 #define VIDEO_LINE_HSA_TIME GENMASK(31, 16) 43 44 #define VIDEO_LINE_TIME 0x2C 45 46 #define VIDEO_VBLK_LINES 0x30 47 #define VFP_LINES GENMASK(9, 0) 48 #define VBP_LINES GENMASK(19, 10) 49 #define VSA_LINES GENMASK(29, 20) 50 51 #define VIDEO_VACTIVE_LINES 0x34 52 53 #define VID_MODE_CFG 0x38 54 #define VID_MODE_TYPE GENMASK(1, 0) 55 #define LP_VSA_EN BIT(8) 56 #define LP_VBP_EN BIT(9) 57 #define LP_VFP_EN BIT(10) 58 #define LP_VACT_EN BIT(11) 59 #define LP_HBP_EN BIT(12) 60 #define LP_HFP_EN BIT(13) 61 #define FRAME_BTA_ACK_EN BIT(14) 62 63 #define TIMEOUT_CNT_CLK_CONFIG 0x40 64 #define HTX_TO_CONFIG 0x44 65 #define LRX_H_TO_CONFIG 0x48 66 67 #define TX_ESC_CLK_CONFIG 0x5C 68 69 #define CMD_MODE_CFG 0x68 70 #define TEAR_FX_EN BIT(0) 71 72 #define GEN_HDR 0x6C 73 #define GEN_DT GENMASK(5, 0) 74 #define GEN_VC GENMASK(7, 6) 75 76 #define GEN_PLD_DATA 0x70 77 78 #define PHY_CLK_LANE_LP_CTRL 0x74 79 #define PHY_CLKLANE_TX_REQ_HS BIT(0) 80 #define AUTO_CLKLANE_CTRL_EN BIT(1) 81 82 #define PHY_INTERFACE_CTRL 0x78 83 #define RF_PHY_SHUTDOWN BIT(0) 84 #define RF_PHY_RESET_N BIT(1) 85 #define RF_PHY_CLK_EN BIT(2) 86 87 #define CMD_MODE_STATUS 0x98 88 #define GEN_CMD_RDATA_FIFO_EMPTY BIT(1) 89 #define GEN_CMD_WDATA_FIFO_EMPTY BIT(3) 90 #define GEN_CMD_CMD_FIFO_EMPTY BIT(5) 91 #define GEN_CMD_RDCMD_DONE BIT(7) 92 93 #define PHY_STATUS 0x9C 94 #define PHY_LOCK BIT(1) 95 96 #define PHY_MIN_STOP_TIME 0xA0 97 #define PHY_LANE_NUM_CONFIG 0xA4 98 99 #define PHY_CLKLANE_TIME_CONFIG 0xA8 100 #define PHY_CLKLANE_LP_TO_HS_TIME GENMASK(15, 0) 101 #define PHY_CLKLANE_HS_TO_LP_TIME GENMASK(31, 16) 102 103 #define PHY_DATALANE_TIME_CONFIG 0xAC 104 #define PHY_DATALANE_LP_TO_HS_TIME GENMASK(15, 0) 105 #define PHY_DATALANE_HS_TO_LP_TIME GENMASK(31, 16) 106 107 #define MAX_READ_TIME 0xB0 108 109 #define RX_PKT_CHECK_CONFIG 0xB4 110 #define RX_PKT_ECC_EN BIT(0) 111 #define RX_PKT_CRC_EN BIT(1) 112 113 #define TA_EN 0xB8 114 115 #define EOTP_EN 0xBC 116 #define TX_EOTP_EN BIT(0) 117 #define RX_EOTP_EN BIT(1) 118 119 #define VIDEO_NULLPKT_SIZE 0xC0 120 #define DCS_WM_PKT_SIZE 0xC4 121 122 #define VIDEO_SIG_DELAY_CONFIG 0xD0 123 #define VIDEO_SIG_DELAY GENMASK(23, 0) 124 125 #define PHY_TST_CTRL0 0xF0 126 #define PHY_TESTCLR BIT(0) 127 #define PHY_TESTCLK BIT(1) 128 129 #define PHY_TST_CTRL1 0xF4 130 #define PHY_TESTDIN GENMASK(7, 0) 131 #define PHY_TESTDOUT GENMASK(15, 8) 132 #define PHY_TESTEN BIT(16) 133 134 #define host_to_dsi(host) \ 135 container_of(host, struct sprd_dsi, host) 136 137 static inline u32 138 dsi_reg_rd(struct dsi_context *ctx, u32 offset, u32 mask, 139 u32 shift) 140 { 141 return (readl(ctx->base + offset) & mask) >> shift; 142 } 143 144 static inline void 145 dsi_reg_wr(struct dsi_context *ctx, u32 offset, u32 mask, 146 u32 shift, u32 val) 147 { 148 u32 ret; 149 150 ret = readl(ctx->base + offset); 151 ret &= ~mask; 152 ret |= (val << shift) & mask; 153 writel(ret, ctx->base + offset); 154 } 155 156 static inline void 157 dsi_reg_up(struct dsi_context *ctx, u32 offset, u32 mask, 158 u32 val) 159 { 160 u32 ret = readl(ctx->base + offset); 161 162 writel((ret & ~mask) | (val & mask), ctx->base + offset); 163 } 164 165 static int regmap_tst_io_write(void *context, u32 reg, u32 val) 166 { 167 struct sprd_dsi *dsi = context; 168 struct dsi_context *ctx = &dsi->ctx; 169 170 if (val > 0xff || reg > 0xff) 171 return -EINVAL; 172 173 drm_dbg(dsi->drm, "reg = 0x%02x, val = 0x%02x\n", reg, val); 174 175 dsi_reg_up(ctx, PHY_TST_CTRL1, PHY_TESTEN, PHY_TESTEN); 176 dsi_reg_wr(ctx, PHY_TST_CTRL1, PHY_TESTDIN, 0, reg); 177 dsi_reg_up(ctx, PHY_TST_CTRL0, PHY_TESTCLK, PHY_TESTCLK); 178 dsi_reg_up(ctx, PHY_TST_CTRL0, PHY_TESTCLK, 0); 179 dsi_reg_up(ctx, PHY_TST_CTRL1, PHY_TESTEN, 0); 180 dsi_reg_wr(ctx, PHY_TST_CTRL1, PHY_TESTDIN, 0, val); 181 dsi_reg_up(ctx, PHY_TST_CTRL0, PHY_TESTCLK, PHY_TESTCLK); 182 dsi_reg_up(ctx, PHY_TST_CTRL0, PHY_TESTCLK, 0); 183 184 return 0; 185 } 186 187 static int regmap_tst_io_read(void *context, u32 reg, u32 *val) 188 { 189 struct sprd_dsi *dsi = context; 190 struct dsi_context *ctx = &dsi->ctx; 191 int ret; 192 193 if (reg > 0xff) 194 return -EINVAL; 195 196 dsi_reg_up(ctx, PHY_TST_CTRL1, PHY_TESTEN, PHY_TESTEN); 197 dsi_reg_wr(ctx, PHY_TST_CTRL1, PHY_TESTDIN, 0, reg); 198 dsi_reg_up(ctx, PHY_TST_CTRL0, PHY_TESTCLK, PHY_TESTCLK); 199 dsi_reg_up(ctx, PHY_TST_CTRL0, PHY_TESTCLK, 0); 200 dsi_reg_up(ctx, PHY_TST_CTRL1, PHY_TESTEN, 0); 201 202 udelay(1); 203 204 ret = dsi_reg_rd(ctx, PHY_TST_CTRL1, PHY_TESTDOUT, 8); 205 if (ret < 0) 206 return ret; 207 208 *val = ret; 209 210 drm_dbg(dsi->drm, "reg = 0x%02x, val = 0x%02x\n", reg, *val); 211 return 0; 212 } 213 214 static struct regmap_bus regmap_tst_io = { 215 .reg_write = regmap_tst_io_write, 216 .reg_read = regmap_tst_io_read, 217 }; 218 219 static const struct regmap_config byte_config = { 220 .reg_bits = 8, 221 .val_bits = 8, 222 }; 223 224 static int dphy_wait_pll_locked(struct dsi_context *ctx) 225 { 226 struct sprd_dsi *dsi = container_of(ctx, struct sprd_dsi, ctx); 227 int i; 228 229 for (i = 0; i < 50000; i++) { 230 if (dsi_reg_rd(ctx, PHY_STATUS, PHY_LOCK, 1)) 231 return 0; 232 udelay(3); 233 } 234 235 drm_err(dsi->drm, "dphy pll can not be locked\n"); 236 return -ETIMEDOUT; 237 } 238 239 static int dsi_wait_tx_payload_fifo_empty(struct dsi_context *ctx) 240 { 241 int i; 242 243 for (i = 0; i < 5000; i++) { 244 if (dsi_reg_rd(ctx, CMD_MODE_STATUS, GEN_CMD_WDATA_FIFO_EMPTY, 3)) 245 return 0; 246 udelay(1); 247 } 248 249 return -ETIMEDOUT; 250 } 251 252 static int dsi_wait_tx_cmd_fifo_empty(struct dsi_context *ctx) 253 { 254 int i; 255 256 for (i = 0; i < 5000; i++) { 257 if (dsi_reg_rd(ctx, CMD_MODE_STATUS, GEN_CMD_CMD_FIFO_EMPTY, 5)) 258 return 0; 259 udelay(1); 260 } 261 262 return -ETIMEDOUT; 263 } 264 265 static int dsi_wait_rd_resp_completed(struct dsi_context *ctx) 266 { 267 int i; 268 269 for (i = 0; i < 10000; i++) { 270 if (dsi_reg_rd(ctx, CMD_MODE_STATUS, GEN_CMD_RDCMD_DONE, 7)) 271 return 0; 272 udelay(10); 273 } 274 275 return -ETIMEDOUT; 276 } 277 278 static u16 calc_bytes_per_pixel_x100(int coding) 279 { 280 u16 bpp_x100; 281 282 switch (coding) { 283 case COLOR_CODE_16BIT_CONFIG1: 284 case COLOR_CODE_16BIT_CONFIG2: 285 case COLOR_CODE_16BIT_CONFIG3: 286 bpp_x100 = 200; 287 break; 288 case COLOR_CODE_18BIT_CONFIG1: 289 case COLOR_CODE_18BIT_CONFIG2: 290 bpp_x100 = 225; 291 break; 292 case COLOR_CODE_24BIT: 293 bpp_x100 = 300; 294 break; 295 case COLOR_CODE_COMPRESSTION: 296 bpp_x100 = 100; 297 break; 298 case COLOR_CODE_20BIT_YCC422_LOOSELY: 299 bpp_x100 = 250; 300 break; 301 case COLOR_CODE_24BIT_YCC422: 302 bpp_x100 = 300; 303 break; 304 case COLOR_CODE_16BIT_YCC422: 305 bpp_x100 = 200; 306 break; 307 case COLOR_CODE_30BIT: 308 bpp_x100 = 375; 309 break; 310 case COLOR_CODE_36BIT: 311 bpp_x100 = 450; 312 break; 313 case COLOR_CODE_12BIT_YCC420: 314 bpp_x100 = 150; 315 break; 316 default: 317 DRM_ERROR("invalid color coding"); 318 bpp_x100 = 0; 319 break; 320 } 321 322 return bpp_x100; 323 } 324 325 static u8 calc_video_size_step(int coding) 326 { 327 u8 video_size_step; 328 329 switch (coding) { 330 case COLOR_CODE_16BIT_CONFIG1: 331 case COLOR_CODE_16BIT_CONFIG2: 332 case COLOR_CODE_16BIT_CONFIG3: 333 case COLOR_CODE_18BIT_CONFIG1: 334 case COLOR_CODE_18BIT_CONFIG2: 335 case COLOR_CODE_24BIT: 336 case COLOR_CODE_COMPRESSTION: 337 return video_size_step = 1; 338 case COLOR_CODE_20BIT_YCC422_LOOSELY: 339 case COLOR_CODE_24BIT_YCC422: 340 case COLOR_CODE_16BIT_YCC422: 341 case COLOR_CODE_30BIT: 342 case COLOR_CODE_36BIT: 343 case COLOR_CODE_12BIT_YCC420: 344 return video_size_step = 2; 345 default: 346 DRM_ERROR("invalid color coding"); 347 return 0; 348 } 349 } 350 351 static u16 round_video_size(int coding, u16 video_size) 352 { 353 switch (coding) { 354 case COLOR_CODE_16BIT_YCC422: 355 case COLOR_CODE_24BIT_YCC422: 356 case COLOR_CODE_20BIT_YCC422_LOOSELY: 357 case COLOR_CODE_12BIT_YCC420: 358 /* round up active H pixels to a multiple of 2 */ 359 if ((video_size % 2) != 0) 360 video_size += 1; 361 break; 362 default: 363 break; 364 } 365 366 return video_size; 367 } 368 369 #define SPRD_MIPI_DSI_FMT_DSC 0xff 370 static u32 fmt_to_coding(u32 fmt) 371 { 372 switch (fmt) { 373 case MIPI_DSI_FMT_RGB565: 374 return COLOR_CODE_16BIT_CONFIG1; 375 case MIPI_DSI_FMT_RGB666: 376 case MIPI_DSI_FMT_RGB666_PACKED: 377 return COLOR_CODE_18BIT_CONFIG1; 378 case MIPI_DSI_FMT_RGB888: 379 return COLOR_CODE_24BIT; 380 case SPRD_MIPI_DSI_FMT_DSC: 381 return COLOR_CODE_COMPRESSTION; 382 default: 383 DRM_ERROR("Unsupported format (%d)\n", fmt); 384 return COLOR_CODE_24BIT; 385 } 386 } 387 388 #define ns_to_cycle(ns, byte_clk) \ 389 DIV_ROUND_UP((ns) * (byte_clk), 1000000) 390 391 static void sprd_dsi_init(struct dsi_context *ctx) 392 { 393 struct sprd_dsi *dsi = container_of(ctx, struct sprd_dsi, ctx); 394 u32 byte_clk = dsi->slave->hs_rate / 8; 395 u16 data_hs2lp, data_lp2hs, clk_hs2lp, clk_lp2hs; 396 u16 max_rd_time; 397 int div; 398 399 writel(0, ctx->base + SOFT_RESET); 400 writel(0xffffffff, ctx->base + MASK_PROTOCOL_INT); 401 writel(0xffffffff, ctx->base + MASK_INTERNAL_INT); 402 writel(1, ctx->base + DSI_MODE_CFG); 403 dsi_reg_up(ctx, EOTP_EN, RX_EOTP_EN, 0); 404 dsi_reg_up(ctx, EOTP_EN, TX_EOTP_EN, 0); 405 dsi_reg_up(ctx, RX_PKT_CHECK_CONFIG, RX_PKT_ECC_EN, RX_PKT_ECC_EN); 406 dsi_reg_up(ctx, RX_PKT_CHECK_CONFIG, RX_PKT_CRC_EN, RX_PKT_CRC_EN); 407 writel(1, ctx->base + TA_EN); 408 dsi_reg_up(ctx, VIRTUAL_CHANNEL_ID, VIDEO_PKT_VCID, 0); 409 dsi_reg_up(ctx, VIRTUAL_CHANNEL_ID, GEN_RX_VCID, 0); 410 411 div = DIV_ROUND_UP(byte_clk, dsi->slave->lp_rate); 412 writel(div, ctx->base + TX_ESC_CLK_CONFIG); 413 414 max_rd_time = ns_to_cycle(ctx->max_rd_time, byte_clk); 415 writel(max_rd_time, ctx->base + MAX_READ_TIME); 416 417 data_hs2lp = ns_to_cycle(ctx->data_hs2lp, byte_clk); 418 data_lp2hs = ns_to_cycle(ctx->data_lp2hs, byte_clk); 419 clk_hs2lp = ns_to_cycle(ctx->clk_hs2lp, byte_clk); 420 clk_lp2hs = ns_to_cycle(ctx->clk_lp2hs, byte_clk); 421 dsi_reg_wr(ctx, PHY_DATALANE_TIME_CONFIG, 422 PHY_DATALANE_HS_TO_LP_TIME, 16, data_hs2lp); 423 dsi_reg_wr(ctx, PHY_DATALANE_TIME_CONFIG, 424 PHY_DATALANE_LP_TO_HS_TIME, 0, data_lp2hs); 425 dsi_reg_wr(ctx, PHY_CLKLANE_TIME_CONFIG, 426 PHY_CLKLANE_HS_TO_LP_TIME, 16, clk_hs2lp); 427 dsi_reg_wr(ctx, PHY_CLKLANE_TIME_CONFIG, 428 PHY_CLKLANE_LP_TO_HS_TIME, 0, clk_lp2hs); 429 430 writel(1, ctx->base + SOFT_RESET); 431 } 432 433 /* 434 * Free up resources and shutdown host controller and PHY 435 */ 436 static void sprd_dsi_fini(struct dsi_context *ctx) 437 { 438 writel(0xffffffff, ctx->base + MASK_PROTOCOL_INT); 439 writel(0xffffffff, ctx->base + MASK_INTERNAL_INT); 440 writel(0, ctx->base + SOFT_RESET); 441 } 442 443 /* 444 * If not in burst mode, it will compute the video and null packet sizes 445 * according to necessity. 446 * Configure timers for data lanes and/or clock lane to return to LP when 447 * bandwidth is not filled by data. 448 */ 449 static int sprd_dsi_dpi_video(struct dsi_context *ctx) 450 { 451 struct sprd_dsi *dsi = container_of(ctx, struct sprd_dsi, ctx); 452 struct videomode *vm = &ctx->vm; 453 u32 byte_clk = dsi->slave->hs_rate / 8; 454 u16 bpp_x100; 455 u16 video_size; 456 u32 ratio_x1000; 457 u16 null_pkt_size = 0; 458 u8 video_size_step; 459 u32 hs_to; 460 u32 total_bytes; 461 u32 bytes_per_chunk; 462 u32 chunks = 0; 463 u32 bytes_left = 0; 464 u32 chunk_overhead; 465 const u8 pkt_header = 6; 466 u8 coding; 467 int div; 468 u16 hline; 469 u16 byte_cycle; 470 471 coding = fmt_to_coding(dsi->slave->format); 472 video_size = round_video_size(coding, vm->hactive); 473 bpp_x100 = calc_bytes_per_pixel_x100(coding); 474 video_size_step = calc_video_size_step(coding); 475 ratio_x1000 = byte_clk * 1000 / (vm->pixelclock / 1000); 476 hline = vm->hactive + vm->hsync_len + vm->hfront_porch + 477 vm->hback_porch; 478 479 writel(0, ctx->base + SOFT_RESET); 480 dsi_reg_wr(ctx, VID_MODE_CFG, FRAME_BTA_ACK_EN, 15, ctx->frame_ack_en); 481 dsi_reg_wr(ctx, DPI_VIDEO_FORMAT, DPI_VIDEO_MODE_FORMAT, 0, coding); 482 dsi_reg_wr(ctx, VID_MODE_CFG, VID_MODE_TYPE, 0, ctx->burst_mode); 483 byte_cycle = 95 * hline * ratio_x1000 / 100000; 484 dsi_reg_wr(ctx, VIDEO_SIG_DELAY_CONFIG, VIDEO_SIG_DELAY, 0, byte_cycle); 485 byte_cycle = hline * ratio_x1000 / 1000; 486 writel(byte_cycle, ctx->base + VIDEO_LINE_TIME); 487 byte_cycle = vm->hsync_len * ratio_x1000 / 1000; 488 dsi_reg_wr(ctx, VIDEO_LINE_HBLK_TIME, VIDEO_LINE_HSA_TIME, 16, byte_cycle); 489 byte_cycle = vm->hback_porch * ratio_x1000 / 1000; 490 dsi_reg_wr(ctx, VIDEO_LINE_HBLK_TIME, VIDEO_LINE_HBP_TIME, 0, byte_cycle); 491 writel(vm->vactive, ctx->base + VIDEO_VACTIVE_LINES); 492 dsi_reg_wr(ctx, VIDEO_VBLK_LINES, VFP_LINES, 0, vm->vfront_porch); 493 dsi_reg_wr(ctx, VIDEO_VBLK_LINES, VBP_LINES, 10, vm->vback_porch); 494 dsi_reg_wr(ctx, VIDEO_VBLK_LINES, VSA_LINES, 20, vm->vsync_len); 495 dsi_reg_up(ctx, VID_MODE_CFG, LP_HBP_EN | LP_HFP_EN | LP_VACT_EN | 496 LP_VFP_EN | LP_VBP_EN | LP_VSA_EN, LP_HBP_EN | LP_HFP_EN | 497 LP_VACT_EN | LP_VFP_EN | LP_VBP_EN | LP_VSA_EN); 498 499 hs_to = (hline * vm->vactive) + (2 * bpp_x100) / 100; 500 for (div = 0x80; (div < hs_to) && (div > 2); div--) { 501 if ((hs_to % div) == 0) { 502 writel(div, ctx->base + TIMEOUT_CNT_CLK_CONFIG); 503 writel(hs_to / div, ctx->base + LRX_H_TO_CONFIG); 504 writel(hs_to / div, ctx->base + HTX_TO_CONFIG); 505 break; 506 } 507 } 508 509 if (ctx->burst_mode == VIDEO_BURST_WITH_SYNC_PULSES) { 510 dsi_reg_wr(ctx, VIDEO_PKT_CONFIG, VIDEO_PKT_SIZE, 0, video_size); 511 writel(0, ctx->base + VIDEO_NULLPKT_SIZE); 512 dsi_reg_up(ctx, VIDEO_PKT_CONFIG, VIDEO_LINE_CHUNK_NUM, 0); 513 } else { 514 /* non burst transmission */ 515 null_pkt_size = 0; 516 517 /* bytes to be sent - first as one chunk */ 518 bytes_per_chunk = vm->hactive * bpp_x100 / 100 + pkt_header; 519 520 /* hline total bytes from the DPI interface */ 521 total_bytes = (vm->hactive + vm->hfront_porch) * 522 ratio_x1000 / dsi->slave->lanes / 1000; 523 524 /* check if the pixels actually fit on the DSI link */ 525 if (total_bytes < bytes_per_chunk) { 526 drm_err(dsi->drm, "current resolution can not be set\n"); 527 return -EINVAL; 528 } 529 530 chunk_overhead = total_bytes - bytes_per_chunk; 531 532 /* overhead higher than 1 -> enable multi packets */ 533 if (chunk_overhead > 1) { 534 /* multi packets */ 535 for (video_size = video_size_step; 536 video_size < vm->hactive; 537 video_size += video_size_step) { 538 if (vm->hactive * 1000 / video_size % 1000) 539 continue; 540 541 chunks = vm->hactive / video_size; 542 bytes_per_chunk = bpp_x100 * video_size / 100 543 + pkt_header; 544 if (total_bytes >= (bytes_per_chunk * chunks)) { 545 bytes_left = total_bytes - 546 bytes_per_chunk * chunks; 547 break; 548 } 549 } 550 551 /* prevent overflow (unsigned - unsigned) */ 552 if (bytes_left > (pkt_header * chunks)) { 553 null_pkt_size = (bytes_left - 554 pkt_header * chunks) / chunks; 555 /* avoid register overflow */ 556 if (null_pkt_size > 1023) 557 null_pkt_size = 1023; 558 } 559 560 } else { 561 /* single packet */ 562 chunks = 1; 563 564 /* must be a multiple of 4 except 18 loosely */ 565 for (video_size = vm->hactive; 566 (video_size % video_size_step) != 0; 567 video_size++) 568 ; 569 } 570 571 dsi_reg_wr(ctx, VIDEO_PKT_CONFIG, VIDEO_PKT_SIZE, 0, video_size); 572 writel(null_pkt_size, ctx->base + VIDEO_NULLPKT_SIZE); 573 dsi_reg_wr(ctx, VIDEO_PKT_CONFIG, VIDEO_LINE_CHUNK_NUM, 16, chunks); 574 } 575 576 writel(ctx->int0_mask, ctx->base + MASK_PROTOCOL_INT); 577 writel(ctx->int1_mask, ctx->base + MASK_INTERNAL_INT); 578 writel(1, ctx->base + SOFT_RESET); 579 580 return 0; 581 } 582 583 static void sprd_dsi_edpi_video(struct dsi_context *ctx) 584 { 585 struct sprd_dsi *dsi = container_of(ctx, struct sprd_dsi, ctx); 586 const u32 fifo_depth = 1096; 587 const u32 word_length = 4; 588 u32 hactive = ctx->vm.hactive; 589 u32 bpp_x100; 590 u32 max_fifo_len; 591 u8 coding; 592 593 coding = fmt_to_coding(dsi->slave->format); 594 bpp_x100 = calc_bytes_per_pixel_x100(coding); 595 max_fifo_len = word_length * fifo_depth * 100 / bpp_x100; 596 597 writel(0, ctx->base + SOFT_RESET); 598 dsi_reg_wr(ctx, DPI_VIDEO_FORMAT, DPI_VIDEO_MODE_FORMAT, 0, coding); 599 dsi_reg_wr(ctx, CMD_MODE_CFG, TEAR_FX_EN, 0, ctx->te_ack_en); 600 601 if (max_fifo_len > hactive) 602 writel(hactive, ctx->base + DCS_WM_PKT_SIZE); 603 else 604 writel(max_fifo_len, ctx->base + DCS_WM_PKT_SIZE); 605 606 writel(ctx->int0_mask, ctx->base + MASK_PROTOCOL_INT); 607 writel(ctx->int1_mask, ctx->base + MASK_INTERNAL_INT); 608 writel(1, ctx->base + SOFT_RESET); 609 } 610 611 /* 612 * Send a packet on the generic interface, 613 * this function has an active delay to wait for the buffer to clear. 614 * The delay is limited to: 615 * (param_length / 4) x DSIH_FIFO_ACTIVE_WAIT x register access time 616 * the controller restricts the sending of. 617 * 618 * This function will not be able to send Null and Blanking packets due to 619 * controller restriction 620 */ 621 static int sprd_dsi_wr_pkt(struct dsi_context *ctx, u8 vc, u8 type, 622 const u8 *param, u16 len) 623 { 624 struct sprd_dsi *dsi = container_of(ctx, struct sprd_dsi, ctx); 625 u8 wc_lsbyte, wc_msbyte; 626 u32 payload; 627 int i, j, ret; 628 629 if (vc > 3) 630 return -EINVAL; 631 632 /* 1st: for long packet, must config payload first */ 633 ret = dsi_wait_tx_payload_fifo_empty(ctx); 634 if (ret) { 635 drm_err(dsi->drm, "tx payload fifo is not empty\n"); 636 return ret; 637 } 638 639 if (len > 2) { 640 for (i = 0, j = 0; i < len; i += j) { 641 payload = 0; 642 for (j = 0; (j < 4) && ((j + i) < (len)); j++) 643 payload |= param[i + j] << (j * 8); 644 645 writel(payload, ctx->base + GEN_PLD_DATA); 646 } 647 wc_lsbyte = len & 0xff; 648 wc_msbyte = len >> 8; 649 } else { 650 wc_lsbyte = (len > 0) ? param[0] : 0; 651 wc_msbyte = (len > 1) ? param[1] : 0; 652 } 653 654 /* 2nd: then set packet header */ 655 ret = dsi_wait_tx_cmd_fifo_empty(ctx); 656 if (ret) { 657 drm_err(dsi->drm, "tx cmd fifo is not empty\n"); 658 return ret; 659 } 660 661 writel(type | (vc << 6) | (wc_lsbyte << 8) | (wc_msbyte << 16), 662 ctx->base + GEN_HDR); 663 664 return 0; 665 } 666 667 /* 668 * Send READ packet to peripheral using the generic interface, 669 * this will force command mode and stop video mode (because of BTA). 670 * 671 * This function has an active delay to wait for the buffer to clear, 672 * the delay is limited to 2 x DSIH_FIFO_ACTIVE_WAIT 673 * (waiting for command buffer, and waiting for receiving) 674 * @note this function will enable BTA 675 */ 676 static int sprd_dsi_rd_pkt(struct dsi_context *ctx, u8 vc, u8 type, 677 u8 msb_byte, u8 lsb_byte, 678 u8 *buffer, u8 bytes_to_read) 679 { 680 struct sprd_dsi *dsi = container_of(ctx, struct sprd_dsi, ctx); 681 int i, ret; 682 int count = 0; 683 u32 temp; 684 685 if (vc > 3) 686 return -EINVAL; 687 688 /* 1st: send read command to peripheral */ 689 ret = dsi_reg_rd(ctx, CMD_MODE_STATUS, GEN_CMD_CMD_FIFO_EMPTY, 5); 690 if (!ret) 691 return -EIO; 692 693 writel(type | (vc << 6) | (lsb_byte << 8) | (msb_byte << 16), 694 ctx->base + GEN_HDR); 695 696 /* 2nd: wait peripheral response completed */ 697 ret = dsi_wait_rd_resp_completed(ctx); 698 if (ret) { 699 drm_err(dsi->drm, "wait read response time out\n"); 700 return ret; 701 } 702 703 /* 3rd: get data from rx payload fifo */ 704 ret = dsi_reg_rd(ctx, CMD_MODE_STATUS, GEN_CMD_RDATA_FIFO_EMPTY, 1); 705 if (ret) { 706 drm_err(dsi->drm, "rx payload fifo empty\n"); 707 return -EIO; 708 } 709 710 for (i = 0; i < 100; i++) { 711 temp = readl(ctx->base + GEN_PLD_DATA); 712 713 if (count < bytes_to_read) 714 buffer[count++] = temp & 0xff; 715 if (count < bytes_to_read) 716 buffer[count++] = (temp >> 8) & 0xff; 717 if (count < bytes_to_read) 718 buffer[count++] = (temp >> 16) & 0xff; 719 if (count < bytes_to_read) 720 buffer[count++] = (temp >> 24) & 0xff; 721 722 ret = dsi_reg_rd(ctx, CMD_MODE_STATUS, GEN_CMD_RDATA_FIFO_EMPTY, 1); 723 if (ret) 724 return count; 725 } 726 727 return 0; 728 } 729 730 static void sprd_dsi_set_work_mode(struct dsi_context *ctx, u8 mode) 731 { 732 if (mode == DSI_MODE_CMD) 733 writel(1, ctx->base + DSI_MODE_CFG); 734 else 735 writel(0, ctx->base + DSI_MODE_CFG); 736 } 737 738 static void sprd_dsi_state_reset(struct dsi_context *ctx) 739 { 740 writel(0, ctx->base + SOFT_RESET); 741 udelay(100); 742 writel(1, ctx->base + SOFT_RESET); 743 } 744 745 static int sprd_dphy_init(struct dsi_context *ctx) 746 { 747 struct sprd_dsi *dsi = container_of(ctx, struct sprd_dsi, ctx); 748 int ret; 749 750 dsi_reg_up(ctx, PHY_INTERFACE_CTRL, RF_PHY_RESET_N, 0); 751 dsi_reg_up(ctx, PHY_INTERFACE_CTRL, RF_PHY_SHUTDOWN, 0); 752 dsi_reg_up(ctx, PHY_INTERFACE_CTRL, RF_PHY_CLK_EN, 0); 753 754 dsi_reg_up(ctx, PHY_TST_CTRL0, PHY_TESTCLR, 0); 755 dsi_reg_up(ctx, PHY_TST_CTRL0, PHY_TESTCLR, PHY_TESTCLR); 756 dsi_reg_up(ctx, PHY_TST_CTRL0, PHY_TESTCLR, 0); 757 758 dphy_pll_config(ctx); 759 dphy_timing_config(ctx); 760 761 dsi_reg_up(ctx, PHY_INTERFACE_CTRL, RF_PHY_SHUTDOWN, RF_PHY_SHUTDOWN); 762 dsi_reg_up(ctx, PHY_INTERFACE_CTRL, RF_PHY_RESET_N, RF_PHY_RESET_N); 763 writel(0x1C, ctx->base + PHY_MIN_STOP_TIME); 764 dsi_reg_up(ctx, PHY_INTERFACE_CTRL, RF_PHY_CLK_EN, RF_PHY_CLK_EN); 765 writel(dsi->slave->lanes - 1, ctx->base + PHY_LANE_NUM_CONFIG); 766 767 ret = dphy_wait_pll_locked(ctx); 768 if (ret) { 769 drm_err(dsi->drm, "dphy initial failed\n"); 770 return ret; 771 } 772 773 return 0; 774 } 775 776 static void sprd_dphy_fini(struct dsi_context *ctx) 777 { 778 dsi_reg_up(ctx, PHY_INTERFACE_CTRL, RF_PHY_RESET_N, 0); 779 dsi_reg_up(ctx, PHY_INTERFACE_CTRL, RF_PHY_SHUTDOWN, 0); 780 dsi_reg_up(ctx, PHY_INTERFACE_CTRL, RF_PHY_RESET_N, RF_PHY_RESET_N); 781 } 782 783 static void sprd_dsi_encoder_mode_set(struct drm_encoder *encoder, 784 struct drm_display_mode *mode, 785 struct drm_display_mode *adj_mode) 786 { 787 struct sprd_dsi *dsi = encoder_to_dsi(encoder); 788 789 drm_display_mode_to_videomode(adj_mode, &dsi->ctx.vm); 790 } 791 792 static void sprd_dsi_encoder_enable(struct drm_encoder *encoder) 793 { 794 struct sprd_dsi *dsi = encoder_to_dsi(encoder); 795 struct sprd_dpu *dpu = to_sprd_crtc(encoder->crtc); 796 struct dsi_context *ctx = &dsi->ctx; 797 798 if (ctx->enabled) { 799 drm_warn(dsi->drm, "dsi is initialized\n"); 800 return; 801 } 802 803 sprd_dsi_init(ctx); 804 if (ctx->work_mode == DSI_MODE_VIDEO) 805 sprd_dsi_dpi_video(ctx); 806 else 807 sprd_dsi_edpi_video(ctx); 808 809 sprd_dphy_init(ctx); 810 811 sprd_dsi_set_work_mode(ctx, ctx->work_mode); 812 sprd_dsi_state_reset(ctx); 813 814 if (dsi->slave->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) { 815 dsi_reg_up(ctx, PHY_CLK_LANE_LP_CTRL, AUTO_CLKLANE_CTRL_EN, 816 AUTO_CLKLANE_CTRL_EN); 817 } else { 818 dsi_reg_up(ctx, PHY_CLK_LANE_LP_CTRL, RF_PHY_CLK_EN, RF_PHY_CLK_EN); 819 dsi_reg_up(ctx, PHY_CLK_LANE_LP_CTRL, PHY_CLKLANE_TX_REQ_HS, 820 PHY_CLKLANE_TX_REQ_HS); 821 dphy_wait_pll_locked(ctx); 822 } 823 824 sprd_dpu_run(dpu); 825 826 ctx->enabled = true; 827 } 828 829 static void sprd_dsi_encoder_disable(struct drm_encoder *encoder) 830 { 831 struct sprd_dsi *dsi = encoder_to_dsi(encoder); 832 struct sprd_dpu *dpu = to_sprd_crtc(encoder->crtc); 833 struct dsi_context *ctx = &dsi->ctx; 834 835 if (!ctx->enabled) { 836 drm_warn(dsi->drm, "dsi isn't initialized\n"); 837 return; 838 } 839 840 sprd_dpu_stop(dpu); 841 sprd_dphy_fini(ctx); 842 sprd_dsi_fini(ctx); 843 844 ctx->enabled = false; 845 } 846 847 static const struct drm_encoder_helper_funcs sprd_encoder_helper_funcs = { 848 .mode_set = sprd_dsi_encoder_mode_set, 849 .enable = sprd_dsi_encoder_enable, 850 .disable = sprd_dsi_encoder_disable 851 }; 852 853 static const struct drm_encoder_funcs sprd_encoder_funcs = { 854 .destroy = drm_encoder_cleanup, 855 }; 856 857 static int sprd_dsi_encoder_init(struct sprd_dsi *dsi, 858 struct device *dev) 859 { 860 struct drm_encoder *encoder = &dsi->encoder; 861 u32 crtc_mask; 862 int ret; 863 864 crtc_mask = drm_of_find_possible_crtcs(dsi->drm, dev->of_node); 865 if (!crtc_mask) { 866 drm_err(dsi->drm, "failed to find crtc mask\n"); 867 return -EINVAL; 868 } 869 870 drm_dbg(dsi->drm, "find possible crtcs: 0x%08x\n", crtc_mask); 871 872 encoder->possible_crtcs = crtc_mask; 873 ret = drm_encoder_init(dsi->drm, encoder, &sprd_encoder_funcs, 874 DRM_MODE_ENCODER_DSI, NULL); 875 if (ret) { 876 drm_err(dsi->drm, "failed to init dsi encoder\n"); 877 return ret; 878 } 879 880 drm_encoder_helper_add(encoder, &sprd_encoder_helper_funcs); 881 882 return 0; 883 } 884 885 static int sprd_dsi_bridge_init(struct sprd_dsi *dsi, 886 struct device *dev) 887 { 888 int ret; 889 890 dsi->panel_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 1, 0); 891 if (IS_ERR(dsi->panel_bridge)) 892 return PTR_ERR(dsi->panel_bridge); 893 894 ret = drm_bridge_attach(&dsi->encoder, dsi->panel_bridge, NULL, 0); 895 if (ret) 896 return ret; 897 898 return 0; 899 } 900 901 static int sprd_dsi_context_init(struct sprd_dsi *dsi, 902 struct device *dev) 903 { 904 struct platform_device *pdev = to_platform_device(dev); 905 struct dsi_context *ctx = &dsi->ctx; 906 struct resource *res; 907 908 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 909 if (!res) { 910 dev_err(dev, "failed to get I/O resource\n"); 911 return -EINVAL; 912 } 913 914 ctx->base = devm_ioremap(dev, res->start, resource_size(res)); 915 if (!ctx->base) { 916 drm_err(dsi->drm, "failed to map dsi host registers\n"); 917 return -ENXIO; 918 } 919 920 ctx->regmap = devm_regmap_init(dev, ®map_tst_io, dsi, &byte_config); 921 if (IS_ERR(ctx->regmap)) { 922 drm_err(dsi->drm, "dphy regmap init failed\n"); 923 return PTR_ERR(ctx->regmap); 924 } 925 926 ctx->data_hs2lp = 120; 927 ctx->data_lp2hs = 500; 928 ctx->clk_hs2lp = 4; 929 ctx->clk_lp2hs = 15; 930 ctx->max_rd_time = 6000; 931 ctx->int0_mask = 0xffffffff; 932 ctx->int1_mask = 0xffffffff; 933 ctx->enabled = true; 934 935 return 0; 936 } 937 938 static int sprd_dsi_bind(struct device *dev, struct device *master, void *data) 939 { 940 struct drm_device *drm = data; 941 struct sprd_dsi *dsi = dev_get_drvdata(dev); 942 int ret; 943 944 dsi->drm = drm; 945 946 ret = sprd_dsi_encoder_init(dsi, dev); 947 if (ret) 948 return ret; 949 950 ret = sprd_dsi_bridge_init(dsi, dev); 951 if (ret) 952 return ret; 953 954 ret = sprd_dsi_context_init(dsi, dev); 955 if (ret) 956 return ret; 957 958 return 0; 959 } 960 961 static void sprd_dsi_unbind(struct device *dev, 962 struct device *master, void *data) 963 { 964 struct sprd_dsi *dsi = dev_get_drvdata(dev); 965 966 drm_of_panel_bridge_remove(dev->of_node, 1, 0); 967 968 drm_encoder_cleanup(&dsi->encoder); 969 } 970 971 static const struct component_ops dsi_component_ops = { 972 .bind = sprd_dsi_bind, 973 .unbind = sprd_dsi_unbind, 974 }; 975 976 static int sprd_dsi_host_attach(struct mipi_dsi_host *host, 977 struct mipi_dsi_device *slave) 978 { 979 struct sprd_dsi *dsi = host_to_dsi(host); 980 struct dsi_context *ctx = &dsi->ctx; 981 982 dsi->slave = slave; 983 984 if (slave->mode_flags & MIPI_DSI_MODE_VIDEO) 985 ctx->work_mode = DSI_MODE_VIDEO; 986 else 987 ctx->work_mode = DSI_MODE_CMD; 988 989 if (slave->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 990 ctx->burst_mode = VIDEO_BURST_WITH_SYNC_PULSES; 991 else if (slave->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 992 ctx->burst_mode = VIDEO_NON_BURST_WITH_SYNC_PULSES; 993 else 994 ctx->burst_mode = VIDEO_NON_BURST_WITH_SYNC_EVENTS; 995 996 return component_add(host->dev, &dsi_component_ops); 997 } 998 999 static int sprd_dsi_host_detach(struct mipi_dsi_host *host, 1000 struct mipi_dsi_device *slave) 1001 { 1002 component_del(host->dev, &dsi_component_ops); 1003 1004 return 0; 1005 } 1006 1007 static ssize_t sprd_dsi_host_transfer(struct mipi_dsi_host *host, 1008 const struct mipi_dsi_msg *msg) 1009 { 1010 struct sprd_dsi *dsi = host_to_dsi(host); 1011 const u8 *tx_buf = msg->tx_buf; 1012 1013 if (msg->rx_buf && msg->rx_len) { 1014 u8 lsb = (msg->tx_len > 0) ? tx_buf[0] : 0; 1015 u8 msb = (msg->tx_len > 1) ? tx_buf[1] : 0; 1016 1017 return sprd_dsi_rd_pkt(&dsi->ctx, msg->channel, msg->type, 1018 msb, lsb, msg->rx_buf, msg->rx_len); 1019 } 1020 1021 if (msg->tx_buf && msg->tx_len) 1022 return sprd_dsi_wr_pkt(&dsi->ctx, msg->channel, msg->type, 1023 tx_buf, msg->tx_len); 1024 1025 return 0; 1026 } 1027 1028 static const struct mipi_dsi_host_ops sprd_dsi_host_ops = { 1029 .attach = sprd_dsi_host_attach, 1030 .detach = sprd_dsi_host_detach, 1031 .transfer = sprd_dsi_host_transfer, 1032 }; 1033 1034 static const struct of_device_id dsi_match_table[] = { 1035 { .compatible = "sprd,sharkl3-dsi-host" }, 1036 { /* sentinel */ }, 1037 }; 1038 1039 static int sprd_dsi_probe(struct platform_device *pdev) 1040 { 1041 struct device *dev = &pdev->dev; 1042 struct sprd_dsi *dsi; 1043 1044 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); 1045 if (!dsi) 1046 return -ENOMEM; 1047 1048 dev_set_drvdata(dev, dsi); 1049 1050 dsi->host.ops = &sprd_dsi_host_ops; 1051 dsi->host.dev = dev; 1052 1053 return mipi_dsi_host_register(&dsi->host); 1054 } 1055 1056 static int sprd_dsi_remove(struct platform_device *pdev) 1057 { 1058 struct sprd_dsi *dsi = dev_get_drvdata(&pdev->dev); 1059 1060 mipi_dsi_host_unregister(&dsi->host); 1061 1062 return 0; 1063 } 1064 1065 struct platform_driver sprd_dsi_driver = { 1066 .probe = sprd_dsi_probe, 1067 .remove = sprd_dsi_remove, 1068 .driver = { 1069 .name = "sprd-dsi-drv", 1070 .of_match_table = dsi_match_table, 1071 }, 1072 }; 1073 1074 MODULE_AUTHOR("Leon He <leon.he@unisoc.com>"); 1075 MODULE_AUTHOR("Kevin Tang <kevin.tang@unisoc.com>"); 1076 MODULE_DESCRIPTION("Unisoc MIPI DSI HOST Controller Driver"); 1077 MODULE_LICENSE("GPL v2"); 1078