1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-msm8996.h> 8#include <dt-bindings/clock/qcom,mmcc-msm8996.h> 9#include <dt-bindings/clock/qcom,rpmcc.h> 10#include <dt-bindings/interconnect/qcom,msm8996.h> 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/power/qcom-rpmpd.h> 13#include <dt-bindings/soc/qcom,apr.h> 14#include <dt-bindings/thermal/thermal.h> 15 16/ { 17 interrupt-parent = <&intc>; 18 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 chosen { }; 23 24 clocks { 25 xo_board: xo-board { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 clock-frequency = <19200000>; 29 clock-output-names = "xo_board"; 30 }; 31 32 sleep_clk: sleep-clk { 33 compatible = "fixed-clock"; 34 #clock-cells = <0>; 35 clock-frequency = <32764>; 36 clock-output-names = "sleep_clk"; 37 }; 38 }; 39 40 cpus { 41 #address-cells = <2>; 42 #size-cells = <0>; 43 44 CPU0: cpu@0 { 45 device_type = "cpu"; 46 compatible = "qcom,kryo"; 47 reg = <0x0 0x0>; 48 enable-method = "psci"; 49 cpu-idle-states = <&CPU_SLEEP_0>; 50 capacity-dmips-mhz = <1024>; 51 clocks = <&kryocc 0>; 52 operating-points-v2 = <&cluster0_opp>; 53 #cooling-cells = <2>; 54 next-level-cache = <&L2_0>; 55 L2_0: l2-cache { 56 compatible = "cache"; 57 cache-level = <2>; 58 }; 59 }; 60 61 CPU1: cpu@1 { 62 device_type = "cpu"; 63 compatible = "qcom,kryo"; 64 reg = <0x0 0x1>; 65 enable-method = "psci"; 66 cpu-idle-states = <&CPU_SLEEP_0>; 67 capacity-dmips-mhz = <1024>; 68 clocks = <&kryocc 0>; 69 operating-points-v2 = <&cluster0_opp>; 70 #cooling-cells = <2>; 71 next-level-cache = <&L2_0>; 72 }; 73 74 CPU2: cpu@100 { 75 device_type = "cpu"; 76 compatible = "qcom,kryo"; 77 reg = <0x0 0x100>; 78 enable-method = "psci"; 79 cpu-idle-states = <&CPU_SLEEP_0>; 80 capacity-dmips-mhz = <1024>; 81 clocks = <&kryocc 1>; 82 operating-points-v2 = <&cluster1_opp>; 83 #cooling-cells = <2>; 84 next-level-cache = <&L2_1>; 85 L2_1: l2-cache { 86 compatible = "cache"; 87 cache-level = <2>; 88 }; 89 }; 90 91 CPU3: cpu@101 { 92 device_type = "cpu"; 93 compatible = "qcom,kryo"; 94 reg = <0x0 0x101>; 95 enable-method = "psci"; 96 cpu-idle-states = <&CPU_SLEEP_0>; 97 capacity-dmips-mhz = <1024>; 98 clocks = <&kryocc 1>; 99 operating-points-v2 = <&cluster1_opp>; 100 #cooling-cells = <2>; 101 next-level-cache = <&L2_1>; 102 }; 103 104 cpu-map { 105 cluster0 { 106 core0 { 107 cpu = <&CPU0>; 108 }; 109 110 core1 { 111 cpu = <&CPU1>; 112 }; 113 }; 114 115 cluster1 { 116 core0 { 117 cpu = <&CPU2>; 118 }; 119 120 core1 { 121 cpu = <&CPU3>; 122 }; 123 }; 124 }; 125 126 idle-states { 127 entry-method = "psci"; 128 129 CPU_SLEEP_0: cpu-sleep-0 { 130 compatible = "arm,idle-state"; 131 idle-state-name = "standalone-power-collapse"; 132 arm,psci-suspend-param = <0x00000004>; 133 entry-latency-us = <130>; 134 exit-latency-us = <80>; 135 min-residency-us = <300>; 136 }; 137 }; 138 }; 139 140 cluster0_opp: opp-table-cluster0 { 141 compatible = "operating-points-v2-kryo-cpu"; 142 nvmem-cells = <&speedbin_efuse>; 143 opp-shared; 144 145 /* Nominal fmax for now */ 146 opp-307200000 { 147 opp-hz = /bits/ 64 <307200000>; 148 opp-supported-hw = <0xf>; 149 clock-latency-ns = <200000>; 150 }; 151 opp-422400000 { 152 opp-hz = /bits/ 64 <422400000>; 153 opp-supported-hw = <0xf>; 154 clock-latency-ns = <200000>; 155 }; 156 opp-480000000 { 157 opp-hz = /bits/ 64 <480000000>; 158 opp-supported-hw = <0xf>; 159 clock-latency-ns = <200000>; 160 }; 161 opp-556800000 { 162 opp-hz = /bits/ 64 <556800000>; 163 opp-supported-hw = <0xf>; 164 clock-latency-ns = <200000>; 165 }; 166 opp-652800000 { 167 opp-hz = /bits/ 64 <652800000>; 168 opp-supported-hw = <0xf>; 169 clock-latency-ns = <200000>; 170 }; 171 opp-729600000 { 172 opp-hz = /bits/ 64 <729600000>; 173 opp-supported-hw = <0xf>; 174 clock-latency-ns = <200000>; 175 }; 176 opp-844800000 { 177 opp-hz = /bits/ 64 <844800000>; 178 opp-supported-hw = <0xf>; 179 clock-latency-ns = <200000>; 180 }; 181 opp-960000000 { 182 opp-hz = /bits/ 64 <960000000>; 183 opp-supported-hw = <0xf>; 184 clock-latency-ns = <200000>; 185 }; 186 opp-1036800000 { 187 opp-hz = /bits/ 64 <1036800000>; 188 opp-supported-hw = <0xf>; 189 clock-latency-ns = <200000>; 190 }; 191 opp-1113600000 { 192 opp-hz = /bits/ 64 <1113600000>; 193 opp-supported-hw = <0xf>; 194 clock-latency-ns = <200000>; 195 }; 196 opp-1190400000 { 197 opp-hz = /bits/ 64 <1190400000>; 198 opp-supported-hw = <0xf>; 199 clock-latency-ns = <200000>; 200 }; 201 opp-1228800000 { 202 opp-hz = /bits/ 64 <1228800000>; 203 opp-supported-hw = <0xf>; 204 clock-latency-ns = <200000>; 205 }; 206 opp-1324800000 { 207 opp-hz = /bits/ 64 <1324800000>; 208 opp-supported-hw = <0xd>; 209 clock-latency-ns = <200000>; 210 }; 211 opp-1363200000 { 212 opp-hz = /bits/ 64 <1363200000>; 213 opp-supported-hw = <0x2>; 214 clock-latency-ns = <200000>; 215 }; 216 opp-1401600000 { 217 opp-hz = /bits/ 64 <1401600000>; 218 opp-supported-hw = <0xd>; 219 clock-latency-ns = <200000>; 220 }; 221 opp-1478400000 { 222 opp-hz = /bits/ 64 <1478400000>; 223 opp-supported-hw = <0x9>; 224 clock-latency-ns = <200000>; 225 }; 226 opp-1497600000 { 227 opp-hz = /bits/ 64 <1497600000>; 228 opp-supported-hw = <0x04>; 229 clock-latency-ns = <200000>; 230 }; 231 opp-1593600000 { 232 opp-hz = /bits/ 64 <1593600000>; 233 opp-supported-hw = <0x9>; 234 clock-latency-ns = <200000>; 235 }; 236 }; 237 238 cluster1_opp: opp-table-cluster1 { 239 compatible = "operating-points-v2-kryo-cpu"; 240 nvmem-cells = <&speedbin_efuse>; 241 opp-shared; 242 243 /* Nominal fmax for now */ 244 opp-307200000 { 245 opp-hz = /bits/ 64 <307200000>; 246 opp-supported-hw = <0xf>; 247 clock-latency-ns = <200000>; 248 }; 249 opp-403200000 { 250 opp-hz = /bits/ 64 <403200000>; 251 opp-supported-hw = <0xf>; 252 clock-latency-ns = <200000>; 253 }; 254 opp-480000000 { 255 opp-hz = /bits/ 64 <480000000>; 256 opp-supported-hw = <0xf>; 257 clock-latency-ns = <200000>; 258 }; 259 opp-556800000 { 260 opp-hz = /bits/ 64 <556800000>; 261 opp-supported-hw = <0xf>; 262 clock-latency-ns = <200000>; 263 }; 264 opp-652800000 { 265 opp-hz = /bits/ 64 <652800000>; 266 opp-supported-hw = <0xf>; 267 clock-latency-ns = <200000>; 268 }; 269 opp-729600000 { 270 opp-hz = /bits/ 64 <729600000>; 271 opp-supported-hw = <0xf>; 272 clock-latency-ns = <200000>; 273 }; 274 opp-806400000 { 275 opp-hz = /bits/ 64 <806400000>; 276 opp-supported-hw = <0xf>; 277 clock-latency-ns = <200000>; 278 }; 279 opp-883200000 { 280 opp-hz = /bits/ 64 <883200000>; 281 opp-supported-hw = <0xf>; 282 clock-latency-ns = <200000>; 283 }; 284 opp-940800000 { 285 opp-hz = /bits/ 64 <940800000>; 286 opp-supported-hw = <0xf>; 287 clock-latency-ns = <200000>; 288 }; 289 opp-1036800000 { 290 opp-hz = /bits/ 64 <1036800000>; 291 opp-supported-hw = <0xf>; 292 clock-latency-ns = <200000>; 293 }; 294 opp-1113600000 { 295 opp-hz = /bits/ 64 <1113600000>; 296 opp-supported-hw = <0xf>; 297 clock-latency-ns = <200000>; 298 }; 299 opp-1190400000 { 300 opp-hz = /bits/ 64 <1190400000>; 301 opp-supported-hw = <0xf>; 302 clock-latency-ns = <200000>; 303 }; 304 opp-1248000000 { 305 opp-hz = /bits/ 64 <1248000000>; 306 opp-supported-hw = <0xf>; 307 clock-latency-ns = <200000>; 308 }; 309 opp-1324800000 { 310 opp-hz = /bits/ 64 <1324800000>; 311 opp-supported-hw = <0xf>; 312 clock-latency-ns = <200000>; 313 }; 314 opp-1401600000 { 315 opp-hz = /bits/ 64 <1401600000>; 316 opp-supported-hw = <0xf>; 317 clock-latency-ns = <200000>; 318 }; 319 opp-1478400000 { 320 opp-hz = /bits/ 64 <1478400000>; 321 opp-supported-hw = <0xf>; 322 clock-latency-ns = <200000>; 323 }; 324 opp-1555200000 { 325 opp-hz = /bits/ 64 <1555200000>; 326 opp-supported-hw = <0xf>; 327 clock-latency-ns = <200000>; 328 }; 329 opp-1632000000 { 330 opp-hz = /bits/ 64 <1632000000>; 331 opp-supported-hw = <0xf>; 332 clock-latency-ns = <200000>; 333 }; 334 opp-1708800000 { 335 opp-hz = /bits/ 64 <1708800000>; 336 opp-supported-hw = <0xf>; 337 clock-latency-ns = <200000>; 338 }; 339 opp-1785600000 { 340 opp-hz = /bits/ 64 <1785600000>; 341 opp-supported-hw = <0xf>; 342 clock-latency-ns = <200000>; 343 }; 344 opp-1804800000 { 345 opp-hz = /bits/ 64 <1804800000>; 346 opp-supported-hw = <0xe>; 347 clock-latency-ns = <200000>; 348 }; 349 opp-1824000000 { 350 opp-hz = /bits/ 64 <1824000000>; 351 opp-supported-hw = <0x1>; 352 clock-latency-ns = <200000>; 353 }; 354 opp-1900800000 { 355 opp-hz = /bits/ 64 <1900800000>; 356 opp-supported-hw = <0x4>; 357 clock-latency-ns = <200000>; 358 }; 359 opp-1920000000 { 360 opp-hz = /bits/ 64 <1920000000>; 361 opp-supported-hw = <0x1>; 362 clock-latency-ns = <200000>; 363 }; 364 opp-1996800000 { 365 opp-hz = /bits/ 64 <1996800000>; 366 opp-supported-hw = <0x1>; 367 clock-latency-ns = <200000>; 368 }; 369 opp-2073600000 { 370 opp-hz = /bits/ 64 <2073600000>; 371 opp-supported-hw = <0x1>; 372 clock-latency-ns = <200000>; 373 }; 374 opp-2150400000 { 375 opp-hz = /bits/ 64 <2150400000>; 376 opp-supported-hw = <0x1>; 377 clock-latency-ns = <200000>; 378 }; 379 }; 380 381 firmware { 382 scm { 383 compatible = "qcom,scm-msm8996", "qcom,scm"; 384 qcom,dload-mode = <&tcsr_2 0x13000>; 385 }; 386 }; 387 388 memory@80000000 { 389 device_type = "memory"; 390 /* We expect the bootloader to fill in the reg */ 391 reg = <0x0 0x80000000 0x0 0x0>; 392 }; 393 394 psci { 395 compatible = "arm,psci-1.0"; 396 method = "smc"; 397 }; 398 399 reserved-memory { 400 #address-cells = <2>; 401 #size-cells = <2>; 402 ranges; 403 404 hyp_mem: memory@85800000 { 405 reg = <0x0 0x85800000 0x0 0x600000>; 406 no-map; 407 }; 408 409 xbl_mem: memory@85e00000 { 410 reg = <0x0 0x85e00000 0x0 0x200000>; 411 no-map; 412 }; 413 414 smem_mem: smem-mem@86000000 { 415 reg = <0x0 0x86000000 0x0 0x200000>; 416 no-map; 417 }; 418 419 tz_mem: memory@86200000 { 420 reg = <0x0 0x86200000 0x0 0x2600000>; 421 no-map; 422 }; 423 424 rmtfs_mem: rmtfs { 425 compatible = "qcom,rmtfs-mem"; 426 427 size = <0x0 0x200000>; 428 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>; 429 no-map; 430 431 qcom,client-id = <1>; 432 qcom,vmid = <15>; 433 }; 434 435 mpss_mem: mpss@88800000 { 436 reg = <0x0 0x88800000 0x0 0x6200000>; 437 no-map; 438 }; 439 440 adsp_mem: adsp@8ea00000 { 441 reg = <0x0 0x8ea00000 0x0 0x1b00000>; 442 no-map; 443 }; 444 445 slpi_mem: slpi@90500000 { 446 reg = <0x0 0x90500000 0x0 0xa00000>; 447 no-map; 448 }; 449 450 gpu_mem: gpu@90f00000 { 451 compatible = "shared-dma-pool"; 452 reg = <0x0 0x90f00000 0x0 0x100000>; 453 no-map; 454 }; 455 456 venus_mem: venus@91000000 { 457 reg = <0x0 0x91000000 0x0 0x500000>; 458 no-map; 459 }; 460 461 mba_mem: mba@91500000 { 462 reg = <0x0 0x91500000 0x0 0x200000>; 463 no-map; 464 }; 465 }; 466 467 rpm-glink { 468 compatible = "qcom,glink-rpm"; 469 470 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 471 472 qcom,rpm-msg-ram = <&rpm_msg_ram>; 473 474 mboxes = <&apcs_glb 0>; 475 476 rpm_requests: rpm-requests { 477 compatible = "qcom,rpm-msm8996"; 478 qcom,glink-channels = "rpm_requests"; 479 480 rpmcc: qcom,rpmcc { 481 compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc"; 482 #clock-cells = <1>; 483 clocks = <&xo_board>; 484 clock-names = "xo"; 485 }; 486 487 rpmpd: power-controller { 488 compatible = "qcom,msm8996-rpmpd"; 489 #power-domain-cells = <1>; 490 operating-points-v2 = <&rpmpd_opp_table>; 491 492 rpmpd_opp_table: opp-table { 493 compatible = "operating-points-v2"; 494 495 rpmpd_opp1: opp1 { 496 opp-level = <1>; 497 }; 498 499 rpmpd_opp2: opp2 { 500 opp-level = <2>; 501 }; 502 503 rpmpd_opp3: opp3 { 504 opp-level = <3>; 505 }; 506 507 rpmpd_opp4: opp4 { 508 opp-level = <4>; 509 }; 510 511 rpmpd_opp5: opp5 { 512 opp-level = <5>; 513 }; 514 515 rpmpd_opp6: opp6 { 516 opp-level = <6>; 517 }; 518 }; 519 }; 520 }; 521 }; 522 523 smem { 524 compatible = "qcom,smem"; 525 memory-region = <&smem_mem>; 526 hwlocks = <&tcsr_mutex 3>; 527 }; 528 529 smp2p-adsp { 530 compatible = "qcom,smp2p"; 531 qcom,smem = <443>, <429>; 532 533 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>; 534 535 mboxes = <&apcs_glb 10>; 536 537 qcom,local-pid = <0>; 538 qcom,remote-pid = <2>; 539 540 adsp_smp2p_out: master-kernel { 541 qcom,entry-name = "master-kernel"; 542 #qcom,smem-state-cells = <1>; 543 }; 544 545 adsp_smp2p_in: slave-kernel { 546 qcom,entry-name = "slave-kernel"; 547 548 interrupt-controller; 549 #interrupt-cells = <2>; 550 }; 551 }; 552 553 smp2p-mpss { 554 compatible = "qcom,smp2p"; 555 qcom,smem = <435>, <428>; 556 557 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 558 559 mboxes = <&apcs_glb 14>; 560 561 qcom,local-pid = <0>; 562 qcom,remote-pid = <1>; 563 564 mpss_smp2p_out: master-kernel { 565 qcom,entry-name = "master-kernel"; 566 #qcom,smem-state-cells = <1>; 567 }; 568 569 mpss_smp2p_in: slave-kernel { 570 qcom,entry-name = "slave-kernel"; 571 572 interrupt-controller; 573 #interrupt-cells = <2>; 574 }; 575 }; 576 577 smp2p-slpi { 578 compatible = "qcom,smp2p"; 579 qcom,smem = <481>, <430>; 580 581 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>; 582 583 mboxes = <&apcs_glb 26>; 584 585 qcom,local-pid = <0>; 586 qcom,remote-pid = <3>; 587 588 slpi_smp2p_out: master-kernel { 589 qcom,entry-name = "master-kernel"; 590 #qcom,smem-state-cells = <1>; 591 }; 592 593 slpi_smp2p_in: slave-kernel { 594 qcom,entry-name = "slave-kernel"; 595 596 interrupt-controller; 597 #interrupt-cells = <2>; 598 }; 599 }; 600 601 soc: soc { 602 #address-cells = <1>; 603 #size-cells = <1>; 604 ranges = <0 0 0 0xffffffff>; 605 compatible = "simple-bus"; 606 607 pcie_phy: phy-wrapper@34000 { 608 compatible = "qcom,msm8996-qmp-pcie-phy"; 609 reg = <0x00034000 0x488>; 610 #address-cells = <1>; 611 #size-cells = <1>; 612 ranges = <0x0 0x00034000 0x4000>; 613 614 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 615 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>, 616 <&gcc GCC_PCIE_CLKREF_CLK>; 617 clock-names = "aux", "cfg_ahb", "ref"; 618 619 resets = <&gcc GCC_PCIE_PHY_BCR>, 620 <&gcc GCC_PCIE_PHY_COM_BCR>, 621 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>; 622 reset-names = "phy", "common", "cfg"; 623 624 status = "disabled"; 625 626 pciephy_0: phy@1000 { 627 reg = <0x1000 0x130>, 628 <0x1200 0x200>, 629 <0x1400 0x1dc>; 630 631 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 632 clock-names = "pipe0"; 633 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 634 reset-names = "lane0"; 635 636 #clock-cells = <0>; 637 clock-output-names = "pcie_0_pipe_clk_src"; 638 639 #phy-cells = <0>; 640 }; 641 642 pciephy_1: phy@2000 { 643 reg = <0x2000 0x130>, 644 <0x2200 0x200>, 645 <0x2400 0x1dc>; 646 647 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 648 clock-names = "pipe1"; 649 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 650 reset-names = "lane1"; 651 652 #clock-cells = <0>; 653 clock-output-names = "pcie_1_pipe_clk_src"; 654 655 #phy-cells = <0>; 656 }; 657 658 pciephy_2: phy@3000 { 659 reg = <0x3000 0x130>, 660 <0x3200 0x200>, 661 <0x3400 0x1dc>; 662 663 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; 664 clock-names = "pipe2"; 665 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 666 reset-names = "lane2"; 667 668 #clock-cells = <0>; 669 clock-output-names = "pcie_2_pipe_clk_src"; 670 671 #phy-cells = <0>; 672 }; 673 }; 674 675 rpm_msg_ram: sram@68000 { 676 compatible = "qcom,rpm-msg-ram"; 677 reg = <0x00068000 0x6000>; 678 }; 679 680 qfprom@74000 { 681 compatible = "qcom,msm8996-qfprom", "qcom,qfprom"; 682 reg = <0x00074000 0x8ff>; 683 #address-cells = <1>; 684 #size-cells = <1>; 685 686 qusb2p_hstx_trim: hstx_trim@24e { 687 reg = <0x24e 0x2>; 688 bits = <5 4>; 689 }; 690 691 qusb2s_hstx_trim: hstx_trim@24f { 692 reg = <0x24f 0x1>; 693 bits = <1 4>; 694 }; 695 696 speedbin_efuse: speedbin@133 { 697 reg = <0x133 0x1>; 698 bits = <5 3>; 699 }; 700 }; 701 702 rng: rng@83000 { 703 compatible = "qcom,prng-ee"; 704 reg = <0x00083000 0x1000>; 705 clocks = <&gcc GCC_PRNG_AHB_CLK>; 706 clock-names = "core"; 707 }; 708 709 gcc: clock-controller@300000 { 710 compatible = "qcom,gcc-msm8996"; 711 #clock-cells = <1>; 712 #reset-cells = <1>; 713 #power-domain-cells = <1>; 714 reg = <0x00300000 0x90000>; 715 716 clocks = <&rpmcc RPM_SMD_BB_CLK1>, 717 <&rpmcc RPM_SMD_LN_BB_CLK>, 718 <&sleep_clk>, 719 <&pciephy_0>, 720 <&pciephy_1>, 721 <&pciephy_2>, 722 <&ssusb_phy_0>, 723 <0>, <0>, <0>; 724 clock-names = "cxo", 725 "cxo2", 726 "sleep_clk", 727 "pcie_0_pipe_clk_src", 728 "pcie_1_pipe_clk_src", 729 "pcie_2_pipe_clk_src", 730 "usb3_phy_pipe_clk_src", 731 "ufs_rx_symbol_0_clk_src", 732 "ufs_rx_symbol_1_clk_src", 733 "ufs_tx_symbol_0_clk_src"; 734 }; 735 736 bimc: interconnect@408000 { 737 compatible = "qcom,msm8996-bimc"; 738 reg = <0x00408000 0x5a000>; 739 #interconnect-cells = <1>; 740 clock-names = "bus", "bus_a"; 741 clocks = <&rpmcc RPM_SMD_BIMC_CLK>, 742 <&rpmcc RPM_SMD_BIMC_A_CLK>; 743 }; 744 745 tsens0: thermal-sensor@4a9000 { 746 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2"; 747 reg = <0x004a9000 0x1000>, /* TM */ 748 <0x004a8000 0x1000>; /* SROT */ 749 #qcom,sensors = <13>; 750 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 751 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; 752 interrupt-names = "uplow", "critical"; 753 #thermal-sensor-cells = <1>; 754 }; 755 756 tsens1: thermal-sensor@4ad000 { 757 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2"; 758 reg = <0x004ad000 0x1000>, /* TM */ 759 <0x004ac000 0x1000>; /* SROT */ 760 #qcom,sensors = <8>; 761 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 762 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; 763 interrupt-names = "uplow", "critical"; 764 #thermal-sensor-cells = <1>; 765 }; 766 767 cryptobam: dma-controller@644000 { 768 compatible = "qcom,bam-v1.7.0"; 769 reg = <0x00644000 0x24000>; 770 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 771 clocks = <&gcc GCC_CE1_CLK>; 772 clock-names = "bam_clk"; 773 #dma-cells = <1>; 774 qcom,ee = <0>; 775 qcom,controlled-remotely; 776 }; 777 778 crypto: crypto@67a000 { 779 compatible = "qcom,crypto-v5.4"; 780 reg = <0x0067a000 0x6000>; 781 clocks = <&gcc GCC_CE1_AHB_CLK>, 782 <&gcc GCC_CE1_AXI_CLK>, 783 <&gcc GCC_CE1_CLK>; 784 clock-names = "iface", "bus", "core"; 785 dmas = <&cryptobam 6>, <&cryptobam 7>; 786 dma-names = "rx", "tx"; 787 }; 788 789 cnoc: interconnect@500000 { 790 compatible = "qcom,msm8996-cnoc"; 791 reg = <0x00500000 0x1000>; 792 #interconnect-cells = <1>; 793 clock-names = "bus", "bus_a"; 794 clocks = <&rpmcc RPM_SMD_CNOC_CLK>, 795 <&rpmcc RPM_SMD_CNOC_A_CLK>; 796 }; 797 798 snoc: interconnect@524000 { 799 compatible = "qcom,msm8996-snoc"; 800 reg = <0x00524000 0x1c000>; 801 #interconnect-cells = <1>; 802 clock-names = "bus", "bus_a"; 803 clocks = <&rpmcc RPM_SMD_SNOC_CLK>, 804 <&rpmcc RPM_SMD_SNOC_A_CLK>; 805 }; 806 807 a0noc: interconnect@543000 { 808 compatible = "qcom,msm8996-a0noc"; 809 reg = <0x00543000 0x6000>; 810 #interconnect-cells = <1>; 811 clock-names = "aggre0_snoc_axi", 812 "aggre0_cnoc_ahb", 813 "aggre0_noc_mpu_cfg"; 814 clocks = <&gcc GCC_AGGRE0_SNOC_AXI_CLK>, 815 <&gcc GCC_AGGRE0_CNOC_AHB_CLK>, 816 <&gcc GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK>; 817 power-domains = <&gcc AGGRE0_NOC_GDSC>; 818 }; 819 820 a1noc: interconnect@562000 { 821 compatible = "qcom,msm8996-a1noc"; 822 reg = <0x00562000 0x5000>; 823 #interconnect-cells = <1>; 824 clock-names = "bus", "bus_a"; 825 clocks = <&rpmcc RPM_SMD_AGGR1_NOC_CLK>, 826 <&rpmcc RPM_SMD_AGGR1_NOC_A_CLK>; 827 }; 828 829 a2noc: interconnect@583000 { 830 compatible = "qcom,msm8996-a2noc"; 831 reg = <0x00583000 0x7000>; 832 #interconnect-cells = <1>; 833 clock-names = "bus", "bus_a"; 834 clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>, 835 <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>; 836 }; 837 838 mnoc: interconnect@5a4000 { 839 compatible = "qcom,msm8996-mnoc"; 840 reg = <0x005a4000 0x1c000>; 841 #interconnect-cells = <1>; 842 clock-names = "bus", "bus_a", "iface"; 843 clocks = <&rpmcc RPM_SMD_MMAXI_CLK>, 844 <&rpmcc RPM_SMD_MMAXI_A_CLK>, 845 <&mmcc AHB_CLK_SRC>; 846 }; 847 848 pnoc: interconnect@5c0000 { 849 compatible = "qcom,msm8996-pnoc"; 850 reg = <0x005c0000 0x3000>; 851 #interconnect-cells = <1>; 852 clock-names = "bus", "bus_a"; 853 clocks = <&rpmcc RPM_SMD_PCNOC_CLK>, 854 <&rpmcc RPM_SMD_PCNOC_A_CLK>; 855 }; 856 857 tcsr_mutex: hwlock@740000 { 858 compatible = "qcom,tcsr-mutex"; 859 reg = <0x00740000 0x20000>; 860 #hwlock-cells = <1>; 861 }; 862 863 tcsr_1: syscon@760000 { 864 compatible = "qcom,tcsr-msm8996", "syscon"; 865 reg = <0x00760000 0x20000>; 866 }; 867 868 tcsr_2: syscon@7a0000 { 869 compatible = "qcom,tcsr-msm8996", "syscon"; 870 reg = <0x007a0000 0x18000>; 871 }; 872 873 mmcc: clock-controller@8c0000 { 874 compatible = "qcom,mmcc-msm8996"; 875 #clock-cells = <1>; 876 #reset-cells = <1>; 877 #power-domain-cells = <1>; 878 reg = <0x008c0000 0x40000>; 879 clocks = <&xo_board>, 880 <&gcc GCC_MMSS_NOC_CFG_AHB_CLK>, 881 <&gcc GPLL0>, 882 <&dsi0_phy 1>, 883 <&dsi0_phy 0>, 884 <&dsi1_phy 1>, 885 <&dsi1_phy 0>, 886 <&hdmi_phy>; 887 clock-names = "xo", 888 "gcc_mmss_noc_cfg_ahb_clk", 889 "gpll0", 890 "dsi0pll", 891 "dsi0pllbyte", 892 "dsi1pll", 893 "dsi1pllbyte", 894 "hdmipll"; 895 assigned-clocks = <&mmcc MMPLL9_PLL>, 896 <&mmcc MMPLL1_PLL>, 897 <&mmcc MMPLL3_PLL>, 898 <&mmcc MMPLL4_PLL>, 899 <&mmcc MMPLL5_PLL>; 900 assigned-clock-rates = <624000000>, 901 <810000000>, 902 <980000000>, 903 <960000000>, 904 <825000000>; 905 }; 906 907 mdss: mdss@900000 { 908 compatible = "qcom,mdss"; 909 910 reg = <0x00900000 0x1000>, 911 <0x009b0000 0x1040>, 912 <0x009b8000 0x1040>; 913 reg-names = "mdss_phys", 914 "vbif_phys", 915 "vbif_nrt_phys"; 916 917 power-domains = <&mmcc MDSS_GDSC>; 918 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 919 920 interrupt-controller; 921 #interrupt-cells = <1>; 922 923 clocks = <&mmcc MDSS_AHB_CLK>, 924 <&mmcc MDSS_MDP_CLK>; 925 clock-names = "iface", "core"; 926 927 #address-cells = <1>; 928 #size-cells = <1>; 929 ranges; 930 931 status = "disabled"; 932 933 mdp: mdp@901000 { 934 compatible = "qcom,mdp5"; 935 reg = <0x00901000 0x90000>; 936 reg-names = "mdp_phys"; 937 938 interrupt-parent = <&mdss>; 939 interrupts = <0>; 940 941 clocks = <&mmcc MDSS_AHB_CLK>, 942 <&mmcc MDSS_AXI_CLK>, 943 <&mmcc MDSS_MDP_CLK>, 944 <&mmcc SMMU_MDP_AXI_CLK>, 945 <&mmcc MDSS_VSYNC_CLK>; 946 clock-names = "iface", 947 "bus", 948 "core", 949 "iommu", 950 "vsync"; 951 952 iommus = <&mdp_smmu 0>; 953 954 assigned-clocks = <&mmcc MDSS_MDP_CLK>, 955 <&mmcc MDSS_VSYNC_CLK>; 956 assigned-clock-rates = <300000000>, 957 <19200000>; 958 959 interconnects = <&mnoc MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>, 960 <&mnoc MASTER_MDP_PORT1 &bimc SLAVE_EBI_CH0>, 961 <&mnoc MASTER_ROTATOR &bimc SLAVE_EBI_CH0>; 962 interconnect-names = "mdp0-mem", "mdp1-mem", "rotator-mem"; 963 964 ports { 965 #address-cells = <1>; 966 #size-cells = <0>; 967 968 port@0 { 969 reg = <0>; 970 mdp5_intf3_out: endpoint { 971 remote-endpoint = <&hdmi_in>; 972 }; 973 }; 974 975 port@1 { 976 reg = <1>; 977 mdp5_intf1_out: endpoint { 978 remote-endpoint = <&dsi0_in>; 979 }; 980 }; 981 982 port@2 { 983 reg = <2>; 984 mdp5_intf2_out: endpoint { 985 remote-endpoint = <&dsi1_in>; 986 }; 987 }; 988 }; 989 }; 990 991 dsi0: dsi@994000 { 992 compatible = "qcom,mdss-dsi-ctrl"; 993 reg = <0x00994000 0x400>; 994 reg-names = "dsi_ctrl"; 995 996 interrupt-parent = <&mdss>; 997 interrupts = <4>; 998 999 clocks = <&mmcc MDSS_MDP_CLK>, 1000 <&mmcc MDSS_BYTE0_CLK>, 1001 <&mmcc MDSS_AHB_CLK>, 1002 <&mmcc MDSS_AXI_CLK>, 1003 <&mmcc MMSS_MISC_AHB_CLK>, 1004 <&mmcc MDSS_PCLK0_CLK>, 1005 <&mmcc MDSS_ESC0_CLK>; 1006 clock-names = "mdp_core", 1007 "byte", 1008 "iface", 1009 "bus", 1010 "core_mmss", 1011 "pixel", 1012 "core"; 1013 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>; 1014 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; 1015 1016 phys = <&dsi0_phy>; 1017 status = "disabled"; 1018 1019 #address-cells = <1>; 1020 #size-cells = <0>; 1021 1022 ports { 1023 #address-cells = <1>; 1024 #size-cells = <0>; 1025 1026 port@0 { 1027 reg = <0>; 1028 dsi0_in: endpoint { 1029 remote-endpoint = <&mdp5_intf1_out>; 1030 }; 1031 }; 1032 1033 port@1 { 1034 reg = <1>; 1035 dsi0_out: endpoint { 1036 }; 1037 }; 1038 }; 1039 }; 1040 1041 dsi0_phy: phy@994400 { 1042 compatible = "qcom,dsi-phy-14nm"; 1043 reg = <0x00994400 0x100>, 1044 <0x00994500 0x300>, 1045 <0x00994800 0x188>; 1046 reg-names = "dsi_phy", 1047 "dsi_phy_lane", 1048 "dsi_pll"; 1049 1050 #clock-cells = <1>; 1051 #phy-cells = <0>; 1052 1053 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_BB_CLK1>; 1054 clock-names = "iface", "ref"; 1055 status = "disabled"; 1056 }; 1057 1058 dsi1: dsi@996000 { 1059 compatible = "qcom,mdss-dsi-ctrl"; 1060 reg = <0x00996000 0x400>; 1061 reg-names = "dsi_ctrl"; 1062 1063 interrupt-parent = <&mdss>; 1064 interrupts = <4>; 1065 1066 clocks = <&mmcc MDSS_MDP_CLK>, 1067 <&mmcc MDSS_BYTE1_CLK>, 1068 <&mmcc MDSS_AHB_CLK>, 1069 <&mmcc MDSS_AXI_CLK>, 1070 <&mmcc MMSS_MISC_AHB_CLK>, 1071 <&mmcc MDSS_PCLK1_CLK>, 1072 <&mmcc MDSS_ESC1_CLK>; 1073 clock-names = "mdp_core", 1074 "byte", 1075 "iface", 1076 "bus", 1077 "core_mmss", 1078 "pixel", 1079 "core"; 1080 assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>; 1081 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; 1082 1083 phys = <&dsi1_phy>; 1084 status = "disabled"; 1085 1086 #address-cells = <1>; 1087 #size-cells = <0>; 1088 1089 ports { 1090 #address-cells = <1>; 1091 #size-cells = <0>; 1092 1093 port@0 { 1094 reg = <0>; 1095 dsi1_in: endpoint { 1096 remote-endpoint = <&mdp5_intf2_out>; 1097 }; 1098 }; 1099 1100 port@1 { 1101 reg = <1>; 1102 dsi1_out: endpoint { 1103 }; 1104 }; 1105 }; 1106 }; 1107 1108 dsi1_phy: phy@996400 { 1109 compatible = "qcom,dsi-phy-14nm"; 1110 reg = <0x00996400 0x100>, 1111 <0x00996500 0x300>, 1112 <0x00996800 0x188>; 1113 reg-names = "dsi_phy", 1114 "dsi_phy_lane", 1115 "dsi_pll"; 1116 1117 #clock-cells = <1>; 1118 #phy-cells = <0>; 1119 1120 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_BB_CLK1>; 1121 clock-names = "iface", "ref"; 1122 status = "disabled"; 1123 }; 1124 1125 hdmi: hdmi-tx@9a0000 { 1126 compatible = "qcom,hdmi-tx-8996"; 1127 reg = <0x009a0000 0x50c>, 1128 <0x00070000 0x6158>, 1129 <0x009e0000 0xfff>; 1130 reg-names = "core_physical", 1131 "qfprom_physical", 1132 "hdcp_physical"; 1133 1134 interrupt-parent = <&mdss>; 1135 interrupts = <8>; 1136 1137 clocks = <&mmcc MDSS_MDP_CLK>, 1138 <&mmcc MDSS_AHB_CLK>, 1139 <&mmcc MDSS_HDMI_CLK>, 1140 <&mmcc MDSS_HDMI_AHB_CLK>, 1141 <&mmcc MDSS_EXTPCLK_CLK>; 1142 clock-names = 1143 "mdp_core", 1144 "iface", 1145 "core", 1146 "alt_iface", 1147 "extp"; 1148 1149 phys = <&hdmi_phy>; 1150 #sound-dai-cells = <1>; 1151 1152 status = "disabled"; 1153 1154 ports { 1155 #address-cells = <1>; 1156 #size-cells = <0>; 1157 1158 port@0 { 1159 reg = <0>; 1160 hdmi_in: endpoint { 1161 remote-endpoint = <&mdp5_intf3_out>; 1162 }; 1163 }; 1164 }; 1165 }; 1166 1167 hdmi_phy: phy@9a0600 { 1168 #phy-cells = <0>; 1169 compatible = "qcom,hdmi-phy-8996"; 1170 reg = <0x009a0600 0x1c4>, 1171 <0x009a0a00 0x124>, 1172 <0x009a0c00 0x124>, 1173 <0x009a0e00 0x124>, 1174 <0x009a1000 0x124>, 1175 <0x009a1200 0x0c8>; 1176 reg-names = "hdmi_pll", 1177 "hdmi_tx_l0", 1178 "hdmi_tx_l1", 1179 "hdmi_tx_l2", 1180 "hdmi_tx_l3", 1181 "hdmi_phy"; 1182 1183 clocks = <&mmcc MDSS_AHB_CLK>, 1184 <&gcc GCC_HDMI_CLKREF_CLK>, 1185 <&xo_board>; 1186 clock-names = "iface", 1187 "ref", 1188 "xo"; 1189 1190 #clock-cells = <0>; 1191 1192 status = "disabled"; 1193 }; 1194 }; 1195 1196 gpu: gpu@b00000 { 1197 compatible = "qcom,adreno-530.2", "qcom,adreno"; 1198 1199 reg = <0x00b00000 0x3f000>; 1200 reg-names = "kgsl_3d0_reg_memory"; 1201 1202 interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; 1203 1204 clocks = <&mmcc GPU_GX_GFX3D_CLK>, 1205 <&mmcc GPU_AHB_CLK>, 1206 <&mmcc GPU_GX_RBBMTIMER_CLK>, 1207 <&gcc GCC_BIMC_GFX_CLK>, 1208 <&gcc GCC_MMSS_BIMC_GFX_CLK>; 1209 1210 clock-names = "core", 1211 "iface", 1212 "rbbmtimer", 1213 "mem", 1214 "mem_iface"; 1215 1216 interconnects = <&bimc MASTER_GRAPHICS_3D &bimc SLAVE_EBI_CH0>; 1217 interconnect-names = "gfx-mem"; 1218 1219 power-domains = <&mmcc GPU_GX_GDSC>; 1220 iommus = <&adreno_smmu 0>; 1221 1222 nvmem-cells = <&speedbin_efuse>; 1223 nvmem-cell-names = "speed_bin"; 1224 1225 operating-points-v2 = <&gpu_opp_table>; 1226 1227 status = "disabled"; 1228 1229 #cooling-cells = <2>; 1230 1231 gpu_opp_table: opp-table { 1232 compatible = "operating-points-v2"; 1233 1234 /* 1235 * 624Mhz is only available on speed bins 0 and 3. 1236 * 560Mhz is only available on speed bins 0, 2 and 3. 1237 * All the rest are available on all bins of the hardware. 1238 */ 1239 opp-624000000 { 1240 opp-hz = /bits/ 64 <624000000>; 1241 opp-supported-hw = <0x09>; 1242 }; 1243 opp-560000000 { 1244 opp-hz = /bits/ 64 <560000000>; 1245 opp-supported-hw = <0x0d>; 1246 }; 1247 opp-510000000 { 1248 opp-hz = /bits/ 64 <510000000>; 1249 opp-supported-hw = <0xFF>; 1250 }; 1251 opp-401800000 { 1252 opp-hz = /bits/ 64 <401800000>; 1253 opp-supported-hw = <0xFF>; 1254 }; 1255 opp-315000000 { 1256 opp-hz = /bits/ 64 <315000000>; 1257 opp-supported-hw = <0xFF>; 1258 }; 1259 opp-214000000 { 1260 opp-hz = /bits/ 64 <214000000>; 1261 opp-supported-hw = <0xFF>; 1262 }; 1263 opp-133000000 { 1264 opp-hz = /bits/ 64 <133000000>; 1265 opp-supported-hw = <0xFF>; 1266 }; 1267 }; 1268 1269 zap-shader { 1270 memory-region = <&gpu_mem>; 1271 }; 1272 }; 1273 1274 tlmm: pinctrl@1010000 { 1275 compatible = "qcom,msm8996-pinctrl"; 1276 reg = <0x01010000 0x300000>; 1277 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1278 gpio-controller; 1279 gpio-ranges = <&tlmm 0 0 150>; 1280 #gpio-cells = <2>; 1281 interrupt-controller; 1282 #interrupt-cells = <2>; 1283 1284 blsp1_spi1_default: blsp1-spi1-default-state { 1285 spi-pins { 1286 pins = "gpio0", "gpio1", "gpio3"; 1287 function = "blsp_spi1"; 1288 drive-strength = <12>; 1289 bias-disable; 1290 }; 1291 1292 cs-pins { 1293 pins = "gpio2"; 1294 function = "gpio"; 1295 drive-strength = <16>; 1296 bias-disable; 1297 output-high; 1298 }; 1299 }; 1300 1301 blsp1_spi1_sleep: blsp1-spi1-sleep-state { 1302 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 1303 function = "gpio"; 1304 drive-strength = <2>; 1305 bias-pull-down; 1306 }; 1307 1308 blsp2_uart2_2pins_default: blsp2-uart2-2pins-state { 1309 pins = "gpio4", "gpio5"; 1310 function = "blsp_uart8"; 1311 drive-strength = <16>; 1312 bias-disable; 1313 }; 1314 1315 blsp2_uart2_2pins_sleep: blsp2-uart2-2pins-sleep-state { 1316 pins = "gpio4", "gpio5"; 1317 function = "gpio"; 1318 drive-strength = <2>; 1319 bias-disable; 1320 }; 1321 1322 blsp2_i2c2_default: blsp2-i2c2-state { 1323 pins = "gpio6", "gpio7"; 1324 function = "blsp_i2c8"; 1325 drive-strength = <16>; 1326 bias-disable; 1327 }; 1328 1329 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state { 1330 pins = "gpio6", "gpio7"; 1331 function = "gpio"; 1332 drive-strength = <2>; 1333 bias-disable; 1334 }; 1335 1336 blsp1_i2c6_default: blsp1-i2c6-state { 1337 pins = "gpio27", "gpio28"; 1338 function = "blsp_i2c6"; 1339 drive-strength = <16>; 1340 bias-disable; 1341 }; 1342 1343 blsp1_i2c6_sleep: blsp1-i2c6-sleep-state { 1344 pins = "gpio27", "gpio28"; 1345 function = "gpio"; 1346 drive-strength = <2>; 1347 bias-pull-up; 1348 }; 1349 1350 cci0_default: cci0-default-state { 1351 pins = "gpio17", "gpio18"; 1352 function = "cci_i2c"; 1353 drive-strength = <16>; 1354 bias-disable; 1355 }; 1356 1357 camera0_state_on: 1358 camera_rear_default: camera-rear-default-state { 1359 camera0_mclk: mclk0-pins { 1360 pins = "gpio13"; 1361 function = "cam_mclk"; 1362 drive-strength = <16>; 1363 bias-disable; 1364 }; 1365 1366 camera0_rst: rst-pins { 1367 pins = "gpio25"; 1368 function = "gpio"; 1369 drive-strength = <16>; 1370 bias-disable; 1371 }; 1372 1373 camera0_pwdn: pwdn-pins { 1374 pins = "gpio26"; 1375 function = "gpio"; 1376 drive-strength = <16>; 1377 bias-disable; 1378 }; 1379 }; 1380 1381 cci1_default: cci1-default-state { 1382 pins = "gpio19", "gpio20"; 1383 function = "cci_i2c"; 1384 drive-strength = <16>; 1385 bias-disable; 1386 }; 1387 1388 camera1_state_on: 1389 camera_board_default: camera-board-default-state { 1390 mclk1-pins { 1391 pins = "gpio14"; 1392 function = "cam_mclk"; 1393 drive-strength = <16>; 1394 bias-disable; 1395 }; 1396 1397 pwdn-pins { 1398 pins = "gpio98"; 1399 function = "gpio"; 1400 drive-strength = <16>; 1401 bias-disable; 1402 }; 1403 1404 rst-pins { 1405 pins = "gpio104"; 1406 function = "gpio"; 1407 drive-strength = <16>; 1408 bias-disable; 1409 }; 1410 }; 1411 1412 camera2_state_on: 1413 camera_front_default: camera-front-default-state { 1414 camera2_mclk: mclk2-pins { 1415 pins = "gpio15"; 1416 function = "cam_mclk"; 1417 drive-strength = <16>; 1418 bias-disable; 1419 }; 1420 1421 camera2_rst: rst-pins { 1422 pins = "gpio23"; 1423 function = "gpio"; 1424 drive-strength = <16>; 1425 bias-disable; 1426 }; 1427 1428 pwdn-pins { 1429 pins = "gpio133"; 1430 function = "gpio"; 1431 drive-strength = <16>; 1432 bias-disable; 1433 }; 1434 }; 1435 1436 pcie0_state_on: pcie0-state-on-state { 1437 perst-pins { 1438 pins = "gpio35"; 1439 function = "gpio"; 1440 drive-strength = <2>; 1441 bias-pull-down; 1442 }; 1443 1444 clkreq-pins { 1445 pins = "gpio36"; 1446 function = "pci_e0"; 1447 drive-strength = <2>; 1448 bias-pull-up; 1449 }; 1450 1451 wake-pins { 1452 pins = "gpio37"; 1453 function = "gpio"; 1454 drive-strength = <2>; 1455 bias-pull-up; 1456 }; 1457 }; 1458 1459 pcie0_state_off: pcie0-state-off-state { 1460 perst-pins { 1461 pins = "gpio35"; 1462 function = "gpio"; 1463 drive-strength = <2>; 1464 bias-pull-down; 1465 }; 1466 1467 clkreq-pins { 1468 pins = "gpio36"; 1469 function = "gpio"; 1470 drive-strength = <2>; 1471 bias-disable; 1472 }; 1473 1474 wake-pins { 1475 pins = "gpio37"; 1476 function = "gpio"; 1477 drive-strength = <2>; 1478 bias-disable; 1479 }; 1480 }; 1481 1482 blsp1_uart2_default: blsp1-uart2-default-state { 1483 pins = "gpio41", "gpio42", "gpio43", "gpio44"; 1484 function = "blsp_uart2"; 1485 drive-strength = <16>; 1486 bias-disable; 1487 }; 1488 1489 blsp1_uart2_sleep: blsp1-uart2-sleep-state { 1490 pins = "gpio41", "gpio42", "gpio43", "gpio44"; 1491 function = "gpio"; 1492 drive-strength = <2>; 1493 bias-disable; 1494 }; 1495 1496 blsp1_i2c3_default: blsp1-i2c3-default-state { 1497 pins = "gpio47", "gpio48"; 1498 function = "blsp_i2c3"; 1499 drive-strength = <16>; 1500 bias-disable; 1501 }; 1502 1503 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state { 1504 pins = "gpio47", "gpio48"; 1505 function = "gpio"; 1506 drive-strength = <2>; 1507 bias-disable; 1508 }; 1509 1510 blsp2_uart3_4pins_default: blsp2-uart3-4pins-state { 1511 pins = "gpio49", "gpio50", "gpio51", "gpio52"; 1512 function = "blsp_uart9"; 1513 drive-strength = <16>; 1514 bias-disable; 1515 }; 1516 1517 blsp2_uart3_4pins_sleep: blsp2-uart3-4pins-sleep-state { 1518 pins = "gpio49", "gpio50", "gpio51", "gpio52"; 1519 function = "blsp_uart9"; 1520 drive-strength = <2>; 1521 bias-disable; 1522 }; 1523 1524 blsp2_i2c3_default: blsp2-i2c3-state-state { 1525 pins = "gpio51", "gpio52"; 1526 function = "blsp_i2c9"; 1527 drive-strength = <16>; 1528 bias-disable; 1529 }; 1530 1531 blsp2_i2c3_sleep: blsp2-i2c3-sleep-state { 1532 pins = "gpio51", "gpio52"; 1533 function = "gpio"; 1534 drive-strength = <2>; 1535 bias-disable; 1536 }; 1537 1538 wcd_intr_default: wcd-intr-default-state { 1539 pins = "gpio54"; 1540 function = "gpio"; 1541 drive-strength = <2>; 1542 bias-pull-down; 1543 input-enable; 1544 }; 1545 1546 blsp2_i2c1_default: blsp2-i2c1-state { 1547 pins = "gpio55", "gpio56"; 1548 function = "blsp_i2c7"; 1549 drive-strength = <16>; 1550 bias-disable; 1551 }; 1552 1553 blsp2_i2c1_sleep: blsp2-i2c1-sleep-state { 1554 pins = "gpio55", "gpio56"; 1555 function = "gpio"; 1556 drive-strength = <2>; 1557 bias-disable; 1558 }; 1559 1560 blsp2_i2c5_default: blsp2-i2c5-state { 1561 pins = "gpio60", "gpio61"; 1562 function = "blsp_i2c11"; 1563 drive-strength = <2>; 1564 bias-disable; 1565 }; 1566 1567 /* Sleep state for BLSP2_I2C5 is missing.. */ 1568 1569 cdc_reset_active: cdc-reset-active-state { 1570 pins = "gpio64"; 1571 function = "gpio"; 1572 drive-strength = <16>; 1573 bias-pull-down; 1574 output-high; 1575 }; 1576 1577 cdc_reset_sleep: cdc-reset-sleep-state { 1578 pins = "gpio64"; 1579 function = "gpio"; 1580 drive-strength = <16>; 1581 bias-disable; 1582 output-low; 1583 }; 1584 1585 blsp2_spi6_default: blsp2-spi6-default-state { 1586 spi-pins { 1587 pins = "gpio85", "gpio86", "gpio88"; 1588 function = "blsp_spi12"; 1589 drive-strength = <12>; 1590 bias-disable; 1591 }; 1592 1593 cs-pins { 1594 pins = "gpio87"; 1595 function = "gpio"; 1596 drive-strength = <16>; 1597 bias-disable; 1598 output-high; 1599 }; 1600 }; 1601 1602 blsp2_spi6_sleep: blsp2-spi6-sleep-state { 1603 pins = "gpio85", "gpio86", "gpio87", "gpio88"; 1604 function = "gpio"; 1605 drive-strength = <2>; 1606 bias-pull-down; 1607 }; 1608 1609 blsp2_i2c6_default: blsp2-i2c6-state { 1610 pins = "gpio87", "gpio88"; 1611 function = "blsp_i2c12"; 1612 drive-strength = <16>; 1613 bias-disable; 1614 }; 1615 1616 blsp2_i2c6_sleep: blsp2-i2c6-sleep-state { 1617 pins = "gpio87", "gpio88"; 1618 function = "gpio"; 1619 drive-strength = <2>; 1620 bias-disable; 1621 }; 1622 1623 pcie1_state_on: pcie1-on-state { 1624 perst-pins { 1625 pins = "gpio130"; 1626 function = "gpio"; 1627 drive-strength = <2>; 1628 bias-pull-down; 1629 }; 1630 1631 clkreq-pins { 1632 pins = "gpio131"; 1633 function = "pci_e1"; 1634 drive-strength = <2>; 1635 bias-pull-up; 1636 }; 1637 1638 wake-pins { 1639 pins = "gpio132"; 1640 function = "gpio"; 1641 drive-strength = <2>; 1642 bias-pull-down; 1643 }; 1644 }; 1645 1646 pcie1_state_off: pcie1-off-state { 1647 /* Perst is missing? */ 1648 clkreq-pins { 1649 pins = "gpio131"; 1650 function = "gpio"; 1651 drive-strength = <2>; 1652 bias-disable; 1653 }; 1654 1655 wake-pins { 1656 pins = "gpio132"; 1657 function = "gpio"; 1658 drive-strength = <2>; 1659 bias-disable; 1660 }; 1661 }; 1662 1663 pcie2_state_on: pcie2-on-state { 1664 perst-pins { 1665 pins = "gpio114"; 1666 function = "gpio"; 1667 drive-strength = <2>; 1668 bias-pull-down; 1669 }; 1670 1671 clkreq-pins { 1672 pins = "gpio115"; 1673 function = "pci_e2"; 1674 drive-strength = <2>; 1675 bias-pull-up; 1676 }; 1677 1678 wake-pins { 1679 pins = "gpio116"; 1680 function = "gpio"; 1681 drive-strength = <2>; 1682 bias-pull-down; 1683 }; 1684 }; 1685 1686 pcie2_state_off: pcie2-off-state { 1687 /* Perst is missing? */ 1688 clkreq-pins { 1689 pins = "gpio115"; 1690 function = "gpio"; 1691 drive-strength = <2>; 1692 bias-disable; 1693 }; 1694 1695 wake-pins { 1696 pins = "gpio116"; 1697 function = "gpio"; 1698 drive-strength = <2>; 1699 bias-disable; 1700 }; 1701 }; 1702 1703 sdc1_state_on: sdc1-on-state { 1704 clk-pins { 1705 pins = "sdc1_clk"; 1706 bias-disable; 1707 drive-strength = <16>; 1708 }; 1709 1710 cmd-pins { 1711 pins = "sdc1_cmd"; 1712 bias-pull-up; 1713 drive-strength = <10>; 1714 }; 1715 1716 data-pins { 1717 pins = "sdc1_data"; 1718 bias-pull-up; 1719 drive-strength = <10>; 1720 }; 1721 1722 rclk-pins { 1723 pins = "sdc1_rclk"; 1724 bias-pull-down; 1725 }; 1726 }; 1727 1728 sdc1_state_off: sdc1-off-state { 1729 clk-pins { 1730 pins = "sdc1_clk"; 1731 bias-disable; 1732 drive-strength = <2>; 1733 }; 1734 1735 cmd-pins { 1736 pins = "sdc1_cmd"; 1737 bias-pull-up; 1738 drive-strength = <2>; 1739 }; 1740 1741 data-pins { 1742 pins = "sdc1_data"; 1743 bias-pull-up; 1744 drive-strength = <2>; 1745 }; 1746 1747 rclk-pins { 1748 pins = "sdc1_rclk"; 1749 bias-pull-down; 1750 }; 1751 }; 1752 1753 sdc2_state_on: sdc2-on-state { 1754 clk-pins { 1755 pins = "sdc2_clk"; 1756 bias-disable; 1757 drive-strength = <16>; 1758 }; 1759 1760 cmd-pins { 1761 pins = "sdc2_cmd"; 1762 bias-pull-up; 1763 drive-strength = <10>; 1764 }; 1765 1766 data-pins { 1767 pins = "sdc2_data"; 1768 bias-pull-up; 1769 drive-strength = <10>; 1770 }; 1771 }; 1772 1773 sdc2_state_off: sdc2-off-state { 1774 clk-pins { 1775 pins = "sdc2_clk"; 1776 bias-disable; 1777 drive-strength = <2>; 1778 }; 1779 1780 cmd-pins { 1781 pins = "sdc2_cmd"; 1782 bias-pull-up; 1783 drive-strength = <2>; 1784 }; 1785 1786 data-pins { 1787 pins = "sdc2_data"; 1788 bias-pull-up; 1789 drive-strength = <2>; 1790 }; 1791 }; 1792 }; 1793 1794 sram@290000 { 1795 compatible = "qcom,rpm-stats"; 1796 reg = <0x00290000 0x10000>; 1797 }; 1798 1799 spmi_bus: spmi@400f000 { 1800 compatible = "qcom,spmi-pmic-arb"; 1801 reg = <0x0400f000 0x1000>, 1802 <0x04400000 0x800000>, 1803 <0x04c00000 0x800000>, 1804 <0x05800000 0x200000>, 1805 <0x0400a000 0x002100>; 1806 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1807 interrupt-names = "periph_irq"; 1808 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 1809 qcom,ee = <0>; 1810 qcom,channel = <0>; 1811 #address-cells = <2>; 1812 #size-cells = <0>; 1813 interrupt-controller; 1814 #interrupt-cells = <4>; 1815 }; 1816 1817 agnoc@0 { 1818 power-domains = <&gcc AGGRE0_NOC_GDSC>; 1819 compatible = "simple-pm-bus"; 1820 #address-cells = <1>; 1821 #size-cells = <1>; 1822 ranges; 1823 1824 pcie0: pcie@600000 { 1825 compatible = "qcom,pcie-msm8996"; 1826 status = "disabled"; 1827 power-domains = <&gcc PCIE0_GDSC>; 1828 bus-range = <0x00 0xff>; 1829 num-lanes = <1>; 1830 1831 reg = <0x00600000 0x2000>, 1832 <0x0c000000 0xf1d>, 1833 <0x0c000f20 0xa8>, 1834 <0x0c100000 0x100000>; 1835 reg-names = "parf", "dbi", "elbi","config"; 1836 1837 phys = <&pciephy_0>; 1838 phy-names = "pciephy"; 1839 1840 #address-cells = <3>; 1841 #size-cells = <2>; 1842 ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>, 1843 <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>; 1844 1845 device_type = "pci"; 1846 1847 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 1848 interrupt-names = "msi"; 1849 #interrupt-cells = <1>; 1850 interrupt-map-mask = <0 0 0 0x7>; 1851 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1852 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1853 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1854 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1855 1856 pinctrl-names = "default", "sleep"; 1857 pinctrl-0 = <&pcie0_state_on>; 1858 pinctrl-1 = <&pcie0_state_off>; 1859 1860 linux,pci-domain = <0>; 1861 1862 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1863 <&gcc GCC_PCIE_0_AUX_CLK>, 1864 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1865 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1866 <&gcc GCC_PCIE_0_SLV_AXI_CLK>; 1867 1868 clock-names = "pipe", 1869 "aux", 1870 "cfg", 1871 "bus_master", 1872 "bus_slave"; 1873 1874 }; 1875 1876 pcie1: pcie@608000 { 1877 compatible = "qcom,pcie-msm8996"; 1878 power-domains = <&gcc PCIE1_GDSC>; 1879 bus-range = <0x00 0xff>; 1880 num-lanes = <1>; 1881 1882 status = "disabled"; 1883 1884 reg = <0x00608000 0x2000>, 1885 <0x0d000000 0xf1d>, 1886 <0x0d000f20 0xa8>, 1887 <0x0d100000 0x100000>; 1888 1889 reg-names = "parf", "dbi", "elbi","config"; 1890 1891 phys = <&pciephy_1>; 1892 phy-names = "pciephy"; 1893 1894 #address-cells = <3>; 1895 #size-cells = <2>; 1896 ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>, 1897 <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>; 1898 1899 device_type = "pci"; 1900 1901 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>; 1902 interrupt-names = "msi"; 1903 #interrupt-cells = <1>; 1904 interrupt-map-mask = <0 0 0 0x7>; 1905 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1906 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1907 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1908 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1909 1910 pinctrl-names = "default", "sleep"; 1911 pinctrl-0 = <&pcie1_state_on>; 1912 pinctrl-1 = <&pcie1_state_off>; 1913 1914 linux,pci-domain = <1>; 1915 1916 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1917 <&gcc GCC_PCIE_1_AUX_CLK>, 1918 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1919 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1920 <&gcc GCC_PCIE_1_SLV_AXI_CLK>; 1921 1922 clock-names = "pipe", 1923 "aux", 1924 "cfg", 1925 "bus_master", 1926 "bus_slave"; 1927 }; 1928 1929 pcie2: pcie@610000 { 1930 compatible = "qcom,pcie-msm8996"; 1931 power-domains = <&gcc PCIE2_GDSC>; 1932 bus-range = <0x00 0xff>; 1933 num-lanes = <1>; 1934 status = "disabled"; 1935 reg = <0x00610000 0x2000>, 1936 <0x0e000000 0xf1d>, 1937 <0x0e000f20 0xa8>, 1938 <0x0e100000 0x100000>; 1939 1940 reg-names = "parf", "dbi", "elbi","config"; 1941 1942 phys = <&pciephy_2>; 1943 phy-names = "pciephy"; 1944 1945 #address-cells = <3>; 1946 #size-cells = <2>; 1947 ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>, 1948 <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>; 1949 1950 device_type = "pci"; 1951 1952 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>; 1953 interrupt-names = "msi"; 1954 #interrupt-cells = <1>; 1955 interrupt-map-mask = <0 0 0 0x7>; 1956 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1957 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1958 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1959 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1960 1961 pinctrl-names = "default", "sleep"; 1962 pinctrl-0 = <&pcie2_state_on>; 1963 pinctrl-1 = <&pcie2_state_off>; 1964 1965 linux,pci-domain = <2>; 1966 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 1967 <&gcc GCC_PCIE_2_AUX_CLK>, 1968 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 1969 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 1970 <&gcc GCC_PCIE_2_SLV_AXI_CLK>; 1971 1972 clock-names = "pipe", 1973 "aux", 1974 "cfg", 1975 "bus_master", 1976 "bus_slave"; 1977 }; 1978 }; 1979 1980 ufshc: ufshc@624000 { 1981 compatible = "qcom,msm8996-ufshc", "qcom,ufshc", 1982 "jedec,ufs-2.0"; 1983 reg = <0x00624000 0x2500>; 1984 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1985 1986 phys = <&ufsphy_lane>; 1987 phy-names = "ufsphy"; 1988 1989 power-domains = <&gcc UFS_GDSC>; 1990 1991 clock-names = 1992 "core_clk_src", 1993 "core_clk", 1994 "bus_clk", 1995 "bus_aggr_clk", 1996 "iface_clk", 1997 "core_clk_unipro_src", 1998 "core_clk_unipro", 1999 "core_clk_ice", 2000 "ref_clk", 2001 "tx_lane0_sync_clk", 2002 "rx_lane0_sync_clk"; 2003 clocks = 2004 <&gcc UFS_AXI_CLK_SRC>, 2005 <&gcc GCC_UFS_AXI_CLK>, 2006 <&gcc GCC_SYS_NOC_UFS_AXI_CLK>, 2007 <&gcc GCC_AGGRE2_UFS_AXI_CLK>, 2008 <&gcc GCC_UFS_AHB_CLK>, 2009 <&gcc UFS_ICE_CORE_CLK_SRC>, 2010 <&gcc GCC_UFS_UNIPRO_CORE_CLK>, 2011 <&gcc GCC_UFS_ICE_CORE_CLK>, 2012 <&rpmcc RPM_SMD_LN_BB_CLK>, 2013 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>, 2014 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>; 2015 freq-table-hz = 2016 <100000000 200000000>, 2017 <0 0>, 2018 <0 0>, 2019 <0 0>, 2020 <0 0>, 2021 <150000000 300000000>, 2022 <0 0>, 2023 <0 0>, 2024 <0 0>, 2025 <0 0>, 2026 <0 0>; 2027 2028 lanes-per-direction = <1>; 2029 #reset-cells = <1>; 2030 status = "disabled"; 2031 }; 2032 2033 ufsphy: phy@627000 { 2034 compatible = "qcom,msm8996-qmp-ufs-phy"; 2035 reg = <0x00627000 0x1c4>; 2036 #address-cells = <1>; 2037 #size-cells = <1>; 2038 ranges; 2039 2040 clocks = <&gcc GCC_UFS_CLKREF_CLK>; 2041 clock-names = "ref"; 2042 2043 resets = <&ufshc 0>; 2044 reset-names = "ufsphy"; 2045 status = "disabled"; 2046 2047 ufsphy_lane: phy@627400 { 2048 reg = <0x627400 0x12c>, 2049 <0x627600 0x200>, 2050 <0x627c00 0x1b4>; 2051 #phy-cells = <0>; 2052 }; 2053 }; 2054 2055 camss: camss@a00000 { 2056 compatible = "qcom,msm8996-camss"; 2057 reg = <0x00a34000 0x1000>, 2058 <0x00a00030 0x4>, 2059 <0x00a35000 0x1000>, 2060 <0x00a00038 0x4>, 2061 <0x00a36000 0x1000>, 2062 <0x00a00040 0x4>, 2063 <0x00a30000 0x100>, 2064 <0x00a30400 0x100>, 2065 <0x00a30800 0x100>, 2066 <0x00a30c00 0x100>, 2067 <0x00a31000 0x500>, 2068 <0x00a00020 0x10>, 2069 <0x00a10000 0x1000>, 2070 <0x00a14000 0x1000>; 2071 reg-names = "csiphy0", 2072 "csiphy0_clk_mux", 2073 "csiphy1", 2074 "csiphy1_clk_mux", 2075 "csiphy2", 2076 "csiphy2_clk_mux", 2077 "csid0", 2078 "csid1", 2079 "csid2", 2080 "csid3", 2081 "ispif", 2082 "csi_clk_mux", 2083 "vfe0", 2084 "vfe1"; 2085 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 2086 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 2087 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, 2088 <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>, 2089 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>, 2090 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>, 2091 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>, 2092 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>, 2093 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>, 2094 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>; 2095 interrupt-names = "csiphy0", 2096 "csiphy1", 2097 "csiphy2", 2098 "csid0", 2099 "csid1", 2100 "csid2", 2101 "csid3", 2102 "ispif", 2103 "vfe0", 2104 "vfe1"; 2105 power-domains = <&mmcc VFE0_GDSC>, 2106 <&mmcc VFE1_GDSC>; 2107 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 2108 <&mmcc CAMSS_ISPIF_AHB_CLK>, 2109 <&mmcc CAMSS_CSI0PHYTIMER_CLK>, 2110 <&mmcc CAMSS_CSI1PHYTIMER_CLK>, 2111 <&mmcc CAMSS_CSI2PHYTIMER_CLK>, 2112 <&mmcc CAMSS_CSI0_AHB_CLK>, 2113 <&mmcc CAMSS_CSI0_CLK>, 2114 <&mmcc CAMSS_CSI0PHY_CLK>, 2115 <&mmcc CAMSS_CSI0PIX_CLK>, 2116 <&mmcc CAMSS_CSI0RDI_CLK>, 2117 <&mmcc CAMSS_CSI1_AHB_CLK>, 2118 <&mmcc CAMSS_CSI1_CLK>, 2119 <&mmcc CAMSS_CSI1PHY_CLK>, 2120 <&mmcc CAMSS_CSI1PIX_CLK>, 2121 <&mmcc CAMSS_CSI1RDI_CLK>, 2122 <&mmcc CAMSS_CSI2_AHB_CLK>, 2123 <&mmcc CAMSS_CSI2_CLK>, 2124 <&mmcc CAMSS_CSI2PHY_CLK>, 2125 <&mmcc CAMSS_CSI2PIX_CLK>, 2126 <&mmcc CAMSS_CSI2RDI_CLK>, 2127 <&mmcc CAMSS_CSI3_AHB_CLK>, 2128 <&mmcc CAMSS_CSI3_CLK>, 2129 <&mmcc CAMSS_CSI3PHY_CLK>, 2130 <&mmcc CAMSS_CSI3PIX_CLK>, 2131 <&mmcc CAMSS_CSI3RDI_CLK>, 2132 <&mmcc CAMSS_AHB_CLK>, 2133 <&mmcc CAMSS_VFE0_CLK>, 2134 <&mmcc CAMSS_CSI_VFE0_CLK>, 2135 <&mmcc CAMSS_VFE0_AHB_CLK>, 2136 <&mmcc CAMSS_VFE0_STREAM_CLK>, 2137 <&mmcc CAMSS_VFE1_CLK>, 2138 <&mmcc CAMSS_CSI_VFE1_CLK>, 2139 <&mmcc CAMSS_VFE1_AHB_CLK>, 2140 <&mmcc CAMSS_VFE1_STREAM_CLK>, 2141 <&mmcc CAMSS_VFE_AHB_CLK>, 2142 <&mmcc CAMSS_VFE_AXI_CLK>; 2143 clock-names = "top_ahb", 2144 "ispif_ahb", 2145 "csiphy0_timer", 2146 "csiphy1_timer", 2147 "csiphy2_timer", 2148 "csi0_ahb", 2149 "csi0", 2150 "csi0_phy", 2151 "csi0_pix", 2152 "csi0_rdi", 2153 "csi1_ahb", 2154 "csi1", 2155 "csi1_phy", 2156 "csi1_pix", 2157 "csi1_rdi", 2158 "csi2_ahb", 2159 "csi2", 2160 "csi2_phy", 2161 "csi2_pix", 2162 "csi2_rdi", 2163 "csi3_ahb", 2164 "csi3", 2165 "csi3_phy", 2166 "csi3_pix", 2167 "csi3_rdi", 2168 "ahb", 2169 "vfe0", 2170 "csi_vfe0", 2171 "vfe0_ahb", 2172 "vfe0_stream", 2173 "vfe1", 2174 "csi_vfe1", 2175 "vfe1_ahb", 2176 "vfe1_stream", 2177 "vfe_ahb", 2178 "vfe_axi"; 2179 iommus = <&vfe_smmu 0>, 2180 <&vfe_smmu 1>, 2181 <&vfe_smmu 2>, 2182 <&vfe_smmu 3>; 2183 status = "disabled"; 2184 ports { 2185 #address-cells = <1>; 2186 #size-cells = <0>; 2187 }; 2188 }; 2189 2190 cci: cci@a0c000 { 2191 compatible = "qcom,msm8996-cci"; 2192 #address-cells = <1>; 2193 #size-cells = <0>; 2194 reg = <0xa0c000 0x1000>; 2195 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>; 2196 power-domains = <&mmcc CAMSS_GDSC>; 2197 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 2198 <&mmcc CAMSS_CCI_AHB_CLK>, 2199 <&mmcc CAMSS_CCI_CLK>, 2200 <&mmcc CAMSS_AHB_CLK>; 2201 clock-names = "camss_top_ahb", 2202 "cci_ahb", 2203 "cci", 2204 "camss_ahb"; 2205 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>, 2206 <&mmcc CAMSS_CCI_CLK>; 2207 assigned-clock-rates = <80000000>, <37500000>; 2208 pinctrl-names = "default"; 2209 pinctrl-0 = <&cci0_default &cci1_default>; 2210 status = "disabled"; 2211 2212 cci_i2c0: i2c-bus@0 { 2213 reg = <0>; 2214 clock-frequency = <400000>; 2215 #address-cells = <1>; 2216 #size-cells = <0>; 2217 }; 2218 2219 cci_i2c1: i2c-bus@1 { 2220 reg = <1>; 2221 clock-frequency = <400000>; 2222 #address-cells = <1>; 2223 #size-cells = <0>; 2224 }; 2225 }; 2226 2227 adreno_smmu: iommu@b40000 { 2228 compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 2229 reg = <0x00b40000 0x10000>; 2230 2231 #global-interrupts = <1>; 2232 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2233 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2234 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 2235 #iommu-cells = <1>; 2236 2237 clocks = <&gcc GCC_MMSS_BIMC_GFX_CLK>, 2238 <&mmcc GPU_AHB_CLK>; 2239 clock-names = "bus", "iface"; 2240 2241 power-domains = <&mmcc GPU_GDSC>; 2242 }; 2243 2244 venus: video-codec@c00000 { 2245 compatible = "qcom,msm8996-venus"; 2246 reg = <0x00c00000 0xff000>; 2247 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 2248 power-domains = <&mmcc VENUS_GDSC>; 2249 clocks = <&mmcc VIDEO_CORE_CLK>, 2250 <&mmcc VIDEO_AHB_CLK>, 2251 <&mmcc VIDEO_AXI_CLK>, 2252 <&mmcc VIDEO_MAXI_CLK>; 2253 clock-names = "core", "iface", "bus", "mbus"; 2254 interconnects = <&mnoc MASTER_VIDEO_P0 &bimc SLAVE_EBI_CH0>, 2255 <&bimc MASTER_AMPSS_M0 &mnoc SLAVE_VENUS_CFG>; 2256 interconnect-names = "video-mem", "cpu-cfg"; 2257 iommus = <&venus_smmu 0x00>, 2258 <&venus_smmu 0x01>, 2259 <&venus_smmu 0x0a>, 2260 <&venus_smmu 0x07>, 2261 <&venus_smmu 0x0e>, 2262 <&venus_smmu 0x0f>, 2263 <&venus_smmu 0x08>, 2264 <&venus_smmu 0x09>, 2265 <&venus_smmu 0x0b>, 2266 <&venus_smmu 0x0c>, 2267 <&venus_smmu 0x0d>, 2268 <&venus_smmu 0x10>, 2269 <&venus_smmu 0x11>, 2270 <&venus_smmu 0x21>, 2271 <&venus_smmu 0x28>, 2272 <&venus_smmu 0x29>, 2273 <&venus_smmu 0x2b>, 2274 <&venus_smmu 0x2c>, 2275 <&venus_smmu 0x2d>, 2276 <&venus_smmu 0x31>; 2277 memory-region = <&venus_mem>; 2278 status = "disabled"; 2279 2280 video-decoder { 2281 compatible = "venus-decoder"; 2282 clocks = <&mmcc VIDEO_SUBCORE0_CLK>; 2283 clock-names = "core"; 2284 power-domains = <&mmcc VENUS_CORE0_GDSC>; 2285 }; 2286 2287 video-encoder { 2288 compatible = "venus-encoder"; 2289 clocks = <&mmcc VIDEO_SUBCORE1_CLK>; 2290 clock-names = "core"; 2291 power-domains = <&mmcc VENUS_CORE1_GDSC>; 2292 }; 2293 }; 2294 2295 mdp_smmu: iommu@d00000 { 2296 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2297 reg = <0x00d00000 0x10000>; 2298 2299 #global-interrupts = <1>; 2300 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 2301 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2302 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 2303 #iommu-cells = <1>; 2304 clocks = <&mmcc SMMU_MDP_AXI_CLK>, 2305 <&mmcc SMMU_MDP_AHB_CLK>; 2306 clock-names = "bus", "iface"; 2307 2308 power-domains = <&mmcc MDSS_GDSC>; 2309 }; 2310 2311 venus_smmu: iommu@d40000 { 2312 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2313 reg = <0x00d40000 0x20000>; 2314 #global-interrupts = <1>; 2315 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, 2316 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 2317 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2318 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2319 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2320 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2321 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2322 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; 2323 power-domains = <&mmcc MMAGIC_VIDEO_GDSC>; 2324 clocks = <&mmcc SMMU_VIDEO_AXI_CLK>, 2325 <&mmcc SMMU_VIDEO_AHB_CLK>; 2326 clock-names = "bus", "iface"; 2327 #iommu-cells = <1>; 2328 status = "okay"; 2329 }; 2330 2331 vfe_smmu: iommu@da0000 { 2332 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2333 reg = <0x00da0000 0x10000>; 2334 2335 #global-interrupts = <1>; 2336 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 2337 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 2338 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 2339 power-domains = <&mmcc MMAGIC_CAMSS_GDSC>; 2340 clocks = <&mmcc SMMU_VFE_AXI_CLK>, 2341 <&mmcc SMMU_VFE_AHB_CLK>; 2342 clock-names = "bus", "iface"; 2343 #iommu-cells = <1>; 2344 }; 2345 2346 lpass_q6_smmu: iommu@1600000 { 2347 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2348 reg = <0x01600000 0x20000>; 2349 #iommu-cells = <1>; 2350 power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>; 2351 2352 #global-interrupts = <1>; 2353 interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 2354 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 2355 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 2356 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 2357 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 2358 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 2359 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 2360 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 2361 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 2362 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 2363 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 2364 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 2365 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>; 2366 2367 clocks = <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>, 2368 <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>; 2369 clock-names = "bus", "iface"; 2370 }; 2371 2372 slpi_pil: remoteproc@1c00000 { 2373 compatible = "qcom,msm8996-slpi-pil"; 2374 reg = <0x01c00000 0x4000>; 2375 2376 interrupts-extended = <&intc 0 390 IRQ_TYPE_EDGE_RISING>, 2377 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2378 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2379 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2380 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2381 interrupt-names = "wdog", 2382 "fatal", 2383 "ready", 2384 "handover", 2385 "stop-ack"; 2386 2387 clocks = <&xo_board>, 2388 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 2389 clock-names = "xo", "aggre2"; 2390 2391 memory-region = <&slpi_mem>; 2392 2393 qcom,smem-states = <&slpi_smp2p_out 0>; 2394 qcom,smem-state-names = "stop"; 2395 2396 power-domains = <&rpmpd MSM8996_VDDSSCX>; 2397 power-domain-names = "ssc_cx"; 2398 2399 status = "disabled"; 2400 2401 smd-edge { 2402 interrupts = <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>; 2403 2404 label = "dsps"; 2405 mboxes = <&apcs_glb 25>; 2406 qcom,smd-edge = <3>; 2407 qcom,remote-pid = <3>; 2408 }; 2409 }; 2410 2411 mss_pil: remoteproc@2080000 { 2412 compatible = "qcom,msm8996-mss-pil"; 2413 reg = <0x2080000 0x100>, 2414 <0x2180000 0x020>; 2415 reg-names = "qdsp6", "rmb"; 2416 2417 interrupts-extended = <&intc 0 448 IRQ_TYPE_EDGE_RISING>, 2418 <&mpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2419 <&mpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2420 <&mpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2421 <&mpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2422 <&mpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2423 interrupt-names = "wdog", "fatal", "ready", 2424 "handover", "stop-ack", 2425 "shutdown-ack"; 2426 2427 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 2428 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, 2429 <&gcc GCC_BOOT_ROM_AHB_CLK>, 2430 <&xo_board>, 2431 <&gcc GCC_MSS_GPLL0_DIV_CLK>, 2432 <&gcc GCC_MSS_SNOC_AXI_CLK>, 2433 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>, 2434 <&rpmcc RPM_SMD_PCNOC_CLK>, 2435 <&rpmcc RPM_SMD_QDSS_CLK>; 2436 clock-names = "iface", "bus", "mem", "xo", "gpll0_mss", 2437 "snoc_axi", "mnoc_axi", "pnoc", "qdss"; 2438 2439 resets = <&gcc GCC_MSS_RESTART>; 2440 reset-names = "mss_restart"; 2441 2442 power-domains = <&rpmpd MSM8996_VDDCX>, 2443 <&rpmpd MSM8996_VDDMX>; 2444 power-domain-names = "cx", "mx"; 2445 2446 qcom,smem-states = <&mpss_smp2p_out 0>; 2447 qcom,smem-state-names = "stop"; 2448 2449 qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x4000>; 2450 2451 status = "disabled"; 2452 2453 mba { 2454 memory-region = <&mba_mem>; 2455 }; 2456 2457 mpss { 2458 memory-region = <&mpss_mem>; 2459 }; 2460 2461 smd-edge { 2462 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2463 2464 label = "mpss"; 2465 mboxes = <&apcs_glb 12>; 2466 qcom,smd-edge = <0>; 2467 qcom,remote-pid = <1>; 2468 }; 2469 }; 2470 2471 stm@3002000 { 2472 compatible = "arm,coresight-stm", "arm,primecell"; 2473 reg = <0x3002000 0x1000>, 2474 <0x8280000 0x180000>; 2475 reg-names = "stm-base", "stm-stimulus-base"; 2476 2477 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2478 clock-names = "apb_pclk", "atclk"; 2479 2480 out-ports { 2481 port { 2482 stm_out: endpoint { 2483 remote-endpoint = 2484 <&funnel0_in>; 2485 }; 2486 }; 2487 }; 2488 }; 2489 2490 tpiu@3020000 { 2491 compatible = "arm,coresight-tpiu", "arm,primecell"; 2492 reg = <0x3020000 0x1000>; 2493 2494 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2495 clock-names = "apb_pclk", "atclk"; 2496 2497 in-ports { 2498 port { 2499 tpiu_in: endpoint { 2500 remote-endpoint = 2501 <&replicator_out1>; 2502 }; 2503 }; 2504 }; 2505 }; 2506 2507 funnel@3021000 { 2508 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2509 reg = <0x3021000 0x1000>; 2510 2511 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2512 clock-names = "apb_pclk", "atclk"; 2513 2514 in-ports { 2515 #address-cells = <1>; 2516 #size-cells = <0>; 2517 2518 port@7 { 2519 reg = <7>; 2520 funnel0_in: endpoint { 2521 remote-endpoint = 2522 <&stm_out>; 2523 }; 2524 }; 2525 }; 2526 2527 out-ports { 2528 port { 2529 funnel0_out: endpoint { 2530 remote-endpoint = 2531 <&merge_funnel_in0>; 2532 }; 2533 }; 2534 }; 2535 }; 2536 2537 funnel@3022000 { 2538 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2539 reg = <0x3022000 0x1000>; 2540 2541 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2542 clock-names = "apb_pclk", "atclk"; 2543 2544 in-ports { 2545 #address-cells = <1>; 2546 #size-cells = <0>; 2547 2548 port@6 { 2549 reg = <6>; 2550 funnel1_in: endpoint { 2551 remote-endpoint = 2552 <&apss_merge_funnel_out>; 2553 }; 2554 }; 2555 }; 2556 2557 out-ports { 2558 port { 2559 funnel1_out: endpoint { 2560 remote-endpoint = 2561 <&merge_funnel_in1>; 2562 }; 2563 }; 2564 }; 2565 }; 2566 2567 funnel@3023000 { 2568 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2569 reg = <0x3023000 0x1000>; 2570 2571 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2572 clock-names = "apb_pclk", "atclk"; 2573 2574 2575 out-ports { 2576 port { 2577 funnel2_out: endpoint { 2578 remote-endpoint = 2579 <&merge_funnel_in2>; 2580 }; 2581 }; 2582 }; 2583 }; 2584 2585 funnel@3025000 { 2586 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2587 reg = <0x3025000 0x1000>; 2588 2589 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2590 clock-names = "apb_pclk", "atclk"; 2591 2592 in-ports { 2593 #address-cells = <1>; 2594 #size-cells = <0>; 2595 2596 port@0 { 2597 reg = <0>; 2598 merge_funnel_in0: endpoint { 2599 remote-endpoint = 2600 <&funnel0_out>; 2601 }; 2602 }; 2603 2604 port@1 { 2605 reg = <1>; 2606 merge_funnel_in1: endpoint { 2607 remote-endpoint = 2608 <&funnel1_out>; 2609 }; 2610 }; 2611 2612 port@2 { 2613 reg = <2>; 2614 merge_funnel_in2: endpoint { 2615 remote-endpoint = 2616 <&funnel2_out>; 2617 }; 2618 }; 2619 }; 2620 2621 out-ports { 2622 port { 2623 merge_funnel_out: endpoint { 2624 remote-endpoint = 2625 <&etf_in>; 2626 }; 2627 }; 2628 }; 2629 }; 2630 2631 replicator@3026000 { 2632 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2633 reg = <0x3026000 0x1000>; 2634 2635 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2636 clock-names = "apb_pclk", "atclk"; 2637 2638 in-ports { 2639 port { 2640 replicator_in: endpoint { 2641 remote-endpoint = 2642 <&etf_out>; 2643 }; 2644 }; 2645 }; 2646 2647 out-ports { 2648 #address-cells = <1>; 2649 #size-cells = <0>; 2650 2651 port@0 { 2652 reg = <0>; 2653 replicator_out0: endpoint { 2654 remote-endpoint = 2655 <&etr_in>; 2656 }; 2657 }; 2658 2659 port@1 { 2660 reg = <1>; 2661 replicator_out1: endpoint { 2662 remote-endpoint = 2663 <&tpiu_in>; 2664 }; 2665 }; 2666 }; 2667 }; 2668 2669 etf@3027000 { 2670 compatible = "arm,coresight-tmc", "arm,primecell"; 2671 reg = <0x3027000 0x1000>; 2672 2673 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2674 clock-names = "apb_pclk", "atclk"; 2675 2676 in-ports { 2677 port { 2678 etf_in: endpoint { 2679 remote-endpoint = 2680 <&merge_funnel_out>; 2681 }; 2682 }; 2683 }; 2684 2685 out-ports { 2686 port { 2687 etf_out: endpoint { 2688 remote-endpoint = 2689 <&replicator_in>; 2690 }; 2691 }; 2692 }; 2693 }; 2694 2695 etr@3028000 { 2696 compatible = "arm,coresight-tmc", "arm,primecell"; 2697 reg = <0x3028000 0x1000>; 2698 2699 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2700 clock-names = "apb_pclk", "atclk"; 2701 arm,scatter-gather; 2702 2703 in-ports { 2704 port { 2705 etr_in: endpoint { 2706 remote-endpoint = 2707 <&replicator_out0>; 2708 }; 2709 }; 2710 }; 2711 }; 2712 2713 debug@3810000 { 2714 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2715 reg = <0x3810000 0x1000>; 2716 2717 clocks = <&rpmcc RPM_QDSS_CLK>; 2718 clock-names = "apb_pclk"; 2719 2720 cpu = <&CPU0>; 2721 }; 2722 2723 etm@3840000 { 2724 compatible = "arm,coresight-etm4x", "arm,primecell"; 2725 reg = <0x3840000 0x1000>; 2726 2727 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2728 clock-names = "apb_pclk", "atclk"; 2729 2730 cpu = <&CPU0>; 2731 2732 out-ports { 2733 port { 2734 etm0_out: endpoint { 2735 remote-endpoint = 2736 <&apss_funnel0_in0>; 2737 }; 2738 }; 2739 }; 2740 }; 2741 2742 debug@3910000 { 2743 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2744 reg = <0x3910000 0x1000>; 2745 2746 clocks = <&rpmcc RPM_QDSS_CLK>; 2747 clock-names = "apb_pclk"; 2748 2749 cpu = <&CPU1>; 2750 }; 2751 2752 etm@3940000 { 2753 compatible = "arm,coresight-etm4x", "arm,primecell"; 2754 reg = <0x3940000 0x1000>; 2755 2756 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2757 clock-names = "apb_pclk", "atclk"; 2758 2759 cpu = <&CPU1>; 2760 2761 out-ports { 2762 port { 2763 etm1_out: endpoint { 2764 remote-endpoint = 2765 <&apss_funnel0_in1>; 2766 }; 2767 }; 2768 }; 2769 }; 2770 2771 funnel@39b0000 { /* APSS Funnel 0 */ 2772 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2773 reg = <0x39b0000 0x1000>; 2774 2775 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2776 clock-names = "apb_pclk", "atclk"; 2777 2778 in-ports { 2779 #address-cells = <1>; 2780 #size-cells = <0>; 2781 2782 port@0 { 2783 reg = <0>; 2784 apss_funnel0_in0: endpoint { 2785 remote-endpoint = <&etm0_out>; 2786 }; 2787 }; 2788 2789 port@1 { 2790 reg = <1>; 2791 apss_funnel0_in1: endpoint { 2792 remote-endpoint = <&etm1_out>; 2793 }; 2794 }; 2795 }; 2796 2797 out-ports { 2798 port { 2799 apss_funnel0_out: endpoint { 2800 remote-endpoint = 2801 <&apss_merge_funnel_in0>; 2802 }; 2803 }; 2804 }; 2805 }; 2806 2807 debug@3a10000 { 2808 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2809 reg = <0x3a10000 0x1000>; 2810 2811 clocks = <&rpmcc RPM_QDSS_CLK>; 2812 clock-names = "apb_pclk"; 2813 2814 cpu = <&CPU2>; 2815 }; 2816 2817 etm@3a40000 { 2818 compatible = "arm,coresight-etm4x", "arm,primecell"; 2819 reg = <0x3a40000 0x1000>; 2820 2821 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2822 clock-names = "apb_pclk", "atclk"; 2823 2824 cpu = <&CPU2>; 2825 2826 out-ports { 2827 port { 2828 etm2_out: endpoint { 2829 remote-endpoint = 2830 <&apss_funnel1_in0>; 2831 }; 2832 }; 2833 }; 2834 }; 2835 2836 debug@3b10000 { 2837 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2838 reg = <0x3b10000 0x1000>; 2839 2840 clocks = <&rpmcc RPM_QDSS_CLK>; 2841 clock-names = "apb_pclk"; 2842 2843 cpu = <&CPU3>; 2844 }; 2845 2846 etm@3b40000 { 2847 compatible = "arm,coresight-etm4x", "arm,primecell"; 2848 reg = <0x3b40000 0x1000>; 2849 2850 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2851 clock-names = "apb_pclk", "atclk"; 2852 2853 cpu = <&CPU3>; 2854 2855 out-ports { 2856 port { 2857 etm3_out: endpoint { 2858 remote-endpoint = 2859 <&apss_funnel1_in1>; 2860 }; 2861 }; 2862 }; 2863 }; 2864 2865 funnel@3bb0000 { /* APSS Funnel 1 */ 2866 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2867 reg = <0x3bb0000 0x1000>; 2868 2869 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2870 clock-names = "apb_pclk", "atclk"; 2871 2872 in-ports { 2873 #address-cells = <1>; 2874 #size-cells = <0>; 2875 2876 port@0 { 2877 reg = <0>; 2878 apss_funnel1_in0: endpoint { 2879 remote-endpoint = <&etm2_out>; 2880 }; 2881 }; 2882 2883 port@1 { 2884 reg = <1>; 2885 apss_funnel1_in1: endpoint { 2886 remote-endpoint = <&etm3_out>; 2887 }; 2888 }; 2889 }; 2890 2891 out-ports { 2892 port { 2893 apss_funnel1_out: endpoint { 2894 remote-endpoint = 2895 <&apss_merge_funnel_in1>; 2896 }; 2897 }; 2898 }; 2899 }; 2900 2901 funnel@3bc0000 { 2902 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2903 reg = <0x3bc0000 0x1000>; 2904 2905 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2906 clock-names = "apb_pclk", "atclk"; 2907 2908 in-ports { 2909 #address-cells = <1>; 2910 #size-cells = <0>; 2911 2912 port@0 { 2913 reg = <0>; 2914 apss_merge_funnel_in0: endpoint { 2915 remote-endpoint = 2916 <&apss_funnel0_out>; 2917 }; 2918 }; 2919 2920 port@1 { 2921 reg = <1>; 2922 apss_merge_funnel_in1: endpoint { 2923 remote-endpoint = 2924 <&apss_funnel1_out>; 2925 }; 2926 }; 2927 }; 2928 2929 out-ports { 2930 port { 2931 apss_merge_funnel_out: endpoint { 2932 remote-endpoint = 2933 <&funnel1_in>; 2934 }; 2935 }; 2936 }; 2937 }; 2938 2939 kryocc: clock-controller@6400000 { 2940 compatible = "qcom,msm8996-apcc"; 2941 reg = <0x06400000 0x90000>; 2942 2943 clock-names = "xo"; 2944 clocks = <&rpmcc RPM_SMD_BB_CLK1>; 2945 2946 #clock-cells = <1>; 2947 }; 2948 2949 usb3: usb@6af8800 { 2950 compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; 2951 reg = <0x06af8800 0x400>; 2952 #address-cells = <1>; 2953 #size-cells = <1>; 2954 ranges; 2955 2956 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 2957 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 2958 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 2959 2960 clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, 2961 <&gcc GCC_USB30_MASTER_CLK>, 2962 <&gcc GCC_AGGRE2_USB3_AXI_CLK>, 2963 <&gcc GCC_USB30_SLEEP_CLK>, 2964 <&gcc GCC_USB30_MOCK_UTMI_CLK>; 2965 clock-names = "cfg_noc", 2966 "core", 2967 "iface", 2968 "sleep", 2969 "mock_utmi"; 2970 2971 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 2972 <&gcc GCC_USB30_MASTER_CLK>; 2973 assigned-clock-rates = <19200000>, <120000000>; 2974 2975 interconnects = <&a2noc MASTER_USB3 &bimc SLAVE_EBI_CH0>, 2976 <&bimc MASTER_AMPSS_M0 &snoc SLAVE_USB3>; 2977 interconnect-names = "usb-ddr", "apps-usb"; 2978 2979 power-domains = <&gcc USB30_GDSC>; 2980 status = "disabled"; 2981 2982 usb3_dwc3: usb@6a00000 { 2983 compatible = "snps,dwc3"; 2984 reg = <0x06a00000 0xcc00>; 2985 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>; 2986 phys = <&hsusb_phy1>, <&ssusb_phy_0>; 2987 phy-names = "usb2-phy", "usb3-phy"; 2988 snps,dis_u2_susphy_quirk; 2989 snps,dis_enblslpm_quirk; 2990 }; 2991 }; 2992 2993 usb3phy: phy@7410000 { 2994 compatible = "qcom,msm8996-qmp-usb3-phy"; 2995 reg = <0x07410000 0x1c4>; 2996 #address-cells = <1>; 2997 #size-cells = <1>; 2998 ranges; 2999 3000 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, 3001 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3002 <&gcc GCC_USB3_CLKREF_CLK>; 3003 clock-names = "aux", "cfg_ahb", "ref"; 3004 3005 resets = <&gcc GCC_USB3_PHY_BCR>, 3006 <&gcc GCC_USB3PHY_PHY_BCR>; 3007 reset-names = "phy", "common"; 3008 status = "disabled"; 3009 3010 ssusb_phy_0: phy@7410200 { 3011 reg = <0x07410200 0x200>, 3012 <0x07410400 0x130>, 3013 <0x07410600 0x1a8>; 3014 #phy-cells = <0>; 3015 3016 #clock-cells = <0>; 3017 clock-output-names = "usb3_phy_pipe_clk_src"; 3018 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; 3019 clock-names = "pipe0"; 3020 }; 3021 }; 3022 3023 hsusb_phy1: phy@7411000 { 3024 compatible = "qcom,msm8996-qusb2-phy"; 3025 reg = <0x07411000 0x180>; 3026 #phy-cells = <0>; 3027 3028 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3029 <&gcc GCC_RX1_USB2_CLKREF_CLK>; 3030 clock-names = "cfg_ahb", "ref"; 3031 3032 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3033 nvmem-cells = <&qusb2p_hstx_trim>; 3034 status = "disabled"; 3035 }; 3036 3037 hsusb_phy2: phy@7412000 { 3038 compatible = "qcom,msm8996-qusb2-phy"; 3039 reg = <0x07412000 0x180>; 3040 #phy-cells = <0>; 3041 3042 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3043 <&gcc GCC_RX2_USB2_CLKREF_CLK>; 3044 clock-names = "cfg_ahb", "ref"; 3045 3046 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3047 nvmem-cells = <&qusb2s_hstx_trim>; 3048 status = "disabled"; 3049 }; 3050 3051 sdhc1: mmc@7464900 { 3052 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; 3053 reg = <0x07464900 0x11c>, <0x07464000 0x800>; 3054 reg-names = "hc", "core"; 3055 3056 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 3057 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 3058 interrupt-names = "hc_irq", "pwr_irq"; 3059 3060 clock-names = "iface", "core", "xo"; 3061 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 3062 <&gcc GCC_SDCC1_APPS_CLK>, 3063 <&rpmcc RPM_SMD_BB_CLK1>; 3064 resets = <&gcc GCC_SDCC1_BCR>; 3065 3066 pinctrl-names = "default", "sleep"; 3067 pinctrl-0 = <&sdc1_state_on>; 3068 pinctrl-1 = <&sdc1_state_off>; 3069 3070 bus-width = <8>; 3071 non-removable; 3072 status = "disabled"; 3073 }; 3074 3075 sdhc2: mmc@74a4900 { 3076 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; 3077 reg = <0x074a4900 0x314>, <0x074a4000 0x800>; 3078 reg-names = "hc", "core"; 3079 3080 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 3081 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 3082 interrupt-names = "hc_irq", "pwr_irq"; 3083 3084 clock-names = "iface", "core", "xo"; 3085 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3086 <&gcc GCC_SDCC2_APPS_CLK>, 3087 <&rpmcc RPM_SMD_BB_CLK1>; 3088 resets = <&gcc GCC_SDCC2_BCR>; 3089 3090 pinctrl-names = "default", "sleep"; 3091 pinctrl-0 = <&sdc2_state_on>; 3092 pinctrl-1 = <&sdc2_state_off>; 3093 3094 bus-width = <4>; 3095 status = "disabled"; 3096 }; 3097 3098 blsp1_dma: dma-controller@7544000 { 3099 compatible = "qcom,bam-v1.7.0"; 3100 reg = <0x07544000 0x2b000>; 3101 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 3102 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 3103 clock-names = "bam_clk"; 3104 qcom,controlled-remotely; 3105 #dma-cells = <1>; 3106 qcom,ee = <0>; 3107 }; 3108 3109 blsp1_uart2: serial@7570000 { 3110 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 3111 reg = <0x07570000 0x1000>; 3112 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 3113 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 3114 <&gcc GCC_BLSP1_AHB_CLK>; 3115 clock-names = "core", "iface"; 3116 pinctrl-names = "default", "sleep"; 3117 pinctrl-0 = <&blsp1_uart2_default>; 3118 pinctrl-1 = <&blsp1_uart2_sleep>; 3119 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; 3120 dma-names = "tx", "rx"; 3121 status = "disabled"; 3122 }; 3123 3124 blsp1_spi1: spi@7575000 { 3125 compatible = "qcom,spi-qup-v2.2.1"; 3126 reg = <0x07575000 0x600>; 3127 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 3128 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 3129 <&gcc GCC_BLSP1_AHB_CLK>; 3130 clock-names = "core", "iface"; 3131 pinctrl-names = "default", "sleep"; 3132 pinctrl-0 = <&blsp1_spi1_default>; 3133 pinctrl-1 = <&blsp1_spi1_sleep>; 3134 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; 3135 dma-names = "tx", "rx"; 3136 #address-cells = <1>; 3137 #size-cells = <0>; 3138 status = "disabled"; 3139 }; 3140 3141 blsp1_i2c3: i2c@7577000 { 3142 compatible = "qcom,i2c-qup-v2.2.1"; 3143 reg = <0x07577000 0x1000>; 3144 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 3145 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 3146 <&gcc GCC_BLSP1_AHB_CLK>; 3147 clock-names = "core", "iface"; 3148 pinctrl-names = "default", "sleep"; 3149 pinctrl-0 = <&blsp1_i2c3_default>; 3150 pinctrl-1 = <&blsp1_i2c3_sleep>; 3151 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>; 3152 dma-names = "tx", "rx"; 3153 #address-cells = <1>; 3154 #size-cells = <0>; 3155 status = "disabled"; 3156 }; 3157 3158 blsp1_i2c6: i2c@757a000 { 3159 compatible = "qcom,i2c-qup-v2.2.1"; 3160 reg = <0x757a000 0x1000>; 3161 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 3162 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 3163 <&gcc GCC_BLSP1_AHB_CLK>; 3164 clock-names = "core", "iface"; 3165 pinctrl-names = "default", "sleep"; 3166 pinctrl-0 = <&blsp1_i2c6_default>; 3167 pinctrl-1 = <&blsp1_i2c6_sleep>; 3168 dmas = <&blsp1_dma 22>, <&blsp1_dma 23>; 3169 dma-names = "tx", "rx"; 3170 #address-cells = <1>; 3171 #size-cells = <0>; 3172 status = "disabled"; 3173 }; 3174 3175 blsp2_dma: dma-controller@7584000 { 3176 compatible = "qcom,bam-v1.7.0"; 3177 reg = <0x07584000 0x2b000>; 3178 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 3179 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 3180 clock-names = "bam_clk"; 3181 qcom,controlled-remotely; 3182 #dma-cells = <1>; 3183 qcom,ee = <0>; 3184 }; 3185 3186 blsp2_uart2: serial@75b0000 { 3187 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 3188 reg = <0x075b0000 0x1000>; 3189 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 3190 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, 3191 <&gcc GCC_BLSP2_AHB_CLK>; 3192 clock-names = "core", "iface"; 3193 status = "disabled"; 3194 }; 3195 3196 blsp2_uart3: serial@75b1000 { 3197 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 3198 reg = <0x075b1000 0x1000>; 3199 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 3200 clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>, 3201 <&gcc GCC_BLSP2_AHB_CLK>; 3202 clock-names = "core", "iface"; 3203 status = "disabled"; 3204 }; 3205 3206 blsp2_i2c1: i2c@75b5000 { 3207 compatible = "qcom,i2c-qup-v2.2.1"; 3208 reg = <0x075b5000 0x1000>; 3209 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 3210 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 3211 <&gcc GCC_BLSP2_AHB_CLK>; 3212 clock-names = "core", "iface"; 3213 pinctrl-names = "default", "sleep"; 3214 pinctrl-0 = <&blsp2_i2c1_default>; 3215 pinctrl-1 = <&blsp2_i2c1_sleep>; 3216 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; 3217 dma-names = "tx", "rx"; 3218 #address-cells = <1>; 3219 #size-cells = <0>; 3220 status = "disabled"; 3221 }; 3222 3223 blsp2_i2c2: i2c@75b6000 { 3224 compatible = "qcom,i2c-qup-v2.2.1"; 3225 reg = <0x075b6000 0x1000>; 3226 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 3227 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 3228 <&gcc GCC_BLSP2_AHB_CLK>; 3229 clock-names = "core", "iface"; 3230 pinctrl-names = "default", "sleep"; 3231 pinctrl-0 = <&blsp2_i2c2_default>; 3232 pinctrl-1 = <&blsp2_i2c2_sleep>; 3233 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>; 3234 dma-names = "tx", "rx"; 3235 #address-cells = <1>; 3236 #size-cells = <0>; 3237 status = "disabled"; 3238 }; 3239 3240 blsp2_i2c3: i2c@75b7000 { 3241 compatible = "qcom,i2c-qup-v2.2.1"; 3242 reg = <0x075b7000 0x1000>; 3243 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 3244 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 3245 <&gcc GCC_BLSP2_AHB_CLK>; 3246 clock-names = "core", "iface"; 3247 clock-frequency = <400000>; 3248 pinctrl-names = "default", "sleep"; 3249 pinctrl-0 = <&blsp2_i2c3_default>; 3250 pinctrl-1 = <&blsp2_i2c3_sleep>; 3251 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>; 3252 dma-names = "tx", "rx"; 3253 #address-cells = <1>; 3254 #size-cells = <0>; 3255 status = "disabled"; 3256 }; 3257 3258 blsp2_i2c5: i2c@75b9000 { 3259 compatible = "qcom,i2c-qup-v2.2.1"; 3260 reg = <0x75b9000 0x1000>; 3261 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 3262 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, 3263 <&gcc GCC_BLSP2_AHB_CLK>; 3264 clock-names = "core", "iface"; 3265 pinctrl-names = "default"; 3266 pinctrl-0 = <&blsp2_i2c5_default>; 3267 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; 3268 dma-names = "tx", "rx"; 3269 #address-cells = <1>; 3270 #size-cells = <0>; 3271 status = "disabled"; 3272 }; 3273 3274 blsp2_i2c6: i2c@75ba000 { 3275 compatible = "qcom,i2c-qup-v2.2.1"; 3276 reg = <0x75ba000 0x1000>; 3277 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 3278 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, 3279 <&gcc GCC_BLSP2_AHB_CLK>; 3280 clock-names = "core", "iface"; 3281 pinctrl-names = "default", "sleep"; 3282 pinctrl-0 = <&blsp2_i2c6_default>; 3283 pinctrl-1 = <&blsp2_i2c6_sleep>; 3284 dmas = <&blsp2_dma 22>, <&blsp2_dma 23>; 3285 dma-names = "tx", "rx"; 3286 #address-cells = <1>; 3287 #size-cells = <0>; 3288 status = "disabled"; 3289 }; 3290 3291 blsp2_spi6: spi@75ba000{ 3292 compatible = "qcom,spi-qup-v2.2.1"; 3293 reg = <0x075ba000 0x600>; 3294 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 3295 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>, 3296 <&gcc GCC_BLSP2_AHB_CLK>; 3297 clock-names = "core", "iface"; 3298 pinctrl-names = "default", "sleep"; 3299 pinctrl-0 = <&blsp2_spi6_default>; 3300 pinctrl-1 = <&blsp2_spi6_sleep>; 3301 dmas = <&blsp2_dma 22>, <&blsp2_dma 23>; 3302 dma-names = "tx", "rx"; 3303 #address-cells = <1>; 3304 #size-cells = <0>; 3305 status = "disabled"; 3306 }; 3307 3308 usb2: usb@76f8800 { 3309 compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; 3310 reg = <0x076f8800 0x400>; 3311 #address-cells = <1>; 3312 #size-cells = <1>; 3313 ranges; 3314 3315 clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>, 3316 <&gcc GCC_USB20_MASTER_CLK>, 3317 <&gcc GCC_USB20_MOCK_UTMI_CLK>, 3318 <&gcc GCC_USB20_SLEEP_CLK>, 3319 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; 3320 clock-names = "cfg_noc", 3321 "core", 3322 "iface", 3323 "sleep", 3324 "mock_utmi"; 3325 3326 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 3327 <&gcc GCC_USB20_MASTER_CLK>; 3328 assigned-clock-rates = <19200000>, <60000000>; 3329 3330 power-domains = <&gcc USB30_GDSC>; 3331 qcom,select-utmi-as-pipe-clk; 3332 status = "disabled"; 3333 3334 usb2_dwc3: usb@7600000 { 3335 compatible = "snps,dwc3"; 3336 reg = <0x07600000 0xcc00>; 3337 interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>; 3338 phys = <&hsusb_phy2>; 3339 phy-names = "usb2-phy"; 3340 maximum-speed = "high-speed"; 3341 snps,dis_u2_susphy_quirk; 3342 snps,dis_enblslpm_quirk; 3343 }; 3344 }; 3345 3346 slimbam: dma-controller@9184000 { 3347 compatible = "qcom,bam-v1.7.0"; 3348 qcom,controlled-remotely; 3349 reg = <0x09184000 0x32000>; 3350 num-channels = <31>; 3351 interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>; 3352 #dma-cells = <1>; 3353 qcom,ee = <1>; 3354 qcom,num-ees = <2>; 3355 }; 3356 3357 slim_msm: slim-ngd@91c0000 { 3358 compatible = "qcom,slim-ngd-v1.5.0"; 3359 reg = <0x091c0000 0x2C000>; 3360 interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>; 3361 dmas = <&slimbam 3>, <&slimbam 4>; 3362 dma-names = "rx", "tx"; 3363 #address-cells = <1>; 3364 #size-cells = <0>; 3365 slim@1 { 3366 reg = <1>; 3367 #address-cells = <2>; 3368 #size-cells = <0>; 3369 3370 tasha_ifd: tas-ifd@0,0 { 3371 compatible = "slim217,1a0"; 3372 reg = <0 0>; 3373 }; 3374 3375 wcd9335: codec@1,0 { 3376 pinctrl-0 = <&cdc_reset_active &wcd_intr_default>; 3377 pinctrl-names = "default"; 3378 3379 compatible = "slim217,1a0"; 3380 reg = <1 0>; 3381 3382 interrupt-parent = <&tlmm>; 3383 interrupts = <54 IRQ_TYPE_LEVEL_HIGH>, 3384 <53 IRQ_TYPE_LEVEL_HIGH>; 3385 interrupt-names = "intr1", "intr2"; 3386 interrupt-controller; 3387 #interrupt-cells = <1>; 3388 reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>; 3389 3390 slim-ifc-dev = <&tasha_ifd>; 3391 3392 #sound-dai-cells = <1>; 3393 }; 3394 }; 3395 }; 3396 3397 adsp_pil: remoteproc@9300000 { 3398 compatible = "qcom,msm8996-adsp-pil"; 3399 reg = <0x09300000 0x80000>; 3400 3401 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>, 3402 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3403 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3404 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3405 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3406 interrupt-names = "wdog", "fatal", "ready", 3407 "handover", "stop-ack"; 3408 3409 clocks = <&rpmcc RPM_SMD_BB_CLK1>; 3410 clock-names = "xo"; 3411 3412 memory-region = <&adsp_mem>; 3413 3414 qcom,smem-states = <&adsp_smp2p_out 0>; 3415 qcom,smem-state-names = "stop"; 3416 3417 power-domains = <&rpmpd MSM8996_VDDCX>; 3418 power-domain-names = "cx"; 3419 3420 status = "disabled"; 3421 3422 smd-edge { 3423 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 3424 3425 label = "lpass"; 3426 mboxes = <&apcs_glb 8>; 3427 qcom,smd-edge = <1>; 3428 qcom,remote-pid = <2>; 3429 #address-cells = <1>; 3430 #size-cells = <0>; 3431 apr { 3432 power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>; 3433 compatible = "qcom,apr-v2"; 3434 qcom,smd-channels = "apr_audio_svc"; 3435 qcom,domain = <APR_DOMAIN_ADSP>; 3436 #address-cells = <1>; 3437 #size-cells = <0>; 3438 3439 service@3 { 3440 reg = <APR_SVC_ADSP_CORE>; 3441 compatible = "qcom,q6core"; 3442 }; 3443 3444 q6afe: service@4 { 3445 compatible = "qcom,q6afe"; 3446 reg = <APR_SVC_AFE>; 3447 q6afedai: dais { 3448 compatible = "qcom,q6afe-dais"; 3449 #address-cells = <1>; 3450 #size-cells = <0>; 3451 #sound-dai-cells = <1>; 3452 dai@1 { 3453 reg = <1>; 3454 }; 3455 }; 3456 }; 3457 3458 q6asm: service@7 { 3459 compatible = "qcom,q6asm"; 3460 reg = <APR_SVC_ASM>; 3461 q6asmdai: dais { 3462 compatible = "qcom,q6asm-dais"; 3463 #address-cells = <1>; 3464 #size-cells = <0>; 3465 #sound-dai-cells = <1>; 3466 iommus = <&lpass_q6_smmu 1>; 3467 }; 3468 }; 3469 3470 q6adm: service@8 { 3471 compatible = "qcom,q6adm"; 3472 reg = <APR_SVC_ADM>; 3473 q6routing: routing { 3474 compatible = "qcom,q6adm-routing"; 3475 #sound-dai-cells = <0>; 3476 }; 3477 }; 3478 }; 3479 3480 }; 3481 }; 3482 3483 apcs_glb: mailbox@9820000 { 3484 compatible = "qcom,msm8996-apcs-hmss-global"; 3485 reg = <0x09820000 0x1000>; 3486 3487 #mbox-cells = <1>; 3488 }; 3489 3490 timer@9840000 { 3491 #address-cells = <1>; 3492 #size-cells = <1>; 3493 ranges; 3494 compatible = "arm,armv7-timer-mem"; 3495 reg = <0x09840000 0x1000>; 3496 clock-frequency = <19200000>; 3497 3498 frame@9850000 { 3499 frame-number = <0>; 3500 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 3501 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 3502 reg = <0x09850000 0x1000>, 3503 <0x09860000 0x1000>; 3504 }; 3505 3506 frame@9870000 { 3507 frame-number = <1>; 3508 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 3509 reg = <0x09870000 0x1000>; 3510 status = "disabled"; 3511 }; 3512 3513 frame@9880000 { 3514 frame-number = <2>; 3515 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 3516 reg = <0x09880000 0x1000>; 3517 status = "disabled"; 3518 }; 3519 3520 frame@9890000 { 3521 frame-number = <3>; 3522 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 3523 reg = <0x09890000 0x1000>; 3524 status = "disabled"; 3525 }; 3526 3527 frame@98a0000 { 3528 frame-number = <4>; 3529 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 3530 reg = <0x098a0000 0x1000>; 3531 status = "disabled"; 3532 }; 3533 3534 frame@98b0000 { 3535 frame-number = <5>; 3536 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 3537 reg = <0x098b0000 0x1000>; 3538 status = "disabled"; 3539 }; 3540 3541 frame@98c0000 { 3542 frame-number = <6>; 3543 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 3544 reg = <0x098c0000 0x1000>; 3545 status = "disabled"; 3546 }; 3547 }; 3548 3549 saw3: syscon@9a10000 { 3550 compatible = "syscon"; 3551 reg = <0x09a10000 0x1000>; 3552 }; 3553 3554 intc: interrupt-controller@9bc0000 { 3555 compatible = "qcom,msm8996-gic-v3", "arm,gic-v3"; 3556 #interrupt-cells = <3>; 3557 interrupt-controller; 3558 #redistributor-regions = <1>; 3559 redistributor-stride = <0x0 0x40000>; 3560 reg = <0x09bc0000 0x10000>, 3561 <0x09c00000 0x100000>; 3562 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3563 }; 3564 }; 3565 3566 sound: sound { 3567 }; 3568 3569 thermal-zones { 3570 cpu0-thermal { 3571 polling-delay-passive = <250>; 3572 polling-delay = <1000>; 3573 3574 thermal-sensors = <&tsens0 3>; 3575 3576 trips { 3577 cpu0_alert0: trip-point0 { 3578 temperature = <75000>; 3579 hysteresis = <2000>; 3580 type = "passive"; 3581 }; 3582 3583 cpu0_crit: cpu_crit { 3584 temperature = <110000>; 3585 hysteresis = <2000>; 3586 type = "critical"; 3587 }; 3588 }; 3589 }; 3590 3591 cpu1-thermal { 3592 polling-delay-passive = <250>; 3593 polling-delay = <1000>; 3594 3595 thermal-sensors = <&tsens0 5>; 3596 3597 trips { 3598 cpu1_alert0: trip-point0 { 3599 temperature = <75000>; 3600 hysteresis = <2000>; 3601 type = "passive"; 3602 }; 3603 3604 cpu1_crit: cpu_crit { 3605 temperature = <110000>; 3606 hysteresis = <2000>; 3607 type = "critical"; 3608 }; 3609 }; 3610 }; 3611 3612 cpu2-thermal { 3613 polling-delay-passive = <250>; 3614 polling-delay = <1000>; 3615 3616 thermal-sensors = <&tsens0 8>; 3617 3618 trips { 3619 cpu2_alert0: trip-point0 { 3620 temperature = <75000>; 3621 hysteresis = <2000>; 3622 type = "passive"; 3623 }; 3624 3625 cpu2_crit: cpu_crit { 3626 temperature = <110000>; 3627 hysteresis = <2000>; 3628 type = "critical"; 3629 }; 3630 }; 3631 }; 3632 3633 cpu3-thermal { 3634 polling-delay-passive = <250>; 3635 polling-delay = <1000>; 3636 3637 thermal-sensors = <&tsens0 10>; 3638 3639 trips { 3640 cpu3_alert0: trip-point0 { 3641 temperature = <75000>; 3642 hysteresis = <2000>; 3643 type = "passive"; 3644 }; 3645 3646 cpu3_crit: cpu_crit { 3647 temperature = <110000>; 3648 hysteresis = <2000>; 3649 type = "critical"; 3650 }; 3651 }; 3652 }; 3653 3654 gpu-top-thermal { 3655 polling-delay-passive = <250>; 3656 polling-delay = <1000>; 3657 3658 thermal-sensors = <&tsens1 6>; 3659 3660 trips { 3661 gpu1_alert0: trip-point0 { 3662 temperature = <90000>; 3663 hysteresis = <2000>; 3664 type = "passive"; 3665 }; 3666 }; 3667 3668 cooling-maps { 3669 map0 { 3670 trip = <&gpu1_alert0>; 3671 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3672 }; 3673 }; 3674 }; 3675 3676 gpu-bottom-thermal { 3677 polling-delay-passive = <250>; 3678 polling-delay = <1000>; 3679 3680 thermal-sensors = <&tsens1 7>; 3681 3682 trips { 3683 gpu2_alert0: trip-point0 { 3684 temperature = <90000>; 3685 hysteresis = <2000>; 3686 type = "passive"; 3687 }; 3688 }; 3689 3690 cooling-maps { 3691 map0 { 3692 trip = <&gpu2_alert0>; 3693 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3694 }; 3695 }; 3696 }; 3697 3698 m4m-thermal { 3699 polling-delay-passive = <250>; 3700 polling-delay = <1000>; 3701 3702 thermal-sensors = <&tsens0 1>; 3703 3704 trips { 3705 m4m_alert0: trip-point0 { 3706 temperature = <90000>; 3707 hysteresis = <2000>; 3708 type = "hot"; 3709 }; 3710 }; 3711 }; 3712 3713 l3-or-venus-thermal { 3714 polling-delay-passive = <250>; 3715 polling-delay = <1000>; 3716 3717 thermal-sensors = <&tsens0 2>; 3718 3719 trips { 3720 l3_or_venus_alert0: trip-point0 { 3721 temperature = <90000>; 3722 hysteresis = <2000>; 3723 type = "hot"; 3724 }; 3725 }; 3726 }; 3727 3728 cluster0-l2-thermal { 3729 polling-delay-passive = <250>; 3730 polling-delay = <1000>; 3731 3732 thermal-sensors = <&tsens0 7>; 3733 3734 trips { 3735 cluster0_l2_alert0: trip-point0 { 3736 temperature = <90000>; 3737 hysteresis = <2000>; 3738 type = "hot"; 3739 }; 3740 }; 3741 }; 3742 3743 cluster1-l2-thermal { 3744 polling-delay-passive = <250>; 3745 polling-delay = <1000>; 3746 3747 thermal-sensors = <&tsens0 12>; 3748 3749 trips { 3750 cluster1_l2_alert0: trip-point0 { 3751 temperature = <90000>; 3752 hysteresis = <2000>; 3753 type = "hot"; 3754 }; 3755 }; 3756 }; 3757 3758 camera-thermal { 3759 polling-delay-passive = <250>; 3760 polling-delay = <1000>; 3761 3762 thermal-sensors = <&tsens1 1>; 3763 3764 trips { 3765 camera_alert0: trip-point0 { 3766 temperature = <90000>; 3767 hysteresis = <2000>; 3768 type = "hot"; 3769 }; 3770 }; 3771 }; 3772 3773 q6-dsp-thermal { 3774 polling-delay-passive = <250>; 3775 polling-delay = <1000>; 3776 3777 thermal-sensors = <&tsens1 2>; 3778 3779 trips { 3780 q6_dsp_alert0: trip-point0 { 3781 temperature = <90000>; 3782 hysteresis = <2000>; 3783 type = "hot"; 3784 }; 3785 }; 3786 }; 3787 3788 mem-thermal { 3789 polling-delay-passive = <250>; 3790 polling-delay = <1000>; 3791 3792 thermal-sensors = <&tsens1 3>; 3793 3794 trips { 3795 mem_alert0: trip-point0 { 3796 temperature = <90000>; 3797 hysteresis = <2000>; 3798 type = "hot"; 3799 }; 3800 }; 3801 }; 3802 3803 modemtx-thermal { 3804 polling-delay-passive = <250>; 3805 polling-delay = <1000>; 3806 3807 thermal-sensors = <&tsens1 4>; 3808 3809 trips { 3810 modemtx_alert0: trip-point0 { 3811 temperature = <90000>; 3812 hysteresis = <2000>; 3813 type = "hot"; 3814 }; 3815 }; 3816 }; 3817 }; 3818 3819 timer { 3820 compatible = "arm,armv8-timer"; 3821 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 3822 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 3823 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 3824 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 3825 }; 3826}; 3827