1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 4 * Author: 5 * Chris Zhong <zyw@rock-chips.com> 6 * Nickey Yang <nickey.yang@rock-chips.com> 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/iopoll.h> 11 #include <linux/math64.h> 12 #include <linux/mfd/syscon.h> 13 #include <linux/module.h> 14 #include <linux/of_device.h> 15 #include <linux/phy/phy.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/regmap.h> 18 19 #include <video/mipi_display.h> 20 21 #include <drm/bridge/dw_mipi_dsi.h> 22 #include <drm/drm_mipi_dsi.h> 23 #include <drm/drm_of.h> 24 #include <drm/drm_simple_kms_helper.h> 25 26 #include "rockchip_drm_drv.h" 27 #include "rockchip_drm_vop.h" 28 29 #define DSI_PHY_RSTZ 0xa0 30 #define PHY_DISFORCEPLL 0 31 #define PHY_ENFORCEPLL BIT(3) 32 #define PHY_DISABLECLK 0 33 #define PHY_ENABLECLK BIT(2) 34 #define PHY_RSTZ 0 35 #define PHY_UNRSTZ BIT(1) 36 #define PHY_SHUTDOWNZ 0 37 #define PHY_UNSHUTDOWNZ BIT(0) 38 39 #define DSI_PHY_IF_CFG 0xa4 40 #define N_LANES(n) ((((n) - 1) & 0x3) << 0) 41 #define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8) 42 43 #define DSI_PHY_STATUS 0xb0 44 #define LOCK BIT(0) 45 #define STOP_STATE_CLK_LANE BIT(2) 46 47 #define DSI_PHY_TST_CTRL0 0xb4 48 #define PHY_TESTCLK BIT(1) 49 #define PHY_UNTESTCLK 0 50 #define PHY_TESTCLR BIT(0) 51 #define PHY_UNTESTCLR 0 52 53 #define DSI_PHY_TST_CTRL1 0xb8 54 #define PHY_TESTEN BIT(16) 55 #define PHY_UNTESTEN 0 56 #define PHY_TESTDOUT(n) (((n) & 0xff) << 8) 57 #define PHY_TESTDIN(n) (((n) & 0xff) << 0) 58 59 #define DSI_INT_ST0 0xbc 60 #define DSI_INT_ST1 0xc0 61 #define DSI_INT_MSK0 0xc4 62 #define DSI_INT_MSK1 0xc8 63 64 #define PHY_STATUS_TIMEOUT_US 10000 65 #define CMD_PKT_STATUS_TIMEOUT_US 20000 66 67 #define BYPASS_VCO_RANGE BIT(7) 68 #define VCO_RANGE_CON_SEL(val) (((val) & 0x7) << 3) 69 #define VCO_IN_CAP_CON_DEFAULT (0x0 << 1) 70 #define VCO_IN_CAP_CON_LOW (0x1 << 1) 71 #define VCO_IN_CAP_CON_HIGH (0x2 << 1) 72 #define REF_BIAS_CUR_SEL BIT(0) 73 74 #define CP_CURRENT_3UA 0x1 75 #define CP_CURRENT_4_5UA 0x2 76 #define CP_CURRENT_7_5UA 0x6 77 #define CP_CURRENT_6UA 0x9 78 #define CP_CURRENT_12UA 0xb 79 #define CP_CURRENT_SEL(val) ((val) & 0xf) 80 #define CP_PROGRAM_EN BIT(7) 81 82 #define LPF_RESISTORS_15_5KOHM 0x1 83 #define LPF_RESISTORS_13KOHM 0x2 84 #define LPF_RESISTORS_11_5KOHM 0x4 85 #define LPF_RESISTORS_10_5KOHM 0x8 86 #define LPF_RESISTORS_8KOHM 0x10 87 #define LPF_PROGRAM_EN BIT(6) 88 #define LPF_RESISTORS_SEL(val) ((val) & 0x3f) 89 90 #define HSFREQRANGE_SEL(val) (((val) & 0x3f) << 1) 91 92 #define INPUT_DIVIDER(val) (((val) - 1) & 0x7f) 93 #define LOW_PROGRAM_EN 0 94 #define HIGH_PROGRAM_EN BIT(7) 95 #define LOOP_DIV_LOW_SEL(val) (((val) - 1) & 0x1f) 96 #define LOOP_DIV_HIGH_SEL(val) ((((val) - 1) >> 5) & 0xf) 97 #define PLL_LOOP_DIV_EN BIT(5) 98 #define PLL_INPUT_DIV_EN BIT(4) 99 100 #define POWER_CONTROL BIT(6) 101 #define INTERNAL_REG_CURRENT BIT(3) 102 #define BIAS_BLOCK_ON BIT(2) 103 #define BANDGAP_ON BIT(0) 104 105 #define TER_RESISTOR_HIGH BIT(7) 106 #define TER_RESISTOR_LOW 0 107 #define LEVEL_SHIFTERS_ON BIT(6) 108 #define TER_CAL_DONE BIT(5) 109 #define SETRD_MAX (0x7 << 2) 110 #define POWER_MANAGE BIT(1) 111 #define TER_RESISTORS_ON BIT(0) 112 113 #define BIASEXTR_SEL(val) ((val) & 0x7) 114 #define BANDGAP_SEL(val) ((val) & 0x7) 115 #define TLP_PROGRAM_EN BIT(7) 116 #define THS_PRE_PROGRAM_EN BIT(7) 117 #define THS_ZERO_PROGRAM_EN BIT(6) 118 119 #define PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL 0x10 120 #define PLL_CP_CONTROL_PLL_LOCK_BYPASS 0x11 121 #define PLL_LPF_AND_CP_CONTROL 0x12 122 #define PLL_INPUT_DIVIDER_RATIO 0x17 123 #define PLL_LOOP_DIVIDER_RATIO 0x18 124 #define PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL 0x19 125 #define BANDGAP_AND_BIAS_CONTROL 0x20 126 #define TERMINATION_RESISTER_CONTROL 0x21 127 #define AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY 0x22 128 #define HS_RX_CONTROL_OF_LANE_CLK 0x34 129 #define HS_RX_CONTROL_OF_LANE_0 0x44 130 #define HS_RX_CONTROL_OF_LANE_1 0x54 131 #define HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL 0x60 132 #define HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL 0x61 133 #define HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL 0x62 134 #define HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL 0x63 135 #define HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL 0x64 136 #define HS_TX_CLOCK_LANE_POST_TIME_CONTROL 0x65 137 #define HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL 0x70 138 #define HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL 0x71 139 #define HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL 0x72 140 #define HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL 0x73 141 #define HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL 0x74 142 #define HS_RX_DATA_LANE_THS_SETTLE_CONTROL 0x75 143 #define HS_RX_CONTROL_OF_LANE_2 0x84 144 #define HS_RX_CONTROL_OF_LANE_3 0x94 145 146 #define DW_MIPI_NEEDS_PHY_CFG_CLK BIT(0) 147 #define DW_MIPI_NEEDS_GRF_CLK BIT(1) 148 149 #define PX30_GRF_PD_VO_CON1 0x0438 150 #define PX30_DSI_FORCETXSTOPMODE (0xf << 7) 151 #define PX30_DSI_FORCERXMODE BIT(6) 152 #define PX30_DSI_TURNDISABLE BIT(5) 153 #define PX30_DSI_LCDC_SEL BIT(0) 154 155 #define RK3288_GRF_SOC_CON6 0x025c 156 #define RK3288_DSI0_LCDC_SEL BIT(6) 157 #define RK3288_DSI1_LCDC_SEL BIT(9) 158 159 #define RK3399_GRF_SOC_CON20 0x6250 160 #define RK3399_DSI0_LCDC_SEL BIT(0) 161 #define RK3399_DSI1_LCDC_SEL BIT(4) 162 163 #define RK3399_GRF_SOC_CON22 0x6258 164 #define RK3399_DSI0_TURNREQUEST (0xf << 12) 165 #define RK3399_DSI0_TURNDISABLE (0xf << 8) 166 #define RK3399_DSI0_FORCETXSTOPMODE (0xf << 4) 167 #define RK3399_DSI0_FORCERXMODE (0xf << 0) 168 169 #define RK3399_GRF_SOC_CON23 0x625c 170 #define RK3399_DSI1_TURNDISABLE (0xf << 12) 171 #define RK3399_DSI1_FORCETXSTOPMODE (0xf << 8) 172 #define RK3399_DSI1_FORCERXMODE (0xf << 4) 173 #define RK3399_DSI1_ENABLE (0xf << 0) 174 175 #define RK3399_GRF_SOC_CON24 0x6260 176 #define RK3399_TXRX_MASTERSLAVEZ BIT(7) 177 #define RK3399_TXRX_ENABLECLK BIT(6) 178 #define RK3399_TXRX_BASEDIR BIT(5) 179 #define RK3399_TXRX_SRC_SEL_ISP0 BIT(4) 180 #define RK3399_TXRX_TURNREQUEST GENMASK(3, 0) 181 182 #define RK3568_GRF_VO_CON2 0x0368 183 #define RK3568_DSI0_SKEWCALHS (0x1f << 11) 184 #define RK3568_DSI0_FORCETXSTOPMODE (0xf << 4) 185 #define RK3568_DSI0_TURNDISABLE BIT(2) 186 #define RK3568_DSI0_FORCERXMODE BIT(0) 187 188 /* 189 * Note these registers do not appear in the datasheet, they are 190 * however present in the BSP driver which is where these values 191 * come from. Name GRF_VO_CON3 is assumed. 192 */ 193 #define RK3568_GRF_VO_CON3 0x36c 194 #define RK3568_DSI1_SKEWCALHS (0x1f << 11) 195 #define RK3568_DSI1_FORCETXSTOPMODE (0xf << 4) 196 #define RK3568_DSI1_TURNDISABLE BIT(2) 197 #define RK3568_DSI1_FORCERXMODE BIT(0) 198 199 #define HIWORD_UPDATE(val, mask) (val | (mask) << 16) 200 201 enum { 202 DW_DSI_USAGE_IDLE, 203 DW_DSI_USAGE_DSI, 204 DW_DSI_USAGE_PHY, 205 }; 206 207 enum { 208 BANDGAP_97_07, 209 BANDGAP_98_05, 210 BANDGAP_99_02, 211 BANDGAP_100_00, 212 BANDGAP_93_17, 213 BANDGAP_94_15, 214 BANDGAP_95_12, 215 BANDGAP_96_10, 216 }; 217 218 enum { 219 BIASEXTR_87_1, 220 BIASEXTR_91_5, 221 BIASEXTR_95_9, 222 BIASEXTR_100, 223 BIASEXTR_105_94, 224 BIASEXTR_111_88, 225 BIASEXTR_118_8, 226 BIASEXTR_127_7, 227 }; 228 229 struct rockchip_dw_dsi_chip_data { 230 u32 reg; 231 232 u32 lcdsel_grf_reg; 233 u32 lcdsel_big; 234 u32 lcdsel_lit; 235 236 u32 enable_grf_reg; 237 u32 enable; 238 239 u32 lanecfg1_grf_reg; 240 u32 lanecfg1; 241 u32 lanecfg2_grf_reg; 242 u32 lanecfg2; 243 244 int (*dphy_rx_init)(struct phy *phy); 245 int (*dphy_rx_power_on)(struct phy *phy); 246 int (*dphy_rx_power_off)(struct phy *phy); 247 248 unsigned int flags; 249 unsigned int max_data_lanes; 250 }; 251 252 struct dw_mipi_dsi_rockchip { 253 struct device *dev; 254 struct rockchip_encoder encoder; 255 void __iomem *base; 256 257 struct regmap *grf_regmap; 258 struct clk *pclk; 259 struct clk *pllref_clk; 260 struct clk *grf_clk; 261 struct clk *phy_cfg_clk; 262 263 /* dual-channel */ 264 bool is_slave; 265 struct dw_mipi_dsi_rockchip *slave; 266 267 /* optional external dphy */ 268 struct phy *phy; 269 union phy_configure_opts phy_opts; 270 271 /* being a phy for other mipi hosts */ 272 unsigned int usage_mode; 273 struct mutex usage_mutex; 274 struct phy *dphy; 275 struct phy_configure_opts_mipi_dphy dphy_config; 276 277 unsigned int lane_mbps; /* per lane */ 278 u16 input_div; 279 u16 feedback_div; 280 u32 format; 281 282 struct dw_mipi_dsi *dmd; 283 const struct rockchip_dw_dsi_chip_data *cdata; 284 struct dw_mipi_dsi_plat_data pdata; 285 286 bool dsi_bound; 287 }; 288 289 static struct dw_mipi_dsi_rockchip *to_dsi(struct drm_encoder *encoder) 290 { 291 struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); 292 293 return container_of(rkencoder, struct dw_mipi_dsi_rockchip, encoder); 294 } 295 296 struct dphy_pll_parameter_map { 297 unsigned int max_mbps; 298 u8 hsfreqrange; 299 u8 icpctrl; 300 u8 lpfctrl; 301 }; 302 303 /* The table is based on 27MHz DPHY pll reference clock. */ 304 static const struct dphy_pll_parameter_map dppa_map[] = { 305 { 89, 0x00, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM }, 306 { 99, 0x10, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM }, 307 { 109, 0x20, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM }, 308 { 129, 0x01, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 309 { 139, 0x11, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 310 { 149, 0x21, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 311 { 169, 0x02, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM }, 312 { 179, 0x12, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM }, 313 { 199, 0x22, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM }, 314 { 219, 0x03, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM }, 315 { 239, 0x13, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM }, 316 { 249, 0x23, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM }, 317 { 269, 0x04, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM }, 318 { 299, 0x14, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM }, 319 { 329, 0x05, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 320 { 359, 0x15, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 321 { 399, 0x25, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 322 { 449, 0x06, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 323 { 499, 0x16, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 324 { 549, 0x07, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM }, 325 { 599, 0x17, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM }, 326 { 649, 0x08, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 327 { 699, 0x18, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 328 { 749, 0x09, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 329 { 799, 0x19, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 330 { 849, 0x29, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 331 { 899, 0x39, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 332 { 949, 0x0a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM }, 333 { 999, 0x1a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM }, 334 {1049, 0x2a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM }, 335 {1099, 0x3a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM }, 336 {1149, 0x0b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 337 {1199, 0x1b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 338 {1249, 0x2b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 339 {1299, 0x3b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 340 {1349, 0x0c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 341 {1399, 0x1c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 342 {1449, 0x2c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 343 {1500, 0x3c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM } 344 }; 345 346 static int max_mbps_to_parameter(unsigned int max_mbps) 347 { 348 int i; 349 350 for (i = 0; i < ARRAY_SIZE(dppa_map); i++) 351 if (dppa_map[i].max_mbps >= max_mbps) 352 return i; 353 354 return -EINVAL; 355 } 356 357 static inline void dsi_write(struct dw_mipi_dsi_rockchip *dsi, u32 reg, u32 val) 358 { 359 writel(val, dsi->base + reg); 360 } 361 362 static inline u32 dsi_read(struct dw_mipi_dsi_rockchip *dsi, u32 reg) 363 { 364 return readl(dsi->base + reg); 365 } 366 367 static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi_rockchip *dsi, 368 u8 test_code, 369 u8 test_data) 370 { 371 /* 372 * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content 373 * is latched internally as the current test code. Test data is 374 * programmed internally by rising edge on TESTCLK. 375 */ 376 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); 377 378 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) | 379 PHY_TESTDIN(test_code)); 380 381 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR); 382 383 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) | 384 PHY_TESTDIN(test_data)); 385 386 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); 387 } 388 389 /* 390 * ns2bc - Nanoseconds to byte clock cycles 391 */ 392 static inline unsigned int ns2bc(struct dw_mipi_dsi_rockchip *dsi, int ns) 393 { 394 return DIV_ROUND_UP(ns * dsi->lane_mbps / 8, 1000); 395 } 396 397 /* 398 * ns2ui - Nanoseconds to UI time periods 399 */ 400 static inline unsigned int ns2ui(struct dw_mipi_dsi_rockchip *dsi, int ns) 401 { 402 return DIV_ROUND_UP(ns * dsi->lane_mbps, 1000); 403 } 404 405 static int dw_mipi_dsi_phy_init(void *priv_data) 406 { 407 struct dw_mipi_dsi_rockchip *dsi = priv_data; 408 int ret, i, vco; 409 410 if (dsi->phy) 411 return 0; 412 413 /* 414 * Get vco from frequency(lane_mbps) 415 * vco frequency table 416 * 000 - between 80 and 200 MHz 417 * 001 - between 200 and 300 MHz 418 * 010 - between 300 and 500 MHz 419 * 011 - between 500 and 700 MHz 420 * 100 - between 700 and 900 MHz 421 * 101 - between 900 and 1100 MHz 422 * 110 - between 1100 and 1300 MHz 423 * 111 - between 1300 and 1500 MHz 424 */ 425 vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200; 426 427 i = max_mbps_to_parameter(dsi->lane_mbps); 428 if (i < 0) { 429 DRM_DEV_ERROR(dsi->dev, 430 "failed to get parameter for %dmbps clock\n", 431 dsi->lane_mbps); 432 return i; 433 } 434 435 ret = clk_prepare_enable(dsi->phy_cfg_clk); 436 if (ret) { 437 DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk\n"); 438 return ret; 439 } 440 441 dw_mipi_dsi_phy_write(dsi, PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL, 442 BYPASS_VCO_RANGE | 443 VCO_RANGE_CON_SEL(vco) | 444 VCO_IN_CAP_CON_LOW | 445 REF_BIAS_CUR_SEL); 446 447 dw_mipi_dsi_phy_write(dsi, PLL_CP_CONTROL_PLL_LOCK_BYPASS, 448 CP_CURRENT_SEL(dppa_map[i].icpctrl)); 449 dw_mipi_dsi_phy_write(dsi, PLL_LPF_AND_CP_CONTROL, 450 CP_PROGRAM_EN | LPF_PROGRAM_EN | 451 LPF_RESISTORS_SEL(dppa_map[i].lpfctrl)); 452 453 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_0, 454 HSFREQRANGE_SEL(dppa_map[i].hsfreqrange)); 455 456 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_DIVIDER_RATIO, 457 INPUT_DIVIDER(dsi->input_div)); 458 dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO, 459 LOOP_DIV_LOW_SEL(dsi->feedback_div) | 460 LOW_PROGRAM_EN); 461 /* 462 * We need set PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL immediately 463 * to make the configured LSB effective according to IP simulation 464 * and lab test results. 465 * Only in this way can we get correct mipi phy pll frequency. 466 */ 467 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL, 468 PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN); 469 dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO, 470 LOOP_DIV_HIGH_SEL(dsi->feedback_div) | 471 HIGH_PROGRAM_EN); 472 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL, 473 PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN); 474 475 dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY, 476 LOW_PROGRAM_EN | BIASEXTR_SEL(BIASEXTR_127_7)); 477 dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY, 478 HIGH_PROGRAM_EN | BANDGAP_SEL(BANDGAP_96_10)); 479 480 dw_mipi_dsi_phy_write(dsi, BANDGAP_AND_BIAS_CONTROL, 481 POWER_CONTROL | INTERNAL_REG_CURRENT | 482 BIAS_BLOCK_ON | BANDGAP_ON); 483 484 dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL, 485 TER_RESISTOR_LOW | TER_CAL_DONE | 486 SETRD_MAX | TER_RESISTORS_ON); 487 dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL, 488 TER_RESISTOR_HIGH | LEVEL_SHIFTERS_ON | 489 SETRD_MAX | POWER_MANAGE | 490 TER_RESISTORS_ON); 491 492 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL, 493 TLP_PROGRAM_EN | ns2bc(dsi, 500)); 494 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL, 495 THS_PRE_PROGRAM_EN | ns2ui(dsi, 40)); 496 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL, 497 THS_ZERO_PROGRAM_EN | ns2bc(dsi, 300)); 498 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL, 499 THS_PRE_PROGRAM_EN | ns2ui(dsi, 100)); 500 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL, 501 BIT(5) | ns2bc(dsi, 100)); 502 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_POST_TIME_CONTROL, 503 BIT(5) | (ns2bc(dsi, 60) + 7)); 504 505 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL, 506 TLP_PROGRAM_EN | ns2bc(dsi, 500)); 507 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL, 508 THS_PRE_PROGRAM_EN | (ns2ui(dsi, 50) + 20)); 509 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL, 510 THS_ZERO_PROGRAM_EN | (ns2bc(dsi, 140) + 2)); 511 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL, 512 THS_PRE_PROGRAM_EN | (ns2ui(dsi, 60) + 8)); 513 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL, 514 BIT(5) | ns2bc(dsi, 100)); 515 516 clk_disable_unprepare(dsi->phy_cfg_clk); 517 518 return ret; 519 } 520 521 static void dw_mipi_dsi_phy_power_on(void *priv_data) 522 { 523 struct dw_mipi_dsi_rockchip *dsi = priv_data; 524 int ret; 525 526 ret = phy_set_mode(dsi->phy, PHY_MODE_MIPI_DPHY); 527 if (ret) { 528 DRM_DEV_ERROR(dsi->dev, "failed to set phy mode: %d\n", ret); 529 return; 530 } 531 532 phy_configure(dsi->phy, &dsi->phy_opts); 533 phy_power_on(dsi->phy); 534 } 535 536 static void dw_mipi_dsi_phy_power_off(void *priv_data) 537 { 538 struct dw_mipi_dsi_rockchip *dsi = priv_data; 539 540 phy_power_off(dsi->phy); 541 } 542 543 static int 544 dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode, 545 unsigned long mode_flags, u32 lanes, u32 format, 546 unsigned int *lane_mbps) 547 { 548 struct dw_mipi_dsi_rockchip *dsi = priv_data; 549 int bpp; 550 unsigned long mpclk, tmp; 551 unsigned int target_mbps = 1000; 552 unsigned int max_mbps = dppa_map[ARRAY_SIZE(dppa_map) - 1].max_mbps; 553 unsigned long best_freq = 0; 554 unsigned long fvco_min, fvco_max, fin, fout; 555 unsigned int min_prediv, max_prediv; 556 unsigned int _prediv, best_prediv; 557 unsigned long _fbdiv, best_fbdiv; 558 unsigned long min_delta = ULONG_MAX; 559 560 dsi->format = format; 561 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); 562 if (bpp < 0) { 563 DRM_DEV_ERROR(dsi->dev, 564 "failed to get bpp for pixel format %d\n", 565 dsi->format); 566 return bpp; 567 } 568 569 mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC); 570 if (mpclk) { 571 /* take 1 / 0.8, since mbps must big than bandwidth of RGB */ 572 tmp = mpclk * (bpp / lanes) * 10 / 8; 573 if (tmp < max_mbps) 574 target_mbps = tmp; 575 else 576 DRM_DEV_ERROR(dsi->dev, 577 "DPHY clock frequency is out of range\n"); 578 } 579 580 /* for external phy only a the mipi_dphy_config is necessary */ 581 if (dsi->phy) { 582 phy_mipi_dphy_get_default_config(mode->clock * 1000 * 10 / 8, 583 bpp, lanes, 584 &dsi->phy_opts.mipi_dphy); 585 dsi->lane_mbps = target_mbps; 586 *lane_mbps = dsi->lane_mbps; 587 588 return 0; 589 } 590 591 fin = clk_get_rate(dsi->pllref_clk); 592 fout = target_mbps * USEC_PER_SEC; 593 594 /* constraint: 5Mhz <= Fref / N <= 40MHz */ 595 min_prediv = DIV_ROUND_UP(fin, 40 * USEC_PER_SEC); 596 max_prediv = fin / (5 * USEC_PER_SEC); 597 598 /* constraint: 80MHz <= Fvco <= 1500Mhz */ 599 fvco_min = 80 * USEC_PER_SEC; 600 fvco_max = 1500 * USEC_PER_SEC; 601 602 for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) { 603 u64 tmp; 604 u32 delta; 605 /* Fvco = Fref * M / N */ 606 tmp = (u64)fout * _prediv; 607 do_div(tmp, fin); 608 _fbdiv = tmp; 609 /* 610 * Due to the use of a "by 2 pre-scaler," the range of the 611 * feedback multiplication value M is limited to even division 612 * numbers, and m must be greater than 6, not bigger than 512. 613 */ 614 if (_fbdiv < 6 || _fbdiv > 512) 615 continue; 616 617 _fbdiv += _fbdiv % 2; 618 619 tmp = (u64)_fbdiv * fin; 620 do_div(tmp, _prediv); 621 if (tmp < fvco_min || tmp > fvco_max) 622 continue; 623 624 delta = abs(fout - tmp); 625 if (delta < min_delta) { 626 best_prediv = _prediv; 627 best_fbdiv = _fbdiv; 628 min_delta = delta; 629 best_freq = tmp; 630 } 631 } 632 633 if (best_freq) { 634 dsi->lane_mbps = DIV_ROUND_UP(best_freq, USEC_PER_SEC); 635 *lane_mbps = dsi->lane_mbps; 636 dsi->input_div = best_prediv; 637 dsi->feedback_div = best_fbdiv; 638 } else { 639 DRM_DEV_ERROR(dsi->dev, "Can not find best_freq for DPHY\n"); 640 return -EINVAL; 641 } 642 643 return 0; 644 } 645 646 struct hstt { 647 unsigned int maxfreq; 648 struct dw_mipi_dsi_dphy_timing timing; 649 }; 650 651 #define HSTT(_maxfreq, _c_lp2hs, _c_hs2lp, _d_lp2hs, _d_hs2lp) \ 652 { \ 653 .maxfreq = _maxfreq, \ 654 .timing = { \ 655 .clk_lp2hs = _c_lp2hs, \ 656 .clk_hs2lp = _c_hs2lp, \ 657 .data_lp2hs = _d_lp2hs, \ 658 .data_hs2lp = _d_hs2lp, \ 659 } \ 660 } 661 662 /* Table A-3 High-Speed Transition Times */ 663 static struct hstt hstt_table[] = { 664 HSTT( 90, 32, 20, 26, 13), 665 HSTT( 100, 35, 23, 28, 14), 666 HSTT( 110, 32, 22, 26, 13), 667 HSTT( 130, 31, 20, 27, 13), 668 HSTT( 140, 33, 22, 26, 14), 669 HSTT( 150, 33, 21, 26, 14), 670 HSTT( 170, 32, 20, 27, 13), 671 HSTT( 180, 36, 23, 30, 15), 672 HSTT( 200, 40, 22, 33, 15), 673 HSTT( 220, 40, 22, 33, 15), 674 HSTT( 240, 44, 24, 36, 16), 675 HSTT( 250, 48, 24, 38, 17), 676 HSTT( 270, 48, 24, 38, 17), 677 HSTT( 300, 50, 27, 41, 18), 678 HSTT( 330, 56, 28, 45, 18), 679 HSTT( 360, 59, 28, 48, 19), 680 HSTT( 400, 61, 30, 50, 20), 681 HSTT( 450, 67, 31, 55, 21), 682 HSTT( 500, 73, 31, 59, 22), 683 HSTT( 550, 79, 36, 63, 24), 684 HSTT( 600, 83, 37, 68, 25), 685 HSTT( 650, 90, 38, 73, 27), 686 HSTT( 700, 95, 40, 77, 28), 687 HSTT( 750, 102, 40, 84, 28), 688 HSTT( 800, 106, 42, 87, 30), 689 HSTT( 850, 113, 44, 93, 31), 690 HSTT( 900, 118, 47, 98, 32), 691 HSTT( 950, 124, 47, 102, 34), 692 HSTT(1000, 130, 49, 107, 35), 693 HSTT(1050, 135, 51, 111, 37), 694 HSTT(1100, 139, 51, 114, 38), 695 HSTT(1150, 146, 54, 120, 40), 696 HSTT(1200, 153, 57, 125, 41), 697 HSTT(1250, 158, 58, 130, 42), 698 HSTT(1300, 163, 58, 135, 44), 699 HSTT(1350, 168, 60, 140, 45), 700 HSTT(1400, 172, 64, 144, 47), 701 HSTT(1450, 176, 65, 148, 48), 702 HSTT(1500, 181, 66, 153, 50) 703 }; 704 705 static int 706 dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps, 707 struct dw_mipi_dsi_dphy_timing *timing) 708 { 709 int i; 710 711 for (i = 0; i < ARRAY_SIZE(hstt_table); i++) 712 if (lane_mbps < hstt_table[i].maxfreq) 713 break; 714 715 if (i == ARRAY_SIZE(hstt_table)) 716 i--; 717 718 *timing = hstt_table[i].timing; 719 720 return 0; 721 } 722 723 static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_rockchip_phy_ops = { 724 .init = dw_mipi_dsi_phy_init, 725 .power_on = dw_mipi_dsi_phy_power_on, 726 .power_off = dw_mipi_dsi_phy_power_off, 727 .get_lane_mbps = dw_mipi_dsi_get_lane_mbps, 728 .get_timing = dw_mipi_dsi_phy_get_timing, 729 }; 730 731 static void dw_mipi_dsi_rockchip_config(struct dw_mipi_dsi_rockchip *dsi) 732 { 733 if (dsi->cdata->lanecfg1_grf_reg) 734 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg1_grf_reg, 735 dsi->cdata->lanecfg1); 736 737 if (dsi->cdata->lanecfg2_grf_reg) 738 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg2_grf_reg, 739 dsi->cdata->lanecfg2); 740 741 if (dsi->cdata->enable_grf_reg) 742 regmap_write(dsi->grf_regmap, dsi->cdata->enable_grf_reg, 743 dsi->cdata->enable); 744 } 745 746 static void dw_mipi_dsi_rockchip_set_lcdsel(struct dw_mipi_dsi_rockchip *dsi, 747 int mux) 748 { 749 if (dsi->cdata->lcdsel_grf_reg) 750 regmap_write(dsi->grf_regmap, dsi->cdata->lcdsel_grf_reg, 751 mux ? dsi->cdata->lcdsel_lit : dsi->cdata->lcdsel_big); 752 } 753 754 static int 755 dw_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder, 756 struct drm_crtc_state *crtc_state, 757 struct drm_connector_state *conn_state) 758 { 759 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); 760 struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder); 761 762 switch (dsi->format) { 763 case MIPI_DSI_FMT_RGB888: 764 s->output_mode = ROCKCHIP_OUT_MODE_P888; 765 break; 766 case MIPI_DSI_FMT_RGB666: 767 s->output_mode = ROCKCHIP_OUT_MODE_P666; 768 break; 769 case MIPI_DSI_FMT_RGB565: 770 s->output_mode = ROCKCHIP_OUT_MODE_P565; 771 break; 772 default: 773 WARN_ON(1); 774 return -EINVAL; 775 } 776 777 s->output_type = DRM_MODE_CONNECTOR_DSI; 778 if (dsi->slave) 779 s->output_flags = ROCKCHIP_OUTPUT_DSI_DUAL; 780 781 return 0; 782 } 783 784 static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder) 785 { 786 struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder); 787 int ret, mux; 788 789 mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, 790 &dsi->encoder.encoder); 791 if (mux < 0) 792 return; 793 794 /* 795 * For the RK3399, the clk of grf must be enabled before writing grf 796 * register. And for RK3288 or other soc, this grf_clk must be NULL, 797 * the clk_prepare_enable return true directly. 798 */ 799 ret = clk_prepare_enable(dsi->grf_clk); 800 if (ret) { 801 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); 802 return; 803 } 804 805 dw_mipi_dsi_rockchip_set_lcdsel(dsi, mux); 806 if (dsi->slave) 807 dw_mipi_dsi_rockchip_set_lcdsel(dsi->slave, mux); 808 809 clk_disable_unprepare(dsi->grf_clk); 810 } 811 812 static const struct drm_encoder_helper_funcs 813 dw_mipi_dsi_encoder_helper_funcs = { 814 .atomic_check = dw_mipi_dsi_encoder_atomic_check, 815 .enable = dw_mipi_dsi_encoder_enable, 816 }; 817 818 static int rockchip_dsi_drm_create_encoder(struct dw_mipi_dsi_rockchip *dsi, 819 struct drm_device *drm_dev) 820 { 821 struct drm_encoder *encoder = &dsi->encoder.encoder; 822 int ret; 823 824 encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev, 825 dsi->dev->of_node); 826 827 ret = drm_simple_encoder_init(drm_dev, encoder, DRM_MODE_ENCODER_DSI); 828 if (ret) { 829 DRM_ERROR("Failed to initialize encoder with drm\n"); 830 return ret; 831 } 832 833 drm_encoder_helper_add(encoder, &dw_mipi_dsi_encoder_helper_funcs); 834 835 return 0; 836 } 837 838 static struct device 839 *dw_mipi_dsi_rockchip_find_second(struct dw_mipi_dsi_rockchip *dsi) 840 { 841 const struct of_device_id *match; 842 struct device_node *node = NULL, *local; 843 844 match = of_match_device(dsi->dev->driver->of_match_table, dsi->dev); 845 846 local = of_graph_get_remote_node(dsi->dev->of_node, 1, 0); 847 if (!local) 848 return NULL; 849 850 while ((node = of_find_compatible_node(node, NULL, 851 match->compatible))) { 852 struct device_node *remote; 853 854 /* found ourself */ 855 if (node == dsi->dev->of_node) 856 continue; 857 858 remote = of_graph_get_remote_node(node, 1, 0); 859 if (!remote) 860 continue; 861 862 /* same display device in port1-ep0 for both */ 863 if (remote == local) { 864 struct dw_mipi_dsi_rockchip *dsi2; 865 struct platform_device *pdev; 866 867 pdev = of_find_device_by_node(node); 868 869 /* 870 * we have found the second, so will either return it 871 * or return with an error. In any case won't need the 872 * nodes anymore nor continue the loop. 873 */ 874 of_node_put(remote); 875 of_node_put(node); 876 of_node_put(local); 877 878 if (!pdev) 879 return ERR_PTR(-EPROBE_DEFER); 880 881 dsi2 = platform_get_drvdata(pdev); 882 if (!dsi2) { 883 platform_device_put(pdev); 884 return ERR_PTR(-EPROBE_DEFER); 885 } 886 887 return &pdev->dev; 888 } 889 890 of_node_put(remote); 891 } 892 893 of_node_put(local); 894 895 return NULL; 896 } 897 898 static int dw_mipi_dsi_rockchip_bind(struct device *dev, 899 struct device *master, 900 void *data) 901 { 902 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev); 903 struct drm_device *drm_dev = data; 904 struct device *second; 905 bool master1, master2; 906 int ret; 907 908 second = dw_mipi_dsi_rockchip_find_second(dsi); 909 if (IS_ERR(second)) 910 return PTR_ERR(second); 911 912 if (second) { 913 master1 = of_property_read_bool(dsi->dev->of_node, 914 "clock-master"); 915 master2 = of_property_read_bool(second->of_node, 916 "clock-master"); 917 918 if (master1 && master2) { 919 DRM_DEV_ERROR(dsi->dev, "only one clock-master allowed\n"); 920 return -EINVAL; 921 } 922 923 if (!master1 && !master2) { 924 DRM_DEV_ERROR(dsi->dev, "no clock-master defined\n"); 925 return -EINVAL; 926 } 927 928 /* we are the slave in dual-DSI */ 929 if (!master1) { 930 dsi->is_slave = true; 931 return 0; 932 } 933 934 dsi->slave = dev_get_drvdata(second); 935 if (!dsi->slave) { 936 DRM_DEV_ERROR(dev, "could not get slaves data\n"); 937 return -ENODEV; 938 } 939 940 dsi->slave->is_slave = true; 941 dw_mipi_dsi_set_slave(dsi->dmd, dsi->slave->dmd); 942 put_device(second); 943 } 944 945 pm_runtime_get_sync(dsi->dev); 946 if (dsi->slave) 947 pm_runtime_get_sync(dsi->slave->dev); 948 949 ret = clk_prepare_enable(dsi->pllref_clk); 950 if (ret) { 951 DRM_DEV_ERROR(dev, "Failed to enable pllref_clk: %d\n", ret); 952 goto out_pm_runtime; 953 } 954 955 /* 956 * With the GRF clock running, write lane and dual-mode configurations 957 * that won't change immediately. If we waited until enable() to do 958 * this, things like panel preparation would not be able to send 959 * commands over DSI. 960 */ 961 ret = clk_prepare_enable(dsi->grf_clk); 962 if (ret) { 963 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); 964 goto out_pll_clk; 965 } 966 967 dw_mipi_dsi_rockchip_config(dsi); 968 if (dsi->slave) 969 dw_mipi_dsi_rockchip_config(dsi->slave); 970 971 clk_disable_unprepare(dsi->grf_clk); 972 973 ret = rockchip_dsi_drm_create_encoder(dsi, drm_dev); 974 if (ret) { 975 DRM_DEV_ERROR(dev, "Failed to create drm encoder\n"); 976 goto out_pll_clk; 977 } 978 rockchip_drm_encoder_set_crtc_endpoint_id(&dsi->encoder, 979 dev->of_node, 0, 0); 980 981 ret = dw_mipi_dsi_bind(dsi->dmd, &dsi->encoder.encoder); 982 if (ret) { 983 DRM_DEV_ERROR(dev, "Failed to bind: %d\n", ret); 984 goto out_pll_clk; 985 } 986 987 dsi->dsi_bound = true; 988 989 return 0; 990 991 out_pll_clk: 992 clk_disable_unprepare(dsi->pllref_clk); 993 out_pm_runtime: 994 pm_runtime_put(dsi->dev); 995 if (dsi->slave) 996 pm_runtime_put(dsi->slave->dev); 997 998 return ret; 999 } 1000 1001 static void dw_mipi_dsi_rockchip_unbind(struct device *dev, 1002 struct device *master, 1003 void *data) 1004 { 1005 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev); 1006 1007 if (dsi->is_slave) 1008 return; 1009 1010 dsi->dsi_bound = false; 1011 1012 dw_mipi_dsi_unbind(dsi->dmd); 1013 1014 clk_disable_unprepare(dsi->pllref_clk); 1015 1016 pm_runtime_put(dsi->dev); 1017 if (dsi->slave) 1018 pm_runtime_put(dsi->slave->dev); 1019 } 1020 1021 static const struct component_ops dw_mipi_dsi_rockchip_ops = { 1022 .bind = dw_mipi_dsi_rockchip_bind, 1023 .unbind = dw_mipi_dsi_rockchip_unbind, 1024 }; 1025 1026 static int dw_mipi_dsi_rockchip_host_attach(void *priv_data, 1027 struct mipi_dsi_device *device) 1028 { 1029 struct dw_mipi_dsi_rockchip *dsi = priv_data; 1030 struct device *second; 1031 int ret; 1032 1033 mutex_lock(&dsi->usage_mutex); 1034 1035 if (dsi->usage_mode != DW_DSI_USAGE_IDLE) { 1036 DRM_DEV_ERROR(dsi->dev, "dsi controller already in use\n"); 1037 mutex_unlock(&dsi->usage_mutex); 1038 return -EBUSY; 1039 } 1040 1041 dsi->usage_mode = DW_DSI_USAGE_DSI; 1042 mutex_unlock(&dsi->usage_mutex); 1043 1044 ret = component_add(dsi->dev, &dw_mipi_dsi_rockchip_ops); 1045 if (ret) { 1046 DRM_DEV_ERROR(dsi->dev, "Failed to register component: %d\n", 1047 ret); 1048 goto out; 1049 } 1050 1051 second = dw_mipi_dsi_rockchip_find_second(dsi); 1052 if (IS_ERR(second)) { 1053 ret = PTR_ERR(second); 1054 goto out; 1055 } 1056 if (second) { 1057 ret = component_add(second, &dw_mipi_dsi_rockchip_ops); 1058 if (ret) { 1059 DRM_DEV_ERROR(second, 1060 "Failed to register component: %d\n", 1061 ret); 1062 goto out; 1063 } 1064 } 1065 1066 return 0; 1067 1068 out: 1069 mutex_lock(&dsi->usage_mutex); 1070 dsi->usage_mode = DW_DSI_USAGE_IDLE; 1071 mutex_unlock(&dsi->usage_mutex); 1072 return ret; 1073 } 1074 1075 static int dw_mipi_dsi_rockchip_host_detach(void *priv_data, 1076 struct mipi_dsi_device *device) 1077 { 1078 struct dw_mipi_dsi_rockchip *dsi = priv_data; 1079 struct device *second; 1080 1081 second = dw_mipi_dsi_rockchip_find_second(dsi); 1082 if (second && !IS_ERR(second)) 1083 component_del(second, &dw_mipi_dsi_rockchip_ops); 1084 1085 component_del(dsi->dev, &dw_mipi_dsi_rockchip_ops); 1086 1087 mutex_lock(&dsi->usage_mutex); 1088 dsi->usage_mode = DW_DSI_USAGE_IDLE; 1089 mutex_unlock(&dsi->usage_mutex); 1090 1091 return 0; 1092 } 1093 1094 static const struct dw_mipi_dsi_host_ops dw_mipi_dsi_rockchip_host_ops = { 1095 .attach = dw_mipi_dsi_rockchip_host_attach, 1096 .detach = dw_mipi_dsi_rockchip_host_detach, 1097 }; 1098 1099 static int dw_mipi_dsi_rockchip_dphy_bind(struct device *dev, 1100 struct device *master, 1101 void *data) 1102 { 1103 /* 1104 * Nothing to do when used as a dphy. 1105 * Just make the rest of Rockchip-DRM happy 1106 * by being here. 1107 */ 1108 1109 return 0; 1110 } 1111 1112 static void dw_mipi_dsi_rockchip_dphy_unbind(struct device *dev, 1113 struct device *master, 1114 void *data) 1115 { 1116 /* Nothing to do when used as a dphy. */ 1117 } 1118 1119 static const struct component_ops dw_mipi_dsi_rockchip_dphy_ops = { 1120 .bind = dw_mipi_dsi_rockchip_dphy_bind, 1121 .unbind = dw_mipi_dsi_rockchip_dphy_unbind, 1122 }; 1123 1124 static int dw_mipi_dsi_dphy_init(struct phy *phy) 1125 { 1126 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1127 int ret; 1128 1129 mutex_lock(&dsi->usage_mutex); 1130 1131 if (dsi->usage_mode != DW_DSI_USAGE_IDLE) { 1132 DRM_DEV_ERROR(dsi->dev, "dsi controller already in use\n"); 1133 mutex_unlock(&dsi->usage_mutex); 1134 return -EBUSY; 1135 } 1136 1137 dsi->usage_mode = DW_DSI_USAGE_PHY; 1138 mutex_unlock(&dsi->usage_mutex); 1139 1140 ret = component_add(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops); 1141 if (ret < 0) 1142 goto err_graph; 1143 1144 if (dsi->cdata->dphy_rx_init) { 1145 ret = clk_prepare_enable(dsi->pclk); 1146 if (ret < 0) 1147 goto err_init; 1148 1149 ret = clk_prepare_enable(dsi->grf_clk); 1150 if (ret) { 1151 clk_disable_unprepare(dsi->pclk); 1152 goto err_init; 1153 } 1154 1155 ret = dsi->cdata->dphy_rx_init(phy); 1156 clk_disable_unprepare(dsi->grf_clk); 1157 clk_disable_unprepare(dsi->pclk); 1158 if (ret < 0) 1159 goto err_init; 1160 } 1161 1162 return 0; 1163 1164 err_init: 1165 component_del(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops); 1166 err_graph: 1167 mutex_lock(&dsi->usage_mutex); 1168 dsi->usage_mode = DW_DSI_USAGE_IDLE; 1169 mutex_unlock(&dsi->usage_mutex); 1170 1171 return ret; 1172 } 1173 1174 static int dw_mipi_dsi_dphy_exit(struct phy *phy) 1175 { 1176 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1177 1178 component_del(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops); 1179 1180 mutex_lock(&dsi->usage_mutex); 1181 dsi->usage_mode = DW_DSI_USAGE_IDLE; 1182 mutex_unlock(&dsi->usage_mutex); 1183 1184 return 0; 1185 } 1186 1187 static int dw_mipi_dsi_dphy_configure(struct phy *phy, union phy_configure_opts *opts) 1188 { 1189 struct phy_configure_opts_mipi_dphy *config = &opts->mipi_dphy; 1190 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1191 int ret; 1192 1193 ret = phy_mipi_dphy_config_validate(&opts->mipi_dphy); 1194 if (ret) 1195 return ret; 1196 1197 dsi->dphy_config = *config; 1198 dsi->lane_mbps = div_u64(config->hs_clk_rate, 1000 * 1000 * 1); 1199 1200 return 0; 1201 } 1202 1203 static int dw_mipi_dsi_dphy_power_on(struct phy *phy) 1204 { 1205 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1206 int i, ret; 1207 1208 DRM_DEV_DEBUG(dsi->dev, "lanes %d - data_rate_mbps %u\n", 1209 dsi->dphy_config.lanes, dsi->lane_mbps); 1210 1211 i = max_mbps_to_parameter(dsi->lane_mbps); 1212 if (i < 0) { 1213 DRM_DEV_ERROR(dsi->dev, "failed to get parameter for %dmbps clock\n", 1214 dsi->lane_mbps); 1215 return i; 1216 } 1217 1218 ret = pm_runtime_resume_and_get(dsi->dev); 1219 if (ret < 0) { 1220 DRM_DEV_ERROR(dsi->dev, "failed to enable device: %d\n", ret); 1221 return ret; 1222 } 1223 1224 ret = clk_prepare_enable(dsi->pclk); 1225 if (ret) { 1226 DRM_DEV_ERROR(dsi->dev, "Failed to enable pclk: %d\n", ret); 1227 goto err_pclk; 1228 } 1229 1230 ret = clk_prepare_enable(dsi->grf_clk); 1231 if (ret) { 1232 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); 1233 goto err_grf_clk; 1234 } 1235 1236 ret = clk_prepare_enable(dsi->phy_cfg_clk); 1237 if (ret) { 1238 DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk: %d\n", ret); 1239 goto err_phy_cfg_clk; 1240 } 1241 1242 /* do soc-variant specific init */ 1243 if (dsi->cdata->dphy_rx_power_on) { 1244 ret = dsi->cdata->dphy_rx_power_on(phy); 1245 if (ret < 0) { 1246 DRM_DEV_ERROR(dsi->dev, "hardware-specific phy bringup failed: %d\n", ret); 1247 goto err_pwr_on; 1248 } 1249 } 1250 1251 /* 1252 * Configure hsfreqrange according to frequency values 1253 * Set clock lane and hsfreqrange by lane0(test code 0x44) 1254 */ 1255 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_CLK, 0); 1256 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_0, 1257 HSFREQRANGE_SEL(dppa_map[i].hsfreqrange)); 1258 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_1, 0); 1259 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_2, 0); 1260 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_3, 0); 1261 1262 /* Normal operation */ 1263 dw_mipi_dsi_phy_write(dsi, 0x0, 0); 1264 1265 clk_disable_unprepare(dsi->phy_cfg_clk); 1266 clk_disable_unprepare(dsi->grf_clk); 1267 1268 return ret; 1269 1270 err_pwr_on: 1271 clk_disable_unprepare(dsi->phy_cfg_clk); 1272 err_phy_cfg_clk: 1273 clk_disable_unprepare(dsi->grf_clk); 1274 err_grf_clk: 1275 clk_disable_unprepare(dsi->pclk); 1276 err_pclk: 1277 pm_runtime_put(dsi->dev); 1278 return ret; 1279 } 1280 1281 static int dw_mipi_dsi_dphy_power_off(struct phy *phy) 1282 { 1283 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1284 int ret; 1285 1286 ret = clk_prepare_enable(dsi->grf_clk); 1287 if (ret) { 1288 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); 1289 return ret; 1290 } 1291 1292 if (dsi->cdata->dphy_rx_power_off) { 1293 ret = dsi->cdata->dphy_rx_power_off(phy); 1294 if (ret < 0) 1295 DRM_DEV_ERROR(dsi->dev, "hardware-specific phy shutdown failed: %d\n", ret); 1296 } 1297 1298 clk_disable_unprepare(dsi->grf_clk); 1299 clk_disable_unprepare(dsi->pclk); 1300 1301 pm_runtime_put(dsi->dev); 1302 1303 return ret; 1304 } 1305 1306 static const struct phy_ops dw_mipi_dsi_dphy_ops = { 1307 .configure = dw_mipi_dsi_dphy_configure, 1308 .power_on = dw_mipi_dsi_dphy_power_on, 1309 .power_off = dw_mipi_dsi_dphy_power_off, 1310 .init = dw_mipi_dsi_dphy_init, 1311 .exit = dw_mipi_dsi_dphy_exit, 1312 }; 1313 1314 static int __maybe_unused dw_mipi_dsi_rockchip_resume(struct device *dev) 1315 { 1316 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev); 1317 int ret; 1318 1319 /* 1320 * Re-configure DSI state, if we were previously initialized. We need 1321 * to do this before rockchip_drm_drv tries to re-enable() any panels. 1322 */ 1323 if (dsi->dsi_bound) { 1324 ret = clk_prepare_enable(dsi->grf_clk); 1325 if (ret) { 1326 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); 1327 return ret; 1328 } 1329 1330 dw_mipi_dsi_rockchip_config(dsi); 1331 if (dsi->slave) 1332 dw_mipi_dsi_rockchip_config(dsi->slave); 1333 1334 clk_disable_unprepare(dsi->grf_clk); 1335 } 1336 1337 return 0; 1338 } 1339 1340 static const struct dev_pm_ops dw_mipi_dsi_rockchip_pm_ops = { 1341 SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, dw_mipi_dsi_rockchip_resume) 1342 }; 1343 1344 static int dw_mipi_dsi_rockchip_probe(struct platform_device *pdev) 1345 { 1346 struct device *dev = &pdev->dev; 1347 struct device_node *np = dev->of_node; 1348 struct dw_mipi_dsi_rockchip *dsi; 1349 struct phy_provider *phy_provider; 1350 struct resource *res; 1351 const struct rockchip_dw_dsi_chip_data *cdata = 1352 of_device_get_match_data(dev); 1353 int ret, i; 1354 1355 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); 1356 if (!dsi) 1357 return -ENOMEM; 1358 1359 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1360 dsi->base = devm_ioremap_resource(dev, res); 1361 if (IS_ERR(dsi->base)) { 1362 DRM_DEV_ERROR(dev, "Unable to get dsi registers\n"); 1363 return PTR_ERR(dsi->base); 1364 } 1365 1366 i = 0; 1367 while (cdata[i].reg) { 1368 if (cdata[i].reg == res->start) { 1369 dsi->cdata = &cdata[i]; 1370 break; 1371 } 1372 1373 i++; 1374 } 1375 1376 if (!dsi->cdata) { 1377 DRM_DEV_ERROR(dev, "no dsi-config for %s node\n", np->name); 1378 return -EINVAL; 1379 } 1380 1381 /* try to get a possible external dphy */ 1382 dsi->phy = devm_phy_optional_get(dev, "dphy"); 1383 if (IS_ERR(dsi->phy)) { 1384 ret = PTR_ERR(dsi->phy); 1385 DRM_DEV_ERROR(dev, "failed to get mipi dphy: %d\n", ret); 1386 return ret; 1387 } 1388 1389 dsi->pclk = devm_clk_get(dev, "pclk"); 1390 if (IS_ERR(dsi->pclk)) { 1391 ret = PTR_ERR(dsi->pclk); 1392 DRM_DEV_ERROR(dev, "Unable to get pclk: %d\n", ret); 1393 return ret; 1394 } 1395 1396 dsi->pllref_clk = devm_clk_get(dev, "ref"); 1397 if (IS_ERR(dsi->pllref_clk)) { 1398 if (dsi->phy) { 1399 /* 1400 * if external phy is present, pll will be 1401 * generated there. 1402 */ 1403 dsi->pllref_clk = NULL; 1404 } else { 1405 ret = PTR_ERR(dsi->pllref_clk); 1406 DRM_DEV_ERROR(dev, 1407 "Unable to get pll reference clock: %d\n", 1408 ret); 1409 return ret; 1410 } 1411 } 1412 1413 if (dsi->cdata->flags & DW_MIPI_NEEDS_PHY_CFG_CLK) { 1414 dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg"); 1415 if (IS_ERR(dsi->phy_cfg_clk)) { 1416 ret = PTR_ERR(dsi->phy_cfg_clk); 1417 DRM_DEV_ERROR(dev, 1418 "Unable to get phy_cfg_clk: %d\n", ret); 1419 return ret; 1420 } 1421 } 1422 1423 if (dsi->cdata->flags & DW_MIPI_NEEDS_GRF_CLK) { 1424 dsi->grf_clk = devm_clk_get(dev, "grf"); 1425 if (IS_ERR(dsi->grf_clk)) { 1426 ret = PTR_ERR(dsi->grf_clk); 1427 DRM_DEV_ERROR(dev, "Unable to get grf_clk: %d\n", ret); 1428 return ret; 1429 } 1430 } 1431 1432 dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); 1433 if (IS_ERR(dsi->grf_regmap)) { 1434 DRM_DEV_ERROR(dev, "Unable to get rockchip,grf\n"); 1435 return PTR_ERR(dsi->grf_regmap); 1436 } 1437 1438 dsi->dev = dev; 1439 dsi->pdata.base = dsi->base; 1440 dsi->pdata.max_data_lanes = dsi->cdata->max_data_lanes; 1441 dsi->pdata.phy_ops = &dw_mipi_dsi_rockchip_phy_ops; 1442 dsi->pdata.host_ops = &dw_mipi_dsi_rockchip_host_ops; 1443 dsi->pdata.priv_data = dsi; 1444 platform_set_drvdata(pdev, dsi); 1445 1446 mutex_init(&dsi->usage_mutex); 1447 1448 dsi->dphy = devm_phy_create(dev, NULL, &dw_mipi_dsi_dphy_ops); 1449 if (IS_ERR(dsi->dphy)) { 1450 DRM_DEV_ERROR(&pdev->dev, "failed to create PHY\n"); 1451 return PTR_ERR(dsi->dphy); 1452 } 1453 1454 phy_set_drvdata(dsi->dphy, dsi); 1455 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 1456 if (IS_ERR(phy_provider)) 1457 return PTR_ERR(phy_provider); 1458 1459 dsi->dmd = dw_mipi_dsi_probe(pdev, &dsi->pdata); 1460 if (IS_ERR(dsi->dmd)) { 1461 ret = PTR_ERR(dsi->dmd); 1462 if (ret != -EPROBE_DEFER) 1463 DRM_DEV_ERROR(dev, 1464 "Failed to probe dw_mipi_dsi: %d\n", ret); 1465 return ret; 1466 } 1467 1468 return 0; 1469 } 1470 1471 static int dw_mipi_dsi_rockchip_remove(struct platform_device *pdev) 1472 { 1473 struct dw_mipi_dsi_rockchip *dsi = platform_get_drvdata(pdev); 1474 1475 dw_mipi_dsi_remove(dsi->dmd); 1476 1477 return 0; 1478 } 1479 1480 static const struct rockchip_dw_dsi_chip_data px30_chip_data[] = { 1481 { 1482 .reg = 0xff450000, 1483 .lcdsel_grf_reg = PX30_GRF_PD_VO_CON1, 1484 .lcdsel_big = HIWORD_UPDATE(0, PX30_DSI_LCDC_SEL), 1485 .lcdsel_lit = HIWORD_UPDATE(PX30_DSI_LCDC_SEL, 1486 PX30_DSI_LCDC_SEL), 1487 1488 .lanecfg1_grf_reg = PX30_GRF_PD_VO_CON1, 1489 .lanecfg1 = HIWORD_UPDATE(0, PX30_DSI_TURNDISABLE | 1490 PX30_DSI_FORCERXMODE | 1491 PX30_DSI_FORCETXSTOPMODE), 1492 1493 .max_data_lanes = 4, 1494 }, 1495 { /* sentinel */ } 1496 }; 1497 1498 static const struct rockchip_dw_dsi_chip_data rk3288_chip_data[] = { 1499 { 1500 .reg = 0xff960000, 1501 .lcdsel_grf_reg = RK3288_GRF_SOC_CON6, 1502 .lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI0_LCDC_SEL), 1503 .lcdsel_lit = HIWORD_UPDATE(RK3288_DSI0_LCDC_SEL, RK3288_DSI0_LCDC_SEL), 1504 1505 .max_data_lanes = 4, 1506 }, 1507 { 1508 .reg = 0xff964000, 1509 .lcdsel_grf_reg = RK3288_GRF_SOC_CON6, 1510 .lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI1_LCDC_SEL), 1511 .lcdsel_lit = HIWORD_UPDATE(RK3288_DSI1_LCDC_SEL, RK3288_DSI1_LCDC_SEL), 1512 1513 .max_data_lanes = 4, 1514 }, 1515 { /* sentinel */ } 1516 }; 1517 1518 static int rk3399_dphy_tx1rx1_init(struct phy *phy) 1519 { 1520 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1521 1522 /* 1523 * Set TX1RX1 source to isp1. 1524 * Assume ISP0 is supplied by the RX0 dphy. 1525 */ 1526 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, 1527 HIWORD_UPDATE(0, RK3399_TXRX_SRC_SEL_ISP0)); 1528 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, 1529 HIWORD_UPDATE(0, RK3399_TXRX_MASTERSLAVEZ)); 1530 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, 1531 HIWORD_UPDATE(0, RK3399_TXRX_BASEDIR)); 1532 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, 1533 HIWORD_UPDATE(0, RK3399_DSI1_ENABLE)); 1534 1535 return 0; 1536 } 1537 1538 static int rk3399_dphy_tx1rx1_power_on(struct phy *phy) 1539 { 1540 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1541 1542 /* tester reset pulse */ 1543 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_TESTCLR); 1544 usleep_range(100, 150); 1545 1546 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, 1547 HIWORD_UPDATE(0, RK3399_TXRX_MASTERSLAVEZ)); 1548 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, 1549 HIWORD_UPDATE(RK3399_TXRX_BASEDIR, RK3399_TXRX_BASEDIR)); 1550 1551 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, 1552 HIWORD_UPDATE(0, RK3399_DSI1_FORCERXMODE)); 1553 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, 1554 HIWORD_UPDATE(0, RK3399_DSI1_FORCETXSTOPMODE)); 1555 1556 /* Disable lane turn around, which is ignored in receive mode */ 1557 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, 1558 HIWORD_UPDATE(0, RK3399_TXRX_TURNREQUEST)); 1559 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, 1560 HIWORD_UPDATE(RK3399_DSI1_TURNDISABLE, 1561 RK3399_DSI1_TURNDISABLE)); 1562 usleep_range(100, 150); 1563 1564 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); 1565 usleep_range(100, 150); 1566 1567 /* Enable dphy lanes */ 1568 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, 1569 HIWORD_UPDATE(GENMASK(dsi->dphy_config.lanes - 1, 0), 1570 RK3399_DSI1_ENABLE)); 1571 1572 usleep_range(100, 150); 1573 1574 return 0; 1575 } 1576 1577 static int rk3399_dphy_tx1rx1_power_off(struct phy *phy) 1578 { 1579 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1580 1581 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, 1582 HIWORD_UPDATE(0, RK3399_DSI1_ENABLE)); 1583 1584 return 0; 1585 } 1586 1587 static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = { 1588 { 1589 .reg = 0xff960000, 1590 .lcdsel_grf_reg = RK3399_GRF_SOC_CON20, 1591 .lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI0_LCDC_SEL), 1592 .lcdsel_lit = HIWORD_UPDATE(RK3399_DSI0_LCDC_SEL, 1593 RK3399_DSI0_LCDC_SEL), 1594 1595 .lanecfg1_grf_reg = RK3399_GRF_SOC_CON22, 1596 .lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI0_TURNREQUEST | 1597 RK3399_DSI0_TURNDISABLE | 1598 RK3399_DSI0_FORCETXSTOPMODE | 1599 RK3399_DSI0_FORCERXMODE), 1600 1601 .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK, 1602 .max_data_lanes = 4, 1603 }, 1604 { 1605 .reg = 0xff968000, 1606 .lcdsel_grf_reg = RK3399_GRF_SOC_CON20, 1607 .lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI1_LCDC_SEL), 1608 .lcdsel_lit = HIWORD_UPDATE(RK3399_DSI1_LCDC_SEL, 1609 RK3399_DSI1_LCDC_SEL), 1610 1611 .lanecfg1_grf_reg = RK3399_GRF_SOC_CON23, 1612 .lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI1_TURNDISABLE | 1613 RK3399_DSI1_FORCETXSTOPMODE | 1614 RK3399_DSI1_FORCERXMODE | 1615 RK3399_DSI1_ENABLE), 1616 1617 .lanecfg2_grf_reg = RK3399_GRF_SOC_CON24, 1618 .lanecfg2 = HIWORD_UPDATE(RK3399_TXRX_MASTERSLAVEZ | 1619 RK3399_TXRX_ENABLECLK, 1620 RK3399_TXRX_MASTERSLAVEZ | 1621 RK3399_TXRX_ENABLECLK | 1622 RK3399_TXRX_BASEDIR), 1623 1624 .enable_grf_reg = RK3399_GRF_SOC_CON23, 1625 .enable = HIWORD_UPDATE(RK3399_DSI1_ENABLE, RK3399_DSI1_ENABLE), 1626 1627 .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK, 1628 .max_data_lanes = 4, 1629 1630 .dphy_rx_init = rk3399_dphy_tx1rx1_init, 1631 .dphy_rx_power_on = rk3399_dphy_tx1rx1_power_on, 1632 .dphy_rx_power_off = rk3399_dphy_tx1rx1_power_off, 1633 }, 1634 { /* sentinel */ } 1635 }; 1636 1637 static const struct rockchip_dw_dsi_chip_data rk3568_chip_data[] = { 1638 { 1639 .reg = 0xfe060000, 1640 .lanecfg1_grf_reg = RK3568_GRF_VO_CON2, 1641 .lanecfg1 = HIWORD_UPDATE(0, RK3568_DSI0_SKEWCALHS | 1642 RK3568_DSI0_FORCETXSTOPMODE | 1643 RK3568_DSI0_TURNDISABLE | 1644 RK3568_DSI0_FORCERXMODE), 1645 .max_data_lanes = 4, 1646 }, 1647 { 1648 .reg = 0xfe070000, 1649 .lanecfg1_grf_reg = RK3568_GRF_VO_CON3, 1650 .lanecfg1 = HIWORD_UPDATE(0, RK3568_DSI1_SKEWCALHS | 1651 RK3568_DSI1_FORCETXSTOPMODE | 1652 RK3568_DSI1_TURNDISABLE | 1653 RK3568_DSI1_FORCERXMODE), 1654 .max_data_lanes = 4, 1655 }, 1656 { /* sentinel */ } 1657 }; 1658 1659 static const struct of_device_id dw_mipi_dsi_rockchip_dt_ids[] = { 1660 { 1661 .compatible = "rockchip,px30-mipi-dsi", 1662 .data = &px30_chip_data, 1663 }, { 1664 .compatible = "rockchip,rk3288-mipi-dsi", 1665 .data = &rk3288_chip_data, 1666 }, { 1667 .compatible = "rockchip,rk3399-mipi-dsi", 1668 .data = &rk3399_chip_data, 1669 }, { 1670 .compatible = "rockchip,rk3568-mipi-dsi", 1671 .data = &rk3568_chip_data, 1672 }, 1673 { /* sentinel */ } 1674 }; 1675 MODULE_DEVICE_TABLE(of, dw_mipi_dsi_rockchip_dt_ids); 1676 1677 struct platform_driver dw_mipi_dsi_rockchip_driver = { 1678 .probe = dw_mipi_dsi_rockchip_probe, 1679 .remove = dw_mipi_dsi_rockchip_remove, 1680 .driver = { 1681 .of_match_table = dw_mipi_dsi_rockchip_dt_ids, 1682 .pm = &dw_mipi_dsi_rockchip_pm_ops, 1683 .name = "dw-mipi-dsi-rockchip", 1684 /* 1685 * For dual-DSI display, one DSI pokes at the other DSI's 1686 * drvdata in dw_mipi_dsi_rockchip_find_second(). This is not 1687 * safe for asynchronous probe. 1688 */ 1689 .probe_type = PROBE_FORCE_SYNCHRONOUS, 1690 }, 1691 }; 1692