1// SPDX-License-Identifier: GPL-2.0 2 3#include <dt-bindings/clock/tegra234-clock.h> 4#include <dt-bindings/gpio/tegra234-gpio.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/mailbox/tegra186-hsp.h> 7#include <dt-bindings/memory/tegra234-mc.h> 8#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 9#include <dt-bindings/power/tegra234-powergate.h> 10#include <dt-bindings/reset/tegra234-reset.h> 11 12/ { 13 compatible = "nvidia,tegra234"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 bus@0 { 19 compatible = "simple-bus"; 20 21 #address-cells = <2>; 22 #size-cells = <2>; 23 ranges = <0x0 0x0 0x0 0x0 0x0 0x40000000>; 24 25 misc@100000 { 26 compatible = "nvidia,tegra234-misc"; 27 reg = <0x0 0x00100000 0x0 0xf000>, 28 <0x0 0x0010f000 0x0 0x1000>; 29 status = "okay"; 30 }; 31 32 timer@2080000 { 33 compatible = "nvidia,tegra234-timer"; 34 reg = <0x0 0x02080000 0x0 0x00121000>; 35 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 36 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 37 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 41 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 42 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 43 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 44 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 45 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 46 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 47 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 48 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 49 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 50 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 51 status = "okay"; 52 }; 53 54 gpio: gpio@2200000 { 55 compatible = "nvidia,tegra234-gpio"; 56 reg-names = "security", "gpio"; 57 reg = <0x0 0x02200000 0x0 0x10000>, 58 <0x0 0x02210000 0x0 0x10000>; 59 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 61 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 62 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 63 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 65 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 69 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 70 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 71 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 72 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 73 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 74 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 75 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 77 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 79 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 87 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 88 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 89 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 90 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 91 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 92 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 94 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 107 #interrupt-cells = <2>; 108 interrupt-controller; 109 #gpio-cells = <2>; 110 gpio-controller; 111 }; 112 113 gpcdma: dma-controller@2600000 { 114 compatible = "nvidia,tegra234-gpcdma", 115 "nvidia,tegra186-gpcdma"; 116 reg = <0x0 0x2600000 0x0 0x210000>; 117 resets = <&bpmp TEGRA234_RESET_GPCDMA>; 118 reset-names = "gpcdma"; 119 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 120 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 121 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 122 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 123 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 124 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 125 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 126 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 127 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 128 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 129 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 130 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 131 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 132 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 133 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 134 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 135 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 136 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 137 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 139 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 140 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 141 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 142 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 143 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 144 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 145 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 146 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 147 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 151 #dma-cells = <1>; 152 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 153 dma-channel-mask = <0xfffffffe>; 154 dma-coherent; 155 }; 156 157 aconnect@2900000 { 158 compatible = "nvidia,tegra234-aconnect", 159 "nvidia,tegra210-aconnect"; 160 clocks = <&bpmp TEGRA234_CLK_APE>, 161 <&bpmp TEGRA234_CLK_APB2APE>; 162 clock-names = "ape", "apb2ape"; 163 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_AUD>; 164 status = "disabled"; 165 166 #address-cells = <2>; 167 #size-cells = <2>; 168 ranges = <0x0 0x02900000 0x0 0x02900000 0x0 0x200000>; 169 170 tegra_ahub: ahub@2900800 { 171 compatible = "nvidia,tegra234-ahub"; 172 reg = <0x0 0x02900800 0x0 0x800>; 173 clocks = <&bpmp TEGRA234_CLK_AHUB>; 174 clock-names = "ahub"; 175 assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>; 176 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 177 status = "disabled"; 178 179 #address-cells = <2>; 180 #size-cells = <2>; 181 ranges = <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>; 182 183 tegra_i2s1: i2s@2901000 { 184 compatible = "nvidia,tegra234-i2s", 185 "nvidia,tegra210-i2s"; 186 reg = <0x0 0x2901000 0x0 0x100>; 187 clocks = <&bpmp TEGRA234_CLK_I2S1>, 188 <&bpmp TEGRA234_CLK_I2S1_SYNC_INPUT>; 189 clock-names = "i2s", "sync_input"; 190 assigned-clocks = <&bpmp TEGRA234_CLK_I2S1>; 191 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 192 assigned-clock-rates = <1536000>; 193 sound-name-prefix = "I2S1"; 194 status = "disabled"; 195 }; 196 197 tegra_i2s2: i2s@2901100 { 198 compatible = "nvidia,tegra234-i2s", 199 "nvidia,tegra210-i2s"; 200 reg = <0x0 0x2901100 0x0 0x100>; 201 clocks = <&bpmp TEGRA234_CLK_I2S2>, 202 <&bpmp TEGRA234_CLK_I2S2_SYNC_INPUT>; 203 clock-names = "i2s", "sync_input"; 204 assigned-clocks = <&bpmp TEGRA234_CLK_I2S2>; 205 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 206 assigned-clock-rates = <1536000>; 207 sound-name-prefix = "I2S2"; 208 status = "disabled"; 209 }; 210 211 tegra_i2s3: i2s@2901200 { 212 compatible = "nvidia,tegra234-i2s", 213 "nvidia,tegra210-i2s"; 214 reg = <0x0 0x2901200 0x0 0x100>; 215 clocks = <&bpmp TEGRA234_CLK_I2S3>, 216 <&bpmp TEGRA234_CLK_I2S3_SYNC_INPUT>; 217 clock-names = "i2s", "sync_input"; 218 assigned-clocks = <&bpmp TEGRA234_CLK_I2S3>; 219 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 220 assigned-clock-rates = <1536000>; 221 sound-name-prefix = "I2S3"; 222 status = "disabled"; 223 }; 224 225 tegra_i2s4: i2s@2901300 { 226 compatible = "nvidia,tegra234-i2s", 227 "nvidia,tegra210-i2s"; 228 reg = <0x0 0x2901300 0x0 0x100>; 229 clocks = <&bpmp TEGRA234_CLK_I2S4>, 230 <&bpmp TEGRA234_CLK_I2S4_SYNC_INPUT>; 231 clock-names = "i2s", "sync_input"; 232 assigned-clocks = <&bpmp TEGRA234_CLK_I2S4>; 233 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 234 assigned-clock-rates = <1536000>; 235 sound-name-prefix = "I2S4"; 236 status = "disabled"; 237 }; 238 239 tegra_i2s5: i2s@2901400 { 240 compatible = "nvidia,tegra234-i2s", 241 "nvidia,tegra210-i2s"; 242 reg = <0x0 0x2901400 0x0 0x100>; 243 clocks = <&bpmp TEGRA234_CLK_I2S5>, 244 <&bpmp TEGRA234_CLK_I2S5_SYNC_INPUT>; 245 clock-names = "i2s", "sync_input"; 246 assigned-clocks = <&bpmp TEGRA234_CLK_I2S5>; 247 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 248 assigned-clock-rates = <1536000>; 249 sound-name-prefix = "I2S5"; 250 status = "disabled"; 251 }; 252 253 tegra_i2s6: i2s@2901500 { 254 compatible = "nvidia,tegra234-i2s", 255 "nvidia,tegra210-i2s"; 256 reg = <0x0 0x2901500 0x0 0x100>; 257 clocks = <&bpmp TEGRA234_CLK_I2S6>, 258 <&bpmp TEGRA234_CLK_I2S6_SYNC_INPUT>; 259 clock-names = "i2s", "sync_input"; 260 assigned-clocks = <&bpmp TEGRA234_CLK_I2S6>; 261 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 262 assigned-clock-rates = <1536000>; 263 sound-name-prefix = "I2S6"; 264 status = "disabled"; 265 }; 266 267 tegra_sfc1: sfc@2902000 { 268 compatible = "nvidia,tegra234-sfc", 269 "nvidia,tegra210-sfc"; 270 reg = <0x0 0x2902000 0x0 0x200>; 271 sound-name-prefix = "SFC1"; 272 status = "disabled"; 273 }; 274 275 tegra_sfc2: sfc@2902200 { 276 compatible = "nvidia,tegra234-sfc", 277 "nvidia,tegra210-sfc"; 278 reg = <0x0 0x2902200 0x0 0x200>; 279 sound-name-prefix = "SFC2"; 280 status = "disabled"; 281 }; 282 283 tegra_sfc3: sfc@2902400 { 284 compatible = "nvidia,tegra234-sfc", 285 "nvidia,tegra210-sfc"; 286 reg = <0x0 0x2902400 0x0 0x200>; 287 sound-name-prefix = "SFC3"; 288 status = "disabled"; 289 }; 290 291 tegra_sfc4: sfc@2902600 { 292 compatible = "nvidia,tegra234-sfc", 293 "nvidia,tegra210-sfc"; 294 reg = <0x0 0x2902600 0x0 0x200>; 295 sound-name-prefix = "SFC4"; 296 status = "disabled"; 297 }; 298 299 tegra_amx1: amx@2903000 { 300 compatible = "nvidia,tegra234-amx", 301 "nvidia,tegra194-amx"; 302 reg = <0x0 0x2903000 0x0 0x100>; 303 sound-name-prefix = "AMX1"; 304 status = "disabled"; 305 }; 306 307 tegra_amx2: amx@2903100 { 308 compatible = "nvidia,tegra234-amx", 309 "nvidia,tegra194-amx"; 310 reg = <0x0 0x2903100 0x0 0x100>; 311 sound-name-prefix = "AMX2"; 312 status = "disabled"; 313 }; 314 315 tegra_amx3: amx@2903200 { 316 compatible = "nvidia,tegra234-amx", 317 "nvidia,tegra194-amx"; 318 reg = <0x0 0x2903200 0x0 0x100>; 319 sound-name-prefix = "AMX3"; 320 status = "disabled"; 321 }; 322 323 tegra_amx4: amx@2903300 { 324 compatible = "nvidia,tegra234-amx", 325 "nvidia,tegra194-amx"; 326 reg = <0x0 0x2903300 0x0 0x100>; 327 sound-name-prefix = "AMX4"; 328 status = "disabled"; 329 }; 330 331 tegra_adx1: adx@2903800 { 332 compatible = "nvidia,tegra234-adx", 333 "nvidia,tegra210-adx"; 334 reg = <0x0 0x2903800 0x0 0x100>; 335 sound-name-prefix = "ADX1"; 336 status = "disabled"; 337 }; 338 339 tegra_adx2: adx@2903900 { 340 compatible = "nvidia,tegra234-adx", 341 "nvidia,tegra210-adx"; 342 reg = <0x0 0x2903900 0x0 0x100>; 343 sound-name-prefix = "ADX2"; 344 status = "disabled"; 345 }; 346 347 tegra_adx3: adx@2903a00 { 348 compatible = "nvidia,tegra234-adx", 349 "nvidia,tegra210-adx"; 350 reg = <0x0 0x2903a00 0x0 0x100>; 351 sound-name-prefix = "ADX3"; 352 status = "disabled"; 353 }; 354 355 tegra_adx4: adx@2903b00 { 356 compatible = "nvidia,tegra234-adx", 357 "nvidia,tegra210-adx"; 358 reg = <0x0 0x2903b00 0x0 0x100>; 359 sound-name-prefix = "ADX4"; 360 status = "disabled"; 361 }; 362 363 364 tegra_dmic1: dmic@2904000 { 365 compatible = "nvidia,tegra234-dmic", 366 "nvidia,tegra210-dmic"; 367 reg = <0x0 0x2904000 0x0 0x100>; 368 clocks = <&bpmp TEGRA234_CLK_DMIC1>; 369 clock-names = "dmic"; 370 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC1>; 371 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 372 assigned-clock-rates = <3072000>; 373 sound-name-prefix = "DMIC1"; 374 status = "disabled"; 375 }; 376 377 tegra_dmic2: dmic@2904100 { 378 compatible = "nvidia,tegra234-dmic", 379 "nvidia,tegra210-dmic"; 380 reg = <0x0 0x2904100 0x0 0x100>; 381 clocks = <&bpmp TEGRA234_CLK_DMIC2>; 382 clock-names = "dmic"; 383 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC2>; 384 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 385 assigned-clock-rates = <3072000>; 386 sound-name-prefix = "DMIC2"; 387 status = "disabled"; 388 }; 389 390 tegra_dmic3: dmic@2904200 { 391 compatible = "nvidia,tegra234-dmic", 392 "nvidia,tegra210-dmic"; 393 reg = <0x0 0x2904200 0x0 0x100>; 394 clocks = <&bpmp TEGRA234_CLK_DMIC3>; 395 clock-names = "dmic"; 396 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC3>; 397 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 398 assigned-clock-rates = <3072000>; 399 sound-name-prefix = "DMIC3"; 400 status = "disabled"; 401 }; 402 403 tegra_dmic4: dmic@2904300 { 404 compatible = "nvidia,tegra234-dmic", 405 "nvidia,tegra210-dmic"; 406 reg = <0x0 0x2904300 0x0 0x100>; 407 clocks = <&bpmp TEGRA234_CLK_DMIC4>; 408 clock-names = "dmic"; 409 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC4>; 410 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 411 assigned-clock-rates = <3072000>; 412 sound-name-prefix = "DMIC4"; 413 status = "disabled"; 414 }; 415 416 tegra_dspk1: dspk@2905000 { 417 compatible = "nvidia,tegra234-dspk", 418 "nvidia,tegra186-dspk"; 419 reg = <0x0 0x2905000 0x0 0x100>; 420 clocks = <&bpmp TEGRA234_CLK_DSPK1>; 421 clock-names = "dspk"; 422 assigned-clocks = <&bpmp TEGRA234_CLK_DSPK1>; 423 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 424 assigned-clock-rates = <12288000>; 425 sound-name-prefix = "DSPK1"; 426 status = "disabled"; 427 }; 428 429 tegra_dspk2: dspk@2905100 { 430 compatible = "nvidia,tegra234-dspk", 431 "nvidia,tegra186-dspk"; 432 reg = <0x0 0x2905100 0x0 0x100>; 433 clocks = <&bpmp TEGRA234_CLK_DSPK2>; 434 clock-names = "dspk"; 435 assigned-clocks = <&bpmp TEGRA234_CLK_DSPK2>; 436 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 437 assigned-clock-rates = <12288000>; 438 sound-name-prefix = "DSPK2"; 439 status = "disabled"; 440 }; 441 442 tegra_ope1: processing-engine@2908000 { 443 compatible = "nvidia,tegra234-ope", 444 "nvidia,tegra210-ope"; 445 reg = <0x0 0x2908000 0x0 0x100>; 446 sound-name-prefix = "OPE1"; 447 status = "disabled"; 448 449 #address-cells = <2>; 450 #size-cells = <2>; 451 ranges; 452 453 equalizer@2908100 { 454 compatible = "nvidia,tegra234-peq", 455 "nvidia,tegra210-peq"; 456 reg = <0x0 0x2908100 0x0 0x100>; 457 }; 458 459 dynamic-range-compressor@2908200 { 460 compatible = "nvidia,tegra234-mbdrc", 461 "nvidia,tegra210-mbdrc"; 462 reg = <0x0 0x2908200 0x0 0x200>; 463 }; 464 }; 465 466 tegra_mvc1: mvc@290a000 { 467 compatible = "nvidia,tegra234-mvc", 468 "nvidia,tegra210-mvc"; 469 reg = <0x0 0x290a000 0x0 0x200>; 470 sound-name-prefix = "MVC1"; 471 status = "disabled"; 472 }; 473 474 tegra_mvc2: mvc@290a200 { 475 compatible = "nvidia,tegra234-mvc", 476 "nvidia,tegra210-mvc"; 477 reg = <0x0 0x290a200 0x0 0x200>; 478 sound-name-prefix = "MVC2"; 479 status = "disabled"; 480 }; 481 482 tegra_amixer: amixer@290bb00 { 483 compatible = "nvidia,tegra234-amixer", 484 "nvidia,tegra210-amixer"; 485 reg = <0x0 0x290bb00 0x0 0x800>; 486 sound-name-prefix = "MIXER1"; 487 status = "disabled"; 488 }; 489 490 tegra_admaif: admaif@290f000 { 491 compatible = "nvidia,tegra234-admaif", 492 "nvidia,tegra186-admaif"; 493 reg = <0x0 0x0290f000 0x0 0x1000>; 494 dmas = <&adma 1>, <&adma 1>, 495 <&adma 2>, <&adma 2>, 496 <&adma 3>, <&adma 3>, 497 <&adma 4>, <&adma 4>, 498 <&adma 5>, <&adma 5>, 499 <&adma 6>, <&adma 6>, 500 <&adma 7>, <&adma 7>, 501 <&adma 8>, <&adma 8>, 502 <&adma 9>, <&adma 9>, 503 <&adma 10>, <&adma 10>, 504 <&adma 11>, <&adma 11>, 505 <&adma 12>, <&adma 12>, 506 <&adma 13>, <&adma 13>, 507 <&adma 14>, <&adma 14>, 508 <&adma 15>, <&adma 15>, 509 <&adma 16>, <&adma 16>, 510 <&adma 17>, <&adma 17>, 511 <&adma 18>, <&adma 18>, 512 <&adma 19>, <&adma 19>, 513 <&adma 20>, <&adma 20>; 514 dma-names = "rx1", "tx1", 515 "rx2", "tx2", 516 "rx3", "tx3", 517 "rx4", "tx4", 518 "rx5", "tx5", 519 "rx6", "tx6", 520 "rx7", "tx7", 521 "rx8", "tx8", 522 "rx9", "tx9", 523 "rx10", "tx10", 524 "rx11", "tx11", 525 "rx12", "tx12", 526 "rx13", "tx13", 527 "rx14", "tx14", 528 "rx15", "tx15", 529 "rx16", "tx16", 530 "rx17", "tx17", 531 "rx18", "tx18", 532 "rx19", "tx19", 533 "rx20", "tx20"; 534 interconnects = <&mc TEGRA234_MEMORY_CLIENT_APEDMAR &emc>, 535 <&mc TEGRA234_MEMORY_CLIENT_APEDMAW &emc>; 536 interconnect-names = "dma-mem", "write"; 537 iommus = <&smmu_niso0 TEGRA234_SID_APE>; 538 status = "disabled"; 539 }; 540 541 tegra_asrc: asrc@2910000 { 542 compatible = "nvidia,tegra234-asrc", 543 "nvidia,tegra186-asrc"; 544 reg = <0x0 0x2910000 0x0 0x2000>; 545 sound-name-prefix = "ASRC1"; 546 status = "disabled"; 547 }; 548 }; 549 550 adma: dma-controller@2930000 { 551 compatible = "nvidia,tegra234-adma", 552 "nvidia,tegra186-adma"; 553 reg = <0x0 0x02930000 0x0 0x20000>; 554 interrupt-parent = <&agic>; 555 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 556 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 557 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 558 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 559 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 560 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 562 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 563 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 564 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 565 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 566 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 567 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 568 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 569 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 570 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 571 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 574 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 575 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 576 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 577 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 578 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 579 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 580 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 581 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 582 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 583 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 584 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 587 #dma-cells = <1>; 588 clocks = <&bpmp TEGRA234_CLK_AHUB>; 589 clock-names = "d_audio"; 590 status = "disabled"; 591 }; 592 593 agic: interrupt-controller@2a40000 { 594 compatible = "nvidia,tegra234-agic", 595 "nvidia,tegra210-agic"; 596 #interrupt-cells = <3>; 597 interrupt-controller; 598 reg = <0x0 0x02a41000 0x0 0x1000>, 599 <0x0 0x02a42000 0x0 0x2000>; 600 interrupts = <GIC_SPI 145 601 (GIC_CPU_MASK_SIMPLE(4) | 602 IRQ_TYPE_LEVEL_HIGH)>; 603 clocks = <&bpmp TEGRA234_CLK_APE>; 604 clock-names = "clk"; 605 status = "disabled"; 606 }; 607 }; 608 609 mc: memory-controller@2c00000 { 610 compatible = "nvidia,tegra234-mc"; 611 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ 612 <0x0 0x02c10000 0x0 0x10000>, /* MC Broadcast*/ 613 <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ 614 <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ 615 <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ 616 <0x0 0x02c50000 0x0 0x10000>, /* MC3 */ 617 <0x0 0x02b80000 0x0 0x10000>, /* MC4 */ 618 <0x0 0x02b90000 0x0 0x10000>, /* MC5 */ 619 <0x0 0x02ba0000 0x0 0x10000>, /* MC6 */ 620 <0x0 0x02bb0000 0x0 0x10000>, /* MC7 */ 621 <0x0 0x01700000 0x0 0x10000>, /* MC8 */ 622 <0x0 0x01710000 0x0 0x10000>, /* MC9 */ 623 <0x0 0x01720000 0x0 0x10000>, /* MC10 */ 624 <0x0 0x01730000 0x0 0x10000>, /* MC11 */ 625 <0x0 0x01740000 0x0 0x10000>, /* MC12 */ 626 <0x0 0x01750000 0x0 0x10000>, /* MC13 */ 627 <0x0 0x01760000 0x0 0x10000>, /* MC14 */ 628 <0x0 0x01770000 0x0 0x10000>; /* MC15 */ 629 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", 630 "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", 631 "ch11", "ch12", "ch13", "ch14", "ch15"; 632 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 633 #interconnect-cells = <1>; 634 status = "okay"; 635 636 #address-cells = <2>; 637 #size-cells = <2>; 638 ranges = <0x0 0x01700000 0x0 0x01700000 0x0 0x100000>, 639 <0x0 0x02b80000 0x0 0x02b80000 0x0 0x040000>, 640 <0x0 0x02c00000 0x0 0x02c00000 0x0 0x100000>; 641 642 /* 643 * Bit 39 of addresses passing through the memory 644 * controller selects the XBAR format used when memory 645 * is accessed. This is used to transparently access 646 * memory in the XBAR format used by the discrete GPU 647 * (bit 39 set) or Tegra (bit 39 clear). 648 * 649 * As a consequence, the operating system must ensure 650 * that bit 39 is never used implicitly, for example 651 * via an I/O virtual address mapping of an IOMMU. If 652 * devices require access to the XBAR switch, their 653 * drivers must set this bit explicitly. 654 * 655 * Limit the DMA range for memory clients to [38:0]. 656 */ 657 dma-ranges = <0x0 0x0 0x0 0x0 0x80 0x0>; 658 659 emc: external-memory-controller@2c60000 { 660 compatible = "nvidia,tegra234-emc"; 661 reg = <0x0 0x02c60000 0x0 0x90000>, 662 <0x0 0x01780000 0x0 0x80000>; 663 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 664 clocks = <&bpmp TEGRA234_CLK_EMC>; 665 clock-names = "emc"; 666 status = "okay"; 667 668 #interconnect-cells = <0>; 669 670 nvidia,bpmp = <&bpmp>; 671 }; 672 }; 673 674 uarta: serial@3100000 { 675 compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart"; 676 reg = <0x0 0x03100000 0x0 0x10000>; 677 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 678 clocks = <&bpmp TEGRA234_CLK_UARTA>; 679 clock-names = "serial"; 680 resets = <&bpmp TEGRA234_RESET_UARTA>; 681 reset-names = "serial"; 682 status = "disabled"; 683 }; 684 685 gen1_i2c: i2c@3160000 { 686 compatible = "nvidia,tegra194-i2c"; 687 reg = <0x0 0x3160000 0x0 0x100>; 688 status = "disabled"; 689 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 690 #address-cells = <1>; 691 #size-cells = <0>; 692 clock-frequency = <400000>; 693 clocks = <&bpmp TEGRA234_CLK_I2C1 694 &bpmp TEGRA234_CLK_PLLP_OUT0>; 695 assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>; 696 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 697 clock-names = "div-clk", "parent"; 698 resets = <&bpmp TEGRA234_RESET_I2C1>; 699 reset-names = "i2c"; 700 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 701 dma-coherent; 702 dmas = <&gpcdma 21>, <&gpcdma 21>; 703 dma-names = "rx", "tx"; 704 }; 705 706 cam_i2c: i2c@3180000 { 707 compatible = "nvidia,tegra194-i2c"; 708 reg = <0x0 0x3180000 0x0 0x100>; 709 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 710 #address-cells = <1>; 711 #size-cells = <0>; 712 status = "disabled"; 713 clock-frequency = <400000>; 714 clocks = <&bpmp TEGRA234_CLK_I2C3 715 &bpmp TEGRA234_CLK_PLLP_OUT0>; 716 assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>; 717 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 718 clock-names = "div-clk", "parent"; 719 resets = <&bpmp TEGRA234_RESET_I2C3>; 720 reset-names = "i2c"; 721 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 722 dma-coherent; 723 dmas = <&gpcdma 23>, <&gpcdma 23>; 724 dma-names = "rx", "tx"; 725 }; 726 727 dp_aux_ch1_i2c: i2c@3190000 { 728 compatible = "nvidia,tegra194-i2c"; 729 reg = <0x0 0x3190000 0x0 0x100>; 730 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 731 #address-cells = <1>; 732 #size-cells = <0>; 733 status = "disabled"; 734 clock-frequency = <100000>; 735 clocks = <&bpmp TEGRA234_CLK_I2C4 736 &bpmp TEGRA234_CLK_PLLP_OUT0>; 737 assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>; 738 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 739 clock-names = "div-clk", "parent"; 740 resets = <&bpmp TEGRA234_RESET_I2C4>; 741 reset-names = "i2c"; 742 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 743 dma-coherent; 744 dmas = <&gpcdma 26>, <&gpcdma 26>; 745 dma-names = "rx", "tx"; 746 }; 747 748 dp_aux_ch0_i2c: i2c@31b0000 { 749 compatible = "nvidia,tegra194-i2c"; 750 reg = <0x0 0x31b0000 0x0 0x100>; 751 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 752 #address-cells = <1>; 753 #size-cells = <0>; 754 status = "disabled"; 755 clock-frequency = <100000>; 756 clocks = <&bpmp TEGRA234_CLK_I2C6 757 &bpmp TEGRA234_CLK_PLLP_OUT0>; 758 assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>; 759 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 760 clock-names = "div-clk", "parent"; 761 resets = <&bpmp TEGRA234_RESET_I2C6>; 762 reset-names = "i2c"; 763 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 764 dma-coherent; 765 dmas = <&gpcdma 30>, <&gpcdma 30>; 766 dma-names = "rx", "tx"; 767 }; 768 769 dp_aux_ch2_i2c: i2c@31c0000 { 770 compatible = "nvidia,tegra194-i2c"; 771 reg = <0x0 0x31c0000 0x0 0x100>; 772 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 773 #address-cells = <1>; 774 #size-cells = <0>; 775 status = "disabled"; 776 clock-frequency = <100000>; 777 clocks = <&bpmp TEGRA234_CLK_I2C7 778 &bpmp TEGRA234_CLK_PLLP_OUT0>; 779 assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>; 780 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 781 clock-names = "div-clk", "parent"; 782 resets = <&bpmp TEGRA234_RESET_I2C7>; 783 reset-names = "i2c"; 784 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 785 dma-coherent; 786 dmas = <&gpcdma 27>, <&gpcdma 27>; 787 dma-names = "rx", "tx"; 788 }; 789 790 uarti: serial@31d0000 { 791 compatible = "arm,sbsa-uart"; 792 reg = <0x0 0x31d0000 0x0 0x10000>; 793 interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; 794 status = "disabled"; 795 }; 796 797 dp_aux_ch3_i2c: i2c@31e0000 { 798 compatible = "nvidia,tegra194-i2c"; 799 reg = <0x0 0x31e0000 0x0 0x100>; 800 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 801 #address-cells = <1>; 802 #size-cells = <0>; 803 status = "disabled"; 804 clock-frequency = <100000>; 805 clocks = <&bpmp TEGRA234_CLK_I2C9 806 &bpmp TEGRA234_CLK_PLLP_OUT0>; 807 assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>; 808 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 809 clock-names = "div-clk", "parent"; 810 resets = <&bpmp TEGRA234_RESET_I2C9>; 811 reset-names = "i2c"; 812 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 813 dma-coherent; 814 dmas = <&gpcdma 31>, <&gpcdma 31>; 815 dma-names = "rx", "tx"; 816 }; 817 818 spi@3270000 { 819 compatible = "nvidia,tegra234-qspi"; 820 reg = <0x0 0x3270000 0x0 0x1000>; 821 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 822 #address-cells = <1>; 823 #size-cells = <0>; 824 clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>, 825 <&bpmp TEGRA234_CLK_QSPI0_PM>; 826 clock-names = "qspi", "qspi_out"; 827 resets = <&bpmp TEGRA234_RESET_QSPI0>; 828 status = "disabled"; 829 }; 830 831 pwm1: pwm@3280000 { 832 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 833 reg = <0x0 0x3280000 0x0 0x10000>; 834 clocks = <&bpmp TEGRA234_CLK_PWM1>; 835 resets = <&bpmp TEGRA234_RESET_PWM1>; 836 reset-names = "pwm"; 837 status = "disabled"; 838 #pwm-cells = <2>; 839 }; 840 841 pwm2: pwm@3290000 { 842 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 843 reg = <0x0 0x3290000 0x0 0x10000>; 844 clocks = <&bpmp TEGRA234_CLK_PWM2>; 845 resets = <&bpmp TEGRA234_RESET_PWM2>; 846 reset-names = "pwm"; 847 status = "disabled"; 848 #pwm-cells = <2>; 849 }; 850 851 pwm3: pwm@32a0000 { 852 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 853 reg = <0x0 0x32a0000 0x0 0x10000>; 854 clocks = <&bpmp TEGRA234_CLK_PWM3>; 855 resets = <&bpmp TEGRA234_RESET_PWM3>; 856 reset-names = "pwm"; 857 status = "disabled"; 858 #pwm-cells = <2>; 859 }; 860 861 pwm5: pwm@32c0000 { 862 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 863 reg = <0x0 0x32c0000 0x0 0x10000>; 864 clocks = <&bpmp TEGRA234_CLK_PWM5>; 865 resets = <&bpmp TEGRA234_RESET_PWM5>; 866 reset-names = "pwm"; 867 status = "disabled"; 868 #pwm-cells = <2>; 869 }; 870 871 pwm6: pwm@32d0000 { 872 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 873 reg = <0x0 0x32d0000 0x0 0x10000>; 874 clocks = <&bpmp TEGRA234_CLK_PWM6>; 875 resets = <&bpmp TEGRA234_RESET_PWM6>; 876 reset-names = "pwm"; 877 status = "disabled"; 878 #pwm-cells = <2>; 879 }; 880 881 pwm7: pwm@32e0000 { 882 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 883 reg = <0x0 0x32e0000 0x0 0x10000>; 884 clocks = <&bpmp TEGRA234_CLK_PWM7>; 885 resets = <&bpmp TEGRA234_RESET_PWM7>; 886 reset-names = "pwm"; 887 status = "disabled"; 888 #pwm-cells = <2>; 889 }; 890 891 pwm8: pwm@32f0000 { 892 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 893 reg = <0x0 0x32f0000 0x0 0x10000>; 894 clocks = <&bpmp TEGRA234_CLK_PWM8>; 895 resets = <&bpmp TEGRA234_RESET_PWM8>; 896 reset-names = "pwm"; 897 status = "disabled"; 898 #pwm-cells = <2>; 899 }; 900 901 spi@3300000 { 902 compatible = "nvidia,tegra234-qspi"; 903 reg = <0x0 0x3300000 0x0 0x1000>; 904 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 905 #address-cells = <1>; 906 #size-cells = <0>; 907 clocks = <&bpmp TEGRA234_CLK_QSPI1_2X_PM>, 908 <&bpmp TEGRA234_CLK_QSPI1_PM>; 909 clock-names = "qspi", "qspi_out"; 910 resets = <&bpmp TEGRA234_RESET_QSPI1>; 911 status = "disabled"; 912 }; 913 914 mmc@3400000 { 915 compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; 916 reg = <0x0 0x03400000 0x0 0x20000>; 917 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 918 clocks = <&bpmp TEGRA234_CLK_SDMMC1>, 919 <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; 920 clock-names = "sdhci", "tmclk"; 921 assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC1>, 922 <&bpmp TEGRA234_CLK_PLLC4_MUXED>; 923 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4_MUXED>, 924 <&bpmp TEGRA234_CLK_PLLC4_VCO_DIV2>; 925 resets = <&bpmp TEGRA234_RESET_SDMMC1>; 926 reset-names = "sdhci"; 927 interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRA &emc>, 928 <&mc TEGRA234_MEMORY_CLIENT_SDMMCWA &emc>; 929 interconnect-names = "dma-mem", "write"; 930 iommus = <&smmu_niso1 TEGRA234_SID_SDMMC1A>; 931 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 932 pinctrl-0 = <&sdmmc1_3v3>; 933 pinctrl-1 = <&sdmmc1_1v8>; 934 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 935 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x07>; 936 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 937 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 938 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 939 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 940 nvidia,default-tap = <14>; 941 nvidia,default-trim = <0x8>; 942 sd-uhs-sdr25; 943 sd-uhs-sdr50; 944 sd-uhs-ddr50; 945 sd-uhs-sdr104; 946 status = "disabled"; 947 }; 948 949 mmc@3460000 { 950 compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; 951 reg = <0x0 0x03460000 0x0 0x20000>; 952 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 953 clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 954 <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; 955 clock-names = "sdhci", "tmclk"; 956 assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 957 <&bpmp TEGRA234_CLK_PLLC4>; 958 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>; 959 resets = <&bpmp TEGRA234_RESET_SDMMC4>; 960 reset-names = "sdhci"; 961 interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRAB &emc>, 962 <&mc TEGRA234_MEMORY_CLIENT_SDMMCWAB &emc>; 963 interconnect-names = "dma-mem", "write"; 964 iommus = <&smmu_niso1 TEGRA234_SID_SDMMC4>; 965 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 966 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 967 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 968 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 969 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 970 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 971 nvidia,default-tap = <0x8>; 972 nvidia,default-trim = <0x14>; 973 nvidia,dqs-trim = <40>; 974 supports-cqe; 975 status = "disabled"; 976 }; 977 978 hda@3510000 { 979 compatible = "nvidia,tegra234-hda"; 980 reg = <0x0 0x3510000 0x0 0x10000>; 981 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 982 clocks = <&bpmp TEGRA234_CLK_AZA_BIT>, 983 <&bpmp TEGRA234_CLK_AZA_2XBIT>; 984 clock-names = "hda", "hda2codec_2x"; 985 resets = <&bpmp TEGRA234_RESET_HDA>, 986 <&bpmp TEGRA234_RESET_HDACODEC>; 987 reset-names = "hda", "hda2codec_2x"; 988 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DISP>; 989 interconnects = <&mc TEGRA234_MEMORY_CLIENT_HDAR &emc>, 990 <&mc TEGRA234_MEMORY_CLIENT_HDAW &emc>; 991 interconnect-names = "dma-mem", "write"; 992 iommus = <&smmu_niso0 TEGRA234_SID_HDA>; 993 status = "disabled"; 994 }; 995 996 xusb_padctl: padctl@3520000 { 997 compatible = "nvidia,tegra234-xusb-padctl"; 998 reg = <0x0 0x03520000 0x0 0x20000>, 999 <0x0 0x03540000 0x0 0x10000>; 1000 reg-names = "padctl", "ao"; 1001 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1002 1003 resets = <&bpmp TEGRA234_RESET_XUSB_PADCTL>; 1004 reset-names = "padctl"; 1005 1006 status = "disabled"; 1007 1008 pads { 1009 usb2 { 1010 clocks = <&bpmp TEGRA234_CLK_USB2_TRK>; 1011 clock-names = "trk"; 1012 1013 lanes { 1014 usb2-0 { 1015 nvidia,function = "xusb"; 1016 status = "disabled"; 1017 #phy-cells = <0>; 1018 }; 1019 1020 usb2-1 { 1021 nvidia,function = "xusb"; 1022 status = "disabled"; 1023 #phy-cells = <0>; 1024 }; 1025 1026 usb2-2 { 1027 nvidia,function = "xusb"; 1028 status = "disabled"; 1029 #phy-cells = <0>; 1030 }; 1031 1032 usb2-3 { 1033 nvidia,function = "xusb"; 1034 status = "disabled"; 1035 #phy-cells = <0>; 1036 }; 1037 }; 1038 }; 1039 1040 usb3 { 1041 lanes { 1042 usb3-0 { 1043 nvidia,function = "xusb"; 1044 status = "disabled"; 1045 #phy-cells = <0>; 1046 }; 1047 1048 usb3-1 { 1049 nvidia,function = "xusb"; 1050 status = "disabled"; 1051 #phy-cells = <0>; 1052 }; 1053 1054 usb3-2 { 1055 nvidia,function = "xusb"; 1056 status = "disabled"; 1057 #phy-cells = <0>; 1058 }; 1059 1060 usb3-3 { 1061 nvidia,function = "xusb"; 1062 status = "disabled"; 1063 #phy-cells = <0>; 1064 }; 1065 }; 1066 }; 1067 }; 1068 1069 ports { 1070 usb2-0 { 1071 status = "disabled"; 1072 }; 1073 1074 usb2-1 { 1075 status = "disabled"; 1076 }; 1077 1078 usb2-2 { 1079 status = "disabled"; 1080 }; 1081 1082 usb2-3 { 1083 status = "disabled"; 1084 }; 1085 1086 usb3-0 { 1087 status = "disabled"; 1088 }; 1089 1090 usb3-1 { 1091 status = "disabled"; 1092 }; 1093 1094 usb3-2 { 1095 status = "disabled"; 1096 }; 1097 1098 usb3-3 { 1099 status = "disabled"; 1100 }; 1101 }; 1102 }; 1103 1104 usb@3610000 { 1105 compatible = "nvidia,tegra234-xusb"; 1106 reg = <0x0 0x03610000 0x0 0x40000>, 1107 <0x0 0x03600000 0x0 0x10000>, 1108 <0x0 0x03650000 0x0 0x10000>; 1109 reg-names = "hcd", "fpci", "bar2"; 1110 1111 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1112 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1113 1114 clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_HOST>, 1115 <&bpmp TEGRA234_CLK_XUSB_FALCON>, 1116 <&bpmp TEGRA234_CLK_XUSB_CORE_SS>, 1117 <&bpmp TEGRA234_CLK_XUSB_SS>, 1118 <&bpmp TEGRA234_CLK_CLK_M>, 1119 <&bpmp TEGRA234_CLK_XUSB_FS>, 1120 <&bpmp TEGRA234_CLK_UTMIP_PLL>, 1121 <&bpmp TEGRA234_CLK_CLK_M>, 1122 <&bpmp TEGRA234_CLK_PLLE>; 1123 clock-names = "xusb_host", "xusb_falcon_src", 1124 "xusb_ss", "xusb_ss_src", "xusb_hs_src", 1125 "xusb_fs_src", "pll_u_480m", "clk_m", 1126 "pll_e"; 1127 interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1128 <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1129 interconnect-names = "dma-mem", "write"; 1130 iommus = <&smmu_niso1 TEGRA234_SID_XUSB_HOST>; 1131 1132 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBC>, 1133 <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>; 1134 power-domain-names = "xusb_host", "xusb_ss"; 1135 1136 nvidia,xusb-padctl = <&xusb_padctl>; 1137 dma-coherent; 1138 status = "disabled"; 1139 }; 1140 1141 fuse@3810000 { 1142 compatible = "nvidia,tegra234-efuse"; 1143 reg = <0x0 0x03810000 0x0 0x10000>; 1144 clocks = <&bpmp TEGRA234_CLK_FUSE>; 1145 clock-names = "fuse"; 1146 }; 1147 1148 hsp_top0: hsp@3c00000 { 1149 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 1150 reg = <0x0 0x03c00000 0x0 0xa0000>; 1151 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1152 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1153 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1154 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1155 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1156 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1157 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1158 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1159 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1160 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 1161 "shared3", "shared4", "shared5", "shared6", 1162 "shared7"; 1163 #mbox-cells = <2>; 1164 }; 1165 1166 p2u_hsio_0: phy@3e00000 { 1167 compatible = "nvidia,tegra234-p2u"; 1168 reg = <0x0 0x03e00000 0x0 0x10000>; 1169 reg-names = "ctl"; 1170 1171 #phy-cells = <0>; 1172 }; 1173 1174 p2u_hsio_1: phy@3e10000 { 1175 compatible = "nvidia,tegra234-p2u"; 1176 reg = <0x0 0x03e10000 0x0 0x10000>; 1177 reg-names = "ctl"; 1178 1179 #phy-cells = <0>; 1180 }; 1181 1182 p2u_hsio_2: phy@3e20000 { 1183 compatible = "nvidia,tegra234-p2u"; 1184 reg = <0x0 0x03e20000 0x0 0x10000>; 1185 reg-names = "ctl"; 1186 1187 #phy-cells = <0>; 1188 }; 1189 1190 p2u_hsio_3: phy@3e30000 { 1191 compatible = "nvidia,tegra234-p2u"; 1192 reg = <0x0 0x03e30000 0x0 0x10000>; 1193 reg-names = "ctl"; 1194 1195 #phy-cells = <0>; 1196 }; 1197 1198 p2u_hsio_4: phy@3e40000 { 1199 compatible = "nvidia,tegra234-p2u"; 1200 reg = <0x0 0x03e40000 0x0 0x10000>; 1201 reg-names = "ctl"; 1202 1203 #phy-cells = <0>; 1204 }; 1205 1206 p2u_hsio_5: phy@3e50000 { 1207 compatible = "nvidia,tegra234-p2u"; 1208 reg = <0x0 0x03e50000 0x0 0x10000>; 1209 reg-names = "ctl"; 1210 1211 #phy-cells = <0>; 1212 }; 1213 1214 p2u_hsio_6: phy@3e60000 { 1215 compatible = "nvidia,tegra234-p2u"; 1216 reg = <0x0 0x03e60000 0x0 0x10000>; 1217 reg-names = "ctl"; 1218 1219 #phy-cells = <0>; 1220 }; 1221 1222 p2u_hsio_7: phy@3e70000 { 1223 compatible = "nvidia,tegra234-p2u"; 1224 reg = <0x0 0x03e70000 0x0 0x10000>; 1225 reg-names = "ctl"; 1226 1227 #phy-cells = <0>; 1228 }; 1229 1230 p2u_nvhs_0: phy@3e90000 { 1231 compatible = "nvidia,tegra234-p2u"; 1232 reg = <0x0 0x03e90000 0x0 0x10000>; 1233 reg-names = "ctl"; 1234 1235 #phy-cells = <0>; 1236 }; 1237 1238 p2u_nvhs_1: phy@3ea0000 { 1239 compatible = "nvidia,tegra234-p2u"; 1240 reg = <0x0 0x03ea0000 0x0 0x10000>; 1241 reg-names = "ctl"; 1242 1243 #phy-cells = <0>; 1244 }; 1245 1246 p2u_nvhs_2: phy@3eb0000 { 1247 compatible = "nvidia,tegra234-p2u"; 1248 reg = <0x0 0x03eb0000 0x0 0x10000>; 1249 reg-names = "ctl"; 1250 1251 #phy-cells = <0>; 1252 }; 1253 1254 p2u_nvhs_3: phy@3ec0000 { 1255 compatible = "nvidia,tegra234-p2u"; 1256 reg = <0x0 0x03ec0000 0x0 0x10000>; 1257 reg-names = "ctl"; 1258 1259 #phy-cells = <0>; 1260 }; 1261 1262 p2u_nvhs_4: phy@3ed0000 { 1263 compatible = "nvidia,tegra234-p2u"; 1264 reg = <0x0 0x03ed0000 0x0 0x10000>; 1265 reg-names = "ctl"; 1266 1267 #phy-cells = <0>; 1268 }; 1269 1270 p2u_nvhs_5: phy@3ee0000 { 1271 compatible = "nvidia,tegra234-p2u"; 1272 reg = <0x0 0x03ee0000 0x0 0x10000>; 1273 reg-names = "ctl"; 1274 1275 #phy-cells = <0>; 1276 }; 1277 1278 p2u_nvhs_6: phy@3ef0000 { 1279 compatible = "nvidia,tegra234-p2u"; 1280 reg = <0x0 0x03ef0000 0x0 0x10000>; 1281 reg-names = "ctl"; 1282 1283 #phy-cells = <0>; 1284 }; 1285 1286 p2u_nvhs_7: phy@3f00000 { 1287 compatible = "nvidia,tegra234-p2u"; 1288 reg = <0x0 0x03f00000 0x0 0x10000>; 1289 reg-names = "ctl"; 1290 1291 #phy-cells = <0>; 1292 }; 1293 1294 p2u_gbe_0: phy@3f20000 { 1295 compatible = "nvidia,tegra234-p2u"; 1296 reg = <0x0 0x03f20000 0x0 0x10000>; 1297 reg-names = "ctl"; 1298 1299 #phy-cells = <0>; 1300 }; 1301 1302 p2u_gbe_1: phy@3f30000 { 1303 compatible = "nvidia,tegra234-p2u"; 1304 reg = <0x0 0x03f30000 0x0 0x10000>; 1305 reg-names = "ctl"; 1306 1307 #phy-cells = <0>; 1308 }; 1309 1310 p2u_gbe_2: phy@3f40000 { 1311 compatible = "nvidia,tegra234-p2u"; 1312 reg = <0x0 0x03f40000 0x0 0x10000>; 1313 reg-names = "ctl"; 1314 1315 #phy-cells = <0>; 1316 }; 1317 1318 p2u_gbe_3: phy@3f50000 { 1319 compatible = "nvidia,tegra234-p2u"; 1320 reg = <0x0 0x03f50000 0x0 0x10000>; 1321 reg-names = "ctl"; 1322 1323 #phy-cells = <0>; 1324 }; 1325 1326 p2u_gbe_4: phy@3f60000 { 1327 compatible = "nvidia,tegra234-p2u"; 1328 reg = <0x0 0x03f60000 0x0 0x10000>; 1329 reg-names = "ctl"; 1330 1331 #phy-cells = <0>; 1332 }; 1333 1334 p2u_gbe_5: phy@3f70000 { 1335 compatible = "nvidia,tegra234-p2u"; 1336 reg = <0x0 0x03f70000 0x0 0x10000>; 1337 reg-names = "ctl"; 1338 1339 #phy-cells = <0>; 1340 }; 1341 1342 p2u_gbe_6: phy@3f80000 { 1343 compatible = "nvidia,tegra234-p2u"; 1344 reg = <0x0 0x03f80000 0x0 0x10000>; 1345 reg-names = "ctl"; 1346 1347 #phy-cells = <0>; 1348 }; 1349 1350 p2u_gbe_7: phy@3f90000 { 1351 compatible = "nvidia,tegra234-p2u"; 1352 reg = <0x0 0x03f90000 0x0 0x10000>; 1353 reg-names = "ctl"; 1354 1355 #phy-cells = <0>; 1356 }; 1357 1358 ethernet@6800000 { 1359 compatible = "nvidia,tegra234-mgbe"; 1360 reg = <0x0 0x06800000 0x0 0x10000>, 1361 <0x0 0x06810000 0x0 0x10000>, 1362 <0x0 0x068a0000 0x0 0x10000>; 1363 reg-names = "hypervisor", "mac", "xpcs"; 1364 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; 1365 interrupt-names = "common"; 1366 clocks = <&bpmp TEGRA234_CLK_MGBE0_APP>, 1367 <&bpmp TEGRA234_CLK_MGBE0_MAC>, 1368 <&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>, 1369 <&bpmp TEGRA234_CLK_MGBE0_PTP_REF>, 1370 <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>, 1371 <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>, 1372 <&bpmp TEGRA234_CLK_MGBE0_TX>, 1373 <&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>, 1374 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>, 1375 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>, 1376 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS>, 1377 <&bpmp TEGRA234_CLK_MGBE0_TX_PCS>; 1378 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1379 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1380 "rx-pcs", "tx-pcs"; 1381 resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>, 1382 <&bpmp TEGRA234_RESET_MGBE0_PCS>; 1383 reset-names = "mac", "pcs"; 1384 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEARD &emc>, 1385 <&mc TEGRA234_MEMORY_CLIENT_MGBEAWR &emc>; 1386 interconnect-names = "dma-mem", "write"; 1387 iommus = <&smmu_niso0 TEGRA234_SID_MGBE>; 1388 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEA>; 1389 status = "disabled"; 1390 }; 1391 1392 ethernet@6900000 { 1393 compatible = "nvidia,tegra234-mgbe"; 1394 reg = <0x0 0x06900000 0x0 0x10000>, 1395 <0x0 0x06910000 0x0 0x10000>, 1396 <0x0 0x069a0000 0x0 0x10000>; 1397 reg-names = "hypervisor", "mac", "xpcs"; 1398 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>; 1399 interrupt-names = "common"; 1400 clocks = <&bpmp TEGRA234_CLK_MGBE1_APP>, 1401 <&bpmp TEGRA234_CLK_MGBE1_MAC>, 1402 <&bpmp TEGRA234_CLK_MGBE1_MAC_DIVIDER>, 1403 <&bpmp TEGRA234_CLK_MGBE1_PTP_REF>, 1404 <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT_M>, 1405 <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT>, 1406 <&bpmp TEGRA234_CLK_MGBE1_TX>, 1407 <&bpmp TEGRA234_CLK_MGBE1_EEE_PCS>, 1408 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_INPUT>, 1409 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_M>, 1410 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS>, 1411 <&bpmp TEGRA234_CLK_MGBE1_TX_PCS>; 1412 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1413 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1414 "rx-pcs", "tx-pcs"; 1415 resets = <&bpmp TEGRA234_RESET_MGBE1_MAC>, 1416 <&bpmp TEGRA234_RESET_MGBE1_PCS>; 1417 reset-names = "mac", "pcs"; 1418 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEBRD &emc>, 1419 <&mc TEGRA234_MEMORY_CLIENT_MGBEBWR &emc>; 1420 interconnect-names = "dma-mem", "write"; 1421 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF1>; 1422 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEB>; 1423 status = "disabled"; 1424 }; 1425 1426 ethernet@6a00000 { 1427 compatible = "nvidia,tegra234-mgbe"; 1428 reg = <0x0 0x06a00000 0x0 0x10000>, 1429 <0x0 0x06a10000 0x0 0x10000>, 1430 <0x0 0x06aa0000 0x0 0x10000>; 1431 reg-names = "hypervisor", "mac", "xpcs"; 1432 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>; 1433 interrupt-names = "common"; 1434 clocks = <&bpmp TEGRA234_CLK_MGBE2_APP>, 1435 <&bpmp TEGRA234_CLK_MGBE2_MAC>, 1436 <&bpmp TEGRA234_CLK_MGBE2_MAC_DIVIDER>, 1437 <&bpmp TEGRA234_CLK_MGBE2_PTP_REF>, 1438 <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT_M>, 1439 <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT>, 1440 <&bpmp TEGRA234_CLK_MGBE2_TX>, 1441 <&bpmp TEGRA234_CLK_MGBE2_EEE_PCS>, 1442 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_INPUT>, 1443 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_M>, 1444 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS>, 1445 <&bpmp TEGRA234_CLK_MGBE2_TX_PCS>; 1446 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1447 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1448 "rx-pcs", "tx-pcs"; 1449 resets = <&bpmp TEGRA234_RESET_MGBE2_MAC>, 1450 <&bpmp TEGRA234_RESET_MGBE2_PCS>; 1451 reset-names = "mac", "pcs"; 1452 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBECRD &emc>, 1453 <&mc TEGRA234_MEMORY_CLIENT_MGBECWR &emc>; 1454 interconnect-names = "dma-mem", "write"; 1455 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF2>; 1456 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEC>; 1457 status = "disabled"; 1458 }; 1459 1460 ethernet@6b00000 { 1461 compatible = "nvidia,tegra234-mgbe"; 1462 reg = <0x0 0x06b00000 0x0 0x10000>, 1463 <0x0 0x06b10000 0x0 0x10000>, 1464 <0x0 0x06ba0000 0x0 0x10000>; 1465 reg-names = "hypervisor", "mac", "xpcs"; 1466 interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 1467 interrupt-names = "common"; 1468 clocks = <&bpmp TEGRA234_CLK_MGBE3_APP>, 1469 <&bpmp TEGRA234_CLK_MGBE3_MAC>, 1470 <&bpmp TEGRA234_CLK_MGBE3_MAC_DIVIDER>, 1471 <&bpmp TEGRA234_CLK_MGBE3_PTP_REF>, 1472 <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT_M>, 1473 <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT>, 1474 <&bpmp TEGRA234_CLK_MGBE3_TX>, 1475 <&bpmp TEGRA234_CLK_MGBE3_EEE_PCS>, 1476 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_INPUT>, 1477 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_M>, 1478 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS>, 1479 <&bpmp TEGRA234_CLK_MGBE3_TX_PCS>; 1480 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1481 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1482 "rx-pcs", "tx-pcs"; 1483 resets = <&bpmp TEGRA234_RESET_MGBE3_MAC>, 1484 <&bpmp TEGRA234_RESET_MGBE3_PCS>; 1485 reset-names = "mac", "pcs"; 1486 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEDRD &emc>, 1487 <&mc TEGRA234_MEMORY_CLIENT_MGBEDWR &emc>; 1488 interconnect-names = "dma-mem", "write"; 1489 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF3>; 1490 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBED>; 1491 status = "disabled"; 1492 }; 1493 1494 smmu_niso1: iommu@8000000 { 1495 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 1496 reg = <0x0 0x8000000 0x0 0x1000000>, 1497 <0x0 0x7000000 0x0 0x1000000>; 1498 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1499 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 1500 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1501 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 1502 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1503 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1504 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1505 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1506 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1507 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1508 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1509 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1510 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1511 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1512 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1513 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1514 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1515 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1516 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1517 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1518 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1519 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1520 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1521 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1522 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1523 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1524 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1525 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1526 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1527 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1528 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1529 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1530 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1531 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1532 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1533 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1534 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1535 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1536 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1537 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1538 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1539 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1540 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1541 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1542 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1543 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1544 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1545 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1546 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1547 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1548 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1549 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1550 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1551 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1552 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1553 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1554 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1555 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1556 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1557 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1558 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1559 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1560 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1561 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1562 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1563 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1564 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1565 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1566 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1567 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1568 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1569 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1570 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1571 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1572 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1573 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1574 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1575 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1576 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1577 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1578 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1579 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1580 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1581 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1582 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1583 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1584 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1585 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1586 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1587 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1588 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1589 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1590 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1591 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1592 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1593 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1594 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1595 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1596 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1597 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1598 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1599 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1600 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1601 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1602 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1603 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1604 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1605 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1606 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1607 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1608 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1609 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1610 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1611 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1612 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1613 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1614 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1615 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1616 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1617 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1618 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1619 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1620 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1621 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1622 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1623 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1624 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1625 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1626 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1627 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1628 stream-match-mask = <0x7f80>; 1629 #global-interrupts = <2>; 1630 #iommu-cells = <1>; 1631 1632 nvidia,memory-controller = <&mc>; 1633 status = "okay"; 1634 }; 1635 1636 sce-fabric@b600000 { 1637 compatible = "nvidia,tegra234-sce-fabric"; 1638 reg = <0x0 0xb600000 0x0 0x40000>; 1639 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 1640 status = "okay"; 1641 }; 1642 1643 rce-fabric@be00000 { 1644 compatible = "nvidia,tegra234-rce-fabric"; 1645 reg = <0x0 0xbe00000 0x0 0x40000>; 1646 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1647 status = "okay"; 1648 }; 1649 1650 hsp_aon: hsp@c150000 { 1651 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 1652 reg = <0x0 0x0c150000 0x0 0x90000>; 1653 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1654 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1655 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1656 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1657 /* 1658 * Shared interrupt 0 is routed only to AON/SPE, so 1659 * we only have 4 shared interrupts for the CCPLEX. 1660 */ 1661 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 1662 #mbox-cells = <2>; 1663 }; 1664 1665 gen2_i2c: i2c@c240000 { 1666 compatible = "nvidia,tegra194-i2c"; 1667 reg = <0x0 0xc240000 0x0 0x100>; 1668 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1669 #address-cells = <1>; 1670 #size-cells = <0>; 1671 status = "disabled"; 1672 clock-frequency = <100000>; 1673 clocks = <&bpmp TEGRA234_CLK_I2C2 1674 &bpmp TEGRA234_CLK_PLLP_OUT0>; 1675 clock-names = "div-clk", "parent"; 1676 assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>; 1677 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 1678 resets = <&bpmp TEGRA234_RESET_I2C2>; 1679 reset-names = "i2c"; 1680 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 1681 dma-coherent; 1682 dmas = <&gpcdma 22>, <&gpcdma 22>; 1683 dma-names = "rx", "tx"; 1684 }; 1685 1686 gen8_i2c: i2c@c250000 { 1687 compatible = "nvidia,tegra194-i2c"; 1688 reg = <0x0 0xc250000 0x0 0x100>; 1689 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1690 #address-cells = <1>; 1691 #size-cells = <0>; 1692 status = "disabled"; 1693 clock-frequency = <400000>; 1694 clocks = <&bpmp TEGRA234_CLK_I2C8 1695 &bpmp TEGRA234_CLK_PLLP_OUT0>; 1696 clock-names = "div-clk", "parent"; 1697 assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>; 1698 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 1699 resets = <&bpmp TEGRA234_RESET_I2C8>; 1700 reset-names = "i2c"; 1701 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 1702 dma-coherent; 1703 dmas = <&gpcdma 0>, <&gpcdma 0>; 1704 dma-names = "rx", "tx"; 1705 }; 1706 1707 rtc@c2a0000 { 1708 compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc"; 1709 reg = <0x0 0x0c2a0000 0x0 0x10000>; 1710 interrupt-parent = <&pmc>; 1711 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1712 clocks = <&bpmp TEGRA234_CLK_CLK_32K>; 1713 clock-names = "rtc"; 1714 status = "disabled"; 1715 }; 1716 1717 gpio_aon: gpio@c2f0000 { 1718 compatible = "nvidia,tegra234-gpio-aon"; 1719 reg-names = "security", "gpio"; 1720 reg = <0x0 0x0c2f0000 0x0 0x1000>, 1721 <0x0 0x0c2f1000 0x0 0x1000>; 1722 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1723 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1724 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1725 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1726 #interrupt-cells = <2>; 1727 interrupt-controller; 1728 #gpio-cells = <2>; 1729 gpio-controller; 1730 }; 1731 1732 pwm4: pwm@c340000 { 1733 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 1734 reg = <0x0 0xc340000 0x0 0x10000>; 1735 clocks = <&bpmp TEGRA234_CLK_PWM4>; 1736 resets = <&bpmp TEGRA234_RESET_PWM4>; 1737 reset-names = "pwm"; 1738 status = "disabled"; 1739 #pwm-cells = <2>; 1740 }; 1741 1742 pmc: pmc@c360000 { 1743 compatible = "nvidia,tegra234-pmc"; 1744 reg = <0x0 0x0c360000 0x0 0x10000>, 1745 <0x0 0x0c370000 0x0 0x10000>, 1746 <0x0 0x0c380000 0x0 0x10000>, 1747 <0x0 0x0c390000 0x0 0x10000>, 1748 <0x0 0x0c3a0000 0x0 0x10000>; 1749 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 1750 1751 #interrupt-cells = <2>; 1752 interrupt-controller; 1753 1754 sdmmc1_1v8: sdmmc1-1v8 { 1755 pins = "sdmmc1-hv"; 1756 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1757 }; 1758 1759 sdmmc1_3v3: sdmmc1-3v3 { 1760 pins = "sdmmc1-hv"; 1761 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1762 }; 1763 1764 sdmmc3_1v8: sdmmc3-1v8 { 1765 pins = "sdmmc3-hv"; 1766 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1767 }; 1768 1769 sdmmc3_3v3: sdmmc3-3v3 { 1770 pins = "sdmmc3-hv"; 1771 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1772 }; 1773 }; 1774 1775 aon-fabric@c600000 { 1776 compatible = "nvidia,tegra234-aon-fabric"; 1777 reg = <0x0 0xc600000 0x0 0x40000>; 1778 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 1779 status = "okay"; 1780 }; 1781 1782 bpmp-fabric@d600000 { 1783 compatible = "nvidia,tegra234-bpmp-fabric"; 1784 reg = <0x0 0xd600000 0x0 0x40000>; 1785 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1786 status = "okay"; 1787 }; 1788 1789 dce-fabric@de00000 { 1790 compatible = "nvidia,tegra234-sce-fabric"; 1791 reg = <0x0 0xde00000 0x0 0x40000>; 1792 interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>; 1793 status = "okay"; 1794 }; 1795 1796 ccplex@e000000 { 1797 compatible = "nvidia,tegra234-ccplex-cluster"; 1798 reg = <0x0 0x0e000000 0x0 0x5ffff>; 1799 nvidia,bpmp = <&bpmp>; 1800 status = "okay"; 1801 }; 1802 1803 gic: interrupt-controller@f400000 { 1804 compatible = "arm,gic-v3"; 1805 reg = <0x0 0x0f400000 0x0 0x010000>, /* GICD */ 1806 <0x0 0x0f440000 0x0 0x200000>; /* GICR */ 1807 interrupt-parent = <&gic>; 1808 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1809 1810 #redistributor-regions = <1>; 1811 #interrupt-cells = <3>; 1812 interrupt-controller; 1813 }; 1814 1815 smmu_iso: iommu@10000000 { 1816 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 1817 reg = <0x0 0x10000000 0x0 0x1000000>; 1818 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1819 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1820 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1821 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1822 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1823 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1824 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1825 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1826 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1827 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1828 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1829 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1830 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1831 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1832 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1833 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1834 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1835 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1836 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1837 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1838 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1839 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1840 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1841 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1842 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1843 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1844 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1845 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1846 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1847 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1848 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1849 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1850 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1851 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1852 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1853 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1854 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1855 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1856 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1857 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1858 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1859 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1860 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1861 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1862 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1863 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1864 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1865 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1866 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1867 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1868 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1869 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1870 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1871 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1872 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1873 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1874 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1875 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1876 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1877 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1878 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1879 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1880 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1881 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1882 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1883 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1884 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1885 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1886 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1887 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1888 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1889 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1890 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1891 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1892 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1893 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1894 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1895 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1896 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1897 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1898 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1899 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1900 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1901 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1902 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1903 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1904 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1905 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1906 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1907 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1908 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1909 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1910 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1911 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1912 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1913 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1914 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1915 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1916 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1917 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1918 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1919 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1920 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1921 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1922 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1923 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1924 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1925 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1926 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1927 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1928 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1929 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1930 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1931 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1932 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1933 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1934 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1935 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1936 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1937 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1938 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1939 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1940 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1941 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1942 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1943 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1944 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1945 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1946 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1947 stream-match-mask = <0x7f80>; 1948 #global-interrupts = <1>; 1949 #iommu-cells = <1>; 1950 1951 nvidia,memory-controller = <&mc>; 1952 status = "okay"; 1953 }; 1954 1955 smmu_niso0: iommu@12000000 { 1956 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 1957 reg = <0x0 0x12000000 0x0 0x1000000>, 1958 <0x0 0x11000000 0x0 0x1000000>; 1959 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1960 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1961 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1962 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1963 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1964 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1965 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1966 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1967 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1968 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1969 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1970 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1971 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1972 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1973 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1974 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1975 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1976 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1977 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1978 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1979 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1980 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1981 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1982 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1983 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1984 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1985 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1986 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1987 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1988 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1989 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1990 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1991 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1992 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1993 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1994 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1995 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1996 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1997 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1998 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1999 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2000 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2001 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2002 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2003 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2004 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2005 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2006 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2007 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2008 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2009 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2010 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2011 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2012 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2013 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2014 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2015 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2016 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2017 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2018 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2019 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2020 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2021 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2022 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2023 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2024 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2025 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2026 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2027 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2028 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2029 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2030 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2031 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2032 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2033 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2034 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2035 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2036 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2037 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2038 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2039 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2040 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2041 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2042 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2043 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2044 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2045 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2046 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2047 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2048 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2049 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2050 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2051 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2052 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2053 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2054 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2055 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2056 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2057 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2058 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2059 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2060 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2061 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2062 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2063 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2064 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2065 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2066 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2067 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2068 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2069 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2070 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2071 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2072 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2073 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2074 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2075 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2076 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2077 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2078 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2079 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2080 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2081 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2082 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2083 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2084 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2085 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2086 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2087 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2088 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2089 stream-match-mask = <0x7f80>; 2090 #global-interrupts = <2>; 2091 #iommu-cells = <1>; 2092 2093 nvidia,memory-controller = <&mc>; 2094 status = "okay"; 2095 }; 2096 2097 cbb-fabric@13a00000 { 2098 compatible = "nvidia,tegra234-cbb-fabric"; 2099 reg = <0x0 0x13a00000 0x0 0x400000>; 2100 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 2101 status = "okay"; 2102 }; 2103 2104 host1x@13e00000 { 2105 compatible = "nvidia,tegra234-host1x"; 2106 reg = <0x0 0x13e00000 0x0 0x10000>, 2107 <0x0 0x13e10000 0x0 0x10000>, 2108 <0x0 0x13e40000 0x0 0x10000>; 2109 reg-names = "common", "hypervisor", "vm"; 2110 interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 2111 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 2112 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 2113 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 2114 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 2115 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 2116 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, 2117 <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, 2118 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 2119 interrupt-names = "syncpt0", "syncpt1", "syncpt2", "syncpt3", "syncpt4", 2120 "syncpt5", "syncpt6", "syncpt7", "host1x"; 2121 clocks = <&bpmp TEGRA234_CLK_HOST1X>; 2122 clock-names = "host1x"; 2123 2124 #address-cells = <2>; 2125 #size-cells = <2>; 2126 ranges = <0x0 0x14800000 0x0 0x14800000 0x0 0x02000000>; 2127 2128 interconnects = <&mc TEGRA234_MEMORY_CLIENT_HOST1XDMAR &emc>; 2129 interconnect-names = "dma-mem"; 2130 iommus = <&smmu_niso1 TEGRA234_SID_HOST1X>; 2131 2132 /* Context isolation domains */ 2133 iommu-map = <0 &smmu_niso0 TEGRA234_SID_HOST1X_CTX0 1>, 2134 <1 &smmu_niso0 TEGRA234_SID_HOST1X_CTX1 1>, 2135 <2 &smmu_niso0 TEGRA234_SID_HOST1X_CTX2 1>, 2136 <3 &smmu_niso0 TEGRA234_SID_HOST1X_CTX3 1>, 2137 <4 &smmu_niso0 TEGRA234_SID_HOST1X_CTX4 1>, 2138 <5 &smmu_niso0 TEGRA234_SID_HOST1X_CTX5 1>, 2139 <6 &smmu_niso0 TEGRA234_SID_HOST1X_CTX6 1>, 2140 <7 &smmu_niso0 TEGRA234_SID_HOST1X_CTX7 1>, 2141 <8 &smmu_niso1 TEGRA234_SID_HOST1X_CTX0 1>, 2142 <9 &smmu_niso1 TEGRA234_SID_HOST1X_CTX1 1>, 2143 <10 &smmu_niso1 TEGRA234_SID_HOST1X_CTX2 1>, 2144 <11 &smmu_niso1 TEGRA234_SID_HOST1X_CTX3 1>, 2145 <12 &smmu_niso1 TEGRA234_SID_HOST1X_CTX4 1>, 2146 <13 &smmu_niso1 TEGRA234_SID_HOST1X_CTX5 1>, 2147 <14 &smmu_niso1 TEGRA234_SID_HOST1X_CTX6 1>, 2148 <15 &smmu_niso1 TEGRA234_SID_HOST1X_CTX7 1>; 2149 2150 vic@15340000 { 2151 compatible = "nvidia,tegra234-vic"; 2152 reg = <0x0 0x15340000 0x0 0x00040000>; 2153 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 2154 clocks = <&bpmp TEGRA234_CLK_VIC>; 2155 clock-names = "vic"; 2156 resets = <&bpmp TEGRA234_RESET_VIC>; 2157 reset-names = "vic"; 2158 2159 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_VIC>; 2160 interconnects = <&mc TEGRA234_MEMORY_CLIENT_VICSRD &emc>, 2161 <&mc TEGRA234_MEMORY_CLIENT_VICSWR &emc>; 2162 interconnect-names = "dma-mem", "write"; 2163 iommus = <&smmu_niso1 TEGRA234_SID_VIC>; 2164 dma-coherent; 2165 }; 2166 2167 nvdec@15480000 { 2168 compatible = "nvidia,tegra234-nvdec"; 2169 reg = <0x0 0x15480000 0x0 0x00040000>; 2170 clocks = <&bpmp TEGRA234_CLK_NVDEC>, 2171 <&bpmp TEGRA234_CLK_FUSE>, 2172 <&bpmp TEGRA234_CLK_TSEC_PKA>; 2173 clock-names = "nvdec", "fuse", "tsec_pka"; 2174 resets = <&bpmp TEGRA234_RESET_NVDEC>; 2175 reset-names = "nvdec"; 2176 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>; 2177 interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDECSRD &emc>, 2178 <&mc TEGRA234_MEMORY_CLIENT_NVDECSWR &emc>; 2179 interconnect-names = "dma-mem", "write"; 2180 iommus = <&smmu_niso1 TEGRA234_SID_NVDEC>; 2181 dma-coherent; 2182 2183 nvidia,memory-controller = <&mc>; 2184 2185 /* 2186 * Placeholder values that firmware needs to update with the real 2187 * offsets parsed from the microcode headers. 2188 */ 2189 nvidia,bl-manifest-offset = <0>; 2190 nvidia,bl-data-offset = <0>; 2191 nvidia,bl-code-offset = <0>; 2192 nvidia,os-manifest-offset = <0>; 2193 nvidia,os-data-offset = <0>; 2194 nvidia,os-code-offset = <0>; 2195 2196 /* 2197 * Firmware needs to set this to "okay" once the above values have 2198 * been updated. 2199 */ 2200 status = "disabled"; 2201 }; 2202 }; 2203 2204 pcie@140a0000 { 2205 compatible = "nvidia,tegra234-pcie"; 2206 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CA>; 2207 reg = <0x00 0x140a0000 0x0 0x00020000>, /* appl registers (128K) */ 2208 <0x00 0x2a000000 0x0 0x00040000>, /* configuration space (256K) */ 2209 <0x00 0x2a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2210 <0x00 0x2a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2211 <0x35 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2212 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2213 2214 #address-cells = <3>; 2215 #size-cells = <2>; 2216 device_type = "pci"; 2217 num-lanes = <4>; 2218 num-viewport = <8>; 2219 linux,pci-domain = <8>; 2220 2221 clocks = <&bpmp TEGRA234_CLK_PEX2_C8_CORE>; 2222 clock-names = "core"; 2223 2224 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_8_APB>, 2225 <&bpmp TEGRA234_RESET_PEX2_CORE_8>; 2226 reset-names = "apb", "core"; 2227 2228 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2229 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2230 interrupt-names = "intr", "msi"; 2231 2232 #interrupt-cells = <1>; 2233 interrupt-map-mask = <0 0 0 0>; 2234 interrupt-map = <0 0 0 0 &gic GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 2235 2236 nvidia,bpmp = <&bpmp 8>; 2237 2238 nvidia,aspm-cmrt-us = <60>; 2239 nvidia,aspm-pwr-on-t-us = <20>; 2240 nvidia,aspm-l0s-entrance-latency-us = <3>; 2241 2242 bus-range = <0x0 0xff>; 2243 2244 ranges = <0x43000000 0x32 0x40000000 0x32 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2245 <0x02000000 0x0 0x40000000 0x35 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2246 <0x01000000 0x0 0x2a100000 0x00 0x2a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2247 2248 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE8AR &emc>, 2249 <&mc TEGRA234_MEMORY_CLIENT_PCIE8AW &emc>; 2250 interconnect-names = "dma-mem", "write"; 2251 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE8 0x1000>; 2252 iommu-map-mask = <0x0>; 2253 dma-coherent; 2254 2255 status = "disabled"; 2256 }; 2257 2258 pcie@140c0000 { 2259 compatible = "nvidia,tegra234-pcie"; 2260 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CB>; 2261 reg = <0x00 0x140c0000 0x0 0x00020000>, /* appl registers (128K) */ 2262 <0x00 0x2c000000 0x0 0x00040000>, /* configuration space (256K) */ 2263 <0x00 0x2c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2264 <0x00 0x2c080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2265 <0x38 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2266 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2267 2268 #address-cells = <3>; 2269 #size-cells = <2>; 2270 device_type = "pci"; 2271 num-lanes = <4>; 2272 num-viewport = <8>; 2273 linux,pci-domain = <9>; 2274 2275 clocks = <&bpmp TEGRA234_CLK_PEX2_C9_CORE>; 2276 clock-names = "core"; 2277 2278 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_9_APB>, 2279 <&bpmp TEGRA234_RESET_PEX2_CORE_9>; 2280 reset-names = "apb", "core"; 2281 2282 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2283 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2284 interrupt-names = "intr", "msi"; 2285 2286 #interrupt-cells = <1>; 2287 interrupt-map-mask = <0 0 0 0>; 2288 interrupt-map = <0 0 0 0 &gic GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2289 2290 nvidia,bpmp = <&bpmp 9>; 2291 2292 nvidia,aspm-cmrt-us = <60>; 2293 nvidia,aspm-pwr-on-t-us = <20>; 2294 nvidia,aspm-l0s-entrance-latency-us = <3>; 2295 2296 bus-range = <0x0 0xff>; 2297 2298 ranges = <0x43000000 0x35 0x40000000 0x35 0x40000000 0x2 0xc0000000>, /* prefetchable memory (11264 MB) */ 2299 <0x02000000 0x0 0x40000000 0x38 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2300 <0x01000000 0x0 0x2c100000 0x00 0x2c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2301 2302 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE9AR &emc>, 2303 <&mc TEGRA234_MEMORY_CLIENT_PCIE9AW &emc>; 2304 interconnect-names = "dma-mem", "write"; 2305 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE9 0x1000>; 2306 iommu-map-mask = <0x0>; 2307 dma-coherent; 2308 2309 status = "disabled"; 2310 }; 2311 2312 pcie@140e0000 { 2313 compatible = "nvidia,tegra234-pcie"; 2314 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>; 2315 reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */ 2316 <0x00 0x2e000000 0x0 0x00040000>, /* configuration space (256K) */ 2317 <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2318 <0x00 0x2e080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2319 <0x3b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2320 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2321 2322 #address-cells = <3>; 2323 #size-cells = <2>; 2324 device_type = "pci"; 2325 num-lanes = <4>; 2326 num-viewport = <8>; 2327 linux,pci-domain = <10>; 2328 2329 clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>; 2330 clock-names = "core"; 2331 2332 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>, 2333 <&bpmp TEGRA234_RESET_PEX2_CORE_10>; 2334 reset-names = "apb", "core"; 2335 2336 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2337 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2338 interrupt-names = "intr", "msi"; 2339 2340 #interrupt-cells = <1>; 2341 interrupt-map-mask = <0 0 0 0>; 2342 interrupt-map = <0 0 0 0 &gic GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 2343 2344 nvidia,bpmp = <&bpmp 10>; 2345 2346 nvidia,aspm-cmrt-us = <60>; 2347 nvidia,aspm-pwr-on-t-us = <20>; 2348 nvidia,aspm-l0s-entrance-latency-us = <3>; 2349 2350 bus-range = <0x0 0xff>; 2351 2352 ranges = <0x43000000 0x38 0x40000000 0x38 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2353 <0x02000000 0x0 0x40000000 0x3b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2354 <0x01000000 0x0 0x2e100000 0x00 0x2e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2355 2356 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, 2357 <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; 2358 interconnect-names = "dma-mem", "write"; 2359 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>; 2360 iommu-map-mask = <0x0>; 2361 dma-coherent; 2362 2363 status = "disabled"; 2364 }; 2365 2366 pcie-ep@140e0000 { 2367 compatible = "nvidia,tegra234-pcie-ep"; 2368 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>; 2369 reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */ 2370 <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2371 <0x00 0x2e080000 0x0 0x00040000>, /* DBI space (256K) */ 2372 <0x38 0x40000000 0x3 0x00000000>; /* Address Space (12G) */ 2373 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2374 2375 num-lanes = <4>; 2376 2377 clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>; 2378 clock-names = "core"; 2379 2380 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>, 2381 <&bpmp TEGRA234_RESET_PEX2_CORE_10>; 2382 reset-names = "apb", "core"; 2383 2384 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2385 interrupt-names = "intr"; 2386 2387 nvidia,bpmp = <&bpmp 10>; 2388 2389 nvidia,enable-ext-refclk; 2390 nvidia,aspm-cmrt-us = <60>; 2391 nvidia,aspm-pwr-on-t-us = <20>; 2392 nvidia,aspm-l0s-entrance-latency-us = <3>; 2393 2394 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, 2395 <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; 2396 interconnect-names = "dma-mem", "write"; 2397 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>; 2398 iommu-map-mask = <0x0>; 2399 dma-coherent; 2400 2401 status = "disabled"; 2402 }; 2403 2404 pcie@14100000 { 2405 compatible = "nvidia,tegra234-pcie"; 2406 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 2407 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 2408 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 2409 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2410 <0x00 0x30080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2411 <0x20 0xb0000000 0x0 0x10000000>; /* ECAM (256MB) */ 2412 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2413 2414 #address-cells = <3>; 2415 #size-cells = <2>; 2416 device_type = "pci"; 2417 num-lanes = <1>; 2418 num-viewport = <8>; 2419 linux,pci-domain = <1>; 2420 2421 clocks = <&bpmp TEGRA234_CLK_PEX0_C1_CORE>; 2422 clock-names = "core"; 2423 2424 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_1_APB>, 2425 <&bpmp TEGRA234_RESET_PEX0_CORE_1>; 2426 reset-names = "apb", "core"; 2427 2428 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2429 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2430 interrupt-names = "intr", "msi"; 2431 2432 #interrupt-cells = <1>; 2433 interrupt-map-mask = <0 0 0 0>; 2434 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 2435 2436 nvidia,bpmp = <&bpmp 1>; 2437 2438 nvidia,aspm-cmrt-us = <60>; 2439 nvidia,aspm-pwr-on-t-us = <20>; 2440 nvidia,aspm-l0s-entrance-latency-us = <3>; 2441 2442 bus-range = <0x0 0xff>; 2443 2444 ranges = <0x43000000 0x20 0x80000000 0x20 0x80000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 2445 <0x02000000 0x0 0x40000000 0x20 0xa8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2446 <0x01000000 0x0 0x30100000 0x00 0x30100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2447 2448 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE1R &emc>, 2449 <&mc TEGRA234_MEMORY_CLIENT_PCIE1W &emc>; 2450 interconnect-names = "dma-mem", "write"; 2451 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE1 0x1000>; 2452 iommu-map-mask = <0x0>; 2453 dma-coherent; 2454 2455 status = "disabled"; 2456 }; 2457 2458 pcie@14120000 { 2459 compatible = "nvidia,tegra234-pcie"; 2460 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 2461 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 2462 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 2463 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2464 <0x00 0x32080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2465 <0x20 0xf0000000 0x0 0x10000000>; /* ECAM (256MB) */ 2466 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2467 2468 #address-cells = <3>; 2469 #size-cells = <2>; 2470 device_type = "pci"; 2471 num-lanes = <1>; 2472 num-viewport = <8>; 2473 linux,pci-domain = <2>; 2474 2475 clocks = <&bpmp TEGRA234_CLK_PEX0_C2_CORE>; 2476 clock-names = "core"; 2477 2478 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_2_APB>, 2479 <&bpmp TEGRA234_RESET_PEX0_CORE_2>; 2480 reset-names = "apb", "core"; 2481 2482 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2483 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2484 interrupt-names = "intr", "msi"; 2485 2486 #interrupt-cells = <1>; 2487 interrupt-map-mask = <0 0 0 0>; 2488 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 2489 2490 nvidia,bpmp = <&bpmp 2>; 2491 2492 nvidia,aspm-cmrt-us = <60>; 2493 nvidia,aspm-pwr-on-t-us = <20>; 2494 nvidia,aspm-l0s-entrance-latency-us = <3>; 2495 2496 bus-range = <0x0 0xff>; 2497 2498 ranges = <0x43000000 0x20 0xc0000000 0x20 0xc0000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 2499 <0x02000000 0x0 0x40000000 0x20 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2500 <0x01000000 0x0 0x32100000 0x00 0x32100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2501 2502 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE2AR &emc>, 2503 <&mc TEGRA234_MEMORY_CLIENT_PCIE2AW &emc>; 2504 interconnect-names = "dma-mem", "write"; 2505 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE2 0x1000>; 2506 iommu-map-mask = <0x0>; 2507 dma-coherent; 2508 2509 status = "disabled"; 2510 }; 2511 2512 pcie@14140000 { 2513 compatible = "nvidia,tegra234-pcie"; 2514 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 2515 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 2516 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 2517 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2518 <0x00 0x34080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2519 <0x21 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2520 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2521 2522 #address-cells = <3>; 2523 #size-cells = <2>; 2524 device_type = "pci"; 2525 num-lanes = <1>; 2526 num-viewport = <8>; 2527 linux,pci-domain = <3>; 2528 2529 clocks = <&bpmp TEGRA234_CLK_PEX0_C3_CORE>; 2530 clock-names = "core"; 2531 2532 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_3_APB>, 2533 <&bpmp TEGRA234_RESET_PEX0_CORE_3>; 2534 reset-names = "apb", "core"; 2535 2536 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2537 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2538 interrupt-names = "intr", "msi"; 2539 2540 #interrupt-cells = <1>; 2541 interrupt-map-mask = <0 0 0 0>; 2542 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 2543 2544 nvidia,bpmp = <&bpmp 3>; 2545 2546 nvidia,aspm-cmrt-us = <60>; 2547 nvidia,aspm-pwr-on-t-us = <20>; 2548 nvidia,aspm-l0s-entrance-latency-us = <3>; 2549 2550 bus-range = <0x0 0xff>; 2551 2552 ranges = <0x43000000 0x21 0x00000000 0x21 0x00000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 2553 <0x02000000 0x0 0x40000000 0x21 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2554 <0x01000000 0x0 0x34100000 0x00 0x34100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2555 2556 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE3R &emc>, 2557 <&mc TEGRA234_MEMORY_CLIENT_PCIE3W &emc>; 2558 interconnect-names = "dma-mem", "write"; 2559 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE3 0x1000>; 2560 iommu-map-mask = <0x0>; 2561 dma-coherent; 2562 2563 status = "disabled"; 2564 }; 2565 2566 pcie@14160000 { 2567 compatible = "nvidia,tegra234-pcie"; 2568 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>; 2569 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2570 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2571 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2572 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2573 <0x24 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2574 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2575 2576 #address-cells = <3>; 2577 #size-cells = <2>; 2578 device_type = "pci"; 2579 num-lanes = <4>; 2580 num-viewport = <8>; 2581 linux,pci-domain = <4>; 2582 2583 clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>; 2584 clock-names = "core"; 2585 2586 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>, 2587 <&bpmp TEGRA234_RESET_PEX0_CORE_4>; 2588 reset-names = "apb", "core"; 2589 2590 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2591 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2592 interrupt-names = "intr", "msi"; 2593 2594 #interrupt-cells = <1>; 2595 interrupt-map-mask = <0 0 0 0>; 2596 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 2597 2598 nvidia,bpmp = <&bpmp 4>; 2599 2600 nvidia,aspm-cmrt-us = <60>; 2601 nvidia,aspm-pwr-on-t-us = <20>; 2602 nvidia,aspm-l0s-entrance-latency-us = <3>; 2603 2604 bus-range = <0x0 0xff>; 2605 2606 ranges = <0x43000000 0x21 0x40000000 0x21 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2607 <0x02000000 0x0 0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2608 <0x01000000 0x0 0x36100000 0x00 0x36100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2609 2610 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE4R &emc>, 2611 <&mc TEGRA234_MEMORY_CLIENT_PCIE4W &emc>; 2612 interconnect-names = "dma-mem", "write"; 2613 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE4 0x1000>; 2614 iommu-map-mask = <0x0>; 2615 dma-coherent; 2616 2617 status = "disabled"; 2618 }; 2619 2620 pcie@14180000 { 2621 compatible = "nvidia,tegra234-pcie"; 2622 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BA>; 2623 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2624 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2625 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2626 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2627 <0x27 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2628 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2629 2630 #address-cells = <3>; 2631 #size-cells = <2>; 2632 device_type = "pci"; 2633 num-lanes = <4>; 2634 num-viewport = <8>; 2635 linux,pci-domain = <0>; 2636 2637 clocks = <&bpmp TEGRA234_CLK_PEX0_C0_CORE>; 2638 clock-names = "core"; 2639 2640 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_0_APB>, 2641 <&bpmp TEGRA234_RESET_PEX0_CORE_0>; 2642 reset-names = "apb", "core"; 2643 2644 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2645 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2646 interrupt-names = "intr", "msi"; 2647 2648 #interrupt-cells = <1>; 2649 interrupt-map-mask = <0 0 0 0>; 2650 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 2651 2652 nvidia,bpmp = <&bpmp 0>; 2653 2654 nvidia,aspm-cmrt-us = <60>; 2655 nvidia,aspm-pwr-on-t-us = <20>; 2656 nvidia,aspm-l0s-entrance-latency-us = <3>; 2657 2658 bus-range = <0x0 0xff>; 2659 2660 ranges = <0x43000000 0x24 0x40000000 0x24 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2661 <0x02000000 0x0 0x40000000 0x27 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2662 <0x01000000 0x0 0x38100000 0x00 0x38100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2663 2664 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE0R &emc>, 2665 <&mc TEGRA234_MEMORY_CLIENT_PCIE0W &emc>; 2666 interconnect-names = "dma-mem", "write"; 2667 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE0 0x1000>; 2668 iommu-map-mask = <0x0>; 2669 dma-coherent; 2670 2671 status = "disabled"; 2672 }; 2673 2674 pcie@141a0000 { 2675 compatible = "nvidia,tegra234-pcie"; 2676 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>; 2677 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2678 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2679 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2680 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2681 <0x2b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2682 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2683 2684 #address-cells = <3>; 2685 #size-cells = <2>; 2686 device_type = "pci"; 2687 num-lanes = <8>; 2688 num-viewport = <8>; 2689 linux,pci-domain = <5>; 2690 2691 clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>; 2692 clock-names = "core"; 2693 2694 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>, 2695 <&bpmp TEGRA234_RESET_PEX1_CORE_5>; 2696 reset-names = "apb", "core"; 2697 2698 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2699 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2700 interrupt-names = "intr", "msi"; 2701 2702 #interrupt-cells = <1>; 2703 interrupt-map-mask = <0 0 0 0>; 2704 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 2705 2706 nvidia,bpmp = <&bpmp 5>; 2707 2708 nvidia,aspm-cmrt-us = <60>; 2709 nvidia,aspm-pwr-on-t-us = <20>; 2710 nvidia,aspm-l0s-entrance-latency-us = <3>; 2711 2712 bus-range = <0x0 0xff>; 2713 2714 ranges = <0x43000000 0x28 0x00000000 0x28 0x00000000 0x3 0x28000000>, /* prefetchable memory (12928 MB) */ 2715 <0x02000000 0x0 0x40000000 0x2b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2716 <0x01000000 0x0 0x3a100000 0x00 0x3a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2717 2718 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, 2719 <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; 2720 interconnect-names = "dma-mem", "write"; 2721 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>; 2722 iommu-map-mask = <0x0>; 2723 dma-coherent; 2724 2725 status = "disabled"; 2726 }; 2727 2728 pcie-ep@141a0000 { 2729 compatible = "nvidia,tegra234-pcie-ep"; 2730 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>; 2731 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2732 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2733 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2734 <0x27 0x40000000 0x4 0x00000000>; /* Address Space (16G) */ 2735 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2736 2737 num-lanes = <8>; 2738 2739 clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>; 2740 clock-names = "core"; 2741 2742 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>, 2743 <&bpmp TEGRA234_RESET_PEX1_CORE_5>; 2744 reset-names = "apb", "core"; 2745 2746 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2747 interrupt-names = "intr"; 2748 2749 nvidia,bpmp = <&bpmp 5>; 2750 2751 nvidia,enable-ext-refclk; 2752 nvidia,aspm-cmrt-us = <60>; 2753 nvidia,aspm-pwr-on-t-us = <20>; 2754 nvidia,aspm-l0s-entrance-latency-us = <3>; 2755 2756 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, 2757 <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; 2758 interconnect-names = "dma-mem", "write"; 2759 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>; 2760 iommu-map-mask = <0x0>; 2761 dma-coherent; 2762 2763 status = "disabled"; 2764 }; 2765 2766 pcie@141c0000 { 2767 compatible = "nvidia,tegra234-pcie"; 2768 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>; 2769 reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */ 2770 <0x00 0x3c000000 0x0 0x00040000>, /* configuration space (256K) */ 2771 <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2772 <0x00 0x3c080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2773 <0x2e 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2774 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2775 2776 #address-cells = <3>; 2777 #size-cells = <2>; 2778 device_type = "pci"; 2779 num-lanes = <4>; 2780 num-viewport = <8>; 2781 linux,pci-domain = <6>; 2782 2783 clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>; 2784 clock-names = "core"; 2785 2786 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>, 2787 <&bpmp TEGRA234_RESET_PEX1_CORE_6>; 2788 reset-names = "apb", "core"; 2789 2790 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2791 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2792 interrupt-names = "intr", "msi"; 2793 2794 #interrupt-cells = <1>; 2795 interrupt-map-mask = <0 0 0 0>; 2796 interrupt-map = <0 0 0 0 &gic GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 2797 2798 nvidia,bpmp = <&bpmp 6>; 2799 2800 nvidia,aspm-cmrt-us = <60>; 2801 nvidia,aspm-pwr-on-t-us = <20>; 2802 nvidia,aspm-l0s-entrance-latency-us = <3>; 2803 2804 bus-range = <0x0 0xff>; 2805 2806 ranges = <0x43000000 0x2b 0x40000000 0x2b 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2807 <0x02000000 0x0 0x40000000 0x2e 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2808 <0x01000000 0x0 0x3c100000 0x00 0x3c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2809 2810 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, 2811 <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; 2812 interconnect-names = "dma-mem", "write"; 2813 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>; 2814 iommu-map-mask = <0x0>; 2815 dma-coherent; 2816 2817 status = "disabled"; 2818 }; 2819 2820 pcie-ep@141c0000 { 2821 compatible = "nvidia,tegra234-pcie-ep"; 2822 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>; 2823 reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */ 2824 <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2825 <0x00 0x3c080000 0x0 0x00040000>, /* DBI space (256K) */ 2826 <0x2b 0x40000000 0x3 0x00000000>; /* Address Space (12G) */ 2827 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2828 2829 num-lanes = <4>; 2830 2831 clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>; 2832 clock-names = "core"; 2833 2834 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>, 2835 <&bpmp TEGRA234_RESET_PEX1_CORE_6>; 2836 reset-names = "apb", "core"; 2837 2838 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2839 interrupt-names = "intr"; 2840 2841 nvidia,bpmp = <&bpmp 6>; 2842 2843 nvidia,enable-ext-refclk; 2844 nvidia,aspm-cmrt-us = <60>; 2845 nvidia,aspm-pwr-on-t-us = <20>; 2846 nvidia,aspm-l0s-entrance-latency-us = <3>; 2847 2848 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, 2849 <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; 2850 interconnect-names = "dma-mem", "write"; 2851 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>; 2852 iommu-map-mask = <0x0>; 2853 dma-coherent; 2854 2855 status = "disabled"; 2856 }; 2857 2858 pcie@141e0000 { 2859 compatible = "nvidia,tegra234-pcie"; 2860 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>; 2861 reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */ 2862 <0x00 0x3e000000 0x0 0x00040000>, /* configuration space (256K) */ 2863 <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2864 <0x00 0x3e080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2865 <0x32 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2866 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2867 2868 #address-cells = <3>; 2869 #size-cells = <2>; 2870 device_type = "pci"; 2871 num-lanes = <8>; 2872 num-viewport = <8>; 2873 linux,pci-domain = <7>; 2874 2875 clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>; 2876 clock-names = "core"; 2877 2878 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>, 2879 <&bpmp TEGRA234_RESET_PEX2_CORE_7>; 2880 reset-names = "apb", "core"; 2881 2882 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2883 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2884 interrupt-names = "intr", "msi"; 2885 2886 #interrupt-cells = <1>; 2887 interrupt-map-mask = <0 0 0 0>; 2888 interrupt-map = <0 0 0 0 &gic GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 2889 2890 nvidia,bpmp = <&bpmp 7>; 2891 2892 nvidia,aspm-cmrt-us = <60>; 2893 nvidia,aspm-pwr-on-t-us = <20>; 2894 nvidia,aspm-l0s-entrance-latency-us = <3>; 2895 2896 bus-range = <0x0 0xff>; 2897 2898 ranges = <0x43000000 0x30 0x00000000 0x30 0x00000000 0x2 0x28000000>, /* prefetchable memory (8832 MB) */ 2899 <0x02000000 0x0 0x40000000 0x32 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2900 <0x01000000 0x0 0x3e100000 0x00 0x3e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2901 2902 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>, 2903 <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>; 2904 interconnect-names = "dma-mem", "write"; 2905 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>; 2906 iommu-map-mask = <0x0>; 2907 dma-coherent; 2908 2909 status = "disabled"; 2910 }; 2911 2912 pcie-ep@141e0000 { 2913 compatible = "nvidia,tegra234-pcie-ep"; 2914 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>; 2915 reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */ 2916 <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2917 <0x00 0x3e080000 0x0 0x00040000>, /* DBI space (256K) */ 2918 <0x2e 0x40000000 0x4 0x00000000>; /* Address Space (16G) */ 2919 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2920 2921 num-lanes = <8>; 2922 2923 clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>; 2924 clock-names = "core"; 2925 2926 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>, 2927 <&bpmp TEGRA234_RESET_PEX2_CORE_7>; 2928 reset-names = "apb", "core"; 2929 2930 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2931 interrupt-names = "intr"; 2932 2933 nvidia,bpmp = <&bpmp 7>; 2934 2935 nvidia,enable-ext-refclk; 2936 nvidia,aspm-cmrt-us = <60>; 2937 nvidia,aspm-pwr-on-t-us = <20>; 2938 nvidia,aspm-l0s-entrance-latency-us = <3>; 2939 2940 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>, 2941 <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>; 2942 interconnect-names = "dma-mem", "write"; 2943 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>; 2944 iommu-map-mask = <0x0>; 2945 dma-coherent; 2946 2947 status = "disabled"; 2948 }; 2949 }; 2950 2951 sram@40000000 { 2952 compatible = "nvidia,tegra234-sysram", "mmio-sram"; 2953 reg = <0x0 0x40000000 0x0 0x80000>; 2954 2955 #address-cells = <1>; 2956 #size-cells = <1>; 2957 ranges = <0x0 0x0 0x40000000 0x80000>; 2958 2959 no-memory-wc; 2960 2961 cpu_bpmp_tx: sram@70000 { 2962 reg = <0x70000 0x1000>; 2963 label = "cpu-bpmp-tx"; 2964 pool; 2965 }; 2966 2967 cpu_bpmp_rx: sram@71000 { 2968 reg = <0x71000 0x1000>; 2969 label = "cpu-bpmp-rx"; 2970 pool; 2971 }; 2972 }; 2973 2974 bpmp: bpmp { 2975 compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp"; 2976 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 2977 TEGRA_HSP_DB_MASTER_BPMP>; 2978 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 2979 #clock-cells = <1>; 2980 #reset-cells = <1>; 2981 #power-domain-cells = <1>; 2982 interconnects = <&mc TEGRA234_MEMORY_CLIENT_BPMPR &emc>, 2983 <&mc TEGRA234_MEMORY_CLIENT_BPMPW &emc>, 2984 <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAR &emc>, 2985 <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAW &emc>; 2986 interconnect-names = "read", "write", "dma-mem", "dma-write"; 2987 iommus = <&smmu_niso1 TEGRA234_SID_BPMP>; 2988 2989 bpmp_i2c: i2c { 2990 compatible = "nvidia,tegra186-bpmp-i2c"; 2991 nvidia,bpmp-bus-id = <5>; 2992 #address-cells = <1>; 2993 #size-cells = <0>; 2994 }; 2995 }; 2996 2997 cpus { 2998 #address-cells = <1>; 2999 #size-cells = <0>; 3000 3001 cpu0_0: cpu@0 { 3002 compatible = "arm,cortex-a78"; 3003 device_type = "cpu"; 3004 reg = <0x00000>; 3005 3006 enable-method = "psci"; 3007 3008 i-cache-size = <65536>; 3009 i-cache-line-size = <64>; 3010 i-cache-sets = <256>; 3011 d-cache-size = <65536>; 3012 d-cache-line-size = <64>; 3013 d-cache-sets = <256>; 3014 next-level-cache = <&l2c0_0>; 3015 }; 3016 3017 cpu0_1: cpu@100 { 3018 compatible = "arm,cortex-a78"; 3019 device_type = "cpu"; 3020 reg = <0x00100>; 3021 3022 enable-method = "psci"; 3023 3024 i-cache-size = <65536>; 3025 i-cache-line-size = <64>; 3026 i-cache-sets = <256>; 3027 d-cache-size = <65536>; 3028 d-cache-line-size = <64>; 3029 d-cache-sets = <256>; 3030 next-level-cache = <&l2c0_1>; 3031 }; 3032 3033 cpu0_2: cpu@200 { 3034 compatible = "arm,cortex-a78"; 3035 device_type = "cpu"; 3036 reg = <0x00200>; 3037 3038 enable-method = "psci"; 3039 3040 i-cache-size = <65536>; 3041 i-cache-line-size = <64>; 3042 i-cache-sets = <256>; 3043 d-cache-size = <65536>; 3044 d-cache-line-size = <64>; 3045 d-cache-sets = <256>; 3046 next-level-cache = <&l2c0_2>; 3047 }; 3048 3049 cpu0_3: cpu@300 { 3050 compatible = "arm,cortex-a78"; 3051 device_type = "cpu"; 3052 reg = <0x00300>; 3053 3054 enable-method = "psci"; 3055 3056 i-cache-size = <65536>; 3057 i-cache-line-size = <64>; 3058 i-cache-sets = <256>; 3059 d-cache-size = <65536>; 3060 d-cache-line-size = <64>; 3061 d-cache-sets = <256>; 3062 next-level-cache = <&l2c0_3>; 3063 }; 3064 3065 cpu1_0: cpu@10000 { 3066 compatible = "arm,cortex-a78"; 3067 device_type = "cpu"; 3068 reg = <0x10000>; 3069 3070 enable-method = "psci"; 3071 3072 i-cache-size = <65536>; 3073 i-cache-line-size = <64>; 3074 i-cache-sets = <256>; 3075 d-cache-size = <65536>; 3076 d-cache-line-size = <64>; 3077 d-cache-sets = <256>; 3078 next-level-cache = <&l2c1_0>; 3079 }; 3080 3081 cpu1_1: cpu@10100 { 3082 compatible = "arm,cortex-a78"; 3083 device_type = "cpu"; 3084 reg = <0x10100>; 3085 3086 enable-method = "psci"; 3087 3088 i-cache-size = <65536>; 3089 i-cache-line-size = <64>; 3090 i-cache-sets = <256>; 3091 d-cache-size = <65536>; 3092 d-cache-line-size = <64>; 3093 d-cache-sets = <256>; 3094 next-level-cache = <&l2c1_1>; 3095 }; 3096 3097 cpu1_2: cpu@10200 { 3098 compatible = "arm,cortex-a78"; 3099 device_type = "cpu"; 3100 reg = <0x10200>; 3101 3102 enable-method = "psci"; 3103 3104 i-cache-size = <65536>; 3105 i-cache-line-size = <64>; 3106 i-cache-sets = <256>; 3107 d-cache-size = <65536>; 3108 d-cache-line-size = <64>; 3109 d-cache-sets = <256>; 3110 next-level-cache = <&l2c1_2>; 3111 }; 3112 3113 cpu1_3: cpu@10300 { 3114 compatible = "arm,cortex-a78"; 3115 device_type = "cpu"; 3116 reg = <0x10300>; 3117 3118 enable-method = "psci"; 3119 3120 i-cache-size = <65536>; 3121 i-cache-line-size = <64>; 3122 i-cache-sets = <256>; 3123 d-cache-size = <65536>; 3124 d-cache-line-size = <64>; 3125 d-cache-sets = <256>; 3126 next-level-cache = <&l2c1_3>; 3127 }; 3128 3129 cpu2_0: cpu@20000 { 3130 compatible = "arm,cortex-a78"; 3131 device_type = "cpu"; 3132 reg = <0x20000>; 3133 3134 enable-method = "psci"; 3135 3136 i-cache-size = <65536>; 3137 i-cache-line-size = <64>; 3138 i-cache-sets = <256>; 3139 d-cache-size = <65536>; 3140 d-cache-line-size = <64>; 3141 d-cache-sets = <256>; 3142 next-level-cache = <&l2c2_0>; 3143 }; 3144 3145 cpu2_1: cpu@20100 { 3146 compatible = "arm,cortex-a78"; 3147 device_type = "cpu"; 3148 reg = <0x20100>; 3149 3150 enable-method = "psci"; 3151 3152 i-cache-size = <65536>; 3153 i-cache-line-size = <64>; 3154 i-cache-sets = <256>; 3155 d-cache-size = <65536>; 3156 d-cache-line-size = <64>; 3157 d-cache-sets = <256>; 3158 next-level-cache = <&l2c2_1>; 3159 }; 3160 3161 cpu2_2: cpu@20200 { 3162 compatible = "arm,cortex-a78"; 3163 device_type = "cpu"; 3164 reg = <0x20200>; 3165 3166 enable-method = "psci"; 3167 3168 i-cache-size = <65536>; 3169 i-cache-line-size = <64>; 3170 i-cache-sets = <256>; 3171 d-cache-size = <65536>; 3172 d-cache-line-size = <64>; 3173 d-cache-sets = <256>; 3174 next-level-cache = <&l2c2_2>; 3175 }; 3176 3177 cpu2_3: cpu@20300 { 3178 compatible = "arm,cortex-a78"; 3179 device_type = "cpu"; 3180 reg = <0x20300>; 3181 3182 enable-method = "psci"; 3183 3184 i-cache-size = <65536>; 3185 i-cache-line-size = <64>; 3186 i-cache-sets = <256>; 3187 d-cache-size = <65536>; 3188 d-cache-line-size = <64>; 3189 d-cache-sets = <256>; 3190 next-level-cache = <&l2c2_3>; 3191 }; 3192 3193 cpu-map { 3194 cluster0 { 3195 core0 { 3196 cpu = <&cpu0_0>; 3197 }; 3198 3199 core1 { 3200 cpu = <&cpu0_1>; 3201 }; 3202 3203 core2 { 3204 cpu = <&cpu0_2>; 3205 }; 3206 3207 core3 { 3208 cpu = <&cpu0_3>; 3209 }; 3210 }; 3211 3212 cluster1 { 3213 core0 { 3214 cpu = <&cpu1_0>; 3215 }; 3216 3217 core1 { 3218 cpu = <&cpu1_1>; 3219 }; 3220 3221 core2 { 3222 cpu = <&cpu1_2>; 3223 }; 3224 3225 core3 { 3226 cpu = <&cpu1_3>; 3227 }; 3228 }; 3229 3230 cluster2 { 3231 core0 { 3232 cpu = <&cpu2_0>; 3233 }; 3234 3235 core1 { 3236 cpu = <&cpu2_1>; 3237 }; 3238 3239 core2 { 3240 cpu = <&cpu2_2>; 3241 }; 3242 3243 core3 { 3244 cpu = <&cpu2_3>; 3245 }; 3246 }; 3247 }; 3248 3249 l2c0_0: l2-cache00 { 3250 compatible = "cache"; 3251 cache-size = <262144>; 3252 cache-line-size = <64>; 3253 cache-sets = <512>; 3254 cache-unified; 3255 cache-level = <2>; 3256 next-level-cache = <&l3c0>; 3257 }; 3258 3259 l2c0_1: l2-cache01 { 3260 compatible = "cache"; 3261 cache-size = <262144>; 3262 cache-line-size = <64>; 3263 cache-sets = <512>; 3264 cache-unified; 3265 cache-level = <2>; 3266 next-level-cache = <&l3c0>; 3267 }; 3268 3269 l2c0_2: l2-cache02 { 3270 compatible = "cache"; 3271 cache-size = <262144>; 3272 cache-line-size = <64>; 3273 cache-sets = <512>; 3274 cache-unified; 3275 cache-level = <2>; 3276 next-level-cache = <&l3c0>; 3277 }; 3278 3279 l2c0_3: l2-cache03 { 3280 compatible = "cache"; 3281 cache-size = <262144>; 3282 cache-line-size = <64>; 3283 cache-sets = <512>; 3284 cache-unified; 3285 cache-level = <2>; 3286 next-level-cache = <&l3c0>; 3287 }; 3288 3289 l2c1_0: l2-cache10 { 3290 compatible = "cache"; 3291 cache-size = <262144>; 3292 cache-line-size = <64>; 3293 cache-sets = <512>; 3294 cache-unified; 3295 cache-level = <2>; 3296 next-level-cache = <&l3c1>; 3297 }; 3298 3299 l2c1_1: l2-cache11 { 3300 compatible = "cache"; 3301 cache-size = <262144>; 3302 cache-line-size = <64>; 3303 cache-sets = <512>; 3304 cache-unified; 3305 cache-level = <2>; 3306 next-level-cache = <&l3c1>; 3307 }; 3308 3309 l2c1_2: l2-cache12 { 3310 compatible = "cache"; 3311 cache-size = <262144>; 3312 cache-line-size = <64>; 3313 cache-sets = <512>; 3314 cache-unified; 3315 cache-level = <2>; 3316 next-level-cache = <&l3c1>; 3317 }; 3318 3319 l2c1_3: l2-cache13 { 3320 compatible = "cache"; 3321 cache-size = <262144>; 3322 cache-line-size = <64>; 3323 cache-sets = <512>; 3324 cache-unified; 3325 cache-level = <2>; 3326 next-level-cache = <&l3c1>; 3327 }; 3328 3329 l2c2_0: l2-cache20 { 3330 compatible = "cache"; 3331 cache-size = <262144>; 3332 cache-line-size = <64>; 3333 cache-sets = <512>; 3334 cache-unified; 3335 cache-level = <2>; 3336 next-level-cache = <&l3c2>; 3337 }; 3338 3339 l2c2_1: l2-cache21 { 3340 compatible = "cache"; 3341 cache-size = <262144>; 3342 cache-line-size = <64>; 3343 cache-sets = <512>; 3344 cache-unified; 3345 cache-level = <2>; 3346 next-level-cache = <&l3c2>; 3347 }; 3348 3349 l2c2_2: l2-cache22 { 3350 compatible = "cache"; 3351 cache-size = <262144>; 3352 cache-line-size = <64>; 3353 cache-sets = <512>; 3354 cache-unified; 3355 cache-level = <2>; 3356 next-level-cache = <&l3c2>; 3357 }; 3358 3359 l2c2_3: l2-cache23 { 3360 compatible = "cache"; 3361 cache-size = <262144>; 3362 cache-line-size = <64>; 3363 cache-sets = <512>; 3364 cache-unified; 3365 cache-level = <2>; 3366 next-level-cache = <&l3c2>; 3367 }; 3368 3369 l3c0: l3-cache0 { 3370 compatible = "cache"; 3371 cache-unified; 3372 cache-size = <2097152>; 3373 cache-line-size = <64>; 3374 cache-sets = <2048>; 3375 cache-level = <3>; 3376 }; 3377 3378 l3c1: l3-cache1 { 3379 compatible = "cache"; 3380 cache-unified; 3381 cache-size = <2097152>; 3382 cache-line-size = <64>; 3383 cache-sets = <2048>; 3384 cache-level = <3>; 3385 }; 3386 3387 l3c2: l3-cache2 { 3388 compatible = "cache"; 3389 cache-unified; 3390 cache-size = <2097152>; 3391 cache-line-size = <64>; 3392 cache-sets = <2048>; 3393 cache-level = <3>; 3394 }; 3395 }; 3396 3397 pmu { 3398 compatible = "arm,cortex-a78-pmu"; 3399 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 3400 status = "okay"; 3401 }; 3402 3403 psci { 3404 compatible = "arm,psci-1.0"; 3405 status = "okay"; 3406 method = "smc"; 3407 }; 3408 3409 tcu: serial { 3410 compatible = "nvidia,tegra234-tcu", "nvidia,tegra194-tcu"; 3411 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 3412 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 3413 mbox-names = "rx", "tx"; 3414 status = "disabled"; 3415 }; 3416 3417 sound { 3418 status = "disabled"; 3419 3420 clocks = <&bpmp TEGRA234_CLK_PLLA>, 3421 <&bpmp TEGRA234_CLK_PLLA_OUT0>; 3422 clock-names = "pll_a", "plla_out0"; 3423 assigned-clocks = <&bpmp TEGRA234_CLK_PLLA>, 3424 <&bpmp TEGRA234_CLK_PLLA_OUT0>, 3425 <&bpmp TEGRA234_CLK_AUD_MCLK>; 3426 assigned-clock-parents = <0>, 3427 <&bpmp TEGRA234_CLK_PLLA>, 3428 <&bpmp TEGRA234_CLK_PLLA_OUT0>; 3429 }; 3430 3431 timer { 3432 compatible = "arm,armv8-timer"; 3433 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3434 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3435 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3436 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 3437 interrupt-parent = <&gic>; 3438 always-on; 3439 }; 3440}; 3441