1// SPDX-License-Identifier: GPL-2.0 2 3#include <dt-bindings/clock/tegra234-clock.h> 4#include <dt-bindings/gpio/tegra234-gpio.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/mailbox/tegra186-hsp.h> 7#include <dt-bindings/memory/tegra234-mc.h> 8#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 9#include <dt-bindings/power/tegra234-powergate.h> 10#include <dt-bindings/reset/tegra234-reset.h> 11 12/ { 13 compatible = "nvidia,tegra234"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 bus@0 { 19 compatible = "simple-bus"; 20 21 #address-cells = <2>; 22 #size-cells = <2>; 23 ranges = <0x0 0x0 0x0 0x0 0x0 0x40000000>; 24 25 misc@100000 { 26 compatible = "nvidia,tegra234-misc"; 27 reg = <0x0 0x00100000 0x0 0xf000>, 28 <0x0 0x0010f000 0x0 0x1000>; 29 status = "okay"; 30 }; 31 32 timer@2080000 { 33 compatible = "nvidia,tegra234-timer"; 34 reg = <0x0 0x02080000 0x0 0x00121000>; 35 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 36 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 37 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 41 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 42 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 43 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 44 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 45 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 46 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 47 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 48 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 49 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 50 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 51 status = "okay"; 52 }; 53 54 gpio: gpio@2200000 { 55 compatible = "nvidia,tegra234-gpio"; 56 reg-names = "security", "gpio"; 57 reg = <0x0 0x02200000 0x0 0x10000>, 58 <0x0 0x02210000 0x0 0x10000>; 59 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 61 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 62 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 63 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 65 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 69 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 70 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 71 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 72 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 73 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 74 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 75 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 77 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 79 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 87 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 88 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 89 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 90 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 91 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 92 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 94 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 107 #interrupt-cells = <2>; 108 interrupt-controller; 109 #gpio-cells = <2>; 110 gpio-controller; 111 }; 112 113 gpcdma: dma-controller@2600000 { 114 compatible = "nvidia,tegra234-gpcdma", 115 "nvidia,tegra186-gpcdma"; 116 reg = <0x0 0x2600000 0x0 0x210000>; 117 resets = <&bpmp TEGRA234_RESET_GPCDMA>; 118 reset-names = "gpcdma"; 119 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 120 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 121 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 122 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 123 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 124 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 125 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 126 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 127 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 128 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 129 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 130 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 131 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 132 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 133 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 134 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 135 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 136 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 137 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 139 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 140 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 141 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 142 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 143 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 144 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 145 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 146 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 147 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 151 #dma-cells = <1>; 152 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 153 dma-channel-mask = <0xfffffffe>; 154 dma-coherent; 155 }; 156 157 aconnect@2900000 { 158 compatible = "nvidia,tegra234-aconnect", 159 "nvidia,tegra210-aconnect"; 160 clocks = <&bpmp TEGRA234_CLK_APE>, 161 <&bpmp TEGRA234_CLK_APB2APE>; 162 clock-names = "ape", "apb2ape"; 163 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_AUD>; 164 status = "disabled"; 165 166 #address-cells = <2>; 167 #size-cells = <2>; 168 ranges = <0x0 0x02900000 0x0 0x02900000 0x0 0x200000>; 169 170 tegra_ahub: ahub@2900800 { 171 compatible = "nvidia,tegra234-ahub"; 172 reg = <0x0 0x02900800 0x0 0x800>; 173 clocks = <&bpmp TEGRA234_CLK_AHUB>; 174 clock-names = "ahub"; 175 assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>; 176 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 177 status = "disabled"; 178 179 #address-cells = <2>; 180 #size-cells = <2>; 181 ranges = <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>; 182 183 tegra_i2s1: i2s@2901000 { 184 compatible = "nvidia,tegra234-i2s", 185 "nvidia,tegra210-i2s"; 186 reg = <0x0 0x2901000 0x0 0x100>; 187 clocks = <&bpmp TEGRA234_CLK_I2S1>, 188 <&bpmp TEGRA234_CLK_I2S1_SYNC_INPUT>; 189 clock-names = "i2s", "sync_input"; 190 assigned-clocks = <&bpmp TEGRA234_CLK_I2S1>; 191 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 192 assigned-clock-rates = <1536000>; 193 sound-name-prefix = "I2S1"; 194 status = "disabled"; 195 }; 196 197 tegra_i2s2: i2s@2901100 { 198 compatible = "nvidia,tegra234-i2s", 199 "nvidia,tegra210-i2s"; 200 reg = <0x0 0x2901100 0x0 0x100>; 201 clocks = <&bpmp TEGRA234_CLK_I2S2>, 202 <&bpmp TEGRA234_CLK_I2S2_SYNC_INPUT>; 203 clock-names = "i2s", "sync_input"; 204 assigned-clocks = <&bpmp TEGRA234_CLK_I2S2>; 205 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 206 assigned-clock-rates = <1536000>; 207 sound-name-prefix = "I2S2"; 208 status = "disabled"; 209 }; 210 211 tegra_i2s3: i2s@2901200 { 212 compatible = "nvidia,tegra234-i2s", 213 "nvidia,tegra210-i2s"; 214 reg = <0x0 0x2901200 0x0 0x100>; 215 clocks = <&bpmp TEGRA234_CLK_I2S3>, 216 <&bpmp TEGRA234_CLK_I2S3_SYNC_INPUT>; 217 clock-names = "i2s", "sync_input"; 218 assigned-clocks = <&bpmp TEGRA234_CLK_I2S3>; 219 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 220 assigned-clock-rates = <1536000>; 221 sound-name-prefix = "I2S3"; 222 status = "disabled"; 223 }; 224 225 tegra_i2s4: i2s@2901300 { 226 compatible = "nvidia,tegra234-i2s", 227 "nvidia,tegra210-i2s"; 228 reg = <0x0 0x2901300 0x0 0x100>; 229 clocks = <&bpmp TEGRA234_CLK_I2S4>, 230 <&bpmp TEGRA234_CLK_I2S4_SYNC_INPUT>; 231 clock-names = "i2s", "sync_input"; 232 assigned-clocks = <&bpmp TEGRA234_CLK_I2S4>; 233 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 234 assigned-clock-rates = <1536000>; 235 sound-name-prefix = "I2S4"; 236 status = "disabled"; 237 }; 238 239 tegra_i2s5: i2s@2901400 { 240 compatible = "nvidia,tegra234-i2s", 241 "nvidia,tegra210-i2s"; 242 reg = <0x0 0x2901400 0x0 0x100>; 243 clocks = <&bpmp TEGRA234_CLK_I2S5>, 244 <&bpmp TEGRA234_CLK_I2S5_SYNC_INPUT>; 245 clock-names = "i2s", "sync_input"; 246 assigned-clocks = <&bpmp TEGRA234_CLK_I2S5>; 247 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 248 assigned-clock-rates = <1536000>; 249 sound-name-prefix = "I2S5"; 250 status = "disabled"; 251 }; 252 253 tegra_i2s6: i2s@2901500 { 254 compatible = "nvidia,tegra234-i2s", 255 "nvidia,tegra210-i2s"; 256 reg = <0x0 0x2901500 0x0 0x100>; 257 clocks = <&bpmp TEGRA234_CLK_I2S6>, 258 <&bpmp TEGRA234_CLK_I2S6_SYNC_INPUT>; 259 clock-names = "i2s", "sync_input"; 260 assigned-clocks = <&bpmp TEGRA234_CLK_I2S6>; 261 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 262 assigned-clock-rates = <1536000>; 263 sound-name-prefix = "I2S6"; 264 status = "disabled"; 265 }; 266 267 tegra_sfc1: sfc@2902000 { 268 compatible = "nvidia,tegra234-sfc", 269 "nvidia,tegra210-sfc"; 270 reg = <0x0 0x2902000 0x0 0x200>; 271 sound-name-prefix = "SFC1"; 272 status = "disabled"; 273 }; 274 275 tegra_sfc2: sfc@2902200 { 276 compatible = "nvidia,tegra234-sfc", 277 "nvidia,tegra210-sfc"; 278 reg = <0x0 0x2902200 0x0 0x200>; 279 sound-name-prefix = "SFC2"; 280 status = "disabled"; 281 }; 282 283 tegra_sfc3: sfc@2902400 { 284 compatible = "nvidia,tegra234-sfc", 285 "nvidia,tegra210-sfc"; 286 reg = <0x0 0x2902400 0x0 0x200>; 287 sound-name-prefix = "SFC3"; 288 status = "disabled"; 289 }; 290 291 tegra_sfc4: sfc@2902600 { 292 compatible = "nvidia,tegra234-sfc", 293 "nvidia,tegra210-sfc"; 294 reg = <0x0 0x2902600 0x0 0x200>; 295 sound-name-prefix = "SFC4"; 296 status = "disabled"; 297 }; 298 299 tegra_amx1: amx@2903000 { 300 compatible = "nvidia,tegra234-amx", 301 "nvidia,tegra194-amx"; 302 reg = <0x0 0x2903000 0x0 0x100>; 303 sound-name-prefix = "AMX1"; 304 status = "disabled"; 305 }; 306 307 tegra_amx2: amx@2903100 { 308 compatible = "nvidia,tegra234-amx", 309 "nvidia,tegra194-amx"; 310 reg = <0x0 0x2903100 0x0 0x100>; 311 sound-name-prefix = "AMX2"; 312 status = "disabled"; 313 }; 314 315 tegra_amx3: amx@2903200 { 316 compatible = "nvidia,tegra234-amx", 317 "nvidia,tegra194-amx"; 318 reg = <0x0 0x2903200 0x0 0x100>; 319 sound-name-prefix = "AMX3"; 320 status = "disabled"; 321 }; 322 323 tegra_amx4: amx@2903300 { 324 compatible = "nvidia,tegra234-amx", 325 "nvidia,tegra194-amx"; 326 reg = <0x0 0x2903300 0x0 0x100>; 327 sound-name-prefix = "AMX4"; 328 status = "disabled"; 329 }; 330 331 tegra_adx1: adx@2903800 { 332 compatible = "nvidia,tegra234-adx", 333 "nvidia,tegra210-adx"; 334 reg = <0x0 0x2903800 0x0 0x100>; 335 sound-name-prefix = "ADX1"; 336 status = "disabled"; 337 }; 338 339 tegra_adx2: adx@2903900 { 340 compatible = "nvidia,tegra234-adx", 341 "nvidia,tegra210-adx"; 342 reg = <0x0 0x2903900 0x0 0x100>; 343 sound-name-prefix = "ADX2"; 344 status = "disabled"; 345 }; 346 347 tegra_adx3: adx@2903a00 { 348 compatible = "nvidia,tegra234-adx", 349 "nvidia,tegra210-adx"; 350 reg = <0x0 0x2903a00 0x0 0x100>; 351 sound-name-prefix = "ADX3"; 352 status = "disabled"; 353 }; 354 355 tegra_adx4: adx@2903b00 { 356 compatible = "nvidia,tegra234-adx", 357 "nvidia,tegra210-adx"; 358 reg = <0x0 0x2903b00 0x0 0x100>; 359 sound-name-prefix = "ADX4"; 360 status = "disabled"; 361 }; 362 363 364 tegra_dmic1: dmic@2904000 { 365 compatible = "nvidia,tegra234-dmic", 366 "nvidia,tegra210-dmic"; 367 reg = <0x0 0x2904000 0x0 0x100>; 368 clocks = <&bpmp TEGRA234_CLK_DMIC1>; 369 clock-names = "dmic"; 370 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC1>; 371 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 372 assigned-clock-rates = <3072000>; 373 sound-name-prefix = "DMIC1"; 374 status = "disabled"; 375 }; 376 377 tegra_dmic2: dmic@2904100 { 378 compatible = "nvidia,tegra234-dmic", 379 "nvidia,tegra210-dmic"; 380 reg = <0x0 0x2904100 0x0 0x100>; 381 clocks = <&bpmp TEGRA234_CLK_DMIC2>; 382 clock-names = "dmic"; 383 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC2>; 384 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 385 assigned-clock-rates = <3072000>; 386 sound-name-prefix = "DMIC2"; 387 status = "disabled"; 388 }; 389 390 tegra_dmic3: dmic@2904200 { 391 compatible = "nvidia,tegra234-dmic", 392 "nvidia,tegra210-dmic"; 393 reg = <0x0 0x2904200 0x0 0x100>; 394 clocks = <&bpmp TEGRA234_CLK_DMIC3>; 395 clock-names = "dmic"; 396 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC3>; 397 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 398 assigned-clock-rates = <3072000>; 399 sound-name-prefix = "DMIC3"; 400 status = "disabled"; 401 }; 402 403 tegra_dmic4: dmic@2904300 { 404 compatible = "nvidia,tegra234-dmic", 405 "nvidia,tegra210-dmic"; 406 reg = <0x0 0x2904300 0x0 0x100>; 407 clocks = <&bpmp TEGRA234_CLK_DMIC4>; 408 clock-names = "dmic"; 409 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC4>; 410 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 411 assigned-clock-rates = <3072000>; 412 sound-name-prefix = "DMIC4"; 413 status = "disabled"; 414 }; 415 416 tegra_dspk1: dspk@2905000 { 417 compatible = "nvidia,tegra234-dspk", 418 "nvidia,tegra186-dspk"; 419 reg = <0x0 0x2905000 0x0 0x100>; 420 clocks = <&bpmp TEGRA234_CLK_DSPK1>; 421 clock-names = "dspk"; 422 assigned-clocks = <&bpmp TEGRA234_CLK_DSPK1>; 423 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 424 assigned-clock-rates = <12288000>; 425 sound-name-prefix = "DSPK1"; 426 status = "disabled"; 427 }; 428 429 tegra_dspk2: dspk@2905100 { 430 compatible = "nvidia,tegra234-dspk", 431 "nvidia,tegra186-dspk"; 432 reg = <0x0 0x2905100 0x0 0x100>; 433 clocks = <&bpmp TEGRA234_CLK_DSPK2>; 434 clock-names = "dspk"; 435 assigned-clocks = <&bpmp TEGRA234_CLK_DSPK2>; 436 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 437 assigned-clock-rates = <12288000>; 438 sound-name-prefix = "DSPK2"; 439 status = "disabled"; 440 }; 441 442 tegra_ope1: processing-engine@2908000 { 443 compatible = "nvidia,tegra234-ope", 444 "nvidia,tegra210-ope"; 445 reg = <0x0 0x2908000 0x0 0x100>; 446 sound-name-prefix = "OPE1"; 447 status = "disabled"; 448 449 #address-cells = <2>; 450 #size-cells = <2>; 451 ranges; 452 453 equalizer@2908100 { 454 compatible = "nvidia,tegra234-peq", 455 "nvidia,tegra210-peq"; 456 reg = <0x0 0x2908100 0x0 0x100>; 457 }; 458 459 dynamic-range-compressor@2908200 { 460 compatible = "nvidia,tegra234-mbdrc", 461 "nvidia,tegra210-mbdrc"; 462 reg = <0x0 0x2908200 0x0 0x200>; 463 }; 464 }; 465 466 tegra_mvc1: mvc@290a000 { 467 compatible = "nvidia,tegra234-mvc", 468 "nvidia,tegra210-mvc"; 469 reg = <0x0 0x290a000 0x0 0x200>; 470 sound-name-prefix = "MVC1"; 471 status = "disabled"; 472 }; 473 474 tegra_mvc2: mvc@290a200 { 475 compatible = "nvidia,tegra234-mvc", 476 "nvidia,tegra210-mvc"; 477 reg = <0x0 0x290a200 0x0 0x200>; 478 sound-name-prefix = "MVC2"; 479 status = "disabled"; 480 }; 481 482 tegra_amixer: amixer@290bb00 { 483 compatible = "nvidia,tegra234-amixer", 484 "nvidia,tegra210-amixer"; 485 reg = <0x0 0x290bb00 0x0 0x800>; 486 sound-name-prefix = "MIXER1"; 487 status = "disabled"; 488 }; 489 490 tegra_admaif: admaif@290f000 { 491 compatible = "nvidia,tegra234-admaif", 492 "nvidia,tegra186-admaif"; 493 reg = <0x0 0x0290f000 0x0 0x1000>; 494 dmas = <&adma 1>, <&adma 1>, 495 <&adma 2>, <&adma 2>, 496 <&adma 3>, <&adma 3>, 497 <&adma 4>, <&adma 4>, 498 <&adma 5>, <&adma 5>, 499 <&adma 6>, <&adma 6>, 500 <&adma 7>, <&adma 7>, 501 <&adma 8>, <&adma 8>, 502 <&adma 9>, <&adma 9>, 503 <&adma 10>, <&adma 10>, 504 <&adma 11>, <&adma 11>, 505 <&adma 12>, <&adma 12>, 506 <&adma 13>, <&adma 13>, 507 <&adma 14>, <&adma 14>, 508 <&adma 15>, <&adma 15>, 509 <&adma 16>, <&adma 16>, 510 <&adma 17>, <&adma 17>, 511 <&adma 18>, <&adma 18>, 512 <&adma 19>, <&adma 19>, 513 <&adma 20>, <&adma 20>; 514 dma-names = "rx1", "tx1", 515 "rx2", "tx2", 516 "rx3", "tx3", 517 "rx4", "tx4", 518 "rx5", "tx5", 519 "rx6", "tx6", 520 "rx7", "tx7", 521 "rx8", "tx8", 522 "rx9", "tx9", 523 "rx10", "tx10", 524 "rx11", "tx11", 525 "rx12", "tx12", 526 "rx13", "tx13", 527 "rx14", "tx14", 528 "rx15", "tx15", 529 "rx16", "tx16", 530 "rx17", "tx17", 531 "rx18", "tx18", 532 "rx19", "tx19", 533 "rx20", "tx20"; 534 interconnects = <&mc TEGRA234_MEMORY_CLIENT_APEDMAR &emc>, 535 <&mc TEGRA234_MEMORY_CLIENT_APEDMAW &emc>; 536 interconnect-names = "dma-mem", "write"; 537 iommus = <&smmu_niso0 TEGRA234_SID_APE>; 538 status = "disabled"; 539 }; 540 541 tegra_asrc: asrc@2910000 { 542 compatible = "nvidia,tegra234-asrc", 543 "nvidia,tegra186-asrc"; 544 reg = <0x0 0x2910000 0x0 0x2000>; 545 sound-name-prefix = "ASRC1"; 546 status = "disabled"; 547 }; 548 }; 549 550 adma: dma-controller@2930000 { 551 compatible = "nvidia,tegra234-adma", 552 "nvidia,tegra186-adma"; 553 reg = <0x0 0x02930000 0x0 0x20000>; 554 interrupt-parent = <&agic>; 555 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 556 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 557 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 558 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 559 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 560 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 562 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 563 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 564 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 565 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 566 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 567 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 568 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 569 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 570 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 571 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 574 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 575 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 576 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 577 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 578 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 579 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 580 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 581 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 582 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 583 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 584 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 587 #dma-cells = <1>; 588 clocks = <&bpmp TEGRA234_CLK_AHUB>; 589 clock-names = "d_audio"; 590 status = "disabled"; 591 }; 592 593 agic: interrupt-controller@2a40000 { 594 compatible = "nvidia,tegra234-agic", 595 "nvidia,tegra210-agic"; 596 #interrupt-cells = <3>; 597 interrupt-controller; 598 reg = <0x0 0x02a41000 0x0 0x1000>, 599 <0x0 0x02a42000 0x0 0x2000>; 600 interrupts = <GIC_SPI 145 601 (GIC_CPU_MASK_SIMPLE(4) | 602 IRQ_TYPE_LEVEL_HIGH)>; 603 clocks = <&bpmp TEGRA234_CLK_APE>; 604 clock-names = "clk"; 605 status = "disabled"; 606 }; 607 }; 608 609 mc: memory-controller@2c00000 { 610 compatible = "nvidia,tegra234-mc"; 611 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ 612 <0x0 0x02c10000 0x0 0x10000>, /* MC Broadcast*/ 613 <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ 614 <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ 615 <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ 616 <0x0 0x02c50000 0x0 0x10000>, /* MC3 */ 617 <0x0 0x02b80000 0x0 0x10000>, /* MC4 */ 618 <0x0 0x02b90000 0x0 0x10000>, /* MC5 */ 619 <0x0 0x02ba0000 0x0 0x10000>, /* MC6 */ 620 <0x0 0x02bb0000 0x0 0x10000>, /* MC7 */ 621 <0x0 0x01700000 0x0 0x10000>, /* MC8 */ 622 <0x0 0x01710000 0x0 0x10000>, /* MC9 */ 623 <0x0 0x01720000 0x0 0x10000>, /* MC10 */ 624 <0x0 0x01730000 0x0 0x10000>, /* MC11 */ 625 <0x0 0x01740000 0x0 0x10000>, /* MC12 */ 626 <0x0 0x01750000 0x0 0x10000>, /* MC13 */ 627 <0x0 0x01760000 0x0 0x10000>, /* MC14 */ 628 <0x0 0x01770000 0x0 0x10000>; /* MC15 */ 629 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", 630 "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", 631 "ch11", "ch12", "ch13", "ch14", "ch15"; 632 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 633 #interconnect-cells = <1>; 634 status = "okay"; 635 636 #address-cells = <2>; 637 #size-cells = <2>; 638 ranges = <0x0 0x01700000 0x0 0x01700000 0x0 0x100000>, 639 <0x0 0x02b80000 0x0 0x02b80000 0x0 0x040000>, 640 <0x0 0x02c00000 0x0 0x02c00000 0x0 0x100000>; 641 642 /* 643 * Bit 39 of addresses passing through the memory 644 * controller selects the XBAR format used when memory 645 * is accessed. This is used to transparently access 646 * memory in the XBAR format used by the discrete GPU 647 * (bit 39 set) or Tegra (bit 39 clear). 648 * 649 * As a consequence, the operating system must ensure 650 * that bit 39 is never used implicitly, for example 651 * via an I/O virtual address mapping of an IOMMU. If 652 * devices require access to the XBAR switch, their 653 * drivers must set this bit explicitly. 654 * 655 * Limit the DMA range for memory clients to [38:0]. 656 */ 657 dma-ranges = <0x0 0x0 0x0 0x0 0x80 0x0>; 658 659 emc: external-memory-controller@2c60000 { 660 compatible = "nvidia,tegra234-emc"; 661 reg = <0x0 0x02c60000 0x0 0x90000>, 662 <0x0 0x01780000 0x0 0x80000>; 663 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 664 clocks = <&bpmp TEGRA234_CLK_EMC>; 665 clock-names = "emc"; 666 status = "okay"; 667 668 #interconnect-cells = <0>; 669 670 nvidia,bpmp = <&bpmp>; 671 }; 672 }; 673 674 uarta: serial@3100000 { 675 compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart"; 676 reg = <0x0 0x03100000 0x0 0x10000>; 677 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 678 clocks = <&bpmp TEGRA234_CLK_UARTA>; 679 clock-names = "serial"; 680 resets = <&bpmp TEGRA234_RESET_UARTA>; 681 reset-names = "serial"; 682 status = "disabled"; 683 }; 684 685 gen1_i2c: i2c@3160000 { 686 compatible = "nvidia,tegra194-i2c"; 687 reg = <0x0 0x3160000 0x0 0x100>; 688 status = "disabled"; 689 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 690 clock-frequency = <400000>; 691 clocks = <&bpmp TEGRA234_CLK_I2C1 692 &bpmp TEGRA234_CLK_PLLP_OUT0>; 693 assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>; 694 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 695 clock-names = "div-clk", "parent"; 696 resets = <&bpmp TEGRA234_RESET_I2C1>; 697 reset-names = "i2c"; 698 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 699 dma-coherent; 700 dmas = <&gpcdma 21>, <&gpcdma 21>; 701 dma-names = "rx", "tx"; 702 }; 703 704 cam_i2c: i2c@3180000 { 705 compatible = "nvidia,tegra194-i2c"; 706 reg = <0x0 0x3180000 0x0 0x100>; 707 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 708 status = "disabled"; 709 clock-frequency = <400000>; 710 clocks = <&bpmp TEGRA234_CLK_I2C3 711 &bpmp TEGRA234_CLK_PLLP_OUT0>; 712 assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>; 713 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 714 clock-names = "div-clk", "parent"; 715 resets = <&bpmp TEGRA234_RESET_I2C3>; 716 reset-names = "i2c"; 717 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 718 dma-coherent; 719 dmas = <&gpcdma 23>, <&gpcdma 23>; 720 dma-names = "rx", "tx"; 721 }; 722 723 dp_aux_ch1_i2c: i2c@3190000 { 724 compatible = "nvidia,tegra194-i2c"; 725 reg = <0x0 0x3190000 0x0 0x100>; 726 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 727 status = "disabled"; 728 clock-frequency = <100000>; 729 clocks = <&bpmp TEGRA234_CLK_I2C4 730 &bpmp TEGRA234_CLK_PLLP_OUT0>; 731 assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>; 732 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 733 clock-names = "div-clk", "parent"; 734 resets = <&bpmp TEGRA234_RESET_I2C4>; 735 reset-names = "i2c"; 736 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 737 dma-coherent; 738 dmas = <&gpcdma 26>, <&gpcdma 26>; 739 dma-names = "rx", "tx"; 740 }; 741 742 dp_aux_ch0_i2c: i2c@31b0000 { 743 compatible = "nvidia,tegra194-i2c"; 744 reg = <0x0 0x31b0000 0x0 0x100>; 745 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 746 status = "disabled"; 747 clock-frequency = <100000>; 748 clocks = <&bpmp TEGRA234_CLK_I2C6 749 &bpmp TEGRA234_CLK_PLLP_OUT0>; 750 assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>; 751 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 752 clock-names = "div-clk", "parent"; 753 resets = <&bpmp TEGRA234_RESET_I2C6>; 754 reset-names = "i2c"; 755 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 756 dma-coherent; 757 dmas = <&gpcdma 30>, <&gpcdma 30>; 758 dma-names = "rx", "tx"; 759 }; 760 761 dp_aux_ch2_i2c: i2c@31c0000 { 762 compatible = "nvidia,tegra194-i2c"; 763 reg = <0x0 0x31c0000 0x0 0x100>; 764 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 765 status = "disabled"; 766 clock-frequency = <100000>; 767 clocks = <&bpmp TEGRA234_CLK_I2C7 768 &bpmp TEGRA234_CLK_PLLP_OUT0>; 769 assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>; 770 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 771 clock-names = "div-clk", "parent"; 772 resets = <&bpmp TEGRA234_RESET_I2C7>; 773 reset-names = "i2c"; 774 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 775 dma-coherent; 776 dmas = <&gpcdma 27>, <&gpcdma 27>; 777 dma-names = "rx", "tx"; 778 }; 779 780 uarti: serial@31d0000 { 781 compatible = "arm,sbsa-uart"; 782 reg = <0x0 0x31d0000 0x0 0x10000>; 783 interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; 784 status = "disabled"; 785 }; 786 787 dp_aux_ch3_i2c: i2c@31e0000 { 788 compatible = "nvidia,tegra194-i2c"; 789 reg = <0x0 0x31e0000 0x0 0x100>; 790 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 791 status = "disabled"; 792 clock-frequency = <100000>; 793 clocks = <&bpmp TEGRA234_CLK_I2C9 794 &bpmp TEGRA234_CLK_PLLP_OUT0>; 795 assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>; 796 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 797 clock-names = "div-clk", "parent"; 798 resets = <&bpmp TEGRA234_RESET_I2C9>; 799 reset-names = "i2c"; 800 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 801 dma-coherent; 802 dmas = <&gpcdma 31>, <&gpcdma 31>; 803 dma-names = "rx", "tx"; 804 }; 805 806 spi@3270000 { 807 compatible = "nvidia,tegra234-qspi"; 808 reg = <0x0 0x3270000 0x0 0x1000>; 809 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 810 #address-cells = <1>; 811 #size-cells = <0>; 812 clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>, 813 <&bpmp TEGRA234_CLK_QSPI0_PM>; 814 clock-names = "qspi", "qspi_out"; 815 resets = <&bpmp TEGRA234_RESET_QSPI0>; 816 status = "disabled"; 817 }; 818 819 pwm1: pwm@3280000 { 820 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 821 reg = <0x0 0x3280000 0x0 0x10000>; 822 clocks = <&bpmp TEGRA234_CLK_PWM1>; 823 resets = <&bpmp TEGRA234_RESET_PWM1>; 824 reset-names = "pwm"; 825 status = "disabled"; 826 #pwm-cells = <2>; 827 }; 828 829 pwm2: pwm@3290000 { 830 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 831 reg = <0x0 0x3290000 0x0 0x10000>; 832 clocks = <&bpmp TEGRA234_CLK_PWM2>; 833 resets = <&bpmp TEGRA234_RESET_PWM2>; 834 reset-names = "pwm"; 835 status = "disabled"; 836 #pwm-cells = <2>; 837 }; 838 839 pwm3: pwm@32a0000 { 840 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 841 reg = <0x0 0x32a0000 0x0 0x10000>; 842 clocks = <&bpmp TEGRA234_CLK_PWM3>; 843 resets = <&bpmp TEGRA234_RESET_PWM3>; 844 reset-names = "pwm"; 845 status = "disabled"; 846 #pwm-cells = <2>; 847 }; 848 849 pwm5: pwm@32c0000 { 850 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 851 reg = <0x0 0x32c0000 0x0 0x10000>; 852 clocks = <&bpmp TEGRA234_CLK_PWM5>; 853 resets = <&bpmp TEGRA234_RESET_PWM5>; 854 reset-names = "pwm"; 855 status = "disabled"; 856 #pwm-cells = <2>; 857 }; 858 859 pwm6: pwm@32d0000 { 860 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 861 reg = <0x0 0x32d0000 0x0 0x10000>; 862 clocks = <&bpmp TEGRA234_CLK_PWM6>; 863 resets = <&bpmp TEGRA234_RESET_PWM6>; 864 reset-names = "pwm"; 865 status = "disabled"; 866 #pwm-cells = <2>; 867 }; 868 869 pwm7: pwm@32e0000 { 870 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 871 reg = <0x0 0x32e0000 0x0 0x10000>; 872 clocks = <&bpmp TEGRA234_CLK_PWM7>; 873 resets = <&bpmp TEGRA234_RESET_PWM7>; 874 reset-names = "pwm"; 875 status = "disabled"; 876 #pwm-cells = <2>; 877 }; 878 879 pwm8: pwm@32f0000 { 880 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 881 reg = <0x0 0x32f0000 0x0 0x10000>; 882 clocks = <&bpmp TEGRA234_CLK_PWM8>; 883 resets = <&bpmp TEGRA234_RESET_PWM8>; 884 reset-names = "pwm"; 885 status = "disabled"; 886 #pwm-cells = <2>; 887 }; 888 889 spi@3300000 { 890 compatible = "nvidia,tegra234-qspi"; 891 reg = <0x0 0x3300000 0x0 0x1000>; 892 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 893 #address-cells = <1>; 894 #size-cells = <0>; 895 clocks = <&bpmp TEGRA234_CLK_QSPI1_2X_PM>, 896 <&bpmp TEGRA234_CLK_QSPI1_PM>; 897 clock-names = "qspi", "qspi_out"; 898 resets = <&bpmp TEGRA234_RESET_QSPI1>; 899 status = "disabled"; 900 }; 901 902 mmc@3400000 { 903 compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; 904 reg = <0x0 0x03400000 0x0 0x20000>; 905 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 906 clocks = <&bpmp TEGRA234_CLK_SDMMC1>, 907 <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; 908 clock-names = "sdhci", "tmclk"; 909 assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC1>, 910 <&bpmp TEGRA234_CLK_PLLC4_MUXED>; 911 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4_MUXED>, 912 <&bpmp TEGRA234_CLK_PLLC4_VCO_DIV2>; 913 resets = <&bpmp TEGRA234_RESET_SDMMC1>; 914 reset-names = "sdhci"; 915 interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRA &emc>, 916 <&mc TEGRA234_MEMORY_CLIENT_SDMMCWA &emc>; 917 interconnect-names = "dma-mem", "write"; 918 iommus = <&smmu_niso1 TEGRA234_SID_SDMMC1A>; 919 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 920 pinctrl-0 = <&sdmmc1_3v3>; 921 pinctrl-1 = <&sdmmc1_1v8>; 922 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 923 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x07>; 924 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 925 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 926 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 927 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 928 nvidia,default-tap = <14>; 929 nvidia,default-trim = <0x8>; 930 sd-uhs-sdr25; 931 sd-uhs-sdr50; 932 sd-uhs-ddr50; 933 sd-uhs-sdr104; 934 status = "disabled"; 935 }; 936 937 mmc@3460000 { 938 compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; 939 reg = <0x0 0x03460000 0x0 0x20000>; 940 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 941 clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 942 <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; 943 clock-names = "sdhci", "tmclk"; 944 assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 945 <&bpmp TEGRA234_CLK_PLLC4>; 946 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>; 947 resets = <&bpmp TEGRA234_RESET_SDMMC4>; 948 reset-names = "sdhci"; 949 interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRAB &emc>, 950 <&mc TEGRA234_MEMORY_CLIENT_SDMMCWAB &emc>; 951 interconnect-names = "dma-mem", "write"; 952 iommus = <&smmu_niso1 TEGRA234_SID_SDMMC4>; 953 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 954 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 955 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 956 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 957 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 958 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 959 nvidia,default-tap = <0x8>; 960 nvidia,default-trim = <0x14>; 961 nvidia,dqs-trim = <40>; 962 supports-cqe; 963 status = "disabled"; 964 }; 965 966 hda@3510000 { 967 compatible = "nvidia,tegra234-hda"; 968 reg = <0x0 0x3510000 0x0 0x10000>; 969 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 970 clocks = <&bpmp TEGRA234_CLK_AZA_BIT>, 971 <&bpmp TEGRA234_CLK_AZA_2XBIT>; 972 clock-names = "hda", "hda2codec_2x"; 973 resets = <&bpmp TEGRA234_RESET_HDA>, 974 <&bpmp TEGRA234_RESET_HDACODEC>; 975 reset-names = "hda", "hda2codec_2x"; 976 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DISP>; 977 interconnects = <&mc TEGRA234_MEMORY_CLIENT_HDAR &emc>, 978 <&mc TEGRA234_MEMORY_CLIENT_HDAW &emc>; 979 interconnect-names = "dma-mem", "write"; 980 iommus = <&smmu_niso0 TEGRA234_SID_HDA>; 981 status = "disabled"; 982 }; 983 984 xusb_padctl: padctl@3520000 { 985 compatible = "nvidia,tegra234-xusb-padctl"; 986 reg = <0x0 0x03520000 0x0 0x20000>, 987 <0x0 0x03540000 0x0 0x10000>; 988 reg-names = "padctl", "ao"; 989 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 990 991 resets = <&bpmp TEGRA234_RESET_XUSB_PADCTL>; 992 reset-names = "padctl"; 993 994 status = "disabled"; 995 996 pads { 997 usb2 { 998 clocks = <&bpmp TEGRA234_CLK_USB2_TRK>; 999 clock-names = "trk"; 1000 1001 lanes { 1002 usb2-0 { 1003 nvidia,function = "xusb"; 1004 status = "disabled"; 1005 #phy-cells = <0>; 1006 }; 1007 1008 usb2-1 { 1009 nvidia,function = "xusb"; 1010 status = "disabled"; 1011 #phy-cells = <0>; 1012 }; 1013 1014 usb2-2 { 1015 nvidia,function = "xusb"; 1016 status = "disabled"; 1017 #phy-cells = <0>; 1018 }; 1019 1020 usb2-3 { 1021 nvidia,function = "xusb"; 1022 status = "disabled"; 1023 #phy-cells = <0>; 1024 }; 1025 }; 1026 }; 1027 1028 usb3 { 1029 lanes { 1030 usb3-0 { 1031 nvidia,function = "xusb"; 1032 status = "disabled"; 1033 #phy-cells = <0>; 1034 }; 1035 1036 usb3-1 { 1037 nvidia,function = "xusb"; 1038 status = "disabled"; 1039 #phy-cells = <0>; 1040 }; 1041 1042 usb3-2 { 1043 nvidia,function = "xusb"; 1044 status = "disabled"; 1045 #phy-cells = <0>; 1046 }; 1047 1048 usb3-3 { 1049 nvidia,function = "xusb"; 1050 status = "disabled"; 1051 #phy-cells = <0>; 1052 }; 1053 }; 1054 }; 1055 }; 1056 1057 ports { 1058 usb2-0 { 1059 status = "disabled"; 1060 }; 1061 1062 usb2-1 { 1063 status = "disabled"; 1064 }; 1065 1066 usb2-2 { 1067 status = "disabled"; 1068 }; 1069 1070 usb2-3 { 1071 status = "disabled"; 1072 }; 1073 1074 usb3-0 { 1075 status = "disabled"; 1076 }; 1077 1078 usb3-1 { 1079 status = "disabled"; 1080 }; 1081 1082 usb3-2 { 1083 status = "disabled"; 1084 }; 1085 1086 usb3-3 { 1087 status = "disabled"; 1088 }; 1089 }; 1090 }; 1091 1092 usb@3610000 { 1093 compatible = "nvidia,tegra234-xusb"; 1094 reg = <0x0 0x03610000 0x0 0x40000>, 1095 <0x0 0x03600000 0x0 0x10000>, 1096 <0x0 0x03650000 0x0 0x10000>; 1097 reg-names = "hcd", "fpci", "bar2"; 1098 1099 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1100 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1101 1102 clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_HOST>, 1103 <&bpmp TEGRA234_CLK_XUSB_FALCON>, 1104 <&bpmp TEGRA234_CLK_XUSB_CORE_SS>, 1105 <&bpmp TEGRA234_CLK_XUSB_SS>, 1106 <&bpmp TEGRA234_CLK_CLK_M>, 1107 <&bpmp TEGRA234_CLK_XUSB_FS>, 1108 <&bpmp TEGRA234_CLK_UTMIP_PLL>, 1109 <&bpmp TEGRA234_CLK_CLK_M>, 1110 <&bpmp TEGRA234_CLK_PLLE>; 1111 clock-names = "xusb_host", "xusb_falcon_src", 1112 "xusb_ss", "xusb_ss_src", "xusb_hs_src", 1113 "xusb_fs_src", "pll_u_480m", "clk_m", 1114 "pll_e"; 1115 interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1116 <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1117 interconnect-names = "dma-mem", "write"; 1118 iommus = <&smmu_niso1 TEGRA234_SID_XUSB_HOST>; 1119 1120 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBC>, 1121 <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>; 1122 power-domain-names = "xusb_host", "xusb_ss"; 1123 1124 nvidia,xusb-padctl = <&xusb_padctl>; 1125 dma-coherent; 1126 status = "disabled"; 1127 }; 1128 1129 fuse@3810000 { 1130 compatible = "nvidia,tegra234-efuse"; 1131 reg = <0x0 0x03810000 0x0 0x10000>; 1132 clocks = <&bpmp TEGRA234_CLK_FUSE>; 1133 clock-names = "fuse"; 1134 }; 1135 1136 hsp_top0: hsp@3c00000 { 1137 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 1138 reg = <0x0 0x03c00000 0x0 0xa0000>; 1139 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1140 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1141 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1142 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1143 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1144 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1145 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1146 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1147 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1148 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 1149 "shared3", "shared4", "shared5", "shared6", 1150 "shared7"; 1151 #mbox-cells = <2>; 1152 }; 1153 1154 p2u_hsio_0: phy@3e00000 { 1155 compatible = "nvidia,tegra234-p2u"; 1156 reg = <0x0 0x03e00000 0x0 0x10000>; 1157 reg-names = "ctl"; 1158 1159 #phy-cells = <0>; 1160 }; 1161 1162 p2u_hsio_1: phy@3e10000 { 1163 compatible = "nvidia,tegra234-p2u"; 1164 reg = <0x0 0x03e10000 0x0 0x10000>; 1165 reg-names = "ctl"; 1166 1167 #phy-cells = <0>; 1168 }; 1169 1170 p2u_hsio_2: phy@3e20000 { 1171 compatible = "nvidia,tegra234-p2u"; 1172 reg = <0x0 0x03e20000 0x0 0x10000>; 1173 reg-names = "ctl"; 1174 1175 #phy-cells = <0>; 1176 }; 1177 1178 p2u_hsio_3: phy@3e30000 { 1179 compatible = "nvidia,tegra234-p2u"; 1180 reg = <0x0 0x03e30000 0x0 0x10000>; 1181 reg-names = "ctl"; 1182 1183 #phy-cells = <0>; 1184 }; 1185 1186 p2u_hsio_4: phy@3e40000 { 1187 compatible = "nvidia,tegra234-p2u"; 1188 reg = <0x0 0x03e40000 0x0 0x10000>; 1189 reg-names = "ctl"; 1190 1191 #phy-cells = <0>; 1192 }; 1193 1194 p2u_hsio_5: phy@3e50000 { 1195 compatible = "nvidia,tegra234-p2u"; 1196 reg = <0x0 0x03e50000 0x0 0x10000>; 1197 reg-names = "ctl"; 1198 1199 #phy-cells = <0>; 1200 }; 1201 1202 p2u_hsio_6: phy@3e60000 { 1203 compatible = "nvidia,tegra234-p2u"; 1204 reg = <0x0 0x03e60000 0x0 0x10000>; 1205 reg-names = "ctl"; 1206 1207 #phy-cells = <0>; 1208 }; 1209 1210 p2u_hsio_7: phy@3e70000 { 1211 compatible = "nvidia,tegra234-p2u"; 1212 reg = <0x0 0x03e70000 0x0 0x10000>; 1213 reg-names = "ctl"; 1214 1215 #phy-cells = <0>; 1216 }; 1217 1218 p2u_nvhs_0: phy@3e90000 { 1219 compatible = "nvidia,tegra234-p2u"; 1220 reg = <0x0 0x03e90000 0x0 0x10000>; 1221 reg-names = "ctl"; 1222 1223 #phy-cells = <0>; 1224 }; 1225 1226 p2u_nvhs_1: phy@3ea0000 { 1227 compatible = "nvidia,tegra234-p2u"; 1228 reg = <0x0 0x03ea0000 0x0 0x10000>; 1229 reg-names = "ctl"; 1230 1231 #phy-cells = <0>; 1232 }; 1233 1234 p2u_nvhs_2: phy@3eb0000 { 1235 compatible = "nvidia,tegra234-p2u"; 1236 reg = <0x0 0x03eb0000 0x0 0x10000>; 1237 reg-names = "ctl"; 1238 1239 #phy-cells = <0>; 1240 }; 1241 1242 p2u_nvhs_3: phy@3ec0000 { 1243 compatible = "nvidia,tegra234-p2u"; 1244 reg = <0x0 0x03ec0000 0x0 0x10000>; 1245 reg-names = "ctl"; 1246 1247 #phy-cells = <0>; 1248 }; 1249 1250 p2u_nvhs_4: phy@3ed0000 { 1251 compatible = "nvidia,tegra234-p2u"; 1252 reg = <0x0 0x03ed0000 0x0 0x10000>; 1253 reg-names = "ctl"; 1254 1255 #phy-cells = <0>; 1256 }; 1257 1258 p2u_nvhs_5: phy@3ee0000 { 1259 compatible = "nvidia,tegra234-p2u"; 1260 reg = <0x0 0x03ee0000 0x0 0x10000>; 1261 reg-names = "ctl"; 1262 1263 #phy-cells = <0>; 1264 }; 1265 1266 p2u_nvhs_6: phy@3ef0000 { 1267 compatible = "nvidia,tegra234-p2u"; 1268 reg = <0x0 0x03ef0000 0x0 0x10000>; 1269 reg-names = "ctl"; 1270 1271 #phy-cells = <0>; 1272 }; 1273 1274 p2u_nvhs_7: phy@3f00000 { 1275 compatible = "nvidia,tegra234-p2u"; 1276 reg = <0x0 0x03f00000 0x0 0x10000>; 1277 reg-names = "ctl"; 1278 1279 #phy-cells = <0>; 1280 }; 1281 1282 p2u_gbe_0: phy@3f20000 { 1283 compatible = "nvidia,tegra234-p2u"; 1284 reg = <0x0 0x03f20000 0x0 0x10000>; 1285 reg-names = "ctl"; 1286 1287 #phy-cells = <0>; 1288 }; 1289 1290 p2u_gbe_1: phy@3f30000 { 1291 compatible = "nvidia,tegra234-p2u"; 1292 reg = <0x0 0x03f30000 0x0 0x10000>; 1293 reg-names = "ctl"; 1294 1295 #phy-cells = <0>; 1296 }; 1297 1298 p2u_gbe_2: phy@3f40000 { 1299 compatible = "nvidia,tegra234-p2u"; 1300 reg = <0x0 0x03f40000 0x0 0x10000>; 1301 reg-names = "ctl"; 1302 1303 #phy-cells = <0>; 1304 }; 1305 1306 p2u_gbe_3: phy@3f50000 { 1307 compatible = "nvidia,tegra234-p2u"; 1308 reg = <0x0 0x03f50000 0x0 0x10000>; 1309 reg-names = "ctl"; 1310 1311 #phy-cells = <0>; 1312 }; 1313 1314 p2u_gbe_4: phy@3f60000 { 1315 compatible = "nvidia,tegra234-p2u"; 1316 reg = <0x0 0x03f60000 0x0 0x10000>; 1317 reg-names = "ctl"; 1318 1319 #phy-cells = <0>; 1320 }; 1321 1322 p2u_gbe_5: phy@3f70000 { 1323 compatible = "nvidia,tegra234-p2u"; 1324 reg = <0x0 0x03f70000 0x0 0x10000>; 1325 reg-names = "ctl"; 1326 1327 #phy-cells = <0>; 1328 }; 1329 1330 p2u_gbe_6: phy@3f80000 { 1331 compatible = "nvidia,tegra234-p2u"; 1332 reg = <0x0 0x03f80000 0x0 0x10000>; 1333 reg-names = "ctl"; 1334 1335 #phy-cells = <0>; 1336 }; 1337 1338 p2u_gbe_7: phy@3f90000 { 1339 compatible = "nvidia,tegra234-p2u"; 1340 reg = <0x0 0x03f90000 0x0 0x10000>; 1341 reg-names = "ctl"; 1342 1343 #phy-cells = <0>; 1344 }; 1345 1346 ethernet@6800000 { 1347 compatible = "nvidia,tegra234-mgbe"; 1348 reg = <0x0 0x06800000 0x0 0x10000>, 1349 <0x0 0x06810000 0x0 0x10000>, 1350 <0x0 0x068a0000 0x0 0x10000>; 1351 reg-names = "hypervisor", "mac", "xpcs"; 1352 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; 1353 interrupt-names = "common"; 1354 clocks = <&bpmp TEGRA234_CLK_MGBE0_APP>, 1355 <&bpmp TEGRA234_CLK_MGBE0_MAC>, 1356 <&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>, 1357 <&bpmp TEGRA234_CLK_MGBE0_PTP_REF>, 1358 <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>, 1359 <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>, 1360 <&bpmp TEGRA234_CLK_MGBE0_TX>, 1361 <&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>, 1362 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>, 1363 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>, 1364 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS>, 1365 <&bpmp TEGRA234_CLK_MGBE0_TX_PCS>; 1366 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1367 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1368 "rx-pcs", "tx-pcs"; 1369 resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>, 1370 <&bpmp TEGRA234_RESET_MGBE0_PCS>; 1371 reset-names = "mac", "pcs"; 1372 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEARD &emc>, 1373 <&mc TEGRA234_MEMORY_CLIENT_MGBEAWR &emc>; 1374 interconnect-names = "dma-mem", "write"; 1375 iommus = <&smmu_niso0 TEGRA234_SID_MGBE>; 1376 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEA>; 1377 status = "disabled"; 1378 }; 1379 1380 ethernet@6900000 { 1381 compatible = "nvidia,tegra234-mgbe"; 1382 reg = <0x0 0x06900000 0x0 0x10000>, 1383 <0x0 0x06910000 0x0 0x10000>, 1384 <0x0 0x069a0000 0x0 0x10000>; 1385 reg-names = "hypervisor", "mac", "xpcs"; 1386 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>; 1387 interrupt-names = "common"; 1388 clocks = <&bpmp TEGRA234_CLK_MGBE1_APP>, 1389 <&bpmp TEGRA234_CLK_MGBE1_MAC>, 1390 <&bpmp TEGRA234_CLK_MGBE1_MAC_DIVIDER>, 1391 <&bpmp TEGRA234_CLK_MGBE1_PTP_REF>, 1392 <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT_M>, 1393 <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT>, 1394 <&bpmp TEGRA234_CLK_MGBE1_TX>, 1395 <&bpmp TEGRA234_CLK_MGBE1_EEE_PCS>, 1396 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_INPUT>, 1397 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_M>, 1398 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS>, 1399 <&bpmp TEGRA234_CLK_MGBE1_TX_PCS>; 1400 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1401 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1402 "rx-pcs", "tx-pcs"; 1403 resets = <&bpmp TEGRA234_RESET_MGBE1_MAC>, 1404 <&bpmp TEGRA234_RESET_MGBE1_PCS>; 1405 reset-names = "mac", "pcs"; 1406 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEBRD &emc>, 1407 <&mc TEGRA234_MEMORY_CLIENT_MGBEBWR &emc>; 1408 interconnect-names = "dma-mem", "write"; 1409 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF1>; 1410 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEB>; 1411 status = "disabled"; 1412 }; 1413 1414 ethernet@6a00000 { 1415 compatible = "nvidia,tegra234-mgbe"; 1416 reg = <0x0 0x06a00000 0x0 0x10000>, 1417 <0x0 0x06a10000 0x0 0x10000>, 1418 <0x0 0x06aa0000 0x0 0x10000>; 1419 reg-names = "hypervisor", "mac", "xpcs"; 1420 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>; 1421 interrupt-names = "common"; 1422 clocks = <&bpmp TEGRA234_CLK_MGBE2_APP>, 1423 <&bpmp TEGRA234_CLK_MGBE2_MAC>, 1424 <&bpmp TEGRA234_CLK_MGBE2_MAC_DIVIDER>, 1425 <&bpmp TEGRA234_CLK_MGBE2_PTP_REF>, 1426 <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT_M>, 1427 <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT>, 1428 <&bpmp TEGRA234_CLK_MGBE2_TX>, 1429 <&bpmp TEGRA234_CLK_MGBE2_EEE_PCS>, 1430 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_INPUT>, 1431 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_M>, 1432 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS>, 1433 <&bpmp TEGRA234_CLK_MGBE2_TX_PCS>; 1434 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1435 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1436 "rx-pcs", "tx-pcs"; 1437 resets = <&bpmp TEGRA234_RESET_MGBE2_MAC>, 1438 <&bpmp TEGRA234_RESET_MGBE2_PCS>; 1439 reset-names = "mac", "pcs"; 1440 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBECRD &emc>, 1441 <&mc TEGRA234_MEMORY_CLIENT_MGBECWR &emc>; 1442 interconnect-names = "dma-mem", "write"; 1443 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF2>; 1444 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEC>; 1445 status = "disabled"; 1446 }; 1447 1448 ethernet@6b00000 { 1449 compatible = "nvidia,tegra234-mgbe"; 1450 reg = <0x0 0x06b00000 0x0 0x10000>, 1451 <0x0 0x06b10000 0x0 0x10000>, 1452 <0x0 0x06ba0000 0x0 0x10000>; 1453 reg-names = "hypervisor", "mac", "xpcs"; 1454 interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 1455 interrupt-names = "common"; 1456 clocks = <&bpmp TEGRA234_CLK_MGBE3_APP>, 1457 <&bpmp TEGRA234_CLK_MGBE3_MAC>, 1458 <&bpmp TEGRA234_CLK_MGBE3_MAC_DIVIDER>, 1459 <&bpmp TEGRA234_CLK_MGBE3_PTP_REF>, 1460 <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT_M>, 1461 <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT>, 1462 <&bpmp TEGRA234_CLK_MGBE3_TX>, 1463 <&bpmp TEGRA234_CLK_MGBE3_EEE_PCS>, 1464 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_INPUT>, 1465 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_M>, 1466 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS>, 1467 <&bpmp TEGRA234_CLK_MGBE3_TX_PCS>; 1468 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1469 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1470 "rx-pcs", "tx-pcs"; 1471 resets = <&bpmp TEGRA234_RESET_MGBE3_MAC>, 1472 <&bpmp TEGRA234_RESET_MGBE3_PCS>; 1473 reset-names = "mac", "pcs"; 1474 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEDRD &emc>, 1475 <&mc TEGRA234_MEMORY_CLIENT_MGBEDWR &emc>; 1476 interconnect-names = "dma-mem", "write"; 1477 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF3>; 1478 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBED>; 1479 status = "disabled"; 1480 }; 1481 1482 smmu_niso1: iommu@8000000 { 1483 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 1484 reg = <0x0 0x8000000 0x0 0x1000000>, 1485 <0x0 0x7000000 0x0 0x1000000>; 1486 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1487 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 1488 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1489 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 1490 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1491 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1492 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1493 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1494 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1495 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1496 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1497 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1498 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1499 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1500 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1501 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1502 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1503 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1504 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1505 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1506 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1507 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1508 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1509 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1510 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1511 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1512 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1513 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1514 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1515 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1516 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1517 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1518 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1519 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1520 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1521 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1522 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1523 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1524 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1525 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1526 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1527 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1528 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1529 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1530 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1531 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1532 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1533 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1534 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1535 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1536 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1537 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1538 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1539 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1540 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1541 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1542 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1543 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1544 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1545 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1546 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1547 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1548 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1549 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1550 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1551 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1552 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1553 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1554 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1555 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1556 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1557 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1558 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1559 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1560 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1561 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1562 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1563 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1564 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1565 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1566 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1567 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1568 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1569 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1570 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1571 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1572 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1573 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1574 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1575 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1576 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1577 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1578 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1579 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1580 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1581 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1582 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1583 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1584 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1585 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1586 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1587 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1588 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1589 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1590 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1591 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1592 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1593 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1594 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1595 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1596 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1597 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1598 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1599 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1600 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1601 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1602 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1603 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1604 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1605 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1606 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1607 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1608 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1609 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1610 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1611 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1612 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1613 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1614 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1615 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1616 stream-match-mask = <0x7f80>; 1617 #global-interrupts = <2>; 1618 #iommu-cells = <1>; 1619 1620 nvidia,memory-controller = <&mc>; 1621 status = "okay"; 1622 }; 1623 1624 sce-fabric@b600000 { 1625 compatible = "nvidia,tegra234-sce-fabric"; 1626 reg = <0x0 0xb600000 0x0 0x40000>; 1627 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 1628 status = "okay"; 1629 }; 1630 1631 rce-fabric@be00000 { 1632 compatible = "nvidia,tegra234-rce-fabric"; 1633 reg = <0x0 0xbe00000 0x0 0x40000>; 1634 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1635 status = "okay"; 1636 }; 1637 1638 hsp_aon: hsp@c150000 { 1639 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 1640 reg = <0x0 0x0c150000 0x0 0x90000>; 1641 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1642 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1643 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1644 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1645 /* 1646 * Shared interrupt 0 is routed only to AON/SPE, so 1647 * we only have 4 shared interrupts for the CCPLEX. 1648 */ 1649 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 1650 #mbox-cells = <2>; 1651 }; 1652 1653 gen2_i2c: i2c@c240000 { 1654 compatible = "nvidia,tegra194-i2c"; 1655 reg = <0x0 0xc240000 0x0 0x100>; 1656 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1657 status = "disabled"; 1658 clock-frequency = <100000>; 1659 clocks = <&bpmp TEGRA234_CLK_I2C2 1660 &bpmp TEGRA234_CLK_PLLP_OUT0>; 1661 clock-names = "div-clk", "parent"; 1662 assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>; 1663 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 1664 resets = <&bpmp TEGRA234_RESET_I2C2>; 1665 reset-names = "i2c"; 1666 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 1667 dma-coherent; 1668 dmas = <&gpcdma 22>, <&gpcdma 22>; 1669 dma-names = "rx", "tx"; 1670 }; 1671 1672 gen8_i2c: i2c@c250000 { 1673 compatible = "nvidia,tegra194-i2c"; 1674 reg = <0x0 0xc250000 0x0 0x100>; 1675 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1676 status = "disabled"; 1677 clock-frequency = <400000>; 1678 clocks = <&bpmp TEGRA234_CLK_I2C8 1679 &bpmp TEGRA234_CLK_PLLP_OUT0>; 1680 clock-names = "div-clk", "parent"; 1681 assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>; 1682 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 1683 resets = <&bpmp TEGRA234_RESET_I2C8>; 1684 reset-names = "i2c"; 1685 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 1686 dma-coherent; 1687 dmas = <&gpcdma 0>, <&gpcdma 0>; 1688 dma-names = "rx", "tx"; 1689 }; 1690 1691 rtc@c2a0000 { 1692 compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc"; 1693 reg = <0x0 0x0c2a0000 0x0 0x10000>; 1694 interrupt-parent = <&pmc>; 1695 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1696 clocks = <&bpmp TEGRA234_CLK_CLK_32K>; 1697 clock-names = "rtc"; 1698 status = "disabled"; 1699 }; 1700 1701 gpio_aon: gpio@c2f0000 { 1702 compatible = "nvidia,tegra234-gpio-aon"; 1703 reg-names = "security", "gpio"; 1704 reg = <0x0 0x0c2f0000 0x0 0x1000>, 1705 <0x0 0x0c2f1000 0x0 0x1000>; 1706 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1707 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1708 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1709 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1710 #interrupt-cells = <2>; 1711 interrupt-controller; 1712 #gpio-cells = <2>; 1713 gpio-controller; 1714 }; 1715 1716 pwm4: pwm@c340000 { 1717 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 1718 reg = <0x0 0xc340000 0x0 0x10000>; 1719 clocks = <&bpmp TEGRA234_CLK_PWM4>; 1720 resets = <&bpmp TEGRA234_RESET_PWM4>; 1721 reset-names = "pwm"; 1722 status = "disabled"; 1723 #pwm-cells = <2>; 1724 }; 1725 1726 pmc: pmc@c360000 { 1727 compatible = "nvidia,tegra234-pmc"; 1728 reg = <0x0 0x0c360000 0x0 0x10000>, 1729 <0x0 0x0c370000 0x0 0x10000>, 1730 <0x0 0x0c380000 0x0 0x10000>, 1731 <0x0 0x0c390000 0x0 0x10000>, 1732 <0x0 0x0c3a0000 0x0 0x10000>; 1733 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 1734 1735 #interrupt-cells = <2>; 1736 interrupt-controller; 1737 1738 sdmmc1_1v8: sdmmc1-1v8 { 1739 pins = "sdmmc1-hv"; 1740 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1741 }; 1742 1743 sdmmc1_3v3: sdmmc1-3v3 { 1744 pins = "sdmmc1-hv"; 1745 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1746 }; 1747 1748 sdmmc3_1v8: sdmmc3-1v8 { 1749 pins = "sdmmc3-hv"; 1750 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1751 }; 1752 1753 sdmmc3_3v3: sdmmc3-3v3 { 1754 pins = "sdmmc3-hv"; 1755 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1756 }; 1757 }; 1758 1759 aon-fabric@c600000 { 1760 compatible = "nvidia,tegra234-aon-fabric"; 1761 reg = <0x0 0xc600000 0x0 0x40000>; 1762 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 1763 status = "okay"; 1764 }; 1765 1766 bpmp-fabric@d600000 { 1767 compatible = "nvidia,tegra234-bpmp-fabric"; 1768 reg = <0x0 0xd600000 0x0 0x40000>; 1769 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1770 status = "okay"; 1771 }; 1772 1773 dce-fabric@de00000 { 1774 compatible = "nvidia,tegra234-sce-fabric"; 1775 reg = <0x0 0xde00000 0x0 0x40000>; 1776 interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>; 1777 status = "okay"; 1778 }; 1779 1780 ccplex@e000000 { 1781 compatible = "nvidia,tegra234-ccplex-cluster"; 1782 reg = <0x0 0x0e000000 0x0 0x5ffff>; 1783 nvidia,bpmp = <&bpmp>; 1784 status = "okay"; 1785 }; 1786 1787 gic: interrupt-controller@f400000 { 1788 compatible = "arm,gic-v3"; 1789 reg = <0x0 0x0f400000 0x0 0x010000>, /* GICD */ 1790 <0x0 0x0f440000 0x0 0x200000>; /* GICR */ 1791 interrupt-parent = <&gic>; 1792 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1793 1794 #redistributor-regions = <1>; 1795 #interrupt-cells = <3>; 1796 interrupt-controller; 1797 }; 1798 1799 smmu_iso: iommu@10000000 { 1800 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 1801 reg = <0x0 0x10000000 0x0 0x1000000>; 1802 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1803 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1804 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1805 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1806 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1807 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1808 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1809 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1810 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1811 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1812 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1813 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1814 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1815 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1816 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1817 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1818 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1819 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1820 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1821 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1822 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1823 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1824 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1825 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1826 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1827 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1828 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1829 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1830 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1831 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1832 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1833 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1834 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1835 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1836 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1837 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1838 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1839 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1840 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1841 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1842 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1843 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1844 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1845 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1846 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1847 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1848 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1849 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1850 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1851 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1852 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1853 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1854 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1855 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1856 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1857 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1858 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1859 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1860 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1861 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1862 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1863 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1864 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1865 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1866 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1867 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1868 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1869 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1870 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1871 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1872 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1873 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1874 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1875 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1876 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1877 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1878 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1879 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1880 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1881 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1882 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1883 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1884 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1885 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1886 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1887 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1888 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1889 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1890 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1891 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1892 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1893 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1894 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1895 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1896 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1897 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1898 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1899 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1900 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1901 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1902 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1903 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1904 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1905 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1906 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1907 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1908 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1909 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1910 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1911 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1912 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1913 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1914 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1915 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1916 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1917 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1918 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1919 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1920 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1921 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1922 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1923 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1924 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1925 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1926 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1927 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1928 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1929 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1930 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1931 stream-match-mask = <0x7f80>; 1932 #global-interrupts = <1>; 1933 #iommu-cells = <1>; 1934 1935 nvidia,memory-controller = <&mc>; 1936 status = "okay"; 1937 }; 1938 1939 smmu_niso0: iommu@12000000 { 1940 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 1941 reg = <0x0 0x12000000 0x0 0x1000000>, 1942 <0x0 0x11000000 0x0 0x1000000>; 1943 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1944 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1945 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1946 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1947 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1948 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1949 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1950 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1951 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1952 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1953 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1954 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1955 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1956 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1957 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1958 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1959 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1960 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1961 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1962 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1963 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1964 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1965 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1966 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1967 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1968 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1969 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1970 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1971 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1972 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1973 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1974 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1975 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1976 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1977 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1978 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1979 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1980 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1981 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1982 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1983 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1984 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1985 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1986 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1987 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1988 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1989 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1990 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1991 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1992 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1993 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1994 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1995 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1996 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1997 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1998 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1999 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2000 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2001 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2002 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2003 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2004 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2005 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2006 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2007 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2008 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2009 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2010 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2011 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2012 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2013 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2014 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2015 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2016 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2017 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2018 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2019 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2020 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2021 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2022 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2023 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2024 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2025 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2026 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2027 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2028 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2029 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2030 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2031 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2032 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2033 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2034 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2035 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2036 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2037 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2038 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2039 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2040 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2041 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2042 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2043 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2044 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2045 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2046 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2047 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2048 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2049 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2050 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2051 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2052 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2053 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2054 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2055 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2056 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2057 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2058 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2059 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2060 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2061 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2062 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2063 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2064 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2065 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2066 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2067 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2068 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2069 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2070 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2071 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2072 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2073 stream-match-mask = <0x7f80>; 2074 #global-interrupts = <2>; 2075 #iommu-cells = <1>; 2076 2077 nvidia,memory-controller = <&mc>; 2078 status = "okay"; 2079 }; 2080 2081 cbb-fabric@13a00000 { 2082 compatible = "nvidia,tegra234-cbb-fabric"; 2083 reg = <0x0 0x13a00000 0x0 0x400000>; 2084 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 2085 status = "okay"; 2086 }; 2087 2088 host1x@13e00000 { 2089 compatible = "nvidia,tegra234-host1x"; 2090 reg = <0x0 0x13e00000 0x0 0x10000>, 2091 <0x0 0x13e10000 0x0 0x10000>, 2092 <0x0 0x13e40000 0x0 0x10000>; 2093 reg-names = "common", "hypervisor", "vm"; 2094 interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 2095 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 2096 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 2097 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 2098 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 2099 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 2100 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, 2101 <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, 2102 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 2103 interrupt-names = "syncpt0", "syncpt1", "syncpt2", "syncpt3", "syncpt4", 2104 "syncpt5", "syncpt6", "syncpt7", "host1x"; 2105 clocks = <&bpmp TEGRA234_CLK_HOST1X>; 2106 clock-names = "host1x"; 2107 2108 #address-cells = <2>; 2109 #size-cells = <2>; 2110 ranges = <0x0 0x14800000 0x0 0x14800000 0x0 0x02000000>; 2111 2112 interconnects = <&mc TEGRA234_MEMORY_CLIENT_HOST1XDMAR &emc>; 2113 interconnect-names = "dma-mem"; 2114 iommus = <&smmu_niso1 TEGRA234_SID_HOST1X>; 2115 2116 /* Context isolation domains */ 2117 iommu-map = <0 &smmu_niso0 TEGRA234_SID_HOST1X_CTX0 1>, 2118 <1 &smmu_niso0 TEGRA234_SID_HOST1X_CTX1 1>, 2119 <2 &smmu_niso0 TEGRA234_SID_HOST1X_CTX2 1>, 2120 <3 &smmu_niso0 TEGRA234_SID_HOST1X_CTX3 1>, 2121 <4 &smmu_niso0 TEGRA234_SID_HOST1X_CTX4 1>, 2122 <5 &smmu_niso0 TEGRA234_SID_HOST1X_CTX5 1>, 2123 <6 &smmu_niso0 TEGRA234_SID_HOST1X_CTX6 1>, 2124 <7 &smmu_niso0 TEGRA234_SID_HOST1X_CTX7 1>, 2125 <8 &smmu_niso1 TEGRA234_SID_HOST1X_CTX0 1>, 2126 <9 &smmu_niso1 TEGRA234_SID_HOST1X_CTX1 1>, 2127 <10 &smmu_niso1 TEGRA234_SID_HOST1X_CTX2 1>, 2128 <11 &smmu_niso1 TEGRA234_SID_HOST1X_CTX3 1>, 2129 <12 &smmu_niso1 TEGRA234_SID_HOST1X_CTX4 1>, 2130 <13 &smmu_niso1 TEGRA234_SID_HOST1X_CTX5 1>, 2131 <14 &smmu_niso1 TEGRA234_SID_HOST1X_CTX6 1>, 2132 <15 &smmu_niso1 TEGRA234_SID_HOST1X_CTX7 1>; 2133 2134 vic@15340000 { 2135 compatible = "nvidia,tegra234-vic"; 2136 reg = <0x0 0x15340000 0x0 0x00040000>; 2137 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 2138 clocks = <&bpmp TEGRA234_CLK_VIC>; 2139 clock-names = "vic"; 2140 resets = <&bpmp TEGRA234_RESET_VIC>; 2141 reset-names = "vic"; 2142 2143 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_VIC>; 2144 interconnects = <&mc TEGRA234_MEMORY_CLIENT_VICSRD &emc>, 2145 <&mc TEGRA234_MEMORY_CLIENT_VICSWR &emc>; 2146 interconnect-names = "dma-mem", "write"; 2147 iommus = <&smmu_niso1 TEGRA234_SID_VIC>; 2148 dma-coherent; 2149 }; 2150 2151 nvdec@15480000 { 2152 compatible = "nvidia,tegra234-nvdec"; 2153 reg = <0x0 0x15480000 0x0 0x00040000>; 2154 clocks = <&bpmp TEGRA234_CLK_NVDEC>, 2155 <&bpmp TEGRA234_CLK_FUSE>, 2156 <&bpmp TEGRA234_CLK_TSEC_PKA>; 2157 clock-names = "nvdec", "fuse", "tsec_pka"; 2158 resets = <&bpmp TEGRA234_RESET_NVDEC>; 2159 reset-names = "nvdec"; 2160 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>; 2161 interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDECSRD &emc>, 2162 <&mc TEGRA234_MEMORY_CLIENT_NVDECSWR &emc>; 2163 interconnect-names = "dma-mem", "write"; 2164 iommus = <&smmu_niso1 TEGRA234_SID_NVDEC>; 2165 dma-coherent; 2166 2167 nvidia,memory-controller = <&mc>; 2168 2169 /* 2170 * Placeholder values that firmware needs to update with the real 2171 * offsets parsed from the microcode headers. 2172 */ 2173 nvidia,bl-manifest-offset = <0>; 2174 nvidia,bl-data-offset = <0>; 2175 nvidia,bl-code-offset = <0>; 2176 nvidia,os-manifest-offset = <0>; 2177 nvidia,os-data-offset = <0>; 2178 nvidia,os-code-offset = <0>; 2179 2180 /* 2181 * Firmware needs to set this to "okay" once the above values have 2182 * been updated. 2183 */ 2184 status = "disabled"; 2185 }; 2186 }; 2187 2188 pcie@140a0000 { 2189 compatible = "nvidia,tegra234-pcie"; 2190 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CA>; 2191 reg = <0x00 0x140a0000 0x0 0x00020000>, /* appl registers (128K) */ 2192 <0x00 0x2a000000 0x0 0x00040000>, /* configuration space (256K) */ 2193 <0x00 0x2a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2194 <0x00 0x2a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2195 <0x35 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2196 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2197 2198 #address-cells = <3>; 2199 #size-cells = <2>; 2200 device_type = "pci"; 2201 num-lanes = <4>; 2202 num-viewport = <8>; 2203 linux,pci-domain = <8>; 2204 2205 clocks = <&bpmp TEGRA234_CLK_PEX2_C8_CORE>; 2206 clock-names = "core"; 2207 2208 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_8_APB>, 2209 <&bpmp TEGRA234_RESET_PEX2_CORE_8>; 2210 reset-names = "apb", "core"; 2211 2212 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2213 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2214 interrupt-names = "intr", "msi"; 2215 2216 #interrupt-cells = <1>; 2217 interrupt-map-mask = <0 0 0 0>; 2218 interrupt-map = <0 0 0 0 &gic GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 2219 2220 nvidia,bpmp = <&bpmp 8>; 2221 2222 nvidia,aspm-cmrt-us = <60>; 2223 nvidia,aspm-pwr-on-t-us = <20>; 2224 nvidia,aspm-l0s-entrance-latency-us = <3>; 2225 2226 bus-range = <0x0 0xff>; 2227 2228 ranges = <0x43000000 0x32 0x40000000 0x32 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2229 <0x02000000 0x0 0x40000000 0x35 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2230 <0x01000000 0x0 0x2a100000 0x00 0x2a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2231 2232 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE8AR &emc>, 2233 <&mc TEGRA234_MEMORY_CLIENT_PCIE8AW &emc>; 2234 interconnect-names = "dma-mem", "write"; 2235 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE8 0x1000>; 2236 iommu-map-mask = <0x0>; 2237 dma-coherent; 2238 2239 status = "disabled"; 2240 }; 2241 2242 pcie@140c0000 { 2243 compatible = "nvidia,tegra234-pcie"; 2244 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CB>; 2245 reg = <0x00 0x140c0000 0x0 0x00020000>, /* appl registers (128K) */ 2246 <0x00 0x2c000000 0x0 0x00040000>, /* configuration space (256K) */ 2247 <0x00 0x2c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2248 <0x00 0x2c080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2249 <0x38 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2250 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2251 2252 #address-cells = <3>; 2253 #size-cells = <2>; 2254 device_type = "pci"; 2255 num-lanes = <4>; 2256 num-viewport = <8>; 2257 linux,pci-domain = <9>; 2258 2259 clocks = <&bpmp TEGRA234_CLK_PEX2_C9_CORE>; 2260 clock-names = "core"; 2261 2262 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_9_APB>, 2263 <&bpmp TEGRA234_RESET_PEX2_CORE_9>; 2264 reset-names = "apb", "core"; 2265 2266 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2267 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2268 interrupt-names = "intr", "msi"; 2269 2270 #interrupt-cells = <1>; 2271 interrupt-map-mask = <0 0 0 0>; 2272 interrupt-map = <0 0 0 0 &gic GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2273 2274 nvidia,bpmp = <&bpmp 9>; 2275 2276 nvidia,aspm-cmrt-us = <60>; 2277 nvidia,aspm-pwr-on-t-us = <20>; 2278 nvidia,aspm-l0s-entrance-latency-us = <3>; 2279 2280 bus-range = <0x0 0xff>; 2281 2282 ranges = <0x43000000 0x35 0x40000000 0x35 0x40000000 0x2 0xc0000000>, /* prefetchable memory (11264 MB) */ 2283 <0x02000000 0x0 0x40000000 0x38 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2284 <0x01000000 0x0 0x2c100000 0x00 0x2c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2285 2286 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE9AR &emc>, 2287 <&mc TEGRA234_MEMORY_CLIENT_PCIE9AW &emc>; 2288 interconnect-names = "dma-mem", "write"; 2289 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE9 0x1000>; 2290 iommu-map-mask = <0x0>; 2291 dma-coherent; 2292 2293 status = "disabled"; 2294 }; 2295 2296 pcie@140e0000 { 2297 compatible = "nvidia,tegra234-pcie"; 2298 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>; 2299 reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */ 2300 <0x00 0x2e000000 0x0 0x00040000>, /* configuration space (256K) */ 2301 <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2302 <0x00 0x2e080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2303 <0x3b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2304 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2305 2306 #address-cells = <3>; 2307 #size-cells = <2>; 2308 device_type = "pci"; 2309 num-lanes = <4>; 2310 num-viewport = <8>; 2311 linux,pci-domain = <10>; 2312 2313 clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>; 2314 clock-names = "core"; 2315 2316 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>, 2317 <&bpmp TEGRA234_RESET_PEX2_CORE_10>; 2318 reset-names = "apb", "core"; 2319 2320 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2321 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2322 interrupt-names = "intr", "msi"; 2323 2324 #interrupt-cells = <1>; 2325 interrupt-map-mask = <0 0 0 0>; 2326 interrupt-map = <0 0 0 0 &gic GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 2327 2328 nvidia,bpmp = <&bpmp 10>; 2329 2330 nvidia,aspm-cmrt-us = <60>; 2331 nvidia,aspm-pwr-on-t-us = <20>; 2332 nvidia,aspm-l0s-entrance-latency-us = <3>; 2333 2334 bus-range = <0x0 0xff>; 2335 2336 ranges = <0x43000000 0x38 0x40000000 0x38 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2337 <0x02000000 0x0 0x40000000 0x3b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2338 <0x01000000 0x0 0x2e100000 0x00 0x2e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2339 2340 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, 2341 <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; 2342 interconnect-names = "dma-mem", "write"; 2343 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>; 2344 iommu-map-mask = <0x0>; 2345 dma-coherent; 2346 2347 status = "disabled"; 2348 }; 2349 2350 pcie-ep@140e0000 { 2351 compatible = "nvidia,tegra234-pcie-ep"; 2352 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>; 2353 reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */ 2354 <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2355 <0x00 0x2e080000 0x0 0x00040000>, /* DBI space (256K) */ 2356 <0x38 0x40000000 0x3 0x00000000>; /* Address Space (12G) */ 2357 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2358 2359 num-lanes = <4>; 2360 2361 clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>; 2362 clock-names = "core"; 2363 2364 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>, 2365 <&bpmp TEGRA234_RESET_PEX2_CORE_10>; 2366 reset-names = "apb", "core"; 2367 2368 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2369 interrupt-names = "intr"; 2370 2371 nvidia,bpmp = <&bpmp 10>; 2372 2373 nvidia,enable-ext-refclk; 2374 nvidia,aspm-cmrt-us = <60>; 2375 nvidia,aspm-pwr-on-t-us = <20>; 2376 nvidia,aspm-l0s-entrance-latency-us = <3>; 2377 2378 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, 2379 <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; 2380 interconnect-names = "dma-mem", "write"; 2381 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>; 2382 iommu-map-mask = <0x0>; 2383 dma-coherent; 2384 2385 status = "disabled"; 2386 }; 2387 2388 pcie@14100000 { 2389 compatible = "nvidia,tegra234-pcie"; 2390 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 2391 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 2392 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 2393 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2394 <0x00 0x30080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2395 <0x20 0xb0000000 0x0 0x10000000>; /* ECAM (256MB) */ 2396 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2397 2398 #address-cells = <3>; 2399 #size-cells = <2>; 2400 device_type = "pci"; 2401 num-lanes = <1>; 2402 num-viewport = <8>; 2403 linux,pci-domain = <1>; 2404 2405 clocks = <&bpmp TEGRA234_CLK_PEX0_C1_CORE>; 2406 clock-names = "core"; 2407 2408 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_1_APB>, 2409 <&bpmp TEGRA234_RESET_PEX0_CORE_1>; 2410 reset-names = "apb", "core"; 2411 2412 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2413 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2414 interrupt-names = "intr", "msi"; 2415 2416 #interrupt-cells = <1>; 2417 interrupt-map-mask = <0 0 0 0>; 2418 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 2419 2420 nvidia,bpmp = <&bpmp 1>; 2421 2422 nvidia,aspm-cmrt-us = <60>; 2423 nvidia,aspm-pwr-on-t-us = <20>; 2424 nvidia,aspm-l0s-entrance-latency-us = <3>; 2425 2426 bus-range = <0x0 0xff>; 2427 2428 ranges = <0x43000000 0x20 0x80000000 0x20 0x80000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 2429 <0x02000000 0x0 0x40000000 0x20 0xa8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2430 <0x01000000 0x0 0x30100000 0x00 0x30100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2431 2432 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE1R &emc>, 2433 <&mc TEGRA234_MEMORY_CLIENT_PCIE1W &emc>; 2434 interconnect-names = "dma-mem", "write"; 2435 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE1 0x1000>; 2436 iommu-map-mask = <0x0>; 2437 dma-coherent; 2438 2439 status = "disabled"; 2440 }; 2441 2442 pcie@14120000 { 2443 compatible = "nvidia,tegra234-pcie"; 2444 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 2445 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 2446 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 2447 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2448 <0x00 0x32080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2449 <0x20 0xf0000000 0x0 0x10000000>; /* ECAM (256MB) */ 2450 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2451 2452 #address-cells = <3>; 2453 #size-cells = <2>; 2454 device_type = "pci"; 2455 num-lanes = <1>; 2456 num-viewport = <8>; 2457 linux,pci-domain = <2>; 2458 2459 clocks = <&bpmp TEGRA234_CLK_PEX0_C2_CORE>; 2460 clock-names = "core"; 2461 2462 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_2_APB>, 2463 <&bpmp TEGRA234_RESET_PEX0_CORE_2>; 2464 reset-names = "apb", "core"; 2465 2466 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2467 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2468 interrupt-names = "intr", "msi"; 2469 2470 #interrupt-cells = <1>; 2471 interrupt-map-mask = <0 0 0 0>; 2472 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 2473 2474 nvidia,bpmp = <&bpmp 2>; 2475 2476 nvidia,aspm-cmrt-us = <60>; 2477 nvidia,aspm-pwr-on-t-us = <20>; 2478 nvidia,aspm-l0s-entrance-latency-us = <3>; 2479 2480 bus-range = <0x0 0xff>; 2481 2482 ranges = <0x43000000 0x20 0xc0000000 0x20 0xc0000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 2483 <0x02000000 0x0 0x40000000 0x20 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2484 <0x01000000 0x0 0x32100000 0x00 0x32100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2485 2486 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE2AR &emc>, 2487 <&mc TEGRA234_MEMORY_CLIENT_PCIE2AW &emc>; 2488 interconnect-names = "dma-mem", "write"; 2489 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE2 0x1000>; 2490 iommu-map-mask = <0x0>; 2491 dma-coherent; 2492 2493 status = "disabled"; 2494 }; 2495 2496 pcie@14140000 { 2497 compatible = "nvidia,tegra234-pcie"; 2498 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 2499 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 2500 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 2501 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2502 <0x00 0x34080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2503 <0x21 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2504 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2505 2506 #address-cells = <3>; 2507 #size-cells = <2>; 2508 device_type = "pci"; 2509 num-lanes = <1>; 2510 num-viewport = <8>; 2511 linux,pci-domain = <3>; 2512 2513 clocks = <&bpmp TEGRA234_CLK_PEX0_C3_CORE>; 2514 clock-names = "core"; 2515 2516 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_3_APB>, 2517 <&bpmp TEGRA234_RESET_PEX0_CORE_3>; 2518 reset-names = "apb", "core"; 2519 2520 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2521 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2522 interrupt-names = "intr", "msi"; 2523 2524 #interrupt-cells = <1>; 2525 interrupt-map-mask = <0 0 0 0>; 2526 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 2527 2528 nvidia,bpmp = <&bpmp 3>; 2529 2530 nvidia,aspm-cmrt-us = <60>; 2531 nvidia,aspm-pwr-on-t-us = <20>; 2532 nvidia,aspm-l0s-entrance-latency-us = <3>; 2533 2534 bus-range = <0x0 0xff>; 2535 2536 ranges = <0x43000000 0x21 0x00000000 0x21 0x00000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 2537 <0x02000000 0x0 0x40000000 0x21 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2538 <0x01000000 0x0 0x34100000 0x00 0x34100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2539 2540 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE3R &emc>, 2541 <&mc TEGRA234_MEMORY_CLIENT_PCIE3W &emc>; 2542 interconnect-names = "dma-mem", "write"; 2543 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE3 0x1000>; 2544 iommu-map-mask = <0x0>; 2545 dma-coherent; 2546 2547 status = "disabled"; 2548 }; 2549 2550 pcie@14160000 { 2551 compatible = "nvidia,tegra234-pcie"; 2552 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>; 2553 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2554 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2555 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2556 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2557 <0x24 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2558 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2559 2560 #address-cells = <3>; 2561 #size-cells = <2>; 2562 device_type = "pci"; 2563 num-lanes = <4>; 2564 num-viewport = <8>; 2565 linux,pci-domain = <4>; 2566 2567 clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>; 2568 clock-names = "core"; 2569 2570 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>, 2571 <&bpmp TEGRA234_RESET_PEX0_CORE_4>; 2572 reset-names = "apb", "core"; 2573 2574 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2575 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2576 interrupt-names = "intr", "msi"; 2577 2578 #interrupt-cells = <1>; 2579 interrupt-map-mask = <0 0 0 0>; 2580 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 2581 2582 nvidia,bpmp = <&bpmp 4>; 2583 2584 nvidia,aspm-cmrt-us = <60>; 2585 nvidia,aspm-pwr-on-t-us = <20>; 2586 nvidia,aspm-l0s-entrance-latency-us = <3>; 2587 2588 bus-range = <0x0 0xff>; 2589 2590 ranges = <0x43000000 0x21 0x40000000 0x21 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2591 <0x02000000 0x0 0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2592 <0x01000000 0x0 0x36100000 0x00 0x36100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2593 2594 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE4R &emc>, 2595 <&mc TEGRA234_MEMORY_CLIENT_PCIE4W &emc>; 2596 interconnect-names = "dma-mem", "write"; 2597 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE4 0x1000>; 2598 iommu-map-mask = <0x0>; 2599 dma-coherent; 2600 2601 status = "disabled"; 2602 }; 2603 2604 pcie@14180000 { 2605 compatible = "nvidia,tegra234-pcie"; 2606 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BA>; 2607 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2608 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2609 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2610 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2611 <0x27 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2612 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2613 2614 #address-cells = <3>; 2615 #size-cells = <2>; 2616 device_type = "pci"; 2617 num-lanes = <4>; 2618 num-viewport = <8>; 2619 linux,pci-domain = <0>; 2620 2621 clocks = <&bpmp TEGRA234_CLK_PEX0_C0_CORE>; 2622 clock-names = "core"; 2623 2624 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_0_APB>, 2625 <&bpmp TEGRA234_RESET_PEX0_CORE_0>; 2626 reset-names = "apb", "core"; 2627 2628 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2629 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2630 interrupt-names = "intr", "msi"; 2631 2632 #interrupt-cells = <1>; 2633 interrupt-map-mask = <0 0 0 0>; 2634 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 2635 2636 nvidia,bpmp = <&bpmp 0>; 2637 2638 nvidia,aspm-cmrt-us = <60>; 2639 nvidia,aspm-pwr-on-t-us = <20>; 2640 nvidia,aspm-l0s-entrance-latency-us = <3>; 2641 2642 bus-range = <0x0 0xff>; 2643 2644 ranges = <0x43000000 0x24 0x40000000 0x24 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2645 <0x02000000 0x0 0x40000000 0x27 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2646 <0x01000000 0x0 0x38100000 0x00 0x38100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2647 2648 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE0R &emc>, 2649 <&mc TEGRA234_MEMORY_CLIENT_PCIE0W &emc>; 2650 interconnect-names = "dma-mem", "write"; 2651 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE0 0x1000>; 2652 iommu-map-mask = <0x0>; 2653 dma-coherent; 2654 2655 status = "disabled"; 2656 }; 2657 2658 pcie@141a0000 { 2659 compatible = "nvidia,tegra234-pcie"; 2660 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>; 2661 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2662 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2663 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2664 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2665 <0x2b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2666 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2667 2668 #address-cells = <3>; 2669 #size-cells = <2>; 2670 device_type = "pci"; 2671 num-lanes = <8>; 2672 num-viewport = <8>; 2673 linux,pci-domain = <5>; 2674 2675 clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>; 2676 clock-names = "core"; 2677 2678 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>, 2679 <&bpmp TEGRA234_RESET_PEX1_CORE_5>; 2680 reset-names = "apb", "core"; 2681 2682 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2683 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2684 interrupt-names = "intr", "msi"; 2685 2686 #interrupt-cells = <1>; 2687 interrupt-map-mask = <0 0 0 0>; 2688 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 2689 2690 nvidia,bpmp = <&bpmp 5>; 2691 2692 nvidia,aspm-cmrt-us = <60>; 2693 nvidia,aspm-pwr-on-t-us = <20>; 2694 nvidia,aspm-l0s-entrance-latency-us = <3>; 2695 2696 bus-range = <0x0 0xff>; 2697 2698 ranges = <0x43000000 0x28 0x00000000 0x28 0x00000000 0x3 0x28000000>, /* prefetchable memory (12928 MB) */ 2699 <0x02000000 0x0 0x40000000 0x2b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2700 <0x01000000 0x0 0x3a100000 0x00 0x3a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2701 2702 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, 2703 <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; 2704 interconnect-names = "dma-mem", "write"; 2705 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>; 2706 iommu-map-mask = <0x0>; 2707 dma-coherent; 2708 2709 status = "disabled"; 2710 }; 2711 2712 pcie-ep@141a0000 { 2713 compatible = "nvidia,tegra234-pcie-ep"; 2714 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>; 2715 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2716 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2717 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2718 <0x27 0x40000000 0x4 0x00000000>; /* Address Space (16G) */ 2719 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2720 2721 num-lanes = <8>; 2722 2723 clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>; 2724 clock-names = "core"; 2725 2726 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>, 2727 <&bpmp TEGRA234_RESET_PEX1_CORE_5>; 2728 reset-names = "apb", "core"; 2729 2730 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2731 interrupt-names = "intr"; 2732 2733 nvidia,bpmp = <&bpmp 5>; 2734 2735 nvidia,enable-ext-refclk; 2736 nvidia,aspm-cmrt-us = <60>; 2737 nvidia,aspm-pwr-on-t-us = <20>; 2738 nvidia,aspm-l0s-entrance-latency-us = <3>; 2739 2740 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, 2741 <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; 2742 interconnect-names = "dma-mem", "write"; 2743 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>; 2744 iommu-map-mask = <0x0>; 2745 dma-coherent; 2746 2747 status = "disabled"; 2748 }; 2749 2750 pcie@141c0000 { 2751 compatible = "nvidia,tegra234-pcie"; 2752 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>; 2753 reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */ 2754 <0x00 0x3c000000 0x0 0x00040000>, /* configuration space (256K) */ 2755 <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2756 <0x00 0x3c080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2757 <0x2e 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2758 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2759 2760 #address-cells = <3>; 2761 #size-cells = <2>; 2762 device_type = "pci"; 2763 num-lanes = <4>; 2764 num-viewport = <8>; 2765 linux,pci-domain = <6>; 2766 2767 clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>; 2768 clock-names = "core"; 2769 2770 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>, 2771 <&bpmp TEGRA234_RESET_PEX1_CORE_6>; 2772 reset-names = "apb", "core"; 2773 2774 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2775 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2776 interrupt-names = "intr", "msi"; 2777 2778 #interrupt-cells = <1>; 2779 interrupt-map-mask = <0 0 0 0>; 2780 interrupt-map = <0 0 0 0 &gic GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 2781 2782 nvidia,bpmp = <&bpmp 6>; 2783 2784 nvidia,aspm-cmrt-us = <60>; 2785 nvidia,aspm-pwr-on-t-us = <20>; 2786 nvidia,aspm-l0s-entrance-latency-us = <3>; 2787 2788 bus-range = <0x0 0xff>; 2789 2790 ranges = <0x43000000 0x2b 0x40000000 0x2b 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2791 <0x02000000 0x0 0x40000000 0x2e 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2792 <0x01000000 0x0 0x3c100000 0x00 0x3c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2793 2794 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, 2795 <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; 2796 interconnect-names = "dma-mem", "write"; 2797 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>; 2798 iommu-map-mask = <0x0>; 2799 dma-coherent; 2800 2801 status = "disabled"; 2802 }; 2803 2804 pcie-ep@141c0000 { 2805 compatible = "nvidia,tegra234-pcie-ep"; 2806 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>; 2807 reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */ 2808 <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2809 <0x00 0x3c080000 0x0 0x00040000>, /* DBI space (256K) */ 2810 <0x2b 0x40000000 0x3 0x00000000>; /* Address Space (12G) */ 2811 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2812 2813 num-lanes = <4>; 2814 2815 clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>; 2816 clock-names = "core"; 2817 2818 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>, 2819 <&bpmp TEGRA234_RESET_PEX1_CORE_6>; 2820 reset-names = "apb", "core"; 2821 2822 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2823 interrupt-names = "intr"; 2824 2825 nvidia,bpmp = <&bpmp 6>; 2826 2827 nvidia,enable-ext-refclk; 2828 nvidia,aspm-cmrt-us = <60>; 2829 nvidia,aspm-pwr-on-t-us = <20>; 2830 nvidia,aspm-l0s-entrance-latency-us = <3>; 2831 2832 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, 2833 <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; 2834 interconnect-names = "dma-mem", "write"; 2835 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>; 2836 iommu-map-mask = <0x0>; 2837 dma-coherent; 2838 2839 status = "disabled"; 2840 }; 2841 2842 pcie@141e0000 { 2843 compatible = "nvidia,tegra234-pcie"; 2844 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>; 2845 reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */ 2846 <0x00 0x3e000000 0x0 0x00040000>, /* configuration space (256K) */ 2847 <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2848 <0x00 0x3e080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2849 <0x32 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2850 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2851 2852 #address-cells = <3>; 2853 #size-cells = <2>; 2854 device_type = "pci"; 2855 num-lanes = <8>; 2856 num-viewport = <8>; 2857 linux,pci-domain = <7>; 2858 2859 clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>; 2860 clock-names = "core"; 2861 2862 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>, 2863 <&bpmp TEGRA234_RESET_PEX2_CORE_7>; 2864 reset-names = "apb", "core"; 2865 2866 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2867 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2868 interrupt-names = "intr", "msi"; 2869 2870 #interrupt-cells = <1>; 2871 interrupt-map-mask = <0 0 0 0>; 2872 interrupt-map = <0 0 0 0 &gic GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 2873 2874 nvidia,bpmp = <&bpmp 7>; 2875 2876 nvidia,aspm-cmrt-us = <60>; 2877 nvidia,aspm-pwr-on-t-us = <20>; 2878 nvidia,aspm-l0s-entrance-latency-us = <3>; 2879 2880 bus-range = <0x0 0xff>; 2881 2882 ranges = <0x43000000 0x30 0x00000000 0x30 0x00000000 0x2 0x28000000>, /* prefetchable memory (8832 MB) */ 2883 <0x02000000 0x0 0x40000000 0x32 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2884 <0x01000000 0x0 0x3e100000 0x00 0x3e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2885 2886 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>, 2887 <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>; 2888 interconnect-names = "dma-mem", "write"; 2889 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>; 2890 iommu-map-mask = <0x0>; 2891 dma-coherent; 2892 2893 status = "disabled"; 2894 }; 2895 2896 pcie-ep@141e0000 { 2897 compatible = "nvidia,tegra234-pcie-ep"; 2898 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>; 2899 reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */ 2900 <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2901 <0x00 0x3e080000 0x0 0x00040000>, /* DBI space (256K) */ 2902 <0x2e 0x40000000 0x4 0x00000000>; /* Address Space (16G) */ 2903 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2904 2905 num-lanes = <8>; 2906 2907 clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>; 2908 clock-names = "core"; 2909 2910 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>, 2911 <&bpmp TEGRA234_RESET_PEX2_CORE_7>; 2912 reset-names = "apb", "core"; 2913 2914 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2915 interrupt-names = "intr"; 2916 2917 nvidia,bpmp = <&bpmp 7>; 2918 2919 nvidia,enable-ext-refclk; 2920 nvidia,aspm-cmrt-us = <60>; 2921 nvidia,aspm-pwr-on-t-us = <20>; 2922 nvidia,aspm-l0s-entrance-latency-us = <3>; 2923 2924 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>, 2925 <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>; 2926 interconnect-names = "dma-mem", "write"; 2927 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>; 2928 iommu-map-mask = <0x0>; 2929 dma-coherent; 2930 2931 status = "disabled"; 2932 }; 2933 }; 2934 2935 sram@40000000 { 2936 compatible = "nvidia,tegra234-sysram", "mmio-sram"; 2937 reg = <0x0 0x40000000 0x0 0x80000>; 2938 2939 #address-cells = <1>; 2940 #size-cells = <1>; 2941 ranges = <0x0 0x0 0x40000000 0x80000>; 2942 2943 no-memory-wc; 2944 2945 cpu_bpmp_tx: sram@70000 { 2946 reg = <0x70000 0x1000>; 2947 label = "cpu-bpmp-tx"; 2948 pool; 2949 }; 2950 2951 cpu_bpmp_rx: sram@71000 { 2952 reg = <0x71000 0x1000>; 2953 label = "cpu-bpmp-rx"; 2954 pool; 2955 }; 2956 }; 2957 2958 bpmp: bpmp { 2959 compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp"; 2960 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 2961 TEGRA_HSP_DB_MASTER_BPMP>; 2962 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 2963 #clock-cells = <1>; 2964 #reset-cells = <1>; 2965 #power-domain-cells = <1>; 2966 interconnects = <&mc TEGRA234_MEMORY_CLIENT_BPMPR &emc>, 2967 <&mc TEGRA234_MEMORY_CLIENT_BPMPW &emc>, 2968 <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAR &emc>, 2969 <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAW &emc>; 2970 interconnect-names = "read", "write", "dma-mem", "dma-write"; 2971 iommus = <&smmu_niso1 TEGRA234_SID_BPMP>; 2972 2973 bpmp_i2c: i2c { 2974 compatible = "nvidia,tegra186-bpmp-i2c"; 2975 nvidia,bpmp-bus-id = <5>; 2976 #address-cells = <1>; 2977 #size-cells = <0>; 2978 }; 2979 }; 2980 2981 cpus { 2982 #address-cells = <1>; 2983 #size-cells = <0>; 2984 2985 cpu0_0: cpu@0 { 2986 compatible = "arm,cortex-a78"; 2987 device_type = "cpu"; 2988 reg = <0x00000>; 2989 2990 enable-method = "psci"; 2991 2992 i-cache-size = <65536>; 2993 i-cache-line-size = <64>; 2994 i-cache-sets = <256>; 2995 d-cache-size = <65536>; 2996 d-cache-line-size = <64>; 2997 d-cache-sets = <256>; 2998 next-level-cache = <&l2c0_0>; 2999 }; 3000 3001 cpu0_1: cpu@100 { 3002 compatible = "arm,cortex-a78"; 3003 device_type = "cpu"; 3004 reg = <0x00100>; 3005 3006 enable-method = "psci"; 3007 3008 i-cache-size = <65536>; 3009 i-cache-line-size = <64>; 3010 i-cache-sets = <256>; 3011 d-cache-size = <65536>; 3012 d-cache-line-size = <64>; 3013 d-cache-sets = <256>; 3014 next-level-cache = <&l2c0_1>; 3015 }; 3016 3017 cpu0_2: cpu@200 { 3018 compatible = "arm,cortex-a78"; 3019 device_type = "cpu"; 3020 reg = <0x00200>; 3021 3022 enable-method = "psci"; 3023 3024 i-cache-size = <65536>; 3025 i-cache-line-size = <64>; 3026 i-cache-sets = <256>; 3027 d-cache-size = <65536>; 3028 d-cache-line-size = <64>; 3029 d-cache-sets = <256>; 3030 next-level-cache = <&l2c0_2>; 3031 }; 3032 3033 cpu0_3: cpu@300 { 3034 compatible = "arm,cortex-a78"; 3035 device_type = "cpu"; 3036 reg = <0x00300>; 3037 3038 enable-method = "psci"; 3039 3040 i-cache-size = <65536>; 3041 i-cache-line-size = <64>; 3042 i-cache-sets = <256>; 3043 d-cache-size = <65536>; 3044 d-cache-line-size = <64>; 3045 d-cache-sets = <256>; 3046 next-level-cache = <&l2c0_3>; 3047 }; 3048 3049 cpu1_0: cpu@10000 { 3050 compatible = "arm,cortex-a78"; 3051 device_type = "cpu"; 3052 reg = <0x10000>; 3053 3054 enable-method = "psci"; 3055 3056 i-cache-size = <65536>; 3057 i-cache-line-size = <64>; 3058 i-cache-sets = <256>; 3059 d-cache-size = <65536>; 3060 d-cache-line-size = <64>; 3061 d-cache-sets = <256>; 3062 next-level-cache = <&l2c1_0>; 3063 }; 3064 3065 cpu1_1: cpu@10100 { 3066 compatible = "arm,cortex-a78"; 3067 device_type = "cpu"; 3068 reg = <0x10100>; 3069 3070 enable-method = "psci"; 3071 3072 i-cache-size = <65536>; 3073 i-cache-line-size = <64>; 3074 i-cache-sets = <256>; 3075 d-cache-size = <65536>; 3076 d-cache-line-size = <64>; 3077 d-cache-sets = <256>; 3078 next-level-cache = <&l2c1_1>; 3079 }; 3080 3081 cpu1_2: cpu@10200 { 3082 compatible = "arm,cortex-a78"; 3083 device_type = "cpu"; 3084 reg = <0x10200>; 3085 3086 enable-method = "psci"; 3087 3088 i-cache-size = <65536>; 3089 i-cache-line-size = <64>; 3090 i-cache-sets = <256>; 3091 d-cache-size = <65536>; 3092 d-cache-line-size = <64>; 3093 d-cache-sets = <256>; 3094 next-level-cache = <&l2c1_2>; 3095 }; 3096 3097 cpu1_3: cpu@10300 { 3098 compatible = "arm,cortex-a78"; 3099 device_type = "cpu"; 3100 reg = <0x10300>; 3101 3102 enable-method = "psci"; 3103 3104 i-cache-size = <65536>; 3105 i-cache-line-size = <64>; 3106 i-cache-sets = <256>; 3107 d-cache-size = <65536>; 3108 d-cache-line-size = <64>; 3109 d-cache-sets = <256>; 3110 next-level-cache = <&l2c1_3>; 3111 }; 3112 3113 cpu2_0: cpu@20000 { 3114 compatible = "arm,cortex-a78"; 3115 device_type = "cpu"; 3116 reg = <0x20000>; 3117 3118 enable-method = "psci"; 3119 3120 i-cache-size = <65536>; 3121 i-cache-line-size = <64>; 3122 i-cache-sets = <256>; 3123 d-cache-size = <65536>; 3124 d-cache-line-size = <64>; 3125 d-cache-sets = <256>; 3126 next-level-cache = <&l2c2_0>; 3127 }; 3128 3129 cpu2_1: cpu@20100 { 3130 compatible = "arm,cortex-a78"; 3131 device_type = "cpu"; 3132 reg = <0x20100>; 3133 3134 enable-method = "psci"; 3135 3136 i-cache-size = <65536>; 3137 i-cache-line-size = <64>; 3138 i-cache-sets = <256>; 3139 d-cache-size = <65536>; 3140 d-cache-line-size = <64>; 3141 d-cache-sets = <256>; 3142 next-level-cache = <&l2c2_1>; 3143 }; 3144 3145 cpu2_2: cpu@20200 { 3146 compatible = "arm,cortex-a78"; 3147 device_type = "cpu"; 3148 reg = <0x20200>; 3149 3150 enable-method = "psci"; 3151 3152 i-cache-size = <65536>; 3153 i-cache-line-size = <64>; 3154 i-cache-sets = <256>; 3155 d-cache-size = <65536>; 3156 d-cache-line-size = <64>; 3157 d-cache-sets = <256>; 3158 next-level-cache = <&l2c2_2>; 3159 }; 3160 3161 cpu2_3: cpu@20300 { 3162 compatible = "arm,cortex-a78"; 3163 device_type = "cpu"; 3164 reg = <0x20300>; 3165 3166 enable-method = "psci"; 3167 3168 i-cache-size = <65536>; 3169 i-cache-line-size = <64>; 3170 i-cache-sets = <256>; 3171 d-cache-size = <65536>; 3172 d-cache-line-size = <64>; 3173 d-cache-sets = <256>; 3174 next-level-cache = <&l2c2_3>; 3175 }; 3176 3177 cpu-map { 3178 cluster0 { 3179 core0 { 3180 cpu = <&cpu0_0>; 3181 }; 3182 3183 core1 { 3184 cpu = <&cpu0_1>; 3185 }; 3186 3187 core2 { 3188 cpu = <&cpu0_2>; 3189 }; 3190 3191 core3 { 3192 cpu = <&cpu0_3>; 3193 }; 3194 }; 3195 3196 cluster1 { 3197 core0 { 3198 cpu = <&cpu1_0>; 3199 }; 3200 3201 core1 { 3202 cpu = <&cpu1_1>; 3203 }; 3204 3205 core2 { 3206 cpu = <&cpu1_2>; 3207 }; 3208 3209 core3 { 3210 cpu = <&cpu1_3>; 3211 }; 3212 }; 3213 3214 cluster2 { 3215 core0 { 3216 cpu = <&cpu2_0>; 3217 }; 3218 3219 core1 { 3220 cpu = <&cpu2_1>; 3221 }; 3222 3223 core2 { 3224 cpu = <&cpu2_2>; 3225 }; 3226 3227 core3 { 3228 cpu = <&cpu2_3>; 3229 }; 3230 }; 3231 }; 3232 3233 l2c0_0: l2-cache00 { 3234 compatible = "cache"; 3235 cache-size = <262144>; 3236 cache-line-size = <64>; 3237 cache-sets = <512>; 3238 cache-unified; 3239 cache-level = <2>; 3240 next-level-cache = <&l3c0>; 3241 }; 3242 3243 l2c0_1: l2-cache01 { 3244 compatible = "cache"; 3245 cache-size = <262144>; 3246 cache-line-size = <64>; 3247 cache-sets = <512>; 3248 cache-unified; 3249 cache-level = <2>; 3250 next-level-cache = <&l3c0>; 3251 }; 3252 3253 l2c0_2: l2-cache02 { 3254 compatible = "cache"; 3255 cache-size = <262144>; 3256 cache-line-size = <64>; 3257 cache-sets = <512>; 3258 cache-unified; 3259 cache-level = <2>; 3260 next-level-cache = <&l3c0>; 3261 }; 3262 3263 l2c0_3: l2-cache03 { 3264 compatible = "cache"; 3265 cache-size = <262144>; 3266 cache-line-size = <64>; 3267 cache-sets = <512>; 3268 cache-unified; 3269 cache-level = <2>; 3270 next-level-cache = <&l3c0>; 3271 }; 3272 3273 l2c1_0: l2-cache10 { 3274 compatible = "cache"; 3275 cache-size = <262144>; 3276 cache-line-size = <64>; 3277 cache-sets = <512>; 3278 cache-unified; 3279 cache-level = <2>; 3280 next-level-cache = <&l3c1>; 3281 }; 3282 3283 l2c1_1: l2-cache11 { 3284 compatible = "cache"; 3285 cache-size = <262144>; 3286 cache-line-size = <64>; 3287 cache-sets = <512>; 3288 cache-unified; 3289 cache-level = <2>; 3290 next-level-cache = <&l3c1>; 3291 }; 3292 3293 l2c1_2: l2-cache12 { 3294 compatible = "cache"; 3295 cache-size = <262144>; 3296 cache-line-size = <64>; 3297 cache-sets = <512>; 3298 cache-unified; 3299 cache-level = <2>; 3300 next-level-cache = <&l3c1>; 3301 }; 3302 3303 l2c1_3: l2-cache13 { 3304 compatible = "cache"; 3305 cache-size = <262144>; 3306 cache-line-size = <64>; 3307 cache-sets = <512>; 3308 cache-unified; 3309 cache-level = <2>; 3310 next-level-cache = <&l3c1>; 3311 }; 3312 3313 l2c2_0: l2-cache20 { 3314 compatible = "cache"; 3315 cache-size = <262144>; 3316 cache-line-size = <64>; 3317 cache-sets = <512>; 3318 cache-unified; 3319 cache-level = <2>; 3320 next-level-cache = <&l3c2>; 3321 }; 3322 3323 l2c2_1: l2-cache21 { 3324 compatible = "cache"; 3325 cache-size = <262144>; 3326 cache-line-size = <64>; 3327 cache-sets = <512>; 3328 cache-unified; 3329 cache-level = <2>; 3330 next-level-cache = <&l3c2>; 3331 }; 3332 3333 l2c2_2: l2-cache22 { 3334 compatible = "cache"; 3335 cache-size = <262144>; 3336 cache-line-size = <64>; 3337 cache-sets = <512>; 3338 cache-unified; 3339 cache-level = <2>; 3340 next-level-cache = <&l3c2>; 3341 }; 3342 3343 l2c2_3: l2-cache23 { 3344 compatible = "cache"; 3345 cache-size = <262144>; 3346 cache-line-size = <64>; 3347 cache-sets = <512>; 3348 cache-unified; 3349 cache-level = <2>; 3350 next-level-cache = <&l3c2>; 3351 }; 3352 3353 l3c0: l3-cache0 { 3354 compatible = "cache"; 3355 cache-unified; 3356 cache-size = <2097152>; 3357 cache-line-size = <64>; 3358 cache-sets = <2048>; 3359 cache-level = <3>; 3360 }; 3361 3362 l3c1: l3-cache1 { 3363 compatible = "cache"; 3364 cache-unified; 3365 cache-size = <2097152>; 3366 cache-line-size = <64>; 3367 cache-sets = <2048>; 3368 cache-level = <3>; 3369 }; 3370 3371 l3c2: l3-cache2 { 3372 compatible = "cache"; 3373 cache-unified; 3374 cache-size = <2097152>; 3375 cache-line-size = <64>; 3376 cache-sets = <2048>; 3377 cache-level = <3>; 3378 }; 3379 }; 3380 3381 pmu { 3382 compatible = "arm,cortex-a78-pmu"; 3383 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 3384 status = "okay"; 3385 }; 3386 3387 psci { 3388 compatible = "arm,psci-1.0"; 3389 status = "okay"; 3390 method = "smc"; 3391 }; 3392 3393 tcu: serial { 3394 compatible = "nvidia,tegra234-tcu", "nvidia,tegra194-tcu"; 3395 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 3396 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 3397 mbox-names = "rx", "tx"; 3398 status = "disabled"; 3399 }; 3400 3401 sound { 3402 status = "disabled"; 3403 3404 clocks = <&bpmp TEGRA234_CLK_PLLA>, 3405 <&bpmp TEGRA234_CLK_PLLA_OUT0>; 3406 clock-names = "pll_a", "plla_out0"; 3407 assigned-clocks = <&bpmp TEGRA234_CLK_PLLA>, 3408 <&bpmp TEGRA234_CLK_PLLA_OUT0>, 3409 <&bpmp TEGRA234_CLK_AUD_MCLK>; 3410 assigned-clock-parents = <0>, 3411 <&bpmp TEGRA234_CLK_PLLA>, 3412 <&bpmp TEGRA234_CLK_PLLA_OUT0>; 3413 }; 3414 3415 timer { 3416 compatible = "arm,armv8-timer"; 3417 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3418 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3419 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3420 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 3421 interrupt-parent = <&gic>; 3422 always-on; 3423 }; 3424}; 3425