6a2f0b2d | 03-Dec-2019 |
Ard Biesheuvel <ardb@kernel.org> |
dt: amd-seattle: add a description of the CPUs and caches
Add a DT description of the CPU and cache hierarchy as found on the AMD Seattle SOC. Given the tight coupling of the PMU with the CPUs, move
dt: amd-seattle: add a description of the CPUs and caches
Add a DT description of the CPU and cache hierarchy as found on the AMD Seattle SOC. Given the tight coupling of the PMU with the CPUs, move the PMU node into the cpu .dtsi file as well, and add the missing affinity description.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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429863e7 | 03-Dec-2019 |
Ard Biesheuvel <ardb@kernel.org> |
dt: amd-seattle: add description of the SATA/CCP SMMUs
Add descriptions of the SMMUs that cover the SATA controller(s) on the AMD Seattle SOC. The CCP crypto accelerator shares its SMMU with the sec
dt: amd-seattle: add description of the SATA/CCP SMMUs
Add descriptions of the SMMUs that cover the SATA controller(s) on the AMD Seattle SOC. The CCP crypto accelerator shares its SMMU with the second SATA controller, which is only enabled on B1 silicon.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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acd9208e | 03-Dec-2019 |
Ard Biesheuvel <ardb@kernel.org> |
dt: amd-seattle: fix PCIe legacy interrupt routing
The AMD Seattle SOC can be configured to expose up to 3 PCIe root ports, each of which is wired to 4 dedicated SPI wired interrupts for legacy INTx
dt: amd-seattle: fix PCIe legacy interrupt routing
The AMD Seattle SOC can be configured to expose up to 3 PCIe root ports, each of which is wired to 4 dedicated SPI wired interrupts for legacy INTx support. Update the SOC DT description to reflect this.
Fix a stale comment about the size of the MMIO64 resource window while at it.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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9bd9a063 | 03-Dec-2019 |
Ard Biesheuvel <ardb@kernel.org> |
dt: amd-seattle: upgrade AMD Seattle XGBE to new SMMU binding
Upgrade the DT descriptions of the AMD Seattle XGBE network controllers to use the current SMMU bindings.
Signed-off-by: Ard Biesheuvel
dt: amd-seattle: upgrade AMD Seattle XGBE to new SMMU binding
Upgrade the DT descriptions of the AMD Seattle XGBE network controllers to use the current SMMU bindings.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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f179eb6b | 03-Dec-2019 |
Ard Biesheuvel <ardb@kernel.org> |
dt: amd-seattle: remove Overdrive revision A0 support
Support for AMD Seattle silicon revision A0 is no longer relevant, since we no longer have a driver for the network controller, and the PCIe on
dt: amd-seattle: remove Overdrive revision A0 support
Support for AMD Seattle silicon revision A0 is no longer relevant, since we no longer have a driver for the network controller, and the PCIe on these boards was very unreliable. So drop the DTS description of the A0 version of the overdrive board.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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4a6e0a77 | 08-Feb-2016 |
Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> |
dtb: amd: Add support for AMD/Linaro 96Boards Enterprise Edition Server board
Add device tree file for AMD/Linaro 96Boards Enterprise Edition Server (Husky) Board. This is based on the AMD Seattle R
dtb: amd: Add support for AMD/Linaro 96Boards Enterprise Edition Server board
Add device tree file for AMD/Linaro 96Boards Enterprise Edition Server (Husky) Board. This is based on the AMD Seattle Rev.B0 system
Signed-off-by: Leo Duran <leo.duran@amd.com> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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08b8940e | 08-Feb-2016 |
Tom Lendacky <thomas.lendacky@amd.com> |
dtb: amd: Add AMD XGBE device tree file
Add AMD XGBE device tree file, which is available in AMD Seattle RevB.
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Olof Johansson <o
dtb: amd: Add AMD XGBE device tree file
Add AMD XGBE device tree file, which is available in AMD Seattle RevB.
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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71edbebb | 08-Feb-2016 |
Brijesh Singh <brijeshkumar.singh@amd.com> |
dtb: amd: Add KCS device tree node
Add KCS device node to support IPMI solution on Overdrive system.
Signed-off-by: Brijesh Singh <brijeshkumar.singh@amd.com> Signed-off-by: Suravee Suthikulpanit <
dtb: amd: Add KCS device tree node
Add KCS device node to support IPMI solution on Overdrive system.
Signed-off-by: Brijesh Singh <brijeshkumar.singh@amd.com> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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7973a3fb | 08-Feb-2016 |
Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> |
dtb: amd: Misc changes for SATA device tree nodes
Add new SATA1 device node, and fix the register range size of SATA0.
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Suravee S
dtb: amd: Misc changes for SATA device tree nodes
Add new SATA1 device node, and fix the register range size of SATA0.
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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1584fd13 | 08-Feb-2016 |
Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> |
dtb: amd: Misc changes for I2C device nodes
Add new i2c1 device node, and fix the incorrect clock frequency.
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Suravee Suthikulpan
dtb: amd: Misc changes for I2C device nodes
Add new i2c1 device node, and fix the incorrect clock frequency.
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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