1 /* drivers/gpu/drm/exynos5433_drm_decon.c 2 * 3 * Copyright (C) 2015 Samsung Electronics Co.Ltd 4 * Authors: 5 * Joonyoung Shim <jy0922.shim@samsung.com> 6 * Hyungwon Hwang <human.hwang@samsung.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundationr 11 */ 12 13 #include <linux/platform_device.h> 14 #include <linux/clk.h> 15 #include <linux/component.h> 16 #include <linux/iopoll.h> 17 #include <linux/irq.h> 18 #include <linux/mfd/syscon.h> 19 #include <linux/of_device.h> 20 #include <linux/of_gpio.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/regmap.h> 23 24 #include <video/exynos5433_decon.h> 25 26 #include "exynos_drm_drv.h" 27 #include "exynos_drm_crtc.h" 28 #include "exynos_drm_fb.h" 29 #include "exynos_drm_plane.h" 30 #include "exynos_drm_iommu.h" 31 32 #define DSD_CFG_MUX 0x1004 33 #define DSD_CFG_MUX_TE_UNMASK_GLOBAL BIT(13) 34 35 #define WINDOWS_NR 3 36 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128 37 38 #define I80_HW_TRG (1 << 0) 39 #define IFTYPE_HDMI (1 << 1) 40 41 static const char * const decon_clks_name[] = { 42 "pclk", 43 "aclk_decon", 44 "aclk_smmu_decon0x", 45 "aclk_xiu_decon0x", 46 "pclk_smmu_decon0x", 47 "sclk_decon_vclk", 48 "sclk_decon_eclk", 49 }; 50 51 struct decon_context { 52 struct device *dev; 53 struct drm_device *drm_dev; 54 struct exynos_drm_crtc *crtc; 55 struct exynos_drm_plane planes[WINDOWS_NR]; 56 struct exynos_drm_plane_config configs[WINDOWS_NR]; 57 void __iomem *addr; 58 struct regmap *sysreg; 59 struct clk *clks[ARRAY_SIZE(decon_clks_name)]; 60 unsigned int irq; 61 unsigned int irq_vsync; 62 unsigned int irq_lcd_sys; 63 unsigned int te_irq; 64 unsigned long out_type; 65 int first_win; 66 spinlock_t vblank_lock; 67 u32 frame_id; 68 }; 69 70 static const uint32_t decon_formats[] = { 71 DRM_FORMAT_XRGB1555, 72 DRM_FORMAT_RGB565, 73 DRM_FORMAT_XRGB8888, 74 DRM_FORMAT_ARGB8888, 75 }; 76 77 static const enum drm_plane_type decon_win_types[WINDOWS_NR] = { 78 DRM_PLANE_TYPE_PRIMARY, 79 DRM_PLANE_TYPE_OVERLAY, 80 DRM_PLANE_TYPE_CURSOR, 81 }; 82 83 static inline void decon_set_bits(struct decon_context *ctx, u32 reg, u32 mask, 84 u32 val) 85 { 86 val = (val & mask) | (readl(ctx->addr + reg) & ~mask); 87 writel(val, ctx->addr + reg); 88 } 89 90 static int decon_enable_vblank(struct exynos_drm_crtc *crtc) 91 { 92 struct decon_context *ctx = crtc->ctx; 93 u32 val; 94 95 val = VIDINTCON0_INTEN; 96 if (crtc->i80_mode) 97 val |= VIDINTCON0_FRAMEDONE; 98 else 99 val |= VIDINTCON0_INTFRMEN | VIDINTCON0_FRAMESEL_FP; 100 101 writel(val, ctx->addr + DECON_VIDINTCON0); 102 103 enable_irq(ctx->irq); 104 if (!(ctx->out_type & I80_HW_TRG)) 105 enable_irq(ctx->te_irq); 106 107 return 0; 108 } 109 110 static void decon_disable_vblank(struct exynos_drm_crtc *crtc) 111 { 112 struct decon_context *ctx = crtc->ctx; 113 114 if (!(ctx->out_type & I80_HW_TRG)) 115 disable_irq_nosync(ctx->te_irq); 116 disable_irq_nosync(ctx->irq); 117 118 writel(0, ctx->addr + DECON_VIDINTCON0); 119 } 120 121 /* return number of starts/ends of frame transmissions since reset */ 122 static u32 decon_get_frame_count(struct decon_context *ctx, bool end) 123 { 124 u32 frm, pfrm, status, cnt = 2; 125 126 /* To get consistent result repeat read until frame id is stable. 127 * Usually the loop will be executed once, in rare cases when the loop 128 * is executed at frame change time 2nd pass will be needed. 129 */ 130 frm = readl(ctx->addr + DECON_CRFMID); 131 do { 132 status = readl(ctx->addr + DECON_VIDCON1); 133 pfrm = frm; 134 frm = readl(ctx->addr + DECON_CRFMID); 135 } while (frm != pfrm && --cnt); 136 137 /* CRFMID is incremented on BPORCH in case of I80 and on VSYNC in case 138 * of RGB, it should be taken into account. 139 */ 140 if (!frm) 141 return 0; 142 143 switch (status & (VIDCON1_VSTATUS_MASK | VIDCON1_I80_ACTIVE)) { 144 case VIDCON1_VSTATUS_VS: 145 if (!(ctx->crtc->i80_mode)) 146 --frm; 147 break; 148 case VIDCON1_VSTATUS_BP: 149 --frm; 150 break; 151 case VIDCON1_I80_ACTIVE: 152 case VIDCON1_VSTATUS_AC: 153 if (end) 154 --frm; 155 break; 156 default: 157 break; 158 } 159 160 return frm; 161 } 162 163 static u32 decon_get_vblank_counter(struct exynos_drm_crtc *crtc) 164 { 165 struct decon_context *ctx = crtc->ctx; 166 167 return decon_get_frame_count(ctx, false); 168 } 169 170 static void decon_setup_trigger(struct decon_context *ctx) 171 { 172 if (!ctx->crtc->i80_mode && !(ctx->out_type & I80_HW_TRG)) 173 return; 174 175 if (!(ctx->out_type & I80_HW_TRG)) { 176 writel(TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F | 177 TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN, 178 ctx->addr + DECON_TRIGCON); 179 return; 180 } 181 182 writel(TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F | TRIGCON_HWTRIGMASK 183 | TRIGCON_HWTRIGEN, ctx->addr + DECON_TRIGCON); 184 185 if (regmap_update_bits(ctx->sysreg, DSD_CFG_MUX, 186 DSD_CFG_MUX_TE_UNMASK_GLOBAL, ~0)) 187 DRM_ERROR("Cannot update sysreg.\n"); 188 } 189 190 static void decon_commit(struct exynos_drm_crtc *crtc) 191 { 192 struct decon_context *ctx = crtc->ctx; 193 struct drm_display_mode *m = &crtc->base.mode; 194 bool interlaced = false; 195 u32 val; 196 197 if (ctx->out_type & IFTYPE_HDMI) { 198 m->crtc_hsync_start = m->crtc_hdisplay + 10; 199 m->crtc_hsync_end = m->crtc_htotal - 92; 200 m->crtc_vsync_start = m->crtc_vdisplay + 1; 201 m->crtc_vsync_end = m->crtc_vsync_start + 1; 202 if (m->flags & DRM_MODE_FLAG_INTERLACE) 203 interlaced = true; 204 } 205 206 decon_setup_trigger(ctx); 207 208 /* lcd on and use command if */ 209 val = VIDOUT_LCD_ON; 210 if (interlaced) 211 val |= VIDOUT_INTERLACE_EN_F; 212 if (crtc->i80_mode) { 213 val |= VIDOUT_COMMAND_IF; 214 } else { 215 val |= VIDOUT_RGB_IF; 216 } 217 218 writel(val, ctx->addr + DECON_VIDOUTCON0); 219 220 if (interlaced) 221 val = VIDTCON2_LINEVAL(m->vdisplay / 2 - 1) | 222 VIDTCON2_HOZVAL(m->hdisplay - 1); 223 else 224 val = VIDTCON2_LINEVAL(m->vdisplay - 1) | 225 VIDTCON2_HOZVAL(m->hdisplay - 1); 226 writel(val, ctx->addr + DECON_VIDTCON2); 227 228 if (!crtc->i80_mode) { 229 int vbp = m->crtc_vtotal - m->crtc_vsync_end; 230 int vfp = m->crtc_vsync_start - m->crtc_vdisplay; 231 232 if (interlaced) 233 vbp = vbp / 2 - 1; 234 val = VIDTCON00_VBPD_F(vbp - 1) | VIDTCON00_VFPD_F(vfp - 1); 235 writel(val, ctx->addr + DECON_VIDTCON00); 236 237 val = VIDTCON01_VSPW_F( 238 m->crtc_vsync_end - m->crtc_vsync_start - 1); 239 writel(val, ctx->addr + DECON_VIDTCON01); 240 241 val = VIDTCON10_HBPD_F( 242 m->crtc_htotal - m->crtc_hsync_end - 1) | 243 VIDTCON10_HFPD_F( 244 m->crtc_hsync_start - m->crtc_hdisplay - 1); 245 writel(val, ctx->addr + DECON_VIDTCON10); 246 247 val = VIDTCON11_HSPW_F( 248 m->crtc_hsync_end - m->crtc_hsync_start - 1); 249 writel(val, ctx->addr + DECON_VIDTCON11); 250 } 251 252 /* enable output and display signal */ 253 decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID | VIDCON0_ENVID_F, ~0); 254 255 decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0); 256 } 257 258 static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win, 259 struct drm_framebuffer *fb) 260 { 261 unsigned long val; 262 263 val = readl(ctx->addr + DECON_WINCONx(win)); 264 val &= ~WINCONx_BPPMODE_MASK; 265 266 switch (fb->format->format) { 267 case DRM_FORMAT_XRGB1555: 268 val |= WINCONx_BPPMODE_16BPP_I1555; 269 val |= WINCONx_HAWSWP_F; 270 val |= WINCONx_BURSTLEN_16WORD; 271 break; 272 case DRM_FORMAT_RGB565: 273 val |= WINCONx_BPPMODE_16BPP_565; 274 val |= WINCONx_HAWSWP_F; 275 val |= WINCONx_BURSTLEN_16WORD; 276 break; 277 case DRM_FORMAT_XRGB8888: 278 val |= WINCONx_BPPMODE_24BPP_888; 279 val |= WINCONx_WSWP_F; 280 val |= WINCONx_BURSTLEN_16WORD; 281 break; 282 case DRM_FORMAT_ARGB8888: 283 default: 284 val |= WINCONx_BPPMODE_32BPP_A8888; 285 val |= WINCONx_WSWP_F | WINCONx_BLD_PIX_F | WINCONx_ALPHA_SEL_F; 286 val |= WINCONx_BURSTLEN_16WORD; 287 break; 288 } 289 290 DRM_DEBUG_KMS("cpp = %u\n", fb->format->cpp[0]); 291 292 /* 293 * In case of exynos, setting dma-burst to 16Word causes permanent 294 * tearing for very small buffers, e.g. cursor buffer. Burst Mode 295 * switching which is based on plane size is not recommended as 296 * plane size varies a lot towards the end of the screen and rapid 297 * movement causes unstable DMA which results into iommu crash/tear. 298 */ 299 300 if (fb->width < MIN_FB_WIDTH_FOR_16WORD_BURST) { 301 val &= ~WINCONx_BURSTLEN_MASK; 302 val |= WINCONx_BURSTLEN_8WORD; 303 } 304 305 writel(val, ctx->addr + DECON_WINCONx(win)); 306 } 307 308 static void decon_shadow_protect(struct decon_context *ctx, bool protect) 309 { 310 decon_set_bits(ctx, DECON_SHADOWCON, SHADOWCON_PROTECT_MASK, 311 protect ? ~0 : 0); 312 } 313 314 static void decon_atomic_begin(struct exynos_drm_crtc *crtc) 315 { 316 struct decon_context *ctx = crtc->ctx; 317 318 decon_shadow_protect(ctx, true); 319 } 320 321 #define BIT_VAL(x, e, s) (((x) & ((1 << ((e) - (s) + 1)) - 1)) << (s)) 322 #define COORDINATE_X(x) BIT_VAL((x), 23, 12) 323 #define COORDINATE_Y(x) BIT_VAL((x), 11, 0) 324 325 static void decon_update_plane(struct exynos_drm_crtc *crtc, 326 struct exynos_drm_plane *plane) 327 { 328 struct exynos_drm_plane_state *state = 329 to_exynos_plane_state(plane->base.state); 330 struct decon_context *ctx = crtc->ctx; 331 struct drm_framebuffer *fb = state->base.fb; 332 unsigned int win = plane->index; 333 unsigned int cpp = fb->format->cpp[0]; 334 unsigned int pitch = fb->pitches[0]; 335 dma_addr_t dma_addr = exynos_drm_fb_dma_addr(fb, 0); 336 u32 val; 337 338 if (crtc->base.mode.flags & DRM_MODE_FLAG_INTERLACE) { 339 val = COORDINATE_X(state->crtc.x) | 340 COORDINATE_Y(state->crtc.y / 2); 341 writel(val, ctx->addr + DECON_VIDOSDxA(win)); 342 343 val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) | 344 COORDINATE_Y((state->crtc.y + state->crtc.h) / 2 - 1); 345 writel(val, ctx->addr + DECON_VIDOSDxB(win)); 346 } else { 347 val = COORDINATE_X(state->crtc.x) | COORDINATE_Y(state->crtc.y); 348 writel(val, ctx->addr + DECON_VIDOSDxA(win)); 349 350 val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) | 351 COORDINATE_Y(state->crtc.y + state->crtc.h - 1); 352 writel(val, ctx->addr + DECON_VIDOSDxB(win)); 353 } 354 355 val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) | 356 VIDOSD_Wx_ALPHA_B_F(0x0); 357 writel(val, ctx->addr + DECON_VIDOSDxC(win)); 358 359 val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) | 360 VIDOSD_Wx_ALPHA_B_F(0x0); 361 writel(val, ctx->addr + DECON_VIDOSDxD(win)); 362 363 writel(dma_addr, ctx->addr + DECON_VIDW0xADD0B0(win)); 364 365 val = dma_addr + pitch * state->src.h; 366 writel(val, ctx->addr + DECON_VIDW0xADD1B0(win)); 367 368 if (!(ctx->out_type & IFTYPE_HDMI)) 369 val = BIT_VAL(pitch - state->crtc.w * cpp, 27, 14) 370 | BIT_VAL(state->crtc.w * cpp, 13, 0); 371 else 372 val = BIT_VAL(pitch - state->crtc.w * cpp, 29, 15) 373 | BIT_VAL(state->crtc.w * cpp, 14, 0); 374 writel(val, ctx->addr + DECON_VIDW0xADD2(win)); 375 376 decon_win_set_pixfmt(ctx, win, fb); 377 378 /* window enable */ 379 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, ~0); 380 } 381 382 static void decon_disable_plane(struct exynos_drm_crtc *crtc, 383 struct exynos_drm_plane *plane) 384 { 385 struct decon_context *ctx = crtc->ctx; 386 unsigned int win = plane->index; 387 388 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0); 389 } 390 391 static void decon_atomic_flush(struct exynos_drm_crtc *crtc) 392 { 393 struct decon_context *ctx = crtc->ctx; 394 unsigned long flags; 395 396 spin_lock_irqsave(&ctx->vblank_lock, flags); 397 398 decon_shadow_protect(ctx, false); 399 400 decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0); 401 402 ctx->frame_id = decon_get_frame_count(ctx, true); 403 404 exynos_crtc_handle_event(crtc); 405 406 spin_unlock_irqrestore(&ctx->vblank_lock, flags); 407 } 408 409 static void decon_swreset(struct decon_context *ctx) 410 { 411 unsigned long flags; 412 u32 val; 413 int ret; 414 415 writel(0, ctx->addr + DECON_VIDCON0); 416 readl_poll_timeout(ctx->addr + DECON_VIDCON0, val, 417 ~val & VIDCON0_STOP_STATUS, 12, 20000); 418 419 writel(VIDCON0_SWRESET, ctx->addr + DECON_VIDCON0); 420 ret = readl_poll_timeout(ctx->addr + DECON_VIDCON0, val, 421 ~val & VIDCON0_SWRESET, 12, 20000); 422 423 WARN(ret < 0, "failed to software reset DECON\n"); 424 425 spin_lock_irqsave(&ctx->vblank_lock, flags); 426 ctx->frame_id = 0; 427 spin_unlock_irqrestore(&ctx->vblank_lock, flags); 428 429 if (!(ctx->out_type & IFTYPE_HDMI)) 430 return; 431 432 writel(VIDCON0_CLKVALUP | VIDCON0_VLCKFREE, ctx->addr + DECON_VIDCON0); 433 decon_set_bits(ctx, DECON_CMU, 434 CMU_CLKGAGE_MODE_SFR_F | CMU_CLKGAGE_MODE_MEM_F, ~0); 435 writel(VIDCON1_VCLK_RUN_VDEN_DISABLE, ctx->addr + DECON_VIDCON1); 436 writel(CRCCTRL_CRCEN | CRCCTRL_CRCSTART_F | CRCCTRL_CRCCLKEN, 437 ctx->addr + DECON_CRCCTRL); 438 } 439 440 static void decon_enable(struct exynos_drm_crtc *crtc) 441 { 442 struct decon_context *ctx = crtc->ctx; 443 444 pm_runtime_get_sync(ctx->dev); 445 446 exynos_drm_pipe_clk_enable(crtc, true); 447 448 decon_swreset(ctx); 449 450 decon_commit(ctx->crtc); 451 } 452 453 static void decon_disable(struct exynos_drm_crtc *crtc) 454 { 455 struct decon_context *ctx = crtc->ctx; 456 int i; 457 458 if (!(ctx->out_type & I80_HW_TRG)) 459 synchronize_irq(ctx->te_irq); 460 synchronize_irq(ctx->irq); 461 462 /* 463 * We need to make sure that all windows are disabled before we 464 * suspend that connector. Otherwise we might try to scan from 465 * a destroyed buffer later. 466 */ 467 for (i = ctx->first_win; i < WINDOWS_NR; i++) 468 decon_disable_plane(crtc, &ctx->planes[i]); 469 470 decon_swreset(ctx); 471 472 exynos_drm_pipe_clk_enable(crtc, false); 473 474 pm_runtime_put_sync(ctx->dev); 475 } 476 477 static irqreturn_t decon_te_irq_handler(int irq, void *dev_id) 478 { 479 struct decon_context *ctx = dev_id; 480 481 decon_set_bits(ctx, DECON_TRIGCON, TRIGCON_SWTRIGCMD, ~0); 482 483 return IRQ_HANDLED; 484 } 485 486 static void decon_clear_channels(struct exynos_drm_crtc *crtc) 487 { 488 struct decon_context *ctx = crtc->ctx; 489 int win, i, ret; 490 491 DRM_DEBUG_KMS("%s\n", __FILE__); 492 493 for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) { 494 ret = clk_prepare_enable(ctx->clks[i]); 495 if (ret < 0) 496 goto err; 497 } 498 499 decon_shadow_protect(ctx, true); 500 for (win = 0; win < WINDOWS_NR; win++) 501 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0); 502 decon_shadow_protect(ctx, false); 503 504 decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0); 505 506 /* TODO: wait for possible vsync */ 507 msleep(50); 508 509 err: 510 while (--i >= 0) 511 clk_disable_unprepare(ctx->clks[i]); 512 } 513 514 static enum drm_mode_status decon_mode_valid(struct exynos_drm_crtc *crtc, 515 const struct drm_display_mode *mode) 516 { 517 struct decon_context *ctx = crtc->ctx; 518 519 ctx->irq = crtc->i80_mode ? ctx->irq_lcd_sys : ctx->irq_vsync; 520 521 if (ctx->irq) 522 return MODE_OK; 523 524 dev_info(ctx->dev, "Sink requires %s mode, but appropriate interrupt is not provided.\n", 525 crtc->i80_mode ? "command" : "video"); 526 527 return MODE_BAD; 528 } 529 530 static const struct exynos_drm_crtc_ops decon_crtc_ops = { 531 .enable = decon_enable, 532 .disable = decon_disable, 533 .enable_vblank = decon_enable_vblank, 534 .disable_vblank = decon_disable_vblank, 535 .get_vblank_counter = decon_get_vblank_counter, 536 .atomic_begin = decon_atomic_begin, 537 .update_plane = decon_update_plane, 538 .disable_plane = decon_disable_plane, 539 .mode_valid = decon_mode_valid, 540 .atomic_flush = decon_atomic_flush, 541 }; 542 543 static int decon_bind(struct device *dev, struct device *master, void *data) 544 { 545 struct decon_context *ctx = dev_get_drvdata(dev); 546 struct drm_device *drm_dev = data; 547 struct exynos_drm_plane *exynos_plane; 548 enum exynos_drm_output_type out_type; 549 unsigned int win; 550 int ret; 551 552 ctx->drm_dev = drm_dev; 553 drm_dev->max_vblank_count = 0xffffffff; 554 555 for (win = ctx->first_win; win < WINDOWS_NR; win++) { 556 int tmp = (win == ctx->first_win) ? 0 : win; 557 558 ctx->configs[win].pixel_formats = decon_formats; 559 ctx->configs[win].num_pixel_formats = ARRAY_SIZE(decon_formats); 560 ctx->configs[win].zpos = win; 561 ctx->configs[win].type = decon_win_types[tmp]; 562 563 ret = exynos_plane_init(drm_dev, &ctx->planes[win], win, 564 &ctx->configs[win]); 565 if (ret) 566 return ret; 567 } 568 569 exynos_plane = &ctx->planes[ctx->first_win]; 570 out_type = (ctx->out_type & IFTYPE_HDMI) ? EXYNOS_DISPLAY_TYPE_HDMI 571 : EXYNOS_DISPLAY_TYPE_LCD; 572 ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base, 573 out_type, &decon_crtc_ops, ctx); 574 if (IS_ERR(ctx->crtc)) 575 return PTR_ERR(ctx->crtc); 576 577 decon_clear_channels(ctx->crtc); 578 579 return drm_iommu_attach_device(drm_dev, dev); 580 } 581 582 static void decon_unbind(struct device *dev, struct device *master, void *data) 583 { 584 struct decon_context *ctx = dev_get_drvdata(dev); 585 586 decon_disable(ctx->crtc); 587 588 /* detach this sub driver from iommu mapping if supported. */ 589 drm_iommu_detach_device(ctx->drm_dev, ctx->dev); 590 } 591 592 static const struct component_ops decon_component_ops = { 593 .bind = decon_bind, 594 .unbind = decon_unbind, 595 }; 596 597 static void decon_handle_vblank(struct decon_context *ctx) 598 { 599 u32 frm; 600 601 spin_lock(&ctx->vblank_lock); 602 603 frm = decon_get_frame_count(ctx, true); 604 605 if (frm != ctx->frame_id) { 606 /* handle only if incremented, take care of wrap-around */ 607 if ((s32)(frm - ctx->frame_id) > 0) 608 drm_crtc_handle_vblank(&ctx->crtc->base); 609 ctx->frame_id = frm; 610 } 611 612 spin_unlock(&ctx->vblank_lock); 613 } 614 615 static irqreturn_t decon_irq_handler(int irq, void *dev_id) 616 { 617 struct decon_context *ctx = dev_id; 618 u32 val; 619 620 val = readl(ctx->addr + DECON_VIDINTCON1); 621 val &= VIDINTCON1_INTFRMDONEPEND | VIDINTCON1_INTFRMPEND; 622 623 if (val) { 624 writel(val, ctx->addr + DECON_VIDINTCON1); 625 if (ctx->out_type & IFTYPE_HDMI) { 626 val = readl(ctx->addr + DECON_VIDOUTCON0); 627 val &= VIDOUT_INTERLACE_EN_F | VIDOUT_INTERLACE_FIELD_F; 628 if (val == 629 (VIDOUT_INTERLACE_EN_F | VIDOUT_INTERLACE_FIELD_F)) 630 return IRQ_HANDLED; 631 } 632 decon_handle_vblank(ctx); 633 } 634 635 return IRQ_HANDLED; 636 } 637 638 #ifdef CONFIG_PM 639 static int exynos5433_decon_suspend(struct device *dev) 640 { 641 struct decon_context *ctx = dev_get_drvdata(dev); 642 int i = ARRAY_SIZE(decon_clks_name); 643 644 while (--i >= 0) 645 clk_disable_unprepare(ctx->clks[i]); 646 647 return 0; 648 } 649 650 static int exynos5433_decon_resume(struct device *dev) 651 { 652 struct decon_context *ctx = dev_get_drvdata(dev); 653 int i, ret; 654 655 for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) { 656 ret = clk_prepare_enable(ctx->clks[i]); 657 if (ret < 0) 658 goto err; 659 } 660 661 return 0; 662 663 err: 664 while (--i >= 0) 665 clk_disable_unprepare(ctx->clks[i]); 666 667 return ret; 668 } 669 #endif 670 671 static const struct dev_pm_ops exynos5433_decon_pm_ops = { 672 SET_RUNTIME_PM_OPS(exynos5433_decon_suspend, exynos5433_decon_resume, 673 NULL) 674 }; 675 676 static const struct of_device_id exynos5433_decon_driver_dt_match[] = { 677 { 678 .compatible = "samsung,exynos5433-decon", 679 .data = (void *)I80_HW_TRG 680 }, 681 { 682 .compatible = "samsung,exynos5433-decon-tv", 683 .data = (void *)(I80_HW_TRG | IFTYPE_HDMI) 684 }, 685 {}, 686 }; 687 MODULE_DEVICE_TABLE(of, exynos5433_decon_driver_dt_match); 688 689 static int decon_conf_irq(struct decon_context *ctx, const char *name, 690 irq_handler_t handler, unsigned long int flags) 691 { 692 struct platform_device *pdev = to_platform_device(ctx->dev); 693 int ret, irq = platform_get_irq_byname(pdev, name); 694 695 if (irq < 0) { 696 switch (irq) { 697 case -EPROBE_DEFER: 698 return irq; 699 case -ENODATA: 700 case -ENXIO: 701 return 0; 702 default: 703 dev_err(ctx->dev, "IRQ %s get failed, %d\n", name, irq); 704 return irq; 705 } 706 } 707 irq_set_status_flags(irq, IRQ_NOAUTOEN); 708 ret = devm_request_irq(ctx->dev, irq, handler, flags, "drm_decon", ctx); 709 if (ret < 0) { 710 dev_err(ctx->dev, "IRQ %s request failed\n", name); 711 return ret; 712 } 713 714 return irq; 715 } 716 717 static int exynos5433_decon_probe(struct platform_device *pdev) 718 { 719 struct device *dev = &pdev->dev; 720 struct decon_context *ctx; 721 struct resource *res; 722 int ret; 723 int i; 724 725 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 726 if (!ctx) 727 return -ENOMEM; 728 729 ctx->dev = dev; 730 ctx->out_type = (unsigned long)of_device_get_match_data(dev); 731 spin_lock_init(&ctx->vblank_lock); 732 733 if (ctx->out_type & IFTYPE_HDMI) 734 ctx->first_win = 1; 735 736 for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) { 737 struct clk *clk; 738 739 clk = devm_clk_get(ctx->dev, decon_clks_name[i]); 740 if (IS_ERR(clk)) 741 return PTR_ERR(clk); 742 743 ctx->clks[i] = clk; 744 } 745 746 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 747 if (!res) { 748 dev_err(dev, "cannot find IO resource\n"); 749 return -ENXIO; 750 } 751 752 ctx->addr = devm_ioremap_resource(dev, res); 753 if (IS_ERR(ctx->addr)) { 754 dev_err(dev, "ioremap failed\n"); 755 return PTR_ERR(ctx->addr); 756 } 757 758 ret = decon_conf_irq(ctx, "vsync", decon_irq_handler, 0); 759 if (ret < 0) 760 return ret; 761 ctx->irq_vsync = ret; 762 763 ret = decon_conf_irq(ctx, "lcd_sys", decon_irq_handler, 0); 764 if (ret < 0) 765 return ret; 766 ctx->irq_lcd_sys = ret; 767 768 ret = decon_conf_irq(ctx, "te", decon_te_irq_handler, 769 IRQF_TRIGGER_RISING); 770 if (ret < 0) 771 return ret; 772 if (ret) { 773 ctx->te_irq = ret; 774 ctx->out_type &= ~I80_HW_TRG; 775 } 776 777 if (ctx->out_type & I80_HW_TRG) { 778 ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node, 779 "samsung,disp-sysreg"); 780 if (IS_ERR(ctx->sysreg)) { 781 dev_err(dev, "failed to get system register\n"); 782 return PTR_ERR(ctx->sysreg); 783 } 784 } 785 786 platform_set_drvdata(pdev, ctx); 787 788 pm_runtime_enable(dev); 789 790 ret = component_add(dev, &decon_component_ops); 791 if (ret) 792 goto err_disable_pm_runtime; 793 794 return 0; 795 796 err_disable_pm_runtime: 797 pm_runtime_disable(dev); 798 799 return ret; 800 } 801 802 static int exynos5433_decon_remove(struct platform_device *pdev) 803 { 804 pm_runtime_disable(&pdev->dev); 805 806 component_del(&pdev->dev, &decon_component_ops); 807 808 return 0; 809 } 810 811 struct platform_driver exynos5433_decon_driver = { 812 .probe = exynos5433_decon_probe, 813 .remove = exynos5433_decon_remove, 814 .driver = { 815 .name = "exynos5433-decon", 816 .pm = &exynos5433_decon_pm_ops, 817 .of_match_table = exynos5433_decon_driver_dt_match, 818 }, 819 }; 820