1 /* 2 * Actions Semi Owl family serial console 3 * 4 * Copyright 2013 Actions Semi Inc. 5 * Author: Actions Semi, Inc. 6 * 7 * Copyright (c) 2016-2017 Andreas Färber 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or (at your 12 * option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program. If not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include <linux/clk.h> 24 #include <linux/console.h> 25 #include <linux/delay.h> 26 #include <linux/io.h> 27 #include <linux/module.h> 28 #include <linux/of.h> 29 #include <linux/platform_device.h> 30 #include <linux/serial.h> 31 #include <linux/serial_core.h> 32 #include <linux/tty.h> 33 #include <linux/tty_flip.h> 34 35 #define OWL_UART_PORT_NUM 7 36 #define OWL_UART_DEV_NAME "ttyOWL" 37 38 #define OWL_UART_CTL 0x000 39 #define OWL_UART_RXDAT 0x004 40 #define OWL_UART_TXDAT 0x008 41 #define OWL_UART_STAT 0x00c 42 43 #define OWL_UART_CTL_DWLS_MASK GENMASK(1, 0) 44 #define OWL_UART_CTL_DWLS_5BITS (0x0 << 0) 45 #define OWL_UART_CTL_DWLS_6BITS (0x1 << 0) 46 #define OWL_UART_CTL_DWLS_7BITS (0x2 << 0) 47 #define OWL_UART_CTL_DWLS_8BITS (0x3 << 0) 48 #define OWL_UART_CTL_STPS_2BITS BIT(2) 49 #define OWL_UART_CTL_PRS_MASK GENMASK(6, 4) 50 #define OWL_UART_CTL_PRS_NONE (0x0 << 4) 51 #define OWL_UART_CTL_PRS_ODD (0x4 << 4) 52 #define OWL_UART_CTL_PRS_MARK (0x5 << 4) 53 #define OWL_UART_CTL_PRS_EVEN (0x6 << 4) 54 #define OWL_UART_CTL_PRS_SPACE (0x7 << 4) 55 #define OWL_UART_CTL_AFE BIT(12) 56 #define OWL_UART_CTL_TRFS_TX BIT(14) 57 #define OWL_UART_CTL_EN BIT(15) 58 #define OWL_UART_CTL_RXDE BIT(16) 59 #define OWL_UART_CTL_TXDE BIT(17) 60 #define OWL_UART_CTL_RXIE BIT(18) 61 #define OWL_UART_CTL_TXIE BIT(19) 62 #define OWL_UART_CTL_LBEN BIT(20) 63 64 #define OWL_UART_STAT_RIP BIT(0) 65 #define OWL_UART_STAT_TIP BIT(1) 66 #define OWL_UART_STAT_RXER BIT(2) 67 #define OWL_UART_STAT_TFER BIT(3) 68 #define OWL_UART_STAT_RXST BIT(4) 69 #define OWL_UART_STAT_RFEM BIT(5) 70 #define OWL_UART_STAT_TFFU BIT(6) 71 #define OWL_UART_STAT_CTSS BIT(7) 72 #define OWL_UART_STAT_RTSS BIT(8) 73 #define OWL_UART_STAT_TFES BIT(10) 74 #define OWL_UART_STAT_TRFL_MASK GENMASK(16, 11) 75 #define OWL_UART_STAT_UTBB BIT(17) 76 77 static struct uart_driver owl_uart_driver; 78 79 struct owl_uart_info { 80 unsigned int tx_fifosize; 81 }; 82 83 struct owl_uart_port { 84 struct uart_port port; 85 struct clk *clk; 86 }; 87 88 #define to_owl_uart_port(prt) container_of(prt, struct owl_uart_port, prt) 89 90 static struct owl_uart_port *owl_uart_ports[OWL_UART_PORT_NUM]; 91 92 static inline void owl_uart_write(struct uart_port *port, u32 val, unsigned int off) 93 { 94 writel(val, port->membase + off); 95 } 96 97 static inline u32 owl_uart_read(struct uart_port *port, unsigned int off) 98 { 99 return readl(port->membase + off); 100 } 101 102 static void owl_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 103 { 104 u32 ctl; 105 106 ctl = owl_uart_read(port, OWL_UART_CTL); 107 108 if (mctrl & TIOCM_LOOP) 109 ctl |= OWL_UART_CTL_LBEN; 110 else 111 ctl &= ~OWL_UART_CTL_LBEN; 112 113 owl_uart_write(port, ctl, OWL_UART_CTL); 114 } 115 116 static unsigned int owl_uart_get_mctrl(struct uart_port *port) 117 { 118 unsigned int mctrl = TIOCM_CAR | TIOCM_DSR; 119 u32 stat, ctl; 120 121 ctl = owl_uart_read(port, OWL_UART_CTL); 122 stat = owl_uart_read(port, OWL_UART_STAT); 123 if (stat & OWL_UART_STAT_RTSS) 124 mctrl |= TIOCM_RTS; 125 if ((stat & OWL_UART_STAT_CTSS) || !(ctl & OWL_UART_CTL_AFE)) 126 mctrl |= TIOCM_CTS; 127 return mctrl; 128 } 129 130 static unsigned int owl_uart_tx_empty(struct uart_port *port) 131 { 132 unsigned long flags; 133 u32 val; 134 unsigned int ret; 135 136 spin_lock_irqsave(&port->lock, flags); 137 138 val = owl_uart_read(port, OWL_UART_STAT); 139 ret = (val & OWL_UART_STAT_TFES) ? TIOCSER_TEMT : 0; 140 141 spin_unlock_irqrestore(&port->lock, flags); 142 143 return ret; 144 } 145 146 static void owl_uart_stop_rx(struct uart_port *port) 147 { 148 u32 val; 149 150 val = owl_uart_read(port, OWL_UART_CTL); 151 val &= ~(OWL_UART_CTL_RXIE | OWL_UART_CTL_RXDE); 152 owl_uart_write(port, val, OWL_UART_CTL); 153 154 val = owl_uart_read(port, OWL_UART_STAT); 155 val |= OWL_UART_STAT_RIP; 156 owl_uart_write(port, val, OWL_UART_STAT); 157 } 158 159 static void owl_uart_stop_tx(struct uart_port *port) 160 { 161 u32 val; 162 163 val = owl_uart_read(port, OWL_UART_CTL); 164 val &= ~(OWL_UART_CTL_TXIE | OWL_UART_CTL_TXDE); 165 owl_uart_write(port, val, OWL_UART_CTL); 166 167 val = owl_uart_read(port, OWL_UART_STAT); 168 val |= OWL_UART_STAT_TIP; 169 owl_uart_write(port, val, OWL_UART_STAT); 170 } 171 172 static void owl_uart_start_tx(struct uart_port *port) 173 { 174 u32 val; 175 176 if (uart_tx_stopped(port)) { 177 owl_uart_stop_tx(port); 178 return; 179 } 180 181 val = owl_uart_read(port, OWL_UART_STAT); 182 val |= OWL_UART_STAT_TIP; 183 owl_uart_write(port, val, OWL_UART_STAT); 184 185 val = owl_uart_read(port, OWL_UART_CTL); 186 val |= OWL_UART_CTL_TXIE; 187 owl_uart_write(port, val, OWL_UART_CTL); 188 } 189 190 static void owl_uart_send_chars(struct uart_port *port) 191 { 192 struct circ_buf *xmit = &port->state->xmit; 193 unsigned int ch; 194 195 if (uart_tx_stopped(port)) 196 return; 197 198 if (port->x_char) { 199 while (!(owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TFFU)) 200 cpu_relax(); 201 owl_uart_write(port, port->x_char, OWL_UART_TXDAT); 202 port->icount.tx++; 203 port->x_char = 0; 204 } 205 206 while (!(owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TFFU)) { 207 if (uart_circ_empty(xmit)) 208 break; 209 210 ch = xmit->buf[xmit->tail]; 211 owl_uart_write(port, ch, OWL_UART_TXDAT); 212 xmit->tail = (xmit->tail + 1) & (SERIAL_XMIT_SIZE - 1); 213 port->icount.tx++; 214 } 215 216 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 217 uart_write_wakeup(port); 218 219 if (uart_circ_empty(xmit)) 220 owl_uart_stop_tx(port); 221 } 222 223 static void owl_uart_receive_chars(struct uart_port *port) 224 { 225 u32 stat, val; 226 227 val = owl_uart_read(port, OWL_UART_CTL); 228 val &= ~OWL_UART_CTL_TRFS_TX; 229 owl_uart_write(port, val, OWL_UART_CTL); 230 231 stat = owl_uart_read(port, OWL_UART_STAT); 232 while (!(stat & OWL_UART_STAT_RFEM)) { 233 char flag = TTY_NORMAL; 234 235 if (stat & OWL_UART_STAT_RXER) 236 port->icount.overrun++; 237 238 if (stat & OWL_UART_STAT_RXST) { 239 /* We are not able to distinguish the error type. */ 240 port->icount.brk++; 241 port->icount.frame++; 242 243 stat &= port->read_status_mask; 244 if (stat & OWL_UART_STAT_RXST) 245 flag = TTY_PARITY; 246 } else 247 port->icount.rx++; 248 249 val = owl_uart_read(port, OWL_UART_RXDAT); 250 val &= 0xff; 251 252 if ((stat & port->ignore_status_mask) == 0) 253 tty_insert_flip_char(&port->state->port, val, flag); 254 255 stat = owl_uart_read(port, OWL_UART_STAT); 256 } 257 258 spin_unlock(&port->lock); 259 tty_flip_buffer_push(&port->state->port); 260 spin_lock(&port->lock); 261 } 262 263 static irqreturn_t owl_uart_irq(int irq, void *dev_id) 264 { 265 struct uart_port *port = dev_id; 266 unsigned long flags; 267 u32 stat; 268 269 spin_lock_irqsave(&port->lock, flags); 270 271 stat = owl_uart_read(port, OWL_UART_STAT); 272 273 if (stat & OWL_UART_STAT_RIP) 274 owl_uart_receive_chars(port); 275 276 if (stat & OWL_UART_STAT_TIP) 277 owl_uart_send_chars(port); 278 279 stat = owl_uart_read(port, OWL_UART_STAT); 280 stat |= OWL_UART_STAT_RIP | OWL_UART_STAT_TIP; 281 owl_uart_write(port, stat, OWL_UART_STAT); 282 283 spin_unlock_irqrestore(&port->lock, flags); 284 285 return IRQ_HANDLED; 286 } 287 288 static void owl_uart_shutdown(struct uart_port *port) 289 { 290 u32 val; 291 unsigned long flags; 292 293 spin_lock_irqsave(&port->lock, flags); 294 295 val = owl_uart_read(port, OWL_UART_CTL); 296 val &= ~(OWL_UART_CTL_TXIE | OWL_UART_CTL_RXIE 297 | OWL_UART_CTL_TXDE | OWL_UART_CTL_RXDE | OWL_UART_CTL_EN); 298 owl_uart_write(port, val, OWL_UART_CTL); 299 300 spin_unlock_irqrestore(&port->lock, flags); 301 302 free_irq(port->irq, port); 303 } 304 305 static int owl_uart_startup(struct uart_port *port) 306 { 307 u32 val; 308 unsigned long flags; 309 int ret; 310 311 ret = request_irq(port->irq, owl_uart_irq, IRQF_TRIGGER_HIGH, 312 "owl-uart", port); 313 if (ret) 314 return ret; 315 316 spin_lock_irqsave(&port->lock, flags); 317 318 val = owl_uart_read(port, OWL_UART_STAT); 319 val |= OWL_UART_STAT_RIP | OWL_UART_STAT_TIP 320 | OWL_UART_STAT_RXER | OWL_UART_STAT_TFER | OWL_UART_STAT_RXST; 321 owl_uart_write(port, val, OWL_UART_STAT); 322 323 val = owl_uart_read(port, OWL_UART_CTL); 324 val |= OWL_UART_CTL_RXIE | OWL_UART_CTL_TXIE; 325 val |= OWL_UART_CTL_EN; 326 owl_uart_write(port, val, OWL_UART_CTL); 327 328 spin_unlock_irqrestore(&port->lock, flags); 329 330 return 0; 331 } 332 333 static void owl_uart_change_baudrate(struct owl_uart_port *owl_port, 334 unsigned long baud) 335 { 336 clk_set_rate(owl_port->clk, baud * 8); 337 } 338 339 static void owl_uart_set_termios(struct uart_port *port, 340 struct ktermios *termios, 341 struct ktermios *old) 342 { 343 struct owl_uart_port *owl_port = to_owl_uart_port(port); 344 unsigned int baud; 345 u32 ctl; 346 unsigned long flags; 347 348 spin_lock_irqsave(&port->lock, flags); 349 350 ctl = owl_uart_read(port, OWL_UART_CTL); 351 352 ctl &= ~OWL_UART_CTL_DWLS_MASK; 353 switch (termios->c_cflag & CSIZE) { 354 case CS5: 355 ctl |= OWL_UART_CTL_DWLS_5BITS; 356 break; 357 case CS6: 358 ctl |= OWL_UART_CTL_DWLS_6BITS; 359 break; 360 case CS7: 361 ctl |= OWL_UART_CTL_DWLS_7BITS; 362 break; 363 case CS8: 364 default: 365 ctl |= OWL_UART_CTL_DWLS_8BITS; 366 break; 367 } 368 369 if (termios->c_cflag & CSTOPB) 370 ctl |= OWL_UART_CTL_STPS_2BITS; 371 else 372 ctl &= ~OWL_UART_CTL_STPS_2BITS; 373 374 ctl &= ~OWL_UART_CTL_PRS_MASK; 375 if (termios->c_cflag & PARENB) { 376 if (termios->c_cflag & CMSPAR) { 377 if (termios->c_cflag & PARODD) 378 ctl |= OWL_UART_CTL_PRS_MARK; 379 else 380 ctl |= OWL_UART_CTL_PRS_SPACE; 381 } else if (termios->c_cflag & PARODD) 382 ctl |= OWL_UART_CTL_PRS_ODD; 383 else 384 ctl |= OWL_UART_CTL_PRS_EVEN; 385 } else 386 ctl |= OWL_UART_CTL_PRS_NONE; 387 388 if (termios->c_cflag & CRTSCTS) 389 ctl |= OWL_UART_CTL_AFE; 390 else 391 ctl &= ~OWL_UART_CTL_AFE; 392 393 owl_uart_write(port, ctl, OWL_UART_CTL); 394 395 baud = uart_get_baud_rate(port, termios, old, 9600, 3200000); 396 owl_uart_change_baudrate(owl_port, baud); 397 398 /* Don't rewrite B0 */ 399 if (tty_termios_baud_rate(termios)) 400 tty_termios_encode_baud_rate(termios, baud, baud); 401 402 port->read_status_mask |= OWL_UART_STAT_RXER; 403 if (termios->c_iflag & INPCK) 404 port->read_status_mask |= OWL_UART_STAT_RXST; 405 406 uart_update_timeout(port, termios->c_cflag, baud); 407 408 spin_unlock_irqrestore(&port->lock, flags); 409 } 410 411 static void owl_uart_release_port(struct uart_port *port) 412 { 413 struct platform_device *pdev = to_platform_device(port->dev); 414 struct resource *res; 415 416 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 417 if (!res) 418 return; 419 420 if (port->flags & UPF_IOREMAP) { 421 devm_release_mem_region(port->dev, port->mapbase, 422 resource_size(res)); 423 devm_iounmap(port->dev, port->membase); 424 port->membase = NULL; 425 } 426 } 427 428 static int owl_uart_request_port(struct uart_port *port) 429 { 430 struct platform_device *pdev = to_platform_device(port->dev); 431 struct resource *res; 432 433 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 434 if (!res) 435 return -ENXIO; 436 437 if (!devm_request_mem_region(port->dev, port->mapbase, 438 resource_size(res), dev_name(port->dev))) 439 return -EBUSY; 440 441 if (port->flags & UPF_IOREMAP) { 442 port->membase = devm_ioremap_nocache(port->dev, port->mapbase, 443 resource_size(res)); 444 if (!port->membase) 445 return -EBUSY; 446 } 447 448 return 0; 449 } 450 451 static const char *owl_uart_type(struct uart_port *port) 452 { 453 return (port->type == PORT_OWL) ? "owl-uart" : NULL; 454 } 455 456 static int owl_uart_verify_port(struct uart_port *port, 457 struct serial_struct *ser) 458 { 459 if (port->type != PORT_OWL) 460 return -EINVAL; 461 462 if (port->irq != ser->irq) 463 return -EINVAL; 464 465 return 0; 466 } 467 468 static void owl_uart_config_port(struct uart_port *port, int flags) 469 { 470 if (flags & UART_CONFIG_TYPE) { 471 port->type = PORT_OWL; 472 owl_uart_request_port(port); 473 } 474 } 475 476 static const struct uart_ops owl_uart_ops = { 477 .set_mctrl = owl_uart_set_mctrl, 478 .get_mctrl = owl_uart_get_mctrl, 479 .tx_empty = owl_uart_tx_empty, 480 .start_tx = owl_uart_start_tx, 481 .stop_rx = owl_uart_stop_rx, 482 .stop_tx = owl_uart_stop_tx, 483 .startup = owl_uart_startup, 484 .shutdown = owl_uart_shutdown, 485 .set_termios = owl_uart_set_termios, 486 .type = owl_uart_type, 487 .config_port = owl_uart_config_port, 488 .request_port = owl_uart_request_port, 489 .release_port = owl_uart_release_port, 490 .verify_port = owl_uart_verify_port, 491 }; 492 493 #ifdef CONFIG_SERIAL_OWL_CONSOLE 494 495 static void owl_console_putchar(struct uart_port *port, int ch) 496 { 497 if (!port->membase) 498 return; 499 500 while (owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TFFU) 501 cpu_relax(); 502 503 owl_uart_write(port, ch, OWL_UART_TXDAT); 504 } 505 506 static void owl_uart_port_write(struct uart_port *port, const char *s, 507 u_int count) 508 { 509 u32 old_ctl, val; 510 unsigned long flags; 511 int locked; 512 513 local_irq_save(flags); 514 515 if (port->sysrq) 516 locked = 0; 517 else if (oops_in_progress) 518 locked = spin_trylock(&port->lock); 519 else { 520 spin_lock(&port->lock); 521 locked = 1; 522 } 523 524 old_ctl = owl_uart_read(port, OWL_UART_CTL); 525 val = old_ctl | OWL_UART_CTL_TRFS_TX; 526 /* disable IRQ */ 527 val &= ~(OWL_UART_CTL_RXIE | OWL_UART_CTL_TXIE); 528 owl_uart_write(port, val, OWL_UART_CTL); 529 530 uart_console_write(port, s, count, owl_console_putchar); 531 532 /* wait until all contents have been sent out */ 533 while (owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TRFL_MASK) 534 cpu_relax(); 535 536 /* clear IRQ pending */ 537 val = owl_uart_read(port, OWL_UART_STAT); 538 val |= OWL_UART_STAT_TIP | OWL_UART_STAT_RIP; 539 owl_uart_write(port, val, OWL_UART_STAT); 540 541 owl_uart_write(port, old_ctl, OWL_UART_CTL); 542 543 if (locked) 544 spin_unlock(&port->lock); 545 546 local_irq_restore(flags); 547 } 548 549 static void owl_uart_console_write(struct console *co, const char *s, 550 u_int count) 551 { 552 struct owl_uart_port *owl_port; 553 554 owl_port = owl_uart_ports[co->index]; 555 if (!owl_port) 556 return; 557 558 owl_uart_port_write(&owl_port->port, s, count); 559 } 560 561 static int owl_uart_console_setup(struct console *co, char *options) 562 { 563 struct owl_uart_port *owl_port; 564 int baud = 115200; 565 int bits = 8; 566 int parity = 'n'; 567 int flow = 'n'; 568 569 if (co->index < 0 || co->index >= OWL_UART_PORT_NUM) 570 return -EINVAL; 571 572 owl_port = owl_uart_ports[co->index]; 573 if (!owl_port || !owl_port->port.membase) 574 return -ENODEV; 575 576 if (options) 577 uart_parse_options(options, &baud, &parity, &bits, &flow); 578 579 return uart_set_options(&owl_port->port, co, baud, parity, bits, flow); 580 } 581 582 static struct console owl_uart_console = { 583 .name = OWL_UART_DEV_NAME, 584 .write = owl_uart_console_write, 585 .device = uart_console_device, 586 .setup = owl_uart_console_setup, 587 .flags = CON_PRINTBUFFER, 588 .index = -1, 589 .data = &owl_uart_driver, 590 }; 591 592 static int __init owl_uart_console_init(void) 593 { 594 register_console(&owl_uart_console); 595 596 return 0; 597 } 598 console_initcall(owl_uart_console_init); 599 600 static void owl_uart_early_console_write(struct console *co, 601 const char *s, 602 u_int count) 603 { 604 struct earlycon_device *dev = co->data; 605 606 owl_uart_port_write(&dev->port, s, count); 607 } 608 609 static int __init 610 owl_uart_early_console_setup(struct earlycon_device *device, const char *opt) 611 { 612 if (!device->port.membase) 613 return -ENODEV; 614 615 device->con->write = owl_uart_early_console_write; 616 617 return 0; 618 } 619 OF_EARLYCON_DECLARE(owl, "actions,owl-uart", 620 owl_uart_early_console_setup); 621 622 #define OWL_UART_CONSOLE (&owl_uart_console) 623 #else 624 #define OWL_UART_CONSOLE NULL 625 #endif 626 627 static struct uart_driver owl_uart_driver = { 628 .owner = THIS_MODULE, 629 .driver_name = "owl-uart", 630 .dev_name = OWL_UART_DEV_NAME, 631 .nr = OWL_UART_PORT_NUM, 632 .cons = OWL_UART_CONSOLE, 633 }; 634 635 static const struct owl_uart_info owl_s500_info = { 636 .tx_fifosize = 16, 637 }; 638 639 static const struct owl_uart_info owl_s900_info = { 640 .tx_fifosize = 32, 641 }; 642 643 static const struct of_device_id owl_uart_dt_matches[] = { 644 { .compatible = "actions,s500-uart", .data = &owl_s500_info }, 645 { .compatible = "actions,s900-uart", .data = &owl_s900_info }, 646 { } 647 }; 648 MODULE_DEVICE_TABLE(of, owl_uart_dt_matches); 649 650 static int owl_uart_probe(struct platform_device *pdev) 651 { 652 const struct of_device_id *match; 653 const struct owl_uart_info *info = NULL; 654 struct resource *res_mem; 655 struct owl_uart_port *owl_port; 656 int ret, irq; 657 658 if (pdev->dev.of_node) { 659 pdev->id = of_alias_get_id(pdev->dev.of_node, "serial"); 660 match = of_match_node(owl_uart_dt_matches, pdev->dev.of_node); 661 if (match) 662 info = match->data; 663 } 664 665 if (pdev->id < 0 || pdev->id >= OWL_UART_PORT_NUM) { 666 dev_err(&pdev->dev, "id %d out of range\n", pdev->id); 667 return -EINVAL; 668 } 669 670 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 671 if (!res_mem) { 672 dev_err(&pdev->dev, "could not get mem\n"); 673 return -ENODEV; 674 } 675 676 irq = platform_get_irq(pdev, 0); 677 if (irq < 0) { 678 dev_err(&pdev->dev, "could not get irq\n"); 679 return irq; 680 } 681 682 if (owl_uart_ports[pdev->id]) { 683 dev_err(&pdev->dev, "port %d already allocated\n", pdev->id); 684 return -EBUSY; 685 } 686 687 owl_port = devm_kzalloc(&pdev->dev, sizeof(*owl_port), GFP_KERNEL); 688 if (!owl_port) 689 return -ENOMEM; 690 691 owl_port->clk = devm_clk_get(&pdev->dev, NULL); 692 if (IS_ERR(owl_port->clk)) { 693 dev_err(&pdev->dev, "could not get clk\n"); 694 return PTR_ERR(owl_port->clk); 695 } 696 697 owl_port->port.dev = &pdev->dev; 698 owl_port->port.line = pdev->id; 699 owl_port->port.type = PORT_OWL; 700 owl_port->port.iotype = UPIO_MEM; 701 owl_port->port.mapbase = res_mem->start; 702 owl_port->port.irq = irq; 703 owl_port->port.uartclk = clk_get_rate(owl_port->clk); 704 if (owl_port->port.uartclk == 0) { 705 dev_err(&pdev->dev, "clock rate is zero\n"); 706 return -EINVAL; 707 } 708 owl_port->port.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_LOW_LATENCY; 709 owl_port->port.x_char = 0; 710 owl_port->port.fifosize = (info) ? info->tx_fifosize : 16; 711 owl_port->port.ops = &owl_uart_ops; 712 713 owl_uart_ports[pdev->id] = owl_port; 714 platform_set_drvdata(pdev, owl_port); 715 716 ret = uart_add_one_port(&owl_uart_driver, &owl_port->port); 717 if (ret) 718 owl_uart_ports[pdev->id] = NULL; 719 720 return ret; 721 } 722 723 static int owl_uart_remove(struct platform_device *pdev) 724 { 725 struct owl_uart_port *owl_port = platform_get_drvdata(pdev); 726 727 uart_remove_one_port(&owl_uart_driver, &owl_port->port); 728 owl_uart_ports[pdev->id] = NULL; 729 730 return 0; 731 } 732 733 static struct platform_driver owl_uart_platform_driver = { 734 .probe = owl_uart_probe, 735 .remove = owl_uart_remove, 736 .driver = { 737 .name = "owl-uart", 738 .of_match_table = owl_uart_dt_matches, 739 }, 740 }; 741 742 static int __init owl_uart_init(void) 743 { 744 int ret; 745 746 ret = uart_register_driver(&owl_uart_driver); 747 if (ret) 748 return ret; 749 750 ret = platform_driver_register(&owl_uart_platform_driver); 751 if (ret) 752 uart_unregister_driver(&owl_uart_driver); 753 754 return ret; 755 } 756 757 static void __init owl_uart_exit(void) 758 { 759 platform_driver_unregister(&owl_uart_platform_driver); 760 uart_unregister_driver(&owl_uart_driver); 761 } 762 763 module_init(owl_uart_init); 764 module_exit(owl_uart_exit); 765 766 MODULE_LICENSE("GPL"); 767