1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __ARM_MPU_H 3 #define __ARM_MPU_H 4 5 #ifdef CONFIG_ARM_MPU 6 7 /* MPUIR layout */ 8 #define MPUIR_nU 1 9 #define MPUIR_DREGION 8 10 #define MPUIR_IREGION 16 11 #define MPUIR_DREGION_SZMASK (0xFF << MPUIR_DREGION) 12 #define MPUIR_IREGION_SZMASK (0xFF << MPUIR_IREGION) 13 14 /* ID_MMFR0 data relevant to MPU */ 15 #define MMFR0_PMSA (0xF << 4) 16 #define MMFR0_PMSAv7 (3 << 4) 17 18 /* MPU D/I Size Register fields */ 19 #define MPU_RSR_SZ 1 20 #define MPU_RSR_EN 0 21 22 /* The D/I RSR value for an enabled region spanning the whole of memory */ 23 #define MPU_RSR_ALL_MEM 63 24 25 /* Individual bits in the DR/IR ACR */ 26 #define MPU_ACR_XN (1 << 12) 27 #define MPU_ACR_SHARED (1 << 2) 28 29 /* C, B and TEX[2:0] bits only have semantic meanings when grouped */ 30 #define MPU_RGN_CACHEABLE 0xB 31 #define MPU_RGN_SHARED_CACHEABLE (MPU_RGN_CACHEABLE | MPU_ACR_SHARED) 32 #define MPU_RGN_STRONGLY_ORDERED 0 33 34 /* Main region should only be shared for SMP */ 35 #ifdef CONFIG_SMP 36 #define MPU_RGN_NORMAL (MPU_RGN_CACHEABLE | MPU_ACR_SHARED) 37 #else 38 #define MPU_RGN_NORMAL MPU_RGN_CACHEABLE 39 #endif 40 41 /* Access permission bits of ACR (only define those that we use)*/ 42 #define MPU_AP_PL1RW_PL0RW (0x3 << 8) 43 #define MPU_AP_PL1RW_PL0R0 (0x2 << 8) 44 #define MPU_AP_PL1RW_PL0NA (0x1 << 8) 45 46 /* For minimal static MPU region configurations */ 47 #define MPU_PROBE_REGION 0 48 #define MPU_BG_REGION 1 49 #define MPU_RAM_REGION 2 50 #define MPU_VECTORS_REGION 3 51 52 /* Maximum number of regions Linux is interested in */ 53 #define MPU_MAX_REGIONS 16 54 55 #define MPU_DATA_SIDE 0 56 #define MPU_INSTR_SIDE 1 57 58 #ifndef __ASSEMBLY__ 59 60 struct mpu_rgn { 61 /* Assume same attributes for d/i-side */ 62 u32 drbar; 63 u32 drsr; 64 u32 dracr; 65 }; 66 67 struct mpu_rgn_info { 68 u32 mpuir; 69 struct mpu_rgn rgns[MPU_MAX_REGIONS]; 70 }; 71 extern struct mpu_rgn_info mpu_rgn_info; 72 73 #endif /* __ASSEMBLY__ */ 74 75 #endif /* CONFIG_ARM_MPU */ 76 77 #endif 78