1 /* 2 * This file contains code to reset and initialize USB host controllers. 3 * Some of it includes work-arounds for PCI hardware and BIOS quirks. 4 * It may need to run early during booting -- before USB would normally 5 * initialize -- to ensure that Linux doesn't use any legacy modes. 6 * 7 * Copyright (c) 1999 Martin Mares <mj@ucw.cz> 8 * (and others) 9 */ 10 11 #include <linux/types.h> 12 #include <linux/kernel.h> 13 #include <linux/pci.h> 14 #include <linux/delay.h> 15 #include <linux/export.h> 16 #include <linux/acpi.h> 17 #include <linux/dmi.h> 18 #include "pci-quirks.h" 19 #include "xhci-ext-caps.h" 20 21 22 #define UHCI_USBLEGSUP 0xc0 /* legacy support */ 23 #define UHCI_USBCMD 0 /* command register */ 24 #define UHCI_USBINTR 4 /* interrupt register */ 25 #define UHCI_USBLEGSUP_RWC 0x8f00 /* the R/WC bits */ 26 #define UHCI_USBLEGSUP_RO 0x5040 /* R/O and reserved bits */ 27 #define UHCI_USBCMD_RUN 0x0001 /* RUN/STOP bit */ 28 #define UHCI_USBCMD_HCRESET 0x0002 /* Host Controller reset */ 29 #define UHCI_USBCMD_EGSM 0x0008 /* Global Suspend Mode */ 30 #define UHCI_USBCMD_CONFIGURE 0x0040 /* Config Flag */ 31 #define UHCI_USBINTR_RESUME 0x0002 /* Resume interrupt enable */ 32 33 #define OHCI_CONTROL 0x04 34 #define OHCI_CMDSTATUS 0x08 35 #define OHCI_INTRSTATUS 0x0c 36 #define OHCI_INTRENABLE 0x10 37 #define OHCI_INTRDISABLE 0x14 38 #define OHCI_FMINTERVAL 0x34 39 #define OHCI_HCFS (3 << 6) /* hc functional state */ 40 #define OHCI_HCR (1 << 0) /* host controller reset */ 41 #define OHCI_OCR (1 << 3) /* ownership change request */ 42 #define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ 43 #define OHCI_CTRL_IR (1 << 8) /* interrupt routing */ 44 #define OHCI_INTR_OC (1 << 30) /* ownership change */ 45 46 #define EHCI_HCC_PARAMS 0x08 /* extended capabilities */ 47 #define EHCI_USBCMD 0 /* command register */ 48 #define EHCI_USBCMD_RUN (1 << 0) /* RUN/STOP bit */ 49 #define EHCI_USBSTS 4 /* status register */ 50 #define EHCI_USBSTS_HALTED (1 << 12) /* HCHalted bit */ 51 #define EHCI_USBINTR 8 /* interrupt register */ 52 #define EHCI_CONFIGFLAG 0x40 /* configured flag register */ 53 #define EHCI_USBLEGSUP 0 /* legacy support register */ 54 #define EHCI_USBLEGSUP_BIOS (1 << 16) /* BIOS semaphore */ 55 #define EHCI_USBLEGSUP_OS (1 << 24) /* OS semaphore */ 56 #define EHCI_USBLEGCTLSTS 4 /* legacy control/status */ 57 #define EHCI_USBLEGCTLSTS_SOOE (1 << 13) /* SMI on ownership change */ 58 59 /* AMD quirk use */ 60 #define AB_REG_BAR_LOW 0xe0 61 #define AB_REG_BAR_HIGH 0xe1 62 #define AB_REG_BAR_SB700 0xf0 63 #define AB_INDX(addr) ((addr) + 0x00) 64 #define AB_DATA(addr) ((addr) + 0x04) 65 #define AX_INDXC 0x30 66 #define AX_DATAC 0x34 67 68 #define NB_PCIE_INDX_ADDR 0xe0 69 #define NB_PCIE_INDX_DATA 0xe4 70 #define PCIE_P_CNTL 0x10040 71 #define BIF_NB 0x10002 72 #define NB_PIF0_PWRDOWN_0 0x01100012 73 #define NB_PIF0_PWRDOWN_1 0x01100013 74 75 #define USB_INTEL_XUSB2PR 0xD0 76 #define USB_INTEL_USB2PRM 0xD4 77 #define USB_INTEL_USB3_PSSEN 0xD8 78 #define USB_INTEL_USB3PRM 0xDC 79 80 /* ASMEDIA quirk use */ 81 #define ASMT_DATA_WRITE0_REG 0xF8 82 #define ASMT_DATA_WRITE1_REG 0xFC 83 #define ASMT_CONTROL_REG 0xE0 84 #define ASMT_CONTROL_WRITE_BIT 0x02 85 #define ASMT_WRITEREG_CMD 0x10423 86 #define ASMT_FLOWCTL_ADDR 0xFA30 87 #define ASMT_FLOWCTL_DATA 0xBA 88 #define ASMT_PSEUDO_DATA 0 89 90 /* 91 * amd_chipset_gen values represent AMD different chipset generations 92 */ 93 enum amd_chipset_gen { 94 NOT_AMD_CHIPSET = 0, 95 AMD_CHIPSET_SB600, 96 AMD_CHIPSET_SB700, 97 AMD_CHIPSET_SB800, 98 AMD_CHIPSET_HUDSON2, 99 AMD_CHIPSET_BOLTON, 100 AMD_CHIPSET_YANGTZE, 101 AMD_CHIPSET_TAISHAN, 102 AMD_CHIPSET_UNKNOWN, 103 }; 104 105 struct amd_chipset_type { 106 enum amd_chipset_gen gen; 107 u8 rev; 108 }; 109 110 static struct amd_chipset_info { 111 struct pci_dev *nb_dev; 112 struct pci_dev *smbus_dev; 113 int nb_type; 114 struct amd_chipset_type sb_type; 115 int isoc_reqs; 116 int probe_count; 117 int probe_result; 118 } amd_chipset; 119 120 static DEFINE_SPINLOCK(amd_lock); 121 122 /* 123 * amd_chipset_sb_type_init - initialize amd chipset southbridge type 124 * 125 * AMD FCH/SB generation and revision is identified by SMBus controller 126 * vendor, device and revision IDs. 127 * 128 * Returns: 1 if it is an AMD chipset, 0 otherwise. 129 */ 130 static int amd_chipset_sb_type_init(struct amd_chipset_info *pinfo) 131 { 132 u8 rev = 0; 133 pinfo->sb_type.gen = AMD_CHIPSET_UNKNOWN; 134 135 pinfo->smbus_dev = pci_get_device(PCI_VENDOR_ID_ATI, 136 PCI_DEVICE_ID_ATI_SBX00_SMBUS, NULL); 137 if (pinfo->smbus_dev) { 138 rev = pinfo->smbus_dev->revision; 139 if (rev >= 0x10 && rev <= 0x1f) 140 pinfo->sb_type.gen = AMD_CHIPSET_SB600; 141 else if (rev >= 0x30 && rev <= 0x3f) 142 pinfo->sb_type.gen = AMD_CHIPSET_SB700; 143 else if (rev >= 0x40 && rev <= 0x4f) 144 pinfo->sb_type.gen = AMD_CHIPSET_SB800; 145 } else { 146 pinfo->smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 147 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL); 148 149 if (pinfo->smbus_dev) { 150 rev = pinfo->smbus_dev->revision; 151 if (rev >= 0x11 && rev <= 0x14) 152 pinfo->sb_type.gen = AMD_CHIPSET_HUDSON2; 153 else if (rev >= 0x15 && rev <= 0x18) 154 pinfo->sb_type.gen = AMD_CHIPSET_BOLTON; 155 else if (rev >= 0x39 && rev <= 0x3a) 156 pinfo->sb_type.gen = AMD_CHIPSET_YANGTZE; 157 } else { 158 pinfo->smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 159 0x145c, NULL); 160 if (pinfo->smbus_dev) { 161 rev = pinfo->smbus_dev->revision; 162 pinfo->sb_type.gen = AMD_CHIPSET_TAISHAN; 163 } else { 164 pinfo->sb_type.gen = NOT_AMD_CHIPSET; 165 return 0; 166 } 167 } 168 } 169 pinfo->sb_type.rev = rev; 170 return 1; 171 } 172 173 void sb800_prefetch(struct device *dev, int on) 174 { 175 u16 misc; 176 struct pci_dev *pdev = to_pci_dev(dev); 177 178 pci_read_config_word(pdev, 0x50, &misc); 179 if (on == 0) 180 pci_write_config_word(pdev, 0x50, misc & 0xfcff); 181 else 182 pci_write_config_word(pdev, 0x50, misc | 0x0300); 183 } 184 EXPORT_SYMBOL_GPL(sb800_prefetch); 185 186 int usb_amd_find_chipset_info(void) 187 { 188 unsigned long flags; 189 struct amd_chipset_info info; 190 int ret; 191 192 spin_lock_irqsave(&amd_lock, flags); 193 194 /* probe only once */ 195 if (amd_chipset.probe_count > 0) { 196 amd_chipset.probe_count++; 197 spin_unlock_irqrestore(&amd_lock, flags); 198 return amd_chipset.probe_result; 199 } 200 memset(&info, 0, sizeof(info)); 201 spin_unlock_irqrestore(&amd_lock, flags); 202 203 if (!amd_chipset_sb_type_init(&info)) { 204 ret = 0; 205 goto commit; 206 } 207 208 /* Below chipset generations needn't enable AMD PLL quirk */ 209 if (info.sb_type.gen == AMD_CHIPSET_UNKNOWN || 210 info.sb_type.gen == AMD_CHIPSET_SB600 || 211 info.sb_type.gen == AMD_CHIPSET_YANGTZE || 212 (info.sb_type.gen == AMD_CHIPSET_SB700 && 213 info.sb_type.rev > 0x3b)) { 214 if (info.smbus_dev) { 215 pci_dev_put(info.smbus_dev); 216 info.smbus_dev = NULL; 217 } 218 ret = 0; 219 goto commit; 220 } 221 222 info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x9601, NULL); 223 if (info.nb_dev) { 224 info.nb_type = 1; 225 } else { 226 info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x1510, NULL); 227 if (info.nb_dev) { 228 info.nb_type = 2; 229 } else { 230 info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 231 0x9600, NULL); 232 if (info.nb_dev) 233 info.nb_type = 3; 234 } 235 } 236 237 ret = info.probe_result = 1; 238 printk(KERN_DEBUG "QUIRK: Enable AMD PLL fix\n"); 239 240 commit: 241 242 spin_lock_irqsave(&amd_lock, flags); 243 if (amd_chipset.probe_count > 0) { 244 /* race - someone else was faster - drop devices */ 245 246 /* Mark that we where here */ 247 amd_chipset.probe_count++; 248 ret = amd_chipset.probe_result; 249 250 spin_unlock_irqrestore(&amd_lock, flags); 251 252 pci_dev_put(info.nb_dev); 253 pci_dev_put(info.smbus_dev); 254 255 } else { 256 /* no race - commit the result */ 257 info.probe_count++; 258 amd_chipset = info; 259 spin_unlock_irqrestore(&amd_lock, flags); 260 } 261 262 return ret; 263 } 264 EXPORT_SYMBOL_GPL(usb_amd_find_chipset_info); 265 266 int usb_hcd_amd_remote_wakeup_quirk(struct pci_dev *pdev) 267 { 268 /* Make sure amd chipset type has already been initialized */ 269 usb_amd_find_chipset_info(); 270 if (amd_chipset.sb_type.gen == AMD_CHIPSET_YANGTZE || 271 amd_chipset.sb_type.gen == AMD_CHIPSET_TAISHAN) { 272 dev_dbg(&pdev->dev, "QUIRK: Enable AMD remote wakeup fix\n"); 273 return 1; 274 } 275 return 0; 276 } 277 EXPORT_SYMBOL_GPL(usb_hcd_amd_remote_wakeup_quirk); 278 279 bool usb_amd_hang_symptom_quirk(void) 280 { 281 u8 rev; 282 283 usb_amd_find_chipset_info(); 284 rev = amd_chipset.sb_type.rev; 285 /* SB600 and old version of SB700 have hang symptom bug */ 286 return amd_chipset.sb_type.gen == AMD_CHIPSET_SB600 || 287 (amd_chipset.sb_type.gen == AMD_CHIPSET_SB700 && 288 rev >= 0x3a && rev <= 0x3b); 289 } 290 EXPORT_SYMBOL_GPL(usb_amd_hang_symptom_quirk); 291 292 bool usb_amd_prefetch_quirk(void) 293 { 294 usb_amd_find_chipset_info(); 295 /* SB800 needs pre-fetch fix */ 296 return amd_chipset.sb_type.gen == AMD_CHIPSET_SB800; 297 } 298 EXPORT_SYMBOL_GPL(usb_amd_prefetch_quirk); 299 300 /* 301 * The hardware normally enables the A-link power management feature, which 302 * lets the system lower the power consumption in idle states. 303 * 304 * This USB quirk prevents the link going into that lower power state 305 * during isochronous transfers. 306 * 307 * Without this quirk, isochronous stream on OHCI/EHCI/xHCI controllers of 308 * some AMD platforms may stutter or have breaks occasionally. 309 */ 310 static void usb_amd_quirk_pll(int disable) 311 { 312 u32 addr, addr_low, addr_high, val; 313 u32 bit = disable ? 0 : 1; 314 unsigned long flags; 315 316 spin_lock_irqsave(&amd_lock, flags); 317 318 if (disable) { 319 amd_chipset.isoc_reqs++; 320 if (amd_chipset.isoc_reqs > 1) { 321 spin_unlock_irqrestore(&amd_lock, flags); 322 return; 323 } 324 } else { 325 amd_chipset.isoc_reqs--; 326 if (amd_chipset.isoc_reqs > 0) { 327 spin_unlock_irqrestore(&amd_lock, flags); 328 return; 329 } 330 } 331 332 if (amd_chipset.sb_type.gen == AMD_CHIPSET_SB800 || 333 amd_chipset.sb_type.gen == AMD_CHIPSET_HUDSON2 || 334 amd_chipset.sb_type.gen == AMD_CHIPSET_BOLTON) { 335 outb_p(AB_REG_BAR_LOW, 0xcd6); 336 addr_low = inb_p(0xcd7); 337 outb_p(AB_REG_BAR_HIGH, 0xcd6); 338 addr_high = inb_p(0xcd7); 339 addr = addr_high << 8 | addr_low; 340 341 outl_p(0x30, AB_INDX(addr)); 342 outl_p(0x40, AB_DATA(addr)); 343 outl_p(0x34, AB_INDX(addr)); 344 val = inl_p(AB_DATA(addr)); 345 } else if (amd_chipset.sb_type.gen == AMD_CHIPSET_SB700 && 346 amd_chipset.sb_type.rev <= 0x3b) { 347 pci_read_config_dword(amd_chipset.smbus_dev, 348 AB_REG_BAR_SB700, &addr); 349 outl(AX_INDXC, AB_INDX(addr)); 350 outl(0x40, AB_DATA(addr)); 351 outl(AX_DATAC, AB_INDX(addr)); 352 val = inl(AB_DATA(addr)); 353 } else { 354 spin_unlock_irqrestore(&amd_lock, flags); 355 return; 356 } 357 358 if (disable) { 359 val &= ~0x08; 360 val |= (1 << 4) | (1 << 9); 361 } else { 362 val |= 0x08; 363 val &= ~((1 << 4) | (1 << 9)); 364 } 365 outl_p(val, AB_DATA(addr)); 366 367 if (!amd_chipset.nb_dev) { 368 spin_unlock_irqrestore(&amd_lock, flags); 369 return; 370 } 371 372 if (amd_chipset.nb_type == 1 || amd_chipset.nb_type == 3) { 373 addr = PCIE_P_CNTL; 374 pci_write_config_dword(amd_chipset.nb_dev, 375 NB_PCIE_INDX_ADDR, addr); 376 pci_read_config_dword(amd_chipset.nb_dev, 377 NB_PCIE_INDX_DATA, &val); 378 379 val &= ~(1 | (1 << 3) | (1 << 4) | (1 << 9) | (1 << 12)); 380 val |= bit | (bit << 3) | (bit << 12); 381 val |= ((!bit) << 4) | ((!bit) << 9); 382 pci_write_config_dword(amd_chipset.nb_dev, 383 NB_PCIE_INDX_DATA, val); 384 385 addr = BIF_NB; 386 pci_write_config_dword(amd_chipset.nb_dev, 387 NB_PCIE_INDX_ADDR, addr); 388 pci_read_config_dword(amd_chipset.nb_dev, 389 NB_PCIE_INDX_DATA, &val); 390 val &= ~(1 << 8); 391 val |= bit << 8; 392 393 pci_write_config_dword(amd_chipset.nb_dev, 394 NB_PCIE_INDX_DATA, val); 395 } else if (amd_chipset.nb_type == 2) { 396 addr = NB_PIF0_PWRDOWN_0; 397 pci_write_config_dword(amd_chipset.nb_dev, 398 NB_PCIE_INDX_ADDR, addr); 399 pci_read_config_dword(amd_chipset.nb_dev, 400 NB_PCIE_INDX_DATA, &val); 401 if (disable) 402 val &= ~(0x3f << 7); 403 else 404 val |= 0x3f << 7; 405 406 pci_write_config_dword(amd_chipset.nb_dev, 407 NB_PCIE_INDX_DATA, val); 408 409 addr = NB_PIF0_PWRDOWN_1; 410 pci_write_config_dword(amd_chipset.nb_dev, 411 NB_PCIE_INDX_ADDR, addr); 412 pci_read_config_dword(amd_chipset.nb_dev, 413 NB_PCIE_INDX_DATA, &val); 414 if (disable) 415 val &= ~(0x3f << 7); 416 else 417 val |= 0x3f << 7; 418 419 pci_write_config_dword(amd_chipset.nb_dev, 420 NB_PCIE_INDX_DATA, val); 421 } 422 423 spin_unlock_irqrestore(&amd_lock, flags); 424 return; 425 } 426 427 void usb_amd_quirk_pll_disable(void) 428 { 429 usb_amd_quirk_pll(1); 430 } 431 EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_disable); 432 433 static int usb_asmedia_wait_write(struct pci_dev *pdev) 434 { 435 unsigned long retry_count; 436 unsigned char value; 437 438 for (retry_count = 1000; retry_count > 0; --retry_count) { 439 440 pci_read_config_byte(pdev, ASMT_CONTROL_REG, &value); 441 442 if (value == 0xff) { 443 dev_err(&pdev->dev, "%s: check_ready ERROR", __func__); 444 return -EIO; 445 } 446 447 if ((value & ASMT_CONTROL_WRITE_BIT) == 0) 448 return 0; 449 450 udelay(50); 451 } 452 453 dev_warn(&pdev->dev, "%s: check_write_ready timeout", __func__); 454 return -ETIMEDOUT; 455 } 456 457 void usb_asmedia_modifyflowcontrol(struct pci_dev *pdev) 458 { 459 if (usb_asmedia_wait_write(pdev) != 0) 460 return; 461 462 /* send command and address to device */ 463 pci_write_config_dword(pdev, ASMT_DATA_WRITE0_REG, ASMT_WRITEREG_CMD); 464 pci_write_config_dword(pdev, ASMT_DATA_WRITE1_REG, ASMT_FLOWCTL_ADDR); 465 pci_write_config_byte(pdev, ASMT_CONTROL_REG, ASMT_CONTROL_WRITE_BIT); 466 467 if (usb_asmedia_wait_write(pdev) != 0) 468 return; 469 470 /* send data to device */ 471 pci_write_config_dword(pdev, ASMT_DATA_WRITE0_REG, ASMT_FLOWCTL_DATA); 472 pci_write_config_dword(pdev, ASMT_DATA_WRITE1_REG, ASMT_PSEUDO_DATA); 473 pci_write_config_byte(pdev, ASMT_CONTROL_REG, ASMT_CONTROL_WRITE_BIT); 474 } 475 EXPORT_SYMBOL_GPL(usb_asmedia_modifyflowcontrol); 476 477 void usb_amd_quirk_pll_enable(void) 478 { 479 usb_amd_quirk_pll(0); 480 } 481 EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_enable); 482 483 void usb_amd_dev_put(void) 484 { 485 struct pci_dev *nb, *smbus; 486 unsigned long flags; 487 488 spin_lock_irqsave(&amd_lock, flags); 489 490 amd_chipset.probe_count--; 491 if (amd_chipset.probe_count > 0) { 492 spin_unlock_irqrestore(&amd_lock, flags); 493 return; 494 } 495 496 /* save them to pci_dev_put outside of spinlock */ 497 nb = amd_chipset.nb_dev; 498 smbus = amd_chipset.smbus_dev; 499 500 amd_chipset.nb_dev = NULL; 501 amd_chipset.smbus_dev = NULL; 502 amd_chipset.nb_type = 0; 503 memset(&amd_chipset.sb_type, 0, sizeof(amd_chipset.sb_type)); 504 amd_chipset.isoc_reqs = 0; 505 amd_chipset.probe_result = 0; 506 507 spin_unlock_irqrestore(&amd_lock, flags); 508 509 pci_dev_put(nb); 510 pci_dev_put(smbus); 511 } 512 EXPORT_SYMBOL_GPL(usb_amd_dev_put); 513 514 /* 515 * Make sure the controller is completely inactive, unable to 516 * generate interrupts or do DMA. 517 */ 518 void uhci_reset_hc(struct pci_dev *pdev, unsigned long base) 519 { 520 /* Turn off PIRQ enable and SMI enable. (This also turns off the 521 * BIOS's USB Legacy Support.) Turn off all the R/WC bits too. 522 */ 523 pci_write_config_word(pdev, UHCI_USBLEGSUP, UHCI_USBLEGSUP_RWC); 524 525 /* Reset the HC - this will force us to get a 526 * new notification of any already connected 527 * ports due to the virtual disconnect that it 528 * implies. 529 */ 530 outw(UHCI_USBCMD_HCRESET, base + UHCI_USBCMD); 531 mb(); 532 udelay(5); 533 if (inw(base + UHCI_USBCMD) & UHCI_USBCMD_HCRESET) 534 dev_warn(&pdev->dev, "HCRESET not completed yet!\n"); 535 536 /* Just to be safe, disable interrupt requests and 537 * make sure the controller is stopped. 538 */ 539 outw(0, base + UHCI_USBINTR); 540 outw(0, base + UHCI_USBCMD); 541 } 542 EXPORT_SYMBOL_GPL(uhci_reset_hc); 543 544 /* 545 * Initialize a controller that was newly discovered or has just been 546 * resumed. In either case we can't be sure of its previous state. 547 * 548 * Returns: 1 if the controller was reset, 0 otherwise. 549 */ 550 int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base) 551 { 552 u16 legsup; 553 unsigned int cmd, intr; 554 555 /* 556 * When restarting a suspended controller, we expect all the 557 * settings to be the same as we left them: 558 * 559 * PIRQ and SMI disabled, no R/W bits set in USBLEGSUP; 560 * Controller is stopped and configured with EGSM set; 561 * No interrupts enabled except possibly Resume Detect. 562 * 563 * If any of these conditions are violated we do a complete reset. 564 */ 565 pci_read_config_word(pdev, UHCI_USBLEGSUP, &legsup); 566 if (legsup & ~(UHCI_USBLEGSUP_RO | UHCI_USBLEGSUP_RWC)) { 567 dev_dbg(&pdev->dev, "%s: legsup = 0x%04x\n", 568 __func__, legsup); 569 goto reset_needed; 570 } 571 572 cmd = inw(base + UHCI_USBCMD); 573 if ((cmd & UHCI_USBCMD_RUN) || !(cmd & UHCI_USBCMD_CONFIGURE) || 574 !(cmd & UHCI_USBCMD_EGSM)) { 575 dev_dbg(&pdev->dev, "%s: cmd = 0x%04x\n", 576 __func__, cmd); 577 goto reset_needed; 578 } 579 580 intr = inw(base + UHCI_USBINTR); 581 if (intr & (~UHCI_USBINTR_RESUME)) { 582 dev_dbg(&pdev->dev, "%s: intr = 0x%04x\n", 583 __func__, intr); 584 goto reset_needed; 585 } 586 return 0; 587 588 reset_needed: 589 dev_dbg(&pdev->dev, "Performing full reset\n"); 590 uhci_reset_hc(pdev, base); 591 return 1; 592 } 593 EXPORT_SYMBOL_GPL(uhci_check_and_reset_hc); 594 595 static inline int io_type_enabled(struct pci_dev *pdev, unsigned int mask) 596 { 597 u16 cmd; 598 return !pci_read_config_word(pdev, PCI_COMMAND, &cmd) && (cmd & mask); 599 } 600 601 #define pio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_IO) 602 #define mmio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_MEMORY) 603 604 static void quirk_usb_handoff_uhci(struct pci_dev *pdev) 605 { 606 unsigned long base = 0; 607 int i; 608 609 if (!pio_enabled(pdev)) 610 return; 611 612 for (i = 0; i < PCI_ROM_RESOURCE; i++) 613 if ((pci_resource_flags(pdev, i) & IORESOURCE_IO)) { 614 base = pci_resource_start(pdev, i); 615 break; 616 } 617 618 if (base) 619 uhci_check_and_reset_hc(pdev, base); 620 } 621 622 static int mmio_resource_enabled(struct pci_dev *pdev, int idx) 623 { 624 return pci_resource_start(pdev, idx) && mmio_enabled(pdev); 625 } 626 627 static void quirk_usb_handoff_ohci(struct pci_dev *pdev) 628 { 629 void __iomem *base; 630 u32 control; 631 u32 fminterval = 0; 632 bool no_fminterval = false; 633 int cnt; 634 635 if (!mmio_resource_enabled(pdev, 0)) 636 return; 637 638 base = pci_ioremap_bar(pdev, 0); 639 if (base == NULL) 640 return; 641 642 /* 643 * ULi M5237 OHCI controller locks the whole system when accessing 644 * the OHCI_FMINTERVAL offset. 645 */ 646 if (pdev->vendor == PCI_VENDOR_ID_AL && pdev->device == 0x5237) 647 no_fminterval = true; 648 649 control = readl(base + OHCI_CONTROL); 650 651 /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */ 652 #ifdef __hppa__ 653 #define OHCI_CTRL_MASK (OHCI_CTRL_RWC | OHCI_CTRL_IR) 654 #else 655 #define OHCI_CTRL_MASK OHCI_CTRL_RWC 656 657 if (control & OHCI_CTRL_IR) { 658 int wait_time = 500; /* arbitrary; 5 seconds */ 659 writel(OHCI_INTR_OC, base + OHCI_INTRENABLE); 660 writel(OHCI_OCR, base + OHCI_CMDSTATUS); 661 while (wait_time > 0 && 662 readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) { 663 wait_time -= 10; 664 msleep(10); 665 } 666 if (wait_time <= 0) 667 dev_warn(&pdev->dev, 668 "OHCI: BIOS handoff failed (BIOS bug?) %08x\n", 669 readl(base + OHCI_CONTROL)); 670 } 671 #endif 672 673 /* disable interrupts */ 674 writel((u32) ~0, base + OHCI_INTRDISABLE); 675 676 /* Reset the USB bus, if the controller isn't already in RESET */ 677 if (control & OHCI_HCFS) { 678 /* Go into RESET, preserving RWC (and possibly IR) */ 679 writel(control & OHCI_CTRL_MASK, base + OHCI_CONTROL); 680 readl(base + OHCI_CONTROL); 681 682 /* drive bus reset for at least 50 ms (7.1.7.5) */ 683 msleep(50); 684 } 685 686 /* software reset of the controller, preserving HcFmInterval */ 687 if (!no_fminterval) 688 fminterval = readl(base + OHCI_FMINTERVAL); 689 690 writel(OHCI_HCR, base + OHCI_CMDSTATUS); 691 692 /* reset requires max 10 us delay */ 693 for (cnt = 30; cnt > 0; --cnt) { /* ... allow extra time */ 694 if ((readl(base + OHCI_CMDSTATUS) & OHCI_HCR) == 0) 695 break; 696 udelay(1); 697 } 698 699 if (!no_fminterval) 700 writel(fminterval, base + OHCI_FMINTERVAL); 701 702 /* Now the controller is safely in SUSPEND and nothing can wake it up */ 703 iounmap(base); 704 } 705 706 static const struct dmi_system_id ehci_dmi_nohandoff_table[] = { 707 { 708 /* Pegatron Lucid (ExoPC) */ 709 .matches = { 710 DMI_MATCH(DMI_BOARD_NAME, "EXOPG06411"), 711 DMI_MATCH(DMI_BIOS_VERSION, "Lucid-CE-133"), 712 }, 713 }, 714 { 715 /* Pegatron Lucid (Ordissimo AIRIS) */ 716 .matches = { 717 DMI_MATCH(DMI_BOARD_NAME, "M11JB"), 718 DMI_MATCH(DMI_BIOS_VERSION, "Lucid-"), 719 }, 720 }, 721 { 722 /* Pegatron Lucid (Ordissimo) */ 723 .matches = { 724 DMI_MATCH(DMI_BOARD_NAME, "Ordissimo"), 725 DMI_MATCH(DMI_BIOS_VERSION, "Lucid-"), 726 }, 727 }, 728 { 729 /* HASEE E200 */ 730 .matches = { 731 DMI_MATCH(DMI_BOARD_VENDOR, "HASEE"), 732 DMI_MATCH(DMI_BOARD_NAME, "E210"), 733 DMI_MATCH(DMI_BIOS_VERSION, "6.00"), 734 }, 735 }, 736 { } 737 }; 738 739 static void ehci_bios_handoff(struct pci_dev *pdev, 740 void __iomem *op_reg_base, 741 u32 cap, u8 offset) 742 { 743 int try_handoff = 1, tried_handoff = 0; 744 745 /* 746 * The Pegatron Lucid tablet sporadically waits for 98 seconds trying 747 * the handoff on its unused controller. Skip it. 748 * 749 * The HASEE E200 hangs when the semaphore is set (bugzilla #77021). 750 */ 751 if (pdev->vendor == 0x8086 && (pdev->device == 0x283a || 752 pdev->device == 0x27cc)) { 753 if (dmi_check_system(ehci_dmi_nohandoff_table)) 754 try_handoff = 0; 755 } 756 757 if (try_handoff && (cap & EHCI_USBLEGSUP_BIOS)) { 758 dev_dbg(&pdev->dev, "EHCI: BIOS handoff\n"); 759 760 #if 0 761 /* aleksey_gorelov@phoenix.com reports that some systems need SMI forced on, 762 * but that seems dubious in general (the BIOS left it off intentionally) 763 * and is known to prevent some systems from booting. so we won't do this 764 * unless maybe we can determine when we're on a system that needs SMI forced. 765 */ 766 /* BIOS workaround (?): be sure the pre-Linux code 767 * receives the SMI 768 */ 769 pci_read_config_dword(pdev, offset + EHCI_USBLEGCTLSTS, &val); 770 pci_write_config_dword(pdev, offset + EHCI_USBLEGCTLSTS, 771 val | EHCI_USBLEGCTLSTS_SOOE); 772 #endif 773 774 /* some systems get upset if this semaphore is 775 * set for any other reason than forcing a BIOS 776 * handoff.. 777 */ 778 pci_write_config_byte(pdev, offset + 3, 1); 779 } 780 781 /* if boot firmware now owns EHCI, spin till it hands it over. */ 782 if (try_handoff) { 783 int msec = 1000; 784 while ((cap & EHCI_USBLEGSUP_BIOS) && (msec > 0)) { 785 tried_handoff = 1; 786 msleep(10); 787 msec -= 10; 788 pci_read_config_dword(pdev, offset, &cap); 789 } 790 } 791 792 if (cap & EHCI_USBLEGSUP_BIOS) { 793 /* well, possibly buggy BIOS... try to shut it down, 794 * and hope nothing goes too wrong 795 */ 796 if (try_handoff) 797 dev_warn(&pdev->dev, 798 "EHCI: BIOS handoff failed (BIOS bug?) %08x\n", 799 cap); 800 pci_write_config_byte(pdev, offset + 2, 0); 801 } 802 803 /* just in case, always disable EHCI SMIs */ 804 pci_write_config_dword(pdev, offset + EHCI_USBLEGCTLSTS, 0); 805 806 /* If the BIOS ever owned the controller then we can't expect 807 * any power sessions to remain intact. 808 */ 809 if (tried_handoff) 810 writel(0, op_reg_base + EHCI_CONFIGFLAG); 811 } 812 813 static void quirk_usb_disable_ehci(struct pci_dev *pdev) 814 { 815 void __iomem *base, *op_reg_base; 816 u32 hcc_params, cap, val; 817 u8 offset, cap_length; 818 int wait_time, count = 256/4; 819 820 if (!mmio_resource_enabled(pdev, 0)) 821 return; 822 823 base = pci_ioremap_bar(pdev, 0); 824 if (base == NULL) 825 return; 826 827 cap_length = readb(base); 828 op_reg_base = base + cap_length; 829 830 /* EHCI 0.96 and later may have "extended capabilities" 831 * spec section 5.1 explains the bios handoff, e.g. for 832 * booting from USB disk or using a usb keyboard 833 */ 834 hcc_params = readl(base + EHCI_HCC_PARAMS); 835 offset = (hcc_params >> 8) & 0xff; 836 while (offset && --count) { 837 pci_read_config_dword(pdev, offset, &cap); 838 839 switch (cap & 0xff) { 840 case 1: 841 ehci_bios_handoff(pdev, op_reg_base, cap, offset); 842 break; 843 case 0: /* Illegal reserved cap, set cap=0 so we exit */ 844 cap = 0; /* then fallthrough... */ 845 default: 846 dev_warn(&pdev->dev, 847 "EHCI: unrecognized capability %02x\n", 848 cap & 0xff); 849 } 850 offset = (cap >> 8) & 0xff; 851 } 852 if (!count) 853 dev_printk(KERN_DEBUG, &pdev->dev, "EHCI: capability loop?\n"); 854 855 /* 856 * halt EHCI & disable its interrupts in any case 857 */ 858 val = readl(op_reg_base + EHCI_USBSTS); 859 if ((val & EHCI_USBSTS_HALTED) == 0) { 860 val = readl(op_reg_base + EHCI_USBCMD); 861 val &= ~EHCI_USBCMD_RUN; 862 writel(val, op_reg_base + EHCI_USBCMD); 863 864 wait_time = 2000; 865 do { 866 writel(0x3f, op_reg_base + EHCI_USBSTS); 867 udelay(100); 868 wait_time -= 100; 869 val = readl(op_reg_base + EHCI_USBSTS); 870 if ((val == ~(u32)0) || (val & EHCI_USBSTS_HALTED)) { 871 break; 872 } 873 } while (wait_time > 0); 874 } 875 writel(0, op_reg_base + EHCI_USBINTR); 876 writel(0x3f, op_reg_base + EHCI_USBSTS); 877 878 iounmap(base); 879 } 880 881 /* 882 * handshake - spin reading a register until handshake completes 883 * @ptr: address of hc register to be read 884 * @mask: bits to look at in result of read 885 * @done: value of those bits when handshake succeeds 886 * @wait_usec: timeout in microseconds 887 * @delay_usec: delay in microseconds to wait between polling 888 * 889 * Polls a register every delay_usec microseconds. 890 * Returns 0 when the mask bits have the value done. 891 * Returns -ETIMEDOUT if this condition is not true after 892 * wait_usec microseconds have passed. 893 */ 894 static int handshake(void __iomem *ptr, u32 mask, u32 done, 895 int wait_usec, int delay_usec) 896 { 897 u32 result; 898 899 do { 900 result = readl(ptr); 901 result &= mask; 902 if (result == done) 903 return 0; 904 udelay(delay_usec); 905 wait_usec -= delay_usec; 906 } while (wait_usec > 0); 907 return -ETIMEDOUT; 908 } 909 910 /* 911 * Intel's Panther Point chipset has two host controllers (EHCI and xHCI) that 912 * share some number of ports. These ports can be switched between either 913 * controller. Not all of the ports under the EHCI host controller may be 914 * switchable. 915 * 916 * The ports should be switched over to xHCI before PCI probes for any device 917 * start. This avoids active devices under EHCI being disconnected during the 918 * port switchover, which could cause loss of data on USB storage devices, or 919 * failed boot when the root file system is on a USB mass storage device and is 920 * enumerated under EHCI first. 921 * 922 * We write into the xHC's PCI configuration space in some Intel-specific 923 * registers to switch the ports over. The USB 3.0 terminations and the USB 924 * 2.0 data wires are switched separately. We want to enable the SuperSpeed 925 * terminations before switching the USB 2.0 wires over, so that USB 3.0 926 * devices connect at SuperSpeed, rather than at USB 2.0 speeds. 927 */ 928 void usb_enable_intel_xhci_ports(struct pci_dev *xhci_pdev) 929 { 930 u32 ports_available; 931 bool ehci_found = false; 932 struct pci_dev *companion = NULL; 933 934 /* Sony VAIO t-series with subsystem device ID 90a8 is not capable of 935 * switching ports from EHCI to xHCI 936 */ 937 if (xhci_pdev->subsystem_vendor == PCI_VENDOR_ID_SONY && 938 xhci_pdev->subsystem_device == 0x90a8) 939 return; 940 941 /* make sure an intel EHCI controller exists */ 942 for_each_pci_dev(companion) { 943 if (companion->class == PCI_CLASS_SERIAL_USB_EHCI && 944 companion->vendor == PCI_VENDOR_ID_INTEL) { 945 ehci_found = true; 946 break; 947 } 948 } 949 950 if (!ehci_found) 951 return; 952 953 /* Don't switchover the ports if the user hasn't compiled the xHCI 954 * driver. Otherwise they will see "dead" USB ports that don't power 955 * the devices. 956 */ 957 if (!IS_ENABLED(CONFIG_USB_XHCI_HCD)) { 958 dev_warn(&xhci_pdev->dev, 959 "CONFIG_USB_XHCI_HCD is turned off, defaulting to EHCI.\n"); 960 dev_warn(&xhci_pdev->dev, 961 "USB 3.0 devices will work at USB 2.0 speeds.\n"); 962 usb_disable_xhci_ports(xhci_pdev); 963 return; 964 } 965 966 /* Read USB3PRM, the USB 3.0 Port Routing Mask Register 967 * Indicate the ports that can be changed from OS. 968 */ 969 pci_read_config_dword(xhci_pdev, USB_INTEL_USB3PRM, 970 &ports_available); 971 972 dev_dbg(&xhci_pdev->dev, "Configurable ports to enable SuperSpeed: 0x%x\n", 973 ports_available); 974 975 /* Write USB3_PSSEN, the USB 3.0 Port SuperSpeed Enable 976 * Register, to turn on SuperSpeed terminations for the 977 * switchable ports. 978 */ 979 pci_write_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN, 980 ports_available); 981 982 pci_read_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN, 983 &ports_available); 984 dev_dbg(&xhci_pdev->dev, 985 "USB 3.0 ports that are now enabled under xHCI: 0x%x\n", 986 ports_available); 987 988 /* Read XUSB2PRM, xHCI USB 2.0 Port Routing Mask Register 989 * Indicate the USB 2.0 ports to be controlled by the xHCI host. 990 */ 991 992 pci_read_config_dword(xhci_pdev, USB_INTEL_USB2PRM, 993 &ports_available); 994 995 dev_dbg(&xhci_pdev->dev, "Configurable USB 2.0 ports to hand over to xCHI: 0x%x\n", 996 ports_available); 997 998 /* Write XUSB2PR, the xHC USB 2.0 Port Routing Register, to 999 * switch the USB 2.0 power and data lines over to the xHCI 1000 * host. 1001 */ 1002 pci_write_config_dword(xhci_pdev, USB_INTEL_XUSB2PR, 1003 ports_available); 1004 1005 pci_read_config_dword(xhci_pdev, USB_INTEL_XUSB2PR, 1006 &ports_available); 1007 dev_dbg(&xhci_pdev->dev, 1008 "USB 2.0 ports that are now switched over to xHCI: 0x%x\n", 1009 ports_available); 1010 } 1011 EXPORT_SYMBOL_GPL(usb_enable_intel_xhci_ports); 1012 1013 void usb_disable_xhci_ports(struct pci_dev *xhci_pdev) 1014 { 1015 pci_write_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN, 0x0); 1016 pci_write_config_dword(xhci_pdev, USB_INTEL_XUSB2PR, 0x0); 1017 } 1018 EXPORT_SYMBOL_GPL(usb_disable_xhci_ports); 1019 1020 /** 1021 * PCI Quirks for xHCI. 1022 * 1023 * Takes care of the handoff between the Pre-OS (i.e. BIOS) and the OS. 1024 * It signals to the BIOS that the OS wants control of the host controller, 1025 * and then waits 1 second for the BIOS to hand over control. 1026 * If we timeout, assume the BIOS is broken and take control anyway. 1027 */ 1028 static void quirk_usb_handoff_xhci(struct pci_dev *pdev) 1029 { 1030 void __iomem *base; 1031 int ext_cap_offset; 1032 void __iomem *op_reg_base; 1033 u32 val; 1034 int timeout; 1035 int len = pci_resource_len(pdev, 0); 1036 1037 if (!mmio_resource_enabled(pdev, 0)) 1038 return; 1039 1040 base = ioremap_nocache(pci_resource_start(pdev, 0), len); 1041 if (base == NULL) 1042 return; 1043 1044 /* 1045 * Find the Legacy Support Capability register - 1046 * this is optional for xHCI host controllers. 1047 */ 1048 ext_cap_offset = xhci_find_next_ext_cap(base, 0, XHCI_EXT_CAPS_LEGACY); 1049 1050 if (!ext_cap_offset) 1051 goto hc_init; 1052 1053 if ((ext_cap_offset + sizeof(val)) > len) { 1054 /* We're reading garbage from the controller */ 1055 dev_warn(&pdev->dev, "xHCI controller failing to respond"); 1056 goto iounmap; 1057 } 1058 val = readl(base + ext_cap_offset); 1059 1060 /* Auto handoff never worked for these devices. Force it and continue */ 1061 if ((pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241) || 1062 (pdev->vendor == PCI_VENDOR_ID_RENESAS 1063 && pdev->device == 0x0014)) { 1064 val = (val | XHCI_HC_OS_OWNED) & ~XHCI_HC_BIOS_OWNED; 1065 writel(val, base + ext_cap_offset); 1066 } 1067 1068 /* If the BIOS owns the HC, signal that the OS wants it, and wait */ 1069 if (val & XHCI_HC_BIOS_OWNED) { 1070 writel(val | XHCI_HC_OS_OWNED, base + ext_cap_offset); 1071 1072 /* Wait for 1 second with 10 microsecond polling interval */ 1073 timeout = handshake(base + ext_cap_offset, XHCI_HC_BIOS_OWNED, 1074 0, 1000000, 10); 1075 1076 /* Assume a buggy BIOS and take HC ownership anyway */ 1077 if (timeout) { 1078 dev_warn(&pdev->dev, 1079 "xHCI BIOS handoff failed (BIOS bug ?) %08x\n", 1080 val); 1081 writel(val & ~XHCI_HC_BIOS_OWNED, base + ext_cap_offset); 1082 } 1083 } 1084 1085 val = readl(base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET); 1086 /* Mask off (turn off) any enabled SMIs */ 1087 val &= XHCI_LEGACY_DISABLE_SMI; 1088 /* Mask all SMI events bits, RW1C */ 1089 val |= XHCI_LEGACY_SMI_EVENTS; 1090 /* Disable any BIOS SMIs and clear all SMI events*/ 1091 writel(val, base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET); 1092 1093 hc_init: 1094 if (pdev->vendor == PCI_VENDOR_ID_INTEL) 1095 usb_enable_intel_xhci_ports(pdev); 1096 1097 op_reg_base = base + XHCI_HC_LENGTH(readl(base)); 1098 1099 /* Wait for the host controller to be ready before writing any 1100 * operational or runtime registers. Wait 5 seconds and no more. 1101 */ 1102 timeout = handshake(op_reg_base + XHCI_STS_OFFSET, XHCI_STS_CNR, 0, 1103 5000000, 10); 1104 /* Assume a buggy HC and start HC initialization anyway */ 1105 if (timeout) { 1106 val = readl(op_reg_base + XHCI_STS_OFFSET); 1107 dev_warn(&pdev->dev, 1108 "xHCI HW not ready after 5 sec (HC bug?) status = 0x%x\n", 1109 val); 1110 } 1111 1112 /* Send the halt and disable interrupts command */ 1113 val = readl(op_reg_base + XHCI_CMD_OFFSET); 1114 val &= ~(XHCI_CMD_RUN | XHCI_IRQS); 1115 writel(val, op_reg_base + XHCI_CMD_OFFSET); 1116 1117 /* Wait for the HC to halt - poll every 125 usec (one microframe). */ 1118 timeout = handshake(op_reg_base + XHCI_STS_OFFSET, XHCI_STS_HALT, 1, 1119 XHCI_MAX_HALT_USEC, 125); 1120 if (timeout) { 1121 val = readl(op_reg_base + XHCI_STS_OFFSET); 1122 dev_warn(&pdev->dev, 1123 "xHCI HW did not halt within %d usec status = 0x%x\n", 1124 XHCI_MAX_HALT_USEC, val); 1125 } 1126 1127 iounmap: 1128 iounmap(base); 1129 } 1130 1131 static void quirk_usb_early_handoff(struct pci_dev *pdev) 1132 { 1133 /* Skip Netlogic mips SoC's internal PCI USB controller. 1134 * This device does not need/support EHCI/OHCI handoff 1135 */ 1136 if (pdev->vendor == 0x184e) /* vendor Netlogic */ 1137 return; 1138 if (pdev->class != PCI_CLASS_SERIAL_USB_UHCI && 1139 pdev->class != PCI_CLASS_SERIAL_USB_OHCI && 1140 pdev->class != PCI_CLASS_SERIAL_USB_EHCI && 1141 pdev->class != PCI_CLASS_SERIAL_USB_XHCI) 1142 return; 1143 1144 if (pci_enable_device(pdev) < 0) { 1145 dev_warn(&pdev->dev, 1146 "Can't enable PCI device, BIOS handoff failed.\n"); 1147 return; 1148 } 1149 if (pdev->class == PCI_CLASS_SERIAL_USB_UHCI) 1150 quirk_usb_handoff_uhci(pdev); 1151 else if (pdev->class == PCI_CLASS_SERIAL_USB_OHCI) 1152 quirk_usb_handoff_ohci(pdev); 1153 else if (pdev->class == PCI_CLASS_SERIAL_USB_EHCI) 1154 quirk_usb_disable_ehci(pdev); 1155 else if (pdev->class == PCI_CLASS_SERIAL_USB_XHCI) 1156 quirk_usb_handoff_xhci(pdev); 1157 pci_disable_device(pdev); 1158 } 1159 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID, 1160 PCI_CLASS_SERIAL_USB, 8, quirk_usb_early_handoff); 1161 1162 bool usb_xhci_needs_pci_reset(struct pci_dev *pdev) 1163 { 1164 /* 1165 * Our dear uPD72020{1,2} friend only partially resets when 1166 * asked to via the XHCI interface, and may end up doing DMA 1167 * at the wrong addresses, as it keeps the top 32bit of some 1168 * addresses from its previous programming under obscure 1169 * circumstances. 1170 * Give it a good wack at probe time. Unfortunately, this 1171 * needs to happen before we've had a chance to discover any 1172 * quirk, or the system will be in a rather bad state. 1173 */ 1174 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 1175 (pdev->device == 0x0014 || pdev->device == 0x0015)) 1176 return true; 1177 1178 return false; 1179 } 1180 EXPORT_SYMBOL_GPL(usb_xhci_needs_pci_reset); 1181