1 /* 2 * New-style PCI core. 3 * 4 * Copyright (c) 2004 - 2009 Paul Mundt 5 * Copyright (c) 2002 M. R. Brown 6 * 7 * Modelled after arch/mips/pci/pci.c: 8 * Copyright (C) 2003, 04 Ralf Baechle (ralf@linux-mips.org) 9 * 10 * This file is subject to the terms and conditions of the GNU General Public 11 * License. See the file "COPYING" in the main directory of this archive 12 * for more details. 13 */ 14 #include <linux/kernel.h> 15 #include <linux/mm.h> 16 #include <linux/pci.h> 17 #include <linux/init.h> 18 #include <linux/types.h> 19 #include <linux/dma-debug.h> 20 #include <linux/io.h> 21 #include <linux/mutex.h> 22 #include <linux/spinlock.h> 23 #include <linux/export.h> 24 25 unsigned long PCIBIOS_MIN_IO = 0x0000; 26 unsigned long PCIBIOS_MIN_MEM = 0; 27 28 /* 29 * The PCI controller list. 30 */ 31 static struct pci_channel *hose_head, **hose_tail = &hose_head; 32 33 static int pci_initialized; 34 35 static void pcibios_scanbus(struct pci_channel *hose) 36 { 37 static int next_busno; 38 static int need_domain_info; 39 LIST_HEAD(resources); 40 struct resource *res; 41 resource_size_t offset; 42 int i, ret; 43 struct pci_host_bridge *bridge; 44 45 bridge = pci_alloc_host_bridge(0); 46 if (!bridge) 47 return; 48 49 for (i = 0; i < hose->nr_resources; i++) { 50 res = hose->resources + i; 51 offset = 0; 52 if (res->flags & IORESOURCE_IO) 53 offset = hose->io_offset; 54 else if (res->flags & IORESOURCE_MEM) 55 offset = hose->mem_offset; 56 pci_add_resource_offset(&resources, res, offset); 57 } 58 59 list_splice_init(&resources, &bridge->windows); 60 bridge->dev.parent = NULL; 61 bridge->sysdata = hose; 62 bridge->busnr = next_busno; 63 bridge->ops = hose->pci_ops; 64 bridge->swizzle_irq = pci_common_swizzle; 65 bridge->map_irq = pcibios_map_platform_irq; 66 67 ret = pci_scan_root_bus_bridge(bridge); 68 if (ret) { 69 pci_free_host_bridge(bridge); 70 return; 71 } 72 73 hose->bus = bridge->bus; 74 75 need_domain_info = need_domain_info || hose->index; 76 hose->need_domain_info = need_domain_info; 77 78 next_busno = hose->bus->busn_res.end + 1; 79 /* Don't allow 8-bit bus number overflow inside the hose - 80 reserve some space for bridges. */ 81 if (next_busno > 224) { 82 next_busno = 0; 83 need_domain_info = 1; 84 } 85 86 pci_bus_size_bridges(hose->bus); 87 pci_bus_assign_resources(hose->bus); 88 pci_bus_add_devices(hose->bus); 89 } 90 91 /* 92 * This interrupt-safe spinlock protects all accesses to PCI 93 * configuration space. 94 */ 95 DEFINE_RAW_SPINLOCK(pci_config_lock); 96 static DEFINE_MUTEX(pci_scan_mutex); 97 98 int register_pci_controller(struct pci_channel *hose) 99 { 100 int i; 101 102 for (i = 0; i < hose->nr_resources; i++) { 103 struct resource *res = hose->resources + i; 104 105 if (res->flags & IORESOURCE_IO) { 106 if (request_resource(&ioport_resource, res) < 0) 107 goto out; 108 } else { 109 if (request_resource(&iomem_resource, res) < 0) 110 goto out; 111 } 112 } 113 114 *hose_tail = hose; 115 hose_tail = &hose->next; 116 117 /* 118 * Do not panic here but later - this might happen before console init. 119 */ 120 if (!hose->io_map_base) { 121 printk(KERN_WARNING 122 "registering PCI controller with io_map_base unset\n"); 123 } 124 125 /* 126 * Setup the ERR/PERR and SERR timers, if available. 127 */ 128 pcibios_enable_timers(hose); 129 130 /* 131 * Scan the bus if it is register after the PCI subsystem 132 * initialization. 133 */ 134 if (pci_initialized) { 135 mutex_lock(&pci_scan_mutex); 136 pcibios_scanbus(hose); 137 mutex_unlock(&pci_scan_mutex); 138 } 139 140 return 0; 141 142 out: 143 for (--i; i >= 0; i--) 144 release_resource(&hose->resources[i]); 145 146 printk(KERN_WARNING "Skipping PCI bus scan due to resource conflict\n"); 147 return -1; 148 } 149 150 static int __init pcibios_init(void) 151 { 152 struct pci_channel *hose; 153 154 /* Scan all of the recorded PCI controllers. */ 155 for (hose = hose_head; hose; hose = hose->next) 156 pcibios_scanbus(hose); 157 158 dma_debug_add_bus(&pci_bus_type); 159 160 pci_initialized = 1; 161 162 return 0; 163 } 164 subsys_initcall(pcibios_init); 165 166 /* 167 * We need to avoid collisions with `mirrored' VGA ports 168 * and other strange ISA hardware, so we always want the 169 * addresses to be allocated in the 0x000-0x0ff region 170 * modulo 0x400. 171 */ 172 resource_size_t pcibios_align_resource(void *data, const struct resource *res, 173 resource_size_t size, resource_size_t align) 174 { 175 struct pci_dev *dev = data; 176 struct pci_channel *hose = dev->sysdata; 177 resource_size_t start = res->start; 178 179 if (res->flags & IORESOURCE_IO) { 180 if (start < PCIBIOS_MIN_IO + hose->resources[0].start) 181 start = PCIBIOS_MIN_IO + hose->resources[0].start; 182 183 /* 184 * Put everything into 0x00-0xff region modulo 0x400. 185 */ 186 if (start & 0x300) 187 start = (start + 0x3ff) & ~0x3ff; 188 } 189 190 return start; 191 } 192 193 static void __init 194 pcibios_bus_report_status_early(struct pci_channel *hose, 195 int top_bus, int current_bus, 196 unsigned int status_mask, int warn) 197 { 198 unsigned int pci_devfn; 199 u16 status; 200 int ret; 201 202 for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++) { 203 if (PCI_FUNC(pci_devfn)) 204 continue; 205 ret = early_read_config_word(hose, top_bus, current_bus, 206 pci_devfn, PCI_STATUS, &status); 207 if (ret != PCIBIOS_SUCCESSFUL) 208 continue; 209 if (status == 0xffff) 210 continue; 211 212 early_write_config_word(hose, top_bus, current_bus, 213 pci_devfn, PCI_STATUS, 214 status & status_mask); 215 if (warn) 216 printk("(%02x:%02x: %04X) ", current_bus, 217 pci_devfn, status); 218 } 219 } 220 221 /* 222 * We can't use pci_find_device() here since we are 223 * called from interrupt context. 224 */ 225 static void __ref 226 pcibios_bus_report_status(struct pci_bus *bus, unsigned int status_mask, 227 int warn) 228 { 229 struct pci_dev *dev; 230 231 list_for_each_entry(dev, &bus->devices, bus_list) { 232 u16 status; 233 234 /* 235 * ignore host bridge - we handle 236 * that separately 237 */ 238 if (dev->bus->number == 0 && dev->devfn == 0) 239 continue; 240 241 pci_read_config_word(dev, PCI_STATUS, &status); 242 if (status == 0xffff) 243 continue; 244 245 if ((status & status_mask) == 0) 246 continue; 247 248 /* clear the status errors */ 249 pci_write_config_word(dev, PCI_STATUS, status & status_mask); 250 251 if (warn) 252 printk("(%s: %04X) ", pci_name(dev), status); 253 } 254 255 list_for_each_entry(dev, &bus->devices, bus_list) 256 if (dev->subordinate) 257 pcibios_bus_report_status(dev->subordinate, status_mask, warn); 258 } 259 260 void __ref pcibios_report_status(unsigned int status_mask, int warn) 261 { 262 struct pci_channel *hose; 263 264 for (hose = hose_head; hose; hose = hose->next) { 265 if (unlikely(!hose->bus)) 266 pcibios_bus_report_status_early(hose, hose_head->index, 267 hose->index, status_mask, warn); 268 else 269 pcibios_bus_report_status(hose->bus, status_mask, warn); 270 } 271 } 272 273 #ifndef CONFIG_GENERIC_IOMAP 274 275 void __iomem *__pci_ioport_map(struct pci_dev *dev, 276 unsigned long port, unsigned int nr) 277 { 278 struct pci_channel *chan = dev->sysdata; 279 280 if (unlikely(!chan->io_map_base)) { 281 chan->io_map_base = sh_io_port_base; 282 283 if (pci_domains_supported) 284 panic("To avoid data corruption io_map_base MUST be " 285 "set with multiple PCI domains."); 286 } 287 288 return (void __iomem *)(chan->io_map_base + port); 289 } 290 291 void pci_iounmap(struct pci_dev *dev, void __iomem *addr) 292 { 293 iounmap(addr); 294 } 295 EXPORT_SYMBOL(pci_iounmap); 296 297 #endif /* CONFIG_GENERIC_IOMAP */ 298 299 EXPORT_SYMBOL(PCIBIOS_MIN_IO); 300 EXPORT_SYMBOL(PCIBIOS_MIN_MEM); 301