07238079 | 26-Jul-2023 |
Rob Herring <robh@kernel.org> |
MIPS: Fixup explicit DT include clean-up
Commit 657c45b303f87d77 ("MIPS: Explicitly include correct DT includes") removed a necessary include by mistake and missed adding an explicit include of spin
MIPS: Fixup explicit DT include clean-up
Commit 657c45b303f87d77 ("MIPS: Explicitly include correct DT includes") removed a necessary include by mistake and missed adding an explicit include of spinlock.h (from of.h -> kobject.h -> spinlock.h).
Fixes: 657c45b303f87d77 ("MIPS: Explicitly include correct DT includes") Reported-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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bf21f3f8 | 27-Sep-2022 |
Dmitry Torokhov <dmitry.torokhov@gmail.com> |
MIPS: Lantiq: vmmc: fix compile break introduced by gpiod patch
"MIPS: Lantiq: switch vmmc to use gpiod API" patch introduced compile errors, this patch fixes them.
Signed-off-by: Dmitry Torokhov <
MIPS: Lantiq: vmmc: fix compile break introduced by gpiod patch
"MIPS: Lantiq: switch vmmc to use gpiod API" patch introduced compile errors, this patch fixes them.
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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49293bbc | 14-Sep-2021 |
Aleksander Jan Bajkowski <olek2@wp.pl> |
MIPS: lantiq: dma: make the burst length configurable by the drivers
Make the burst length configurable by the drivers.
Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl> Acked-by: Hauke Mehrten
MIPS: lantiq: dma: make the burst length configurable by the drivers
Make the burst length configurable by the drivers.
Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl> Acked-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: David S. Miller <davem@davemloft.net>
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5ad74d39 | 14-Sep-2021 |
Aleksander Jan Bajkowski <olek2@wp.pl> |
MIPS: lantiq: dma: fix burst length for DEU
The current definition of 2W burst length is invalid. This patch fixes it. Current downstream DEU driver doesn't use DMA. An incorrect burst length value
MIPS: lantiq: dma: fix burst length for DEU
The current definition of 2W burst length is invalid. This patch fixes it. Current downstream DEU driver doesn't use DMA. An incorrect burst length value doesn't cause any errors. This patch also adds other burst length values.
Fixes: dfec1a827d2b ("MIPS: Lantiq: Add DMA support") Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl> Signed-off-by: David S. Miller <davem@davemloft.net>
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5ca9ce2b | 14-Sep-2021 |
Aleksander Jan Bajkowski <olek2@wp.pl> |
MIPS: lantiq: dma: reset correct number of channel
Different SoCs have a different number of channels, e.g .: * amazon-se has 10 channels, * danube+ar9 have 20 channels, * vr9 has 28 channels, * ar1
MIPS: lantiq: dma: reset correct number of channel
Different SoCs have a different number of channels, e.g .: * amazon-se has 10 channels, * danube+ar9 have 20 channels, * vr9 has 28 channels, * ar10 has 24 channels.
We can read the ID register and, depending on the reported number of channels, reset the appropriate number of channels.
Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl> Signed-off-by: David S. Miller <davem@davemloft.net>
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14fceff4 | 09-Sep-2018 |
Hauke Mehrtens <hauke@hauke-m.de> |
net: dsa: Add Lantiq / Intel DSA driver for vrx200
This adds the DSA driver for the GSWIP Switch found in the VRX200 SoC. This switch is integrated in the DSL SoC, this SoC uses a GSWIP version 2.1,
net: dsa: Add Lantiq / Intel DSA driver for vrx200
This adds the DSA driver for the GSWIP Switch found in the VRX200 SoC. This switch is integrated in the DSL SoC, this SoC uses a GSWIP version 2.1, there are other SoCs using different versions of this IP block, but this driver was only tested with the version found in the VRX200. Currently only the basic features are implemented which will forward all packages to the CPU and let the CPU do the forwarding. The hardware also support Layer 2 offloading which is not yet implemented in this driver.
The GPHY FW loaded is now done by this driver and not any more by the separate driver in drivers/soc/lantiq/gphy.c, I will remove this driver is a separate patch. to make use of the GPHY this switch driver is needed anyway. Other SoCs have more embedded GPHYs so this driver should support a variable number of GPHYs. After the firmware was loaded the GPHY can be probed on the MDIO bus and it behaves like an external GPHY, without the firmware it can not be probed on the MDIO bus.
The clock names in the sysctrl.c file have to be changed because the clocks are now used by a different driver. This should be cleaned up and a real common clock driver should provide the clocks instead.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: David S. Miller <davem@davemloft.net>
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