1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Atmel MultiMedia Card Interface driver 4 * 5 * Copyright (C) 2004-2008 Atmel Corporation 6 */ 7 #include <linux/blkdev.h> 8 #include <linux/clk.h> 9 #include <linux/debugfs.h> 10 #include <linux/device.h> 11 #include <linux/dmaengine.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/err.h> 14 #include <linux/gpio.h> 15 #include <linux/init.h> 16 #include <linux/interrupt.h> 17 #include <linux/io.h> 18 #include <linux/ioport.h> 19 #include <linux/module.h> 20 #include <linux/of.h> 21 #include <linux/of_device.h> 22 #include <linux/of_gpio.h> 23 #include <linux/platform_device.h> 24 #include <linux/scatterlist.h> 25 #include <linux/seq_file.h> 26 #include <linux/slab.h> 27 #include <linux/stat.h> 28 #include <linux/types.h> 29 30 #include <linux/mmc/host.h> 31 #include <linux/mmc/sdio.h> 32 33 #include <linux/atmel-mci.h> 34 #include <linux/atmel_pdc.h> 35 #include <linux/pm.h> 36 #include <linux/pm_runtime.h> 37 #include <linux/pinctrl/consumer.h> 38 39 #include <asm/cacheflush.h> 40 #include <asm/io.h> 41 #include <asm/unaligned.h> 42 43 /* 44 * Superset of MCI IP registers integrated in Atmel AT91 Processor 45 * Registers and bitfields marked with [2] are only available in MCI2 46 */ 47 48 /* MCI Register Definitions */ 49 #define ATMCI_CR 0x0000 /* Control */ 50 #define ATMCI_CR_MCIEN BIT(0) /* MCI Enable */ 51 #define ATMCI_CR_MCIDIS BIT(1) /* MCI Disable */ 52 #define ATMCI_CR_PWSEN BIT(2) /* Power Save Enable */ 53 #define ATMCI_CR_PWSDIS BIT(3) /* Power Save Disable */ 54 #define ATMCI_CR_SWRST BIT(7) /* Software Reset */ 55 #define ATMCI_MR 0x0004 /* Mode */ 56 #define ATMCI_MR_CLKDIV(x) ((x) << 0) /* Clock Divider */ 57 #define ATMCI_MR_PWSDIV(x) ((x) << 8) /* Power Saving Divider */ 58 #define ATMCI_MR_RDPROOF BIT(11) /* Read Proof */ 59 #define ATMCI_MR_WRPROOF BIT(12) /* Write Proof */ 60 #define ATMCI_MR_PDCFBYTE BIT(13) /* Force Byte Transfer */ 61 #define ATMCI_MR_PDCPADV BIT(14) /* Padding Value */ 62 #define ATMCI_MR_PDCMODE BIT(15) /* PDC-oriented Mode */ 63 #define ATMCI_MR_CLKODD(x) ((x) << 16) /* LSB of Clock Divider */ 64 #define ATMCI_DTOR 0x0008 /* Data Timeout */ 65 #define ATMCI_DTOCYC(x) ((x) << 0) /* Data Timeout Cycles */ 66 #define ATMCI_DTOMUL(x) ((x) << 4) /* Data Timeout Multiplier */ 67 #define ATMCI_SDCR 0x000c /* SD Card / SDIO */ 68 #define ATMCI_SDCSEL_SLOT_A (0 << 0) /* Select SD slot A */ 69 #define ATMCI_SDCSEL_SLOT_B (1 << 0) /* Select SD slot A */ 70 #define ATMCI_SDCSEL_MASK (3 << 0) 71 #define ATMCI_SDCBUS_1BIT (0 << 6) /* 1-bit data bus */ 72 #define ATMCI_SDCBUS_4BIT (2 << 6) /* 4-bit data bus */ 73 #define ATMCI_SDCBUS_8BIT (3 << 6) /* 8-bit data bus[2] */ 74 #define ATMCI_SDCBUS_MASK (3 << 6) 75 #define ATMCI_ARGR 0x0010 /* Command Argument */ 76 #define ATMCI_CMDR 0x0014 /* Command */ 77 #define ATMCI_CMDR_CMDNB(x) ((x) << 0) /* Command Opcode */ 78 #define ATMCI_CMDR_RSPTYP_NONE (0 << 6) /* No response */ 79 #define ATMCI_CMDR_RSPTYP_48BIT (1 << 6) /* 48-bit response */ 80 #define ATMCI_CMDR_RSPTYP_136BIT (2 << 6) /* 136-bit response */ 81 #define ATMCI_CMDR_SPCMD_INIT (1 << 8) /* Initialization command */ 82 #define ATMCI_CMDR_SPCMD_SYNC (2 << 8) /* Synchronized command */ 83 #define ATMCI_CMDR_SPCMD_INT (4 << 8) /* Interrupt command */ 84 #define ATMCI_CMDR_SPCMD_INTRESP (5 << 8) /* Interrupt response */ 85 #define ATMCI_CMDR_OPDCMD (1 << 11) /* Open Drain */ 86 #define ATMCI_CMDR_MAXLAT_5CYC (0 << 12) /* Max latency 5 cycles */ 87 #define ATMCI_CMDR_MAXLAT_64CYC (1 << 12) /* Max latency 64 cycles */ 88 #define ATMCI_CMDR_START_XFER (1 << 16) /* Start data transfer */ 89 #define ATMCI_CMDR_STOP_XFER (2 << 16) /* Stop data transfer */ 90 #define ATMCI_CMDR_TRDIR_WRITE (0 << 18) /* Write data */ 91 #define ATMCI_CMDR_TRDIR_READ (1 << 18) /* Read data */ 92 #define ATMCI_CMDR_BLOCK (0 << 19) /* Single-block transfer */ 93 #define ATMCI_CMDR_MULTI_BLOCK (1 << 19) /* Multi-block transfer */ 94 #define ATMCI_CMDR_STREAM (2 << 19) /* MMC Stream transfer */ 95 #define ATMCI_CMDR_SDIO_BYTE (4 << 19) /* SDIO Byte transfer */ 96 #define ATMCI_CMDR_SDIO_BLOCK (5 << 19) /* SDIO Block transfer */ 97 #define ATMCI_CMDR_SDIO_SUSPEND (1 << 24) /* SDIO Suspend Command */ 98 #define ATMCI_CMDR_SDIO_RESUME (2 << 24) /* SDIO Resume Command */ 99 #define ATMCI_BLKR 0x0018 /* Block */ 100 #define ATMCI_BCNT(x) ((x) << 0) /* Data Block Count */ 101 #define ATMCI_BLKLEN(x) ((x) << 16) /* Data Block Length */ 102 #define ATMCI_CSTOR 0x001c /* Completion Signal Timeout[2] */ 103 #define ATMCI_CSTOCYC(x) ((x) << 0) /* CST cycles */ 104 #define ATMCI_CSTOMUL(x) ((x) << 4) /* CST multiplier */ 105 #define ATMCI_RSPR 0x0020 /* Response 0 */ 106 #define ATMCI_RSPR1 0x0024 /* Response 1 */ 107 #define ATMCI_RSPR2 0x0028 /* Response 2 */ 108 #define ATMCI_RSPR3 0x002c /* Response 3 */ 109 #define ATMCI_RDR 0x0030 /* Receive Data */ 110 #define ATMCI_TDR 0x0034 /* Transmit Data */ 111 #define ATMCI_SR 0x0040 /* Status */ 112 #define ATMCI_IER 0x0044 /* Interrupt Enable */ 113 #define ATMCI_IDR 0x0048 /* Interrupt Disable */ 114 #define ATMCI_IMR 0x004c /* Interrupt Mask */ 115 #define ATMCI_CMDRDY BIT(0) /* Command Ready */ 116 #define ATMCI_RXRDY BIT(1) /* Receiver Ready */ 117 #define ATMCI_TXRDY BIT(2) /* Transmitter Ready */ 118 #define ATMCI_BLKE BIT(3) /* Data Block Ended */ 119 #define ATMCI_DTIP BIT(4) /* Data Transfer In Progress */ 120 #define ATMCI_NOTBUSY BIT(5) /* Data Not Busy */ 121 #define ATMCI_ENDRX BIT(6) /* End of RX Buffer */ 122 #define ATMCI_ENDTX BIT(7) /* End of TX Buffer */ 123 #define ATMCI_SDIOIRQA BIT(8) /* SDIO IRQ in slot A */ 124 #define ATMCI_SDIOIRQB BIT(9) /* SDIO IRQ in slot B */ 125 #define ATMCI_SDIOWAIT BIT(12) /* SDIO Read Wait Operation Status */ 126 #define ATMCI_CSRCV BIT(13) /* CE-ATA Completion Signal Received */ 127 #define ATMCI_RXBUFF BIT(14) /* RX Buffer Full */ 128 #define ATMCI_TXBUFE BIT(15) /* TX Buffer Empty */ 129 #define ATMCI_RINDE BIT(16) /* Response Index Error */ 130 #define ATMCI_RDIRE BIT(17) /* Response Direction Error */ 131 #define ATMCI_RCRCE BIT(18) /* Response CRC Error */ 132 #define ATMCI_RENDE BIT(19) /* Response End Bit Error */ 133 #define ATMCI_RTOE BIT(20) /* Response Time-Out Error */ 134 #define ATMCI_DCRCE BIT(21) /* Data CRC Error */ 135 #define ATMCI_DTOE BIT(22) /* Data Time-Out Error */ 136 #define ATMCI_CSTOE BIT(23) /* Completion Signal Time-out Error */ 137 #define ATMCI_BLKOVRE BIT(24) /* DMA Block Overrun Error */ 138 #define ATMCI_DMADONE BIT(25) /* DMA Transfer Done */ 139 #define ATMCI_FIFOEMPTY BIT(26) /* FIFO Empty Flag */ 140 #define ATMCI_XFRDONE BIT(27) /* Transfer Done Flag */ 141 #define ATMCI_ACKRCV BIT(28) /* Boot Operation Acknowledge Received */ 142 #define ATMCI_ACKRCVE BIT(29) /* Boot Operation Acknowledge Error */ 143 #define ATMCI_OVRE BIT(30) /* RX Overrun Error */ 144 #define ATMCI_UNRE BIT(31) /* TX Underrun Error */ 145 #define ATMCI_DMA 0x0050 /* DMA Configuration[2] */ 146 #define ATMCI_DMA_OFFSET(x) ((x) << 0) /* DMA Write Buffer Offset */ 147 #define ATMCI_DMA_CHKSIZE(x) ((x) << 4) /* DMA Channel Read and Write Chunk Size */ 148 #define ATMCI_DMAEN BIT(8) /* DMA Hardware Handshaking Enable */ 149 #define ATMCI_CFG 0x0054 /* Configuration[2] */ 150 #define ATMCI_CFG_FIFOMODE_1DATA BIT(0) /* MCI Internal FIFO control mode */ 151 #define ATMCI_CFG_FERRCTRL_COR BIT(4) /* Flow Error flag reset control mode */ 152 #define ATMCI_CFG_HSMODE BIT(8) /* High Speed Mode */ 153 #define ATMCI_CFG_LSYNC BIT(12) /* Synchronize on the last block */ 154 #define ATMCI_WPMR 0x00e4 /* Write Protection Mode[2] */ 155 #define ATMCI_WP_EN BIT(0) /* WP Enable */ 156 #define ATMCI_WP_KEY (0x4d4349 << 8) /* WP Key */ 157 #define ATMCI_WPSR 0x00e8 /* Write Protection Status[2] */ 158 #define ATMCI_GET_WP_VS(x) ((x) & 0x0f) 159 #define ATMCI_GET_WP_VSRC(x) (((x) >> 8) & 0xffff) 160 #define ATMCI_VERSION 0x00FC /* Version */ 161 #define ATMCI_FIFO_APERTURE 0x0200 /* FIFO Aperture[2] */ 162 163 /* This is not including the FIFO Aperture on MCI2 */ 164 #define ATMCI_REGS_SIZE 0x100 165 166 /* Register access macros */ 167 #define atmci_readl(port, reg) \ 168 __raw_readl((port)->regs + reg) 169 #define atmci_writel(port, reg, value) \ 170 __raw_writel((value), (port)->regs + reg) 171 172 #define AUTOSUSPEND_DELAY 50 173 174 #define ATMCI_DATA_ERROR_FLAGS (ATMCI_DCRCE | ATMCI_DTOE | ATMCI_OVRE | ATMCI_UNRE) 175 #define ATMCI_DMA_THRESHOLD 16 176 177 enum { 178 EVENT_CMD_RDY = 0, 179 EVENT_XFER_COMPLETE, 180 EVENT_NOTBUSY, 181 EVENT_DATA_ERROR, 182 }; 183 184 enum atmel_mci_state { 185 STATE_IDLE = 0, 186 STATE_SENDING_CMD, 187 STATE_DATA_XFER, 188 STATE_WAITING_NOTBUSY, 189 STATE_SENDING_STOP, 190 STATE_END_REQUEST, 191 }; 192 193 enum atmci_xfer_dir { 194 XFER_RECEIVE = 0, 195 XFER_TRANSMIT, 196 }; 197 198 enum atmci_pdc_buf { 199 PDC_FIRST_BUF = 0, 200 PDC_SECOND_BUF, 201 }; 202 203 struct atmel_mci_caps { 204 bool has_dma_conf_reg; 205 bool has_pdc; 206 bool has_cfg_reg; 207 bool has_cstor_reg; 208 bool has_highspeed; 209 bool has_rwproof; 210 bool has_odd_clk_div; 211 bool has_bad_data_ordering; 212 bool need_reset_after_xfer; 213 bool need_blksz_mul_4; 214 bool need_notbusy_for_read_ops; 215 }; 216 217 struct atmel_mci_dma { 218 struct dma_chan *chan; 219 struct dma_async_tx_descriptor *data_desc; 220 }; 221 222 /** 223 * struct atmel_mci - MMC controller state shared between all slots 224 * @lock: Spinlock protecting the queue and associated data. 225 * @regs: Pointer to MMIO registers. 226 * @sg: Scatterlist entry currently being processed by PIO or PDC code. 227 * @pio_offset: Offset into the current scatterlist entry. 228 * @buffer: Buffer used if we don't have the r/w proof capability. We 229 * don't have the time to switch pdc buffers so we have to use only 230 * one buffer for the full transaction. 231 * @buf_size: size of the buffer. 232 * @phys_buf_addr: buffer address needed for pdc. 233 * @cur_slot: The slot which is currently using the controller. 234 * @mrq: The request currently being processed on @cur_slot, 235 * or NULL if the controller is idle. 236 * @cmd: The command currently being sent to the card, or NULL. 237 * @data: The data currently being transferred, or NULL if no data 238 * transfer is in progress. 239 * @data_size: just data->blocks * data->blksz. 240 * @dma: DMA client state. 241 * @data_chan: DMA channel being used for the current data transfer. 242 * @cmd_status: Snapshot of SR taken upon completion of the current 243 * command. Only valid when EVENT_CMD_COMPLETE is pending. 244 * @data_status: Snapshot of SR taken upon completion of the current 245 * data transfer. Only valid when EVENT_DATA_COMPLETE or 246 * EVENT_DATA_ERROR is pending. 247 * @stop_cmdr: Value to be loaded into CMDR when the stop command is 248 * to be sent. 249 * @tasklet: Tasklet running the request state machine. 250 * @pending_events: Bitmask of events flagged by the interrupt handler 251 * to be processed by the tasklet. 252 * @completed_events: Bitmask of events which the state machine has 253 * processed. 254 * @state: Tasklet state. 255 * @queue: List of slots waiting for access to the controller. 256 * @need_clock_update: Update the clock rate before the next request. 257 * @need_reset: Reset controller before next request. 258 * @timer: Timer to balance the data timeout error flag which cannot rise. 259 * @mode_reg: Value of the MR register. 260 * @cfg_reg: Value of the CFG register. 261 * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus 262 * rate and timeout calculations. 263 * @mapbase: Physical address of the MMIO registers. 264 * @mck: The peripheral bus clock hooked up to the MMC controller. 265 * @pdev: Platform device associated with the MMC controller. 266 * @slot: Slots sharing this MMC controller. 267 * @caps: MCI capabilities depending on MCI version. 268 * @prepare_data: function to setup MCI before data transfer which 269 * depends on MCI capabilities. 270 * @submit_data: function to start data transfer which depends on MCI 271 * capabilities. 272 * @stop_transfer: function to stop data transfer which depends on MCI 273 * capabilities. 274 * 275 * Locking 276 * ======= 277 * 278 * @lock is a softirq-safe spinlock protecting @queue as well as 279 * @cur_slot, @mrq and @state. These must always be updated 280 * at the same time while holding @lock. 281 * 282 * @lock also protects mode_reg and need_clock_update since these are 283 * used to synchronize mode register updates with the queue 284 * processing. 285 * 286 * The @mrq field of struct atmel_mci_slot is also protected by @lock, 287 * and must always be written at the same time as the slot is added to 288 * @queue. 289 * 290 * @pending_events and @completed_events are accessed using atomic bit 291 * operations, so they don't need any locking. 292 * 293 * None of the fields touched by the interrupt handler need any 294 * locking. However, ordering is important: Before EVENT_DATA_ERROR or 295 * EVENT_DATA_COMPLETE is set in @pending_events, all data-related 296 * interrupts must be disabled and @data_status updated with a 297 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the 298 * CMDRDY interrupt must be disabled and @cmd_status updated with a 299 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the 300 * bytes_xfered field of @data must be written. This is ensured by 301 * using barriers. 302 */ 303 struct atmel_mci { 304 spinlock_t lock; 305 void __iomem *regs; 306 307 struct scatterlist *sg; 308 unsigned int sg_len; 309 unsigned int pio_offset; 310 unsigned int *buffer; 311 unsigned int buf_size; 312 dma_addr_t buf_phys_addr; 313 314 struct atmel_mci_slot *cur_slot; 315 struct mmc_request *mrq; 316 struct mmc_command *cmd; 317 struct mmc_data *data; 318 unsigned int data_size; 319 320 struct atmel_mci_dma dma; 321 struct dma_chan *data_chan; 322 struct dma_slave_config dma_conf; 323 324 u32 cmd_status; 325 u32 data_status; 326 u32 stop_cmdr; 327 328 struct tasklet_struct tasklet; 329 unsigned long pending_events; 330 unsigned long completed_events; 331 enum atmel_mci_state state; 332 struct list_head queue; 333 334 bool need_clock_update; 335 bool need_reset; 336 struct timer_list timer; 337 u32 mode_reg; 338 u32 cfg_reg; 339 unsigned long bus_hz; 340 unsigned long mapbase; 341 struct clk *mck; 342 struct platform_device *pdev; 343 344 struct atmel_mci_slot *slot[ATMCI_MAX_NR_SLOTS]; 345 346 struct atmel_mci_caps caps; 347 348 u32 (*prepare_data)(struct atmel_mci *host, struct mmc_data *data); 349 void (*submit_data)(struct atmel_mci *host, struct mmc_data *data); 350 void (*stop_transfer)(struct atmel_mci *host); 351 }; 352 353 /** 354 * struct atmel_mci_slot - MMC slot state 355 * @mmc: The mmc_host representing this slot. 356 * @host: The MMC controller this slot is using. 357 * @sdc_reg: Value of SDCR to be written before using this slot. 358 * @sdio_irq: SDIO irq mask for this slot. 359 * @mrq: mmc_request currently being processed or waiting to be 360 * processed, or NULL when the slot is idle. 361 * @queue_node: List node for placing this node in the @queue list of 362 * &struct atmel_mci. 363 * @clock: Clock rate configured by set_ios(). Protected by host->lock. 364 * @flags: Random state bits associated with the slot. 365 * @detect_pin: GPIO pin used for card detection, or negative if not 366 * available. 367 * @wp_pin: GPIO pin used for card write protect sending, or negative 368 * if not available. 369 * @detect_is_active_high: The state of the detect pin when it is active. 370 * @detect_timer: Timer used for debouncing @detect_pin interrupts. 371 */ 372 struct atmel_mci_slot { 373 struct mmc_host *mmc; 374 struct atmel_mci *host; 375 376 u32 sdc_reg; 377 u32 sdio_irq; 378 379 struct mmc_request *mrq; 380 struct list_head queue_node; 381 382 unsigned int clock; 383 unsigned long flags; 384 #define ATMCI_CARD_PRESENT 0 385 #define ATMCI_CARD_NEED_INIT 1 386 #define ATMCI_SHUTDOWN 2 387 388 int detect_pin; 389 int wp_pin; 390 bool detect_is_active_high; 391 392 struct timer_list detect_timer; 393 }; 394 395 #define atmci_test_and_clear_pending(host, event) \ 396 test_and_clear_bit(event, &host->pending_events) 397 #define atmci_set_completed(host, event) \ 398 set_bit(event, &host->completed_events) 399 #define atmci_set_pending(host, event) \ 400 set_bit(event, &host->pending_events) 401 402 /* 403 * The debugfs stuff below is mostly optimized away when 404 * CONFIG_DEBUG_FS is not set. 405 */ 406 static int atmci_req_show(struct seq_file *s, void *v) 407 { 408 struct atmel_mci_slot *slot = s->private; 409 struct mmc_request *mrq; 410 struct mmc_command *cmd; 411 struct mmc_command *stop; 412 struct mmc_data *data; 413 414 /* Make sure we get a consistent snapshot */ 415 spin_lock_bh(&slot->host->lock); 416 mrq = slot->mrq; 417 418 if (mrq) { 419 cmd = mrq->cmd; 420 data = mrq->data; 421 stop = mrq->stop; 422 423 if (cmd) 424 seq_printf(s, 425 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 426 cmd->opcode, cmd->arg, cmd->flags, 427 cmd->resp[0], cmd->resp[1], cmd->resp[2], 428 cmd->resp[3], cmd->error); 429 if (data) 430 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n", 431 data->bytes_xfered, data->blocks, 432 data->blksz, data->flags, data->error); 433 if (stop) 434 seq_printf(s, 435 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 436 stop->opcode, stop->arg, stop->flags, 437 stop->resp[0], stop->resp[1], stop->resp[2], 438 stop->resp[3], stop->error); 439 } 440 441 spin_unlock_bh(&slot->host->lock); 442 443 return 0; 444 } 445 446 DEFINE_SHOW_ATTRIBUTE(atmci_req); 447 448 static void atmci_show_status_reg(struct seq_file *s, 449 const char *regname, u32 value) 450 { 451 static const char *sr_bit[] = { 452 [0] = "CMDRDY", 453 [1] = "RXRDY", 454 [2] = "TXRDY", 455 [3] = "BLKE", 456 [4] = "DTIP", 457 [5] = "NOTBUSY", 458 [6] = "ENDRX", 459 [7] = "ENDTX", 460 [8] = "SDIOIRQA", 461 [9] = "SDIOIRQB", 462 [12] = "SDIOWAIT", 463 [14] = "RXBUFF", 464 [15] = "TXBUFE", 465 [16] = "RINDE", 466 [17] = "RDIRE", 467 [18] = "RCRCE", 468 [19] = "RENDE", 469 [20] = "RTOE", 470 [21] = "DCRCE", 471 [22] = "DTOE", 472 [23] = "CSTOE", 473 [24] = "BLKOVRE", 474 [25] = "DMADONE", 475 [26] = "FIFOEMPTY", 476 [27] = "XFRDONE", 477 [30] = "OVRE", 478 [31] = "UNRE", 479 }; 480 unsigned int i; 481 482 seq_printf(s, "%s:\t0x%08x", regname, value); 483 for (i = 0; i < ARRAY_SIZE(sr_bit); i++) { 484 if (value & (1 << i)) { 485 if (sr_bit[i]) 486 seq_printf(s, " %s", sr_bit[i]); 487 else 488 seq_puts(s, " UNKNOWN"); 489 } 490 } 491 seq_putc(s, '\n'); 492 } 493 494 static int atmci_regs_show(struct seq_file *s, void *v) 495 { 496 struct atmel_mci *host = s->private; 497 u32 *buf; 498 int ret = 0; 499 500 501 buf = kmalloc(ATMCI_REGS_SIZE, GFP_KERNEL); 502 if (!buf) 503 return -ENOMEM; 504 505 pm_runtime_get_sync(&host->pdev->dev); 506 507 /* 508 * Grab a more or less consistent snapshot. Note that we're 509 * not disabling interrupts, so IMR and SR may not be 510 * consistent. 511 */ 512 spin_lock_bh(&host->lock); 513 memcpy_fromio(buf, host->regs, ATMCI_REGS_SIZE); 514 spin_unlock_bh(&host->lock); 515 516 pm_runtime_mark_last_busy(&host->pdev->dev); 517 pm_runtime_put_autosuspend(&host->pdev->dev); 518 519 seq_printf(s, "MR:\t0x%08x%s%s ", 520 buf[ATMCI_MR / 4], 521 buf[ATMCI_MR / 4] & ATMCI_MR_RDPROOF ? " RDPROOF" : "", 522 buf[ATMCI_MR / 4] & ATMCI_MR_WRPROOF ? " WRPROOF" : ""); 523 if (host->caps.has_odd_clk_div) 524 seq_printf(s, "{CLKDIV,CLKODD}=%u\n", 525 ((buf[ATMCI_MR / 4] & 0xff) << 1) 526 | ((buf[ATMCI_MR / 4] >> 16) & 1)); 527 else 528 seq_printf(s, "CLKDIV=%u\n", 529 (buf[ATMCI_MR / 4] & 0xff)); 530 seq_printf(s, "DTOR:\t0x%08x\n", buf[ATMCI_DTOR / 4]); 531 seq_printf(s, "SDCR:\t0x%08x\n", buf[ATMCI_SDCR / 4]); 532 seq_printf(s, "ARGR:\t0x%08x\n", buf[ATMCI_ARGR / 4]); 533 seq_printf(s, "BLKR:\t0x%08x BCNT=%u BLKLEN=%u\n", 534 buf[ATMCI_BLKR / 4], 535 buf[ATMCI_BLKR / 4] & 0xffff, 536 (buf[ATMCI_BLKR / 4] >> 16) & 0xffff); 537 if (host->caps.has_cstor_reg) 538 seq_printf(s, "CSTOR:\t0x%08x\n", buf[ATMCI_CSTOR / 4]); 539 540 /* Don't read RSPR and RDR; it will consume the data there */ 541 542 atmci_show_status_reg(s, "SR", buf[ATMCI_SR / 4]); 543 atmci_show_status_reg(s, "IMR", buf[ATMCI_IMR / 4]); 544 545 if (host->caps.has_dma_conf_reg) { 546 u32 val; 547 548 val = buf[ATMCI_DMA / 4]; 549 seq_printf(s, "DMA:\t0x%08x OFFSET=%u CHKSIZE=%u%s\n", 550 val, val & 3, 551 ((val >> 4) & 3) ? 552 1 << (((val >> 4) & 3) + 1) : 1, 553 val & ATMCI_DMAEN ? " DMAEN" : ""); 554 } 555 if (host->caps.has_cfg_reg) { 556 u32 val; 557 558 val = buf[ATMCI_CFG / 4]; 559 seq_printf(s, "CFG:\t0x%08x%s%s%s%s\n", 560 val, 561 val & ATMCI_CFG_FIFOMODE_1DATA ? " FIFOMODE_ONE_DATA" : "", 562 val & ATMCI_CFG_FERRCTRL_COR ? " FERRCTRL_CLEAR_ON_READ" : "", 563 val & ATMCI_CFG_HSMODE ? " HSMODE" : "", 564 val & ATMCI_CFG_LSYNC ? " LSYNC" : ""); 565 } 566 567 kfree(buf); 568 569 return ret; 570 } 571 572 DEFINE_SHOW_ATTRIBUTE(atmci_regs); 573 574 static void atmci_init_debugfs(struct atmel_mci_slot *slot) 575 { 576 struct mmc_host *mmc = slot->mmc; 577 struct atmel_mci *host = slot->host; 578 struct dentry *root; 579 struct dentry *node; 580 581 root = mmc->debugfs_root; 582 if (!root) 583 return; 584 585 node = debugfs_create_file("regs", S_IRUSR, root, host, 586 &atmci_regs_fops); 587 if (IS_ERR(node)) 588 return; 589 if (!node) 590 goto err; 591 592 node = debugfs_create_file("req", S_IRUSR, root, slot, 593 &atmci_req_fops); 594 if (!node) 595 goto err; 596 597 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state); 598 if (!node) 599 goto err; 600 601 node = debugfs_create_x32("pending_events", S_IRUSR, root, 602 (u32 *)&host->pending_events); 603 if (!node) 604 goto err; 605 606 node = debugfs_create_x32("completed_events", S_IRUSR, root, 607 (u32 *)&host->completed_events); 608 if (!node) 609 goto err; 610 611 return; 612 613 err: 614 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n"); 615 } 616 617 #if defined(CONFIG_OF) 618 static const struct of_device_id atmci_dt_ids[] = { 619 { .compatible = "atmel,hsmci" }, 620 { /* sentinel */ } 621 }; 622 623 MODULE_DEVICE_TABLE(of, atmci_dt_ids); 624 625 static struct mci_platform_data* 626 atmci_of_init(struct platform_device *pdev) 627 { 628 struct device_node *np = pdev->dev.of_node; 629 struct device_node *cnp; 630 struct mci_platform_data *pdata; 631 u32 slot_id; 632 633 if (!np) { 634 dev_err(&pdev->dev, "device node not found\n"); 635 return ERR_PTR(-EINVAL); 636 } 637 638 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 639 if (!pdata) 640 return ERR_PTR(-ENOMEM); 641 642 for_each_child_of_node(np, cnp) { 643 if (of_property_read_u32(cnp, "reg", &slot_id)) { 644 dev_warn(&pdev->dev, "reg property is missing for %pOF\n", 645 cnp); 646 continue; 647 } 648 649 if (slot_id >= ATMCI_MAX_NR_SLOTS) { 650 dev_warn(&pdev->dev, "can't have more than %d slots\n", 651 ATMCI_MAX_NR_SLOTS); 652 of_node_put(cnp); 653 break; 654 } 655 656 if (of_property_read_u32(cnp, "bus-width", 657 &pdata->slot[slot_id].bus_width)) 658 pdata->slot[slot_id].bus_width = 1; 659 660 pdata->slot[slot_id].detect_pin = 661 of_get_named_gpio(cnp, "cd-gpios", 0); 662 663 pdata->slot[slot_id].detect_is_active_high = 664 of_property_read_bool(cnp, "cd-inverted"); 665 666 pdata->slot[slot_id].non_removable = 667 of_property_read_bool(cnp, "non-removable"); 668 669 pdata->slot[slot_id].wp_pin = 670 of_get_named_gpio(cnp, "wp-gpios", 0); 671 } 672 673 return pdata; 674 } 675 #else /* CONFIG_OF */ 676 static inline struct mci_platform_data* 677 atmci_of_init(struct platform_device *dev) 678 { 679 return ERR_PTR(-EINVAL); 680 } 681 #endif 682 683 static inline unsigned int atmci_get_version(struct atmel_mci *host) 684 { 685 return atmci_readl(host, ATMCI_VERSION) & 0x00000fff; 686 } 687 688 /* 689 * Fix sconfig's burst size according to atmel MCI. We need to convert them as: 690 * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3. 691 * With version 0x600, we need to convert them as: 1 -> 0, 2 -> 1, 4 -> 2, 692 * 8 -> 3, 16 -> 4. 693 * 694 * This can be done by finding most significant bit set. 695 */ 696 static inline unsigned int atmci_convert_chksize(struct atmel_mci *host, 697 unsigned int maxburst) 698 { 699 unsigned int version = atmci_get_version(host); 700 unsigned int offset = 2; 701 702 if (version >= 0x600) 703 offset = 1; 704 705 if (maxburst > 1) 706 return fls(maxburst) - offset; 707 else 708 return 0; 709 } 710 711 static void atmci_timeout_timer(struct timer_list *t) 712 { 713 struct atmel_mci *host; 714 715 host = from_timer(host, t, timer); 716 717 dev_dbg(&host->pdev->dev, "software timeout\n"); 718 719 if (host->mrq->cmd->data) { 720 host->mrq->cmd->data->error = -ETIMEDOUT; 721 host->data = NULL; 722 /* 723 * With some SDIO modules, sometimes DMA transfer hangs. If 724 * stop_transfer() is not called then the DMA request is not 725 * removed, following ones are queued and never computed. 726 */ 727 if (host->state == STATE_DATA_XFER) 728 host->stop_transfer(host); 729 } else { 730 host->mrq->cmd->error = -ETIMEDOUT; 731 host->cmd = NULL; 732 } 733 host->need_reset = 1; 734 host->state = STATE_END_REQUEST; 735 smp_wmb(); 736 tasklet_schedule(&host->tasklet); 737 } 738 739 static inline unsigned int atmci_ns_to_clocks(struct atmel_mci *host, 740 unsigned int ns) 741 { 742 /* 743 * It is easier here to use us instead of ns for the timeout, 744 * it prevents from overflows during calculation. 745 */ 746 unsigned int us = DIV_ROUND_UP(ns, 1000); 747 748 /* Maximum clock frequency is host->bus_hz/2 */ 749 return us * (DIV_ROUND_UP(host->bus_hz, 2000000)); 750 } 751 752 static void atmci_set_timeout(struct atmel_mci *host, 753 struct atmel_mci_slot *slot, struct mmc_data *data) 754 { 755 static unsigned dtomul_to_shift[] = { 756 0, 4, 7, 8, 10, 12, 16, 20 757 }; 758 unsigned timeout; 759 unsigned dtocyc; 760 unsigned dtomul; 761 762 timeout = atmci_ns_to_clocks(host, data->timeout_ns) 763 + data->timeout_clks; 764 765 for (dtomul = 0; dtomul < 8; dtomul++) { 766 unsigned shift = dtomul_to_shift[dtomul]; 767 dtocyc = (timeout + (1 << shift) - 1) >> shift; 768 if (dtocyc < 15) 769 break; 770 } 771 772 if (dtomul >= 8) { 773 dtomul = 7; 774 dtocyc = 15; 775 } 776 777 dev_vdbg(&slot->mmc->class_dev, "setting timeout to %u cycles\n", 778 dtocyc << dtomul_to_shift[dtomul]); 779 atmci_writel(host, ATMCI_DTOR, (ATMCI_DTOMUL(dtomul) | ATMCI_DTOCYC(dtocyc))); 780 } 781 782 /* 783 * Return mask with command flags to be enabled for this command. 784 */ 785 static u32 atmci_prepare_command(struct mmc_host *mmc, 786 struct mmc_command *cmd) 787 { 788 struct mmc_data *data; 789 u32 cmdr; 790 791 cmd->error = -EINPROGRESS; 792 793 cmdr = ATMCI_CMDR_CMDNB(cmd->opcode); 794 795 if (cmd->flags & MMC_RSP_PRESENT) { 796 if (cmd->flags & MMC_RSP_136) 797 cmdr |= ATMCI_CMDR_RSPTYP_136BIT; 798 else 799 cmdr |= ATMCI_CMDR_RSPTYP_48BIT; 800 } 801 802 /* 803 * This should really be MAXLAT_5 for CMD2 and ACMD41, but 804 * it's too difficult to determine whether this is an ACMD or 805 * not. Better make it 64. 806 */ 807 cmdr |= ATMCI_CMDR_MAXLAT_64CYC; 808 809 if (mmc->ios.bus_mode == MMC_BUSMODE_OPENDRAIN) 810 cmdr |= ATMCI_CMDR_OPDCMD; 811 812 data = cmd->data; 813 if (data) { 814 cmdr |= ATMCI_CMDR_START_XFER; 815 816 if (cmd->opcode == SD_IO_RW_EXTENDED) { 817 cmdr |= ATMCI_CMDR_SDIO_BLOCK; 818 } else { 819 if (data->blocks > 1) 820 cmdr |= ATMCI_CMDR_MULTI_BLOCK; 821 else 822 cmdr |= ATMCI_CMDR_BLOCK; 823 } 824 825 if (data->flags & MMC_DATA_READ) 826 cmdr |= ATMCI_CMDR_TRDIR_READ; 827 } 828 829 return cmdr; 830 } 831 832 static void atmci_send_command(struct atmel_mci *host, 833 struct mmc_command *cmd, u32 cmd_flags) 834 { 835 WARN_ON(host->cmd); 836 host->cmd = cmd; 837 838 dev_vdbg(&host->pdev->dev, 839 "start command: ARGR=0x%08x CMDR=0x%08x\n", 840 cmd->arg, cmd_flags); 841 842 atmci_writel(host, ATMCI_ARGR, cmd->arg); 843 atmci_writel(host, ATMCI_CMDR, cmd_flags); 844 } 845 846 static void atmci_send_stop_cmd(struct atmel_mci *host, struct mmc_data *data) 847 { 848 dev_dbg(&host->pdev->dev, "send stop command\n"); 849 atmci_send_command(host, data->stop, host->stop_cmdr); 850 atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY); 851 } 852 853 /* 854 * Configure given PDC buffer taking care of alignement issues. 855 * Update host->data_size and host->sg. 856 */ 857 static void atmci_pdc_set_single_buf(struct atmel_mci *host, 858 enum atmci_xfer_dir dir, enum atmci_pdc_buf buf_nb) 859 { 860 u32 pointer_reg, counter_reg; 861 unsigned int buf_size; 862 863 if (dir == XFER_RECEIVE) { 864 pointer_reg = ATMEL_PDC_RPR; 865 counter_reg = ATMEL_PDC_RCR; 866 } else { 867 pointer_reg = ATMEL_PDC_TPR; 868 counter_reg = ATMEL_PDC_TCR; 869 } 870 871 if (buf_nb == PDC_SECOND_BUF) { 872 pointer_reg += ATMEL_PDC_SCND_BUF_OFF; 873 counter_reg += ATMEL_PDC_SCND_BUF_OFF; 874 } 875 876 if (!host->caps.has_rwproof) { 877 buf_size = host->buf_size; 878 atmci_writel(host, pointer_reg, host->buf_phys_addr); 879 } else { 880 buf_size = sg_dma_len(host->sg); 881 atmci_writel(host, pointer_reg, sg_dma_address(host->sg)); 882 } 883 884 if (host->data_size <= buf_size) { 885 if (host->data_size & 0x3) { 886 /* If size is different from modulo 4, transfer bytes */ 887 atmci_writel(host, counter_reg, host->data_size); 888 atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCFBYTE); 889 } else { 890 /* Else transfer 32-bits words */ 891 atmci_writel(host, counter_reg, host->data_size / 4); 892 } 893 host->data_size = 0; 894 } else { 895 /* We assume the size of a page is 32-bits aligned */ 896 atmci_writel(host, counter_reg, sg_dma_len(host->sg) / 4); 897 host->data_size -= sg_dma_len(host->sg); 898 if (host->data_size) 899 host->sg = sg_next(host->sg); 900 } 901 } 902 903 /* 904 * Configure PDC buffer according to the data size ie configuring one or two 905 * buffers. Don't use this function if you want to configure only the second 906 * buffer. In this case, use atmci_pdc_set_single_buf. 907 */ 908 static void atmci_pdc_set_both_buf(struct atmel_mci *host, int dir) 909 { 910 atmci_pdc_set_single_buf(host, dir, PDC_FIRST_BUF); 911 if (host->data_size) 912 atmci_pdc_set_single_buf(host, dir, PDC_SECOND_BUF); 913 } 914 915 /* 916 * Unmap sg lists, called when transfer is finished. 917 */ 918 static void atmci_pdc_cleanup(struct atmel_mci *host) 919 { 920 struct mmc_data *data = host->data; 921 922 if (data) 923 dma_unmap_sg(&host->pdev->dev, 924 data->sg, data->sg_len, 925 mmc_get_dma_dir(data)); 926 } 927 928 /* 929 * Disable PDC transfers. Update pending flags to EVENT_XFER_COMPLETE after 930 * having received ATMCI_TXBUFE or ATMCI_RXBUFF interrupt. Enable ATMCI_NOTBUSY 931 * interrupt needed for both transfer directions. 932 */ 933 static void atmci_pdc_complete(struct atmel_mci *host) 934 { 935 int transfer_size = host->data->blocks * host->data->blksz; 936 int i; 937 938 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS); 939 940 if ((!host->caps.has_rwproof) 941 && (host->data->flags & MMC_DATA_READ)) { 942 if (host->caps.has_bad_data_ordering) 943 for (i = 0; i < transfer_size; i++) 944 host->buffer[i] = swab32(host->buffer[i]); 945 sg_copy_from_buffer(host->data->sg, host->data->sg_len, 946 host->buffer, transfer_size); 947 } 948 949 atmci_pdc_cleanup(host); 950 951 dev_dbg(&host->pdev->dev, "(%s) set pending xfer complete\n", __func__); 952 atmci_set_pending(host, EVENT_XFER_COMPLETE); 953 tasklet_schedule(&host->tasklet); 954 } 955 956 static void atmci_dma_cleanup(struct atmel_mci *host) 957 { 958 struct mmc_data *data = host->data; 959 960 if (data) 961 dma_unmap_sg(host->dma.chan->device->dev, 962 data->sg, data->sg_len, 963 mmc_get_dma_dir(data)); 964 } 965 966 /* 967 * This function is called by the DMA driver from tasklet context. 968 */ 969 static void atmci_dma_complete(void *arg) 970 { 971 struct atmel_mci *host = arg; 972 struct mmc_data *data = host->data; 973 974 dev_vdbg(&host->pdev->dev, "DMA complete\n"); 975 976 if (host->caps.has_dma_conf_reg) 977 /* Disable DMA hardware handshaking on MCI */ 978 atmci_writel(host, ATMCI_DMA, atmci_readl(host, ATMCI_DMA) & ~ATMCI_DMAEN); 979 980 atmci_dma_cleanup(host); 981 982 /* 983 * If the card was removed, data will be NULL. No point trying 984 * to send the stop command or waiting for NBUSY in this case. 985 */ 986 if (data) { 987 dev_dbg(&host->pdev->dev, 988 "(%s) set pending xfer complete\n", __func__); 989 atmci_set_pending(host, EVENT_XFER_COMPLETE); 990 tasklet_schedule(&host->tasklet); 991 992 /* 993 * Regardless of what the documentation says, we have 994 * to wait for NOTBUSY even after block read 995 * operations. 996 * 997 * When the DMA transfer is complete, the controller 998 * may still be reading the CRC from the card, i.e. 999 * the data transfer is still in progress and we 1000 * haven't seen all the potential error bits yet. 1001 * 1002 * The interrupt handler will schedule a different 1003 * tasklet to finish things up when the data transfer 1004 * is completely done. 1005 * 1006 * We may not complete the mmc request here anyway 1007 * because the mmc layer may call back and cause us to 1008 * violate the "don't submit new operations from the 1009 * completion callback" rule of the dma engine 1010 * framework. 1011 */ 1012 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); 1013 } 1014 } 1015 1016 /* 1017 * Returns a mask of interrupt flags to be enabled after the whole 1018 * request has been prepared. 1019 */ 1020 static u32 atmci_prepare_data(struct atmel_mci *host, struct mmc_data *data) 1021 { 1022 u32 iflags; 1023 1024 data->error = -EINPROGRESS; 1025 1026 host->sg = data->sg; 1027 host->sg_len = data->sg_len; 1028 host->data = data; 1029 host->data_chan = NULL; 1030 1031 iflags = ATMCI_DATA_ERROR_FLAGS; 1032 1033 /* 1034 * Errata: MMC data write operation with less than 12 1035 * bytes is impossible. 1036 * 1037 * Errata: MCI Transmit Data Register (TDR) FIFO 1038 * corruption when length is not multiple of 4. 1039 */ 1040 if (data->blocks * data->blksz < 12 1041 || (data->blocks * data->blksz) & 3) 1042 host->need_reset = true; 1043 1044 host->pio_offset = 0; 1045 if (data->flags & MMC_DATA_READ) 1046 iflags |= ATMCI_RXRDY; 1047 else 1048 iflags |= ATMCI_TXRDY; 1049 1050 return iflags; 1051 } 1052 1053 /* 1054 * Set interrupt flags and set block length into the MCI mode register even 1055 * if this value is also accessible in the MCI block register. It seems to be 1056 * necessary before the High Speed MCI version. It also map sg and configure 1057 * PDC registers. 1058 */ 1059 static u32 1060 atmci_prepare_data_pdc(struct atmel_mci *host, struct mmc_data *data) 1061 { 1062 u32 iflags, tmp; 1063 int i; 1064 1065 data->error = -EINPROGRESS; 1066 1067 host->data = data; 1068 host->sg = data->sg; 1069 iflags = ATMCI_DATA_ERROR_FLAGS; 1070 1071 /* Enable pdc mode */ 1072 atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCMODE); 1073 1074 if (data->flags & MMC_DATA_READ) 1075 iflags |= ATMCI_ENDRX | ATMCI_RXBUFF; 1076 else 1077 iflags |= ATMCI_ENDTX | ATMCI_TXBUFE | ATMCI_BLKE; 1078 1079 /* Set BLKLEN */ 1080 tmp = atmci_readl(host, ATMCI_MR); 1081 tmp &= 0x0000ffff; 1082 tmp |= ATMCI_BLKLEN(data->blksz); 1083 atmci_writel(host, ATMCI_MR, tmp); 1084 1085 /* Configure PDC */ 1086 host->data_size = data->blocks * data->blksz; 1087 dma_map_sg(&host->pdev->dev, data->sg, data->sg_len, 1088 mmc_get_dma_dir(data)); 1089 1090 if ((!host->caps.has_rwproof) 1091 && (host->data->flags & MMC_DATA_WRITE)) { 1092 sg_copy_to_buffer(host->data->sg, host->data->sg_len, 1093 host->buffer, host->data_size); 1094 if (host->caps.has_bad_data_ordering) 1095 for (i = 0; i < host->data_size; i++) 1096 host->buffer[i] = swab32(host->buffer[i]); 1097 } 1098 1099 if (host->data_size) 1100 atmci_pdc_set_both_buf(host, data->flags & MMC_DATA_READ ? 1101 XFER_RECEIVE : XFER_TRANSMIT); 1102 return iflags; 1103 } 1104 1105 static u32 1106 atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data) 1107 { 1108 struct dma_chan *chan; 1109 struct dma_async_tx_descriptor *desc; 1110 struct scatterlist *sg; 1111 unsigned int i; 1112 enum dma_transfer_direction slave_dirn; 1113 unsigned int sglen; 1114 u32 maxburst; 1115 u32 iflags; 1116 1117 data->error = -EINPROGRESS; 1118 1119 WARN_ON(host->data); 1120 host->sg = NULL; 1121 host->data = data; 1122 1123 iflags = ATMCI_DATA_ERROR_FLAGS; 1124 1125 /* 1126 * We don't do DMA on "complex" transfers, i.e. with 1127 * non-word-aligned buffers or lengths. Also, we don't bother 1128 * with all the DMA setup overhead for short transfers. 1129 */ 1130 if (data->blocks * data->blksz < ATMCI_DMA_THRESHOLD) 1131 return atmci_prepare_data(host, data); 1132 if (data->blksz & 3) 1133 return atmci_prepare_data(host, data); 1134 1135 for_each_sg(data->sg, sg, data->sg_len, i) { 1136 if (sg->offset & 3 || sg->length & 3) 1137 return atmci_prepare_data(host, data); 1138 } 1139 1140 /* If we don't have a channel, we can't do DMA */ 1141 chan = host->dma.chan; 1142 if (chan) 1143 host->data_chan = chan; 1144 1145 if (!chan) 1146 return -ENODEV; 1147 1148 if (data->flags & MMC_DATA_READ) { 1149 host->dma_conf.direction = slave_dirn = DMA_DEV_TO_MEM; 1150 maxburst = atmci_convert_chksize(host, 1151 host->dma_conf.src_maxburst); 1152 } else { 1153 host->dma_conf.direction = slave_dirn = DMA_MEM_TO_DEV; 1154 maxburst = atmci_convert_chksize(host, 1155 host->dma_conf.dst_maxburst); 1156 } 1157 1158 if (host->caps.has_dma_conf_reg) 1159 atmci_writel(host, ATMCI_DMA, ATMCI_DMA_CHKSIZE(maxburst) | 1160 ATMCI_DMAEN); 1161 1162 sglen = dma_map_sg(chan->device->dev, data->sg, 1163 data->sg_len, mmc_get_dma_dir(data)); 1164 1165 dmaengine_slave_config(chan, &host->dma_conf); 1166 desc = dmaengine_prep_slave_sg(chan, 1167 data->sg, sglen, slave_dirn, 1168 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1169 if (!desc) 1170 goto unmap_exit; 1171 1172 host->dma.data_desc = desc; 1173 desc->callback = atmci_dma_complete; 1174 desc->callback_param = host; 1175 1176 return iflags; 1177 unmap_exit: 1178 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, 1179 mmc_get_dma_dir(data)); 1180 return -ENOMEM; 1181 } 1182 1183 static void 1184 atmci_submit_data(struct atmel_mci *host, struct mmc_data *data) 1185 { 1186 return; 1187 } 1188 1189 /* 1190 * Start PDC according to transfer direction. 1191 */ 1192 static void 1193 atmci_submit_data_pdc(struct atmel_mci *host, struct mmc_data *data) 1194 { 1195 if (data->flags & MMC_DATA_READ) 1196 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN); 1197 else 1198 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN); 1199 } 1200 1201 static void 1202 atmci_submit_data_dma(struct atmel_mci *host, struct mmc_data *data) 1203 { 1204 struct dma_chan *chan = host->data_chan; 1205 struct dma_async_tx_descriptor *desc = host->dma.data_desc; 1206 1207 if (chan) { 1208 dmaengine_submit(desc); 1209 dma_async_issue_pending(chan); 1210 } 1211 } 1212 1213 static void atmci_stop_transfer(struct atmel_mci *host) 1214 { 1215 dev_dbg(&host->pdev->dev, 1216 "(%s) set pending xfer complete\n", __func__); 1217 atmci_set_pending(host, EVENT_XFER_COMPLETE); 1218 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); 1219 } 1220 1221 /* 1222 * Stop data transfer because error(s) occurred. 1223 */ 1224 static void atmci_stop_transfer_pdc(struct atmel_mci *host) 1225 { 1226 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS); 1227 } 1228 1229 static void atmci_stop_transfer_dma(struct atmel_mci *host) 1230 { 1231 struct dma_chan *chan = host->data_chan; 1232 1233 if (chan) { 1234 dmaengine_terminate_all(chan); 1235 atmci_dma_cleanup(host); 1236 } else { 1237 /* Data transfer was stopped by the interrupt handler */ 1238 dev_dbg(&host->pdev->dev, 1239 "(%s) set pending xfer complete\n", __func__); 1240 atmci_set_pending(host, EVENT_XFER_COMPLETE); 1241 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); 1242 } 1243 } 1244 1245 /* 1246 * Start a request: prepare data if needed, prepare the command and activate 1247 * interrupts. 1248 */ 1249 static void atmci_start_request(struct atmel_mci *host, 1250 struct atmel_mci_slot *slot) 1251 { 1252 struct mmc_request *mrq; 1253 struct mmc_command *cmd; 1254 struct mmc_data *data; 1255 u32 iflags; 1256 u32 cmdflags; 1257 1258 mrq = slot->mrq; 1259 host->cur_slot = slot; 1260 host->mrq = mrq; 1261 1262 host->pending_events = 0; 1263 host->completed_events = 0; 1264 host->cmd_status = 0; 1265 host->data_status = 0; 1266 1267 dev_dbg(&host->pdev->dev, "start request: cmd %u\n", mrq->cmd->opcode); 1268 1269 if (host->need_reset || host->caps.need_reset_after_xfer) { 1270 iflags = atmci_readl(host, ATMCI_IMR); 1271 iflags &= (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB); 1272 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST); 1273 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN); 1274 atmci_writel(host, ATMCI_MR, host->mode_reg); 1275 if (host->caps.has_cfg_reg) 1276 atmci_writel(host, ATMCI_CFG, host->cfg_reg); 1277 atmci_writel(host, ATMCI_IER, iflags); 1278 host->need_reset = false; 1279 } 1280 atmci_writel(host, ATMCI_SDCR, slot->sdc_reg); 1281 1282 iflags = atmci_readl(host, ATMCI_IMR); 1283 if (iflags & ~(ATMCI_SDIOIRQA | ATMCI_SDIOIRQB)) 1284 dev_dbg(&slot->mmc->class_dev, "WARNING: IMR=0x%08x\n", 1285 iflags); 1286 1287 if (unlikely(test_and_clear_bit(ATMCI_CARD_NEED_INIT, &slot->flags))) { 1288 /* Send init sequence (74 clock cycles) */ 1289 atmci_writel(host, ATMCI_CMDR, ATMCI_CMDR_SPCMD_INIT); 1290 while (!(atmci_readl(host, ATMCI_SR) & ATMCI_CMDRDY)) 1291 cpu_relax(); 1292 } 1293 iflags = 0; 1294 data = mrq->data; 1295 if (data) { 1296 atmci_set_timeout(host, slot, data); 1297 1298 /* Must set block count/size before sending command */ 1299 atmci_writel(host, ATMCI_BLKR, ATMCI_BCNT(data->blocks) 1300 | ATMCI_BLKLEN(data->blksz)); 1301 dev_vdbg(&slot->mmc->class_dev, "BLKR=0x%08x\n", 1302 ATMCI_BCNT(data->blocks) | ATMCI_BLKLEN(data->blksz)); 1303 1304 iflags |= host->prepare_data(host, data); 1305 } 1306 1307 iflags |= ATMCI_CMDRDY; 1308 cmd = mrq->cmd; 1309 cmdflags = atmci_prepare_command(slot->mmc, cmd); 1310 1311 /* 1312 * DMA transfer should be started before sending the command to avoid 1313 * unexpected errors especially for read operations in SDIO mode. 1314 * Unfortunately, in PDC mode, command has to be sent before starting 1315 * the transfer. 1316 */ 1317 if (host->submit_data != &atmci_submit_data_dma) 1318 atmci_send_command(host, cmd, cmdflags); 1319 1320 if (data) 1321 host->submit_data(host, data); 1322 1323 if (host->submit_data == &atmci_submit_data_dma) 1324 atmci_send_command(host, cmd, cmdflags); 1325 1326 if (mrq->stop) { 1327 host->stop_cmdr = atmci_prepare_command(slot->mmc, mrq->stop); 1328 host->stop_cmdr |= ATMCI_CMDR_STOP_XFER; 1329 if (!(data->flags & MMC_DATA_WRITE)) 1330 host->stop_cmdr |= ATMCI_CMDR_TRDIR_READ; 1331 host->stop_cmdr |= ATMCI_CMDR_MULTI_BLOCK; 1332 } 1333 1334 /* 1335 * We could have enabled interrupts earlier, but I suspect 1336 * that would open up a nice can of interesting race 1337 * conditions (e.g. command and data complete, but stop not 1338 * prepared yet.) 1339 */ 1340 atmci_writel(host, ATMCI_IER, iflags); 1341 1342 mod_timer(&host->timer, jiffies + msecs_to_jiffies(2000)); 1343 } 1344 1345 static void atmci_queue_request(struct atmel_mci *host, 1346 struct atmel_mci_slot *slot, struct mmc_request *mrq) 1347 { 1348 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n", 1349 host->state); 1350 1351 spin_lock_bh(&host->lock); 1352 slot->mrq = mrq; 1353 if (host->state == STATE_IDLE) { 1354 host->state = STATE_SENDING_CMD; 1355 atmci_start_request(host, slot); 1356 } else { 1357 dev_dbg(&host->pdev->dev, "queue request\n"); 1358 list_add_tail(&slot->queue_node, &host->queue); 1359 } 1360 spin_unlock_bh(&host->lock); 1361 } 1362 1363 static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1364 { 1365 struct atmel_mci_slot *slot = mmc_priv(mmc); 1366 struct atmel_mci *host = slot->host; 1367 struct mmc_data *data; 1368 1369 WARN_ON(slot->mrq); 1370 dev_dbg(&host->pdev->dev, "MRQ: cmd %u\n", mrq->cmd->opcode); 1371 1372 /* 1373 * We may "know" the card is gone even though there's still an 1374 * electrical connection. If so, we really need to communicate 1375 * this to the MMC core since there won't be any more 1376 * interrupts as the card is completely removed. Otherwise, 1377 * the MMC core might believe the card is still there even 1378 * though the card was just removed very slowly. 1379 */ 1380 if (!test_bit(ATMCI_CARD_PRESENT, &slot->flags)) { 1381 mrq->cmd->error = -ENOMEDIUM; 1382 mmc_request_done(mmc, mrq); 1383 return; 1384 } 1385 1386 /* We don't support multiple blocks of weird lengths. */ 1387 data = mrq->data; 1388 if (data && data->blocks > 1 && data->blksz & 3) { 1389 mrq->cmd->error = -EINVAL; 1390 mmc_request_done(mmc, mrq); 1391 } 1392 1393 atmci_queue_request(host, slot, mrq); 1394 } 1395 1396 static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1397 { 1398 struct atmel_mci_slot *slot = mmc_priv(mmc); 1399 struct atmel_mci *host = slot->host; 1400 unsigned int i; 1401 1402 slot->sdc_reg &= ~ATMCI_SDCBUS_MASK; 1403 switch (ios->bus_width) { 1404 case MMC_BUS_WIDTH_1: 1405 slot->sdc_reg |= ATMCI_SDCBUS_1BIT; 1406 break; 1407 case MMC_BUS_WIDTH_4: 1408 slot->sdc_reg |= ATMCI_SDCBUS_4BIT; 1409 break; 1410 case MMC_BUS_WIDTH_8: 1411 slot->sdc_reg |= ATMCI_SDCBUS_8BIT; 1412 break; 1413 } 1414 1415 if (ios->clock) { 1416 unsigned int clock_min = ~0U; 1417 int clkdiv; 1418 1419 spin_lock_bh(&host->lock); 1420 if (!host->mode_reg) { 1421 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST); 1422 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN); 1423 if (host->caps.has_cfg_reg) 1424 atmci_writel(host, ATMCI_CFG, host->cfg_reg); 1425 } 1426 1427 /* 1428 * Use mirror of ios->clock to prevent race with mmc 1429 * core ios update when finding the minimum. 1430 */ 1431 slot->clock = ios->clock; 1432 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) { 1433 if (host->slot[i] && host->slot[i]->clock 1434 && host->slot[i]->clock < clock_min) 1435 clock_min = host->slot[i]->clock; 1436 } 1437 1438 /* Calculate clock divider */ 1439 if (host->caps.has_odd_clk_div) { 1440 clkdiv = DIV_ROUND_UP(host->bus_hz, clock_min) - 2; 1441 if (clkdiv < 0) { 1442 dev_warn(&mmc->class_dev, 1443 "clock %u too fast; using %lu\n", 1444 clock_min, host->bus_hz / 2); 1445 clkdiv = 0; 1446 } else if (clkdiv > 511) { 1447 dev_warn(&mmc->class_dev, 1448 "clock %u too slow; using %lu\n", 1449 clock_min, host->bus_hz / (511 + 2)); 1450 clkdiv = 511; 1451 } 1452 host->mode_reg = ATMCI_MR_CLKDIV(clkdiv >> 1) 1453 | ATMCI_MR_CLKODD(clkdiv & 1); 1454 } else { 1455 clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * clock_min) - 1; 1456 if (clkdiv > 255) { 1457 dev_warn(&mmc->class_dev, 1458 "clock %u too slow; using %lu\n", 1459 clock_min, host->bus_hz / (2 * 256)); 1460 clkdiv = 255; 1461 } 1462 host->mode_reg = ATMCI_MR_CLKDIV(clkdiv); 1463 } 1464 1465 /* 1466 * WRPROOF and RDPROOF prevent overruns/underruns by 1467 * stopping the clock when the FIFO is full/empty. 1468 * This state is not expected to last for long. 1469 */ 1470 if (host->caps.has_rwproof) 1471 host->mode_reg |= (ATMCI_MR_WRPROOF | ATMCI_MR_RDPROOF); 1472 1473 if (host->caps.has_cfg_reg) { 1474 /* setup High Speed mode in relation with card capacity */ 1475 if (ios->timing == MMC_TIMING_SD_HS) 1476 host->cfg_reg |= ATMCI_CFG_HSMODE; 1477 else 1478 host->cfg_reg &= ~ATMCI_CFG_HSMODE; 1479 } 1480 1481 if (list_empty(&host->queue)) { 1482 atmci_writel(host, ATMCI_MR, host->mode_reg); 1483 if (host->caps.has_cfg_reg) 1484 atmci_writel(host, ATMCI_CFG, host->cfg_reg); 1485 } else { 1486 host->need_clock_update = true; 1487 } 1488 1489 spin_unlock_bh(&host->lock); 1490 } else { 1491 bool any_slot_active = false; 1492 1493 spin_lock_bh(&host->lock); 1494 slot->clock = 0; 1495 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) { 1496 if (host->slot[i] && host->slot[i]->clock) { 1497 any_slot_active = true; 1498 break; 1499 } 1500 } 1501 if (!any_slot_active) { 1502 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS); 1503 if (host->mode_reg) { 1504 atmci_readl(host, ATMCI_MR); 1505 } 1506 host->mode_reg = 0; 1507 } 1508 spin_unlock_bh(&host->lock); 1509 } 1510 1511 switch (ios->power_mode) { 1512 case MMC_POWER_OFF: 1513 if (!IS_ERR(mmc->supply.vmmc)) 1514 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1515 break; 1516 case MMC_POWER_UP: 1517 set_bit(ATMCI_CARD_NEED_INIT, &slot->flags); 1518 if (!IS_ERR(mmc->supply.vmmc)) 1519 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 1520 break; 1521 default: 1522 break; 1523 } 1524 } 1525 1526 static int atmci_get_ro(struct mmc_host *mmc) 1527 { 1528 int read_only = -ENOSYS; 1529 struct atmel_mci_slot *slot = mmc_priv(mmc); 1530 1531 if (gpio_is_valid(slot->wp_pin)) { 1532 read_only = gpio_get_value(slot->wp_pin); 1533 dev_dbg(&mmc->class_dev, "card is %s\n", 1534 read_only ? "read-only" : "read-write"); 1535 } 1536 1537 return read_only; 1538 } 1539 1540 static int atmci_get_cd(struct mmc_host *mmc) 1541 { 1542 int present = -ENOSYS; 1543 struct atmel_mci_slot *slot = mmc_priv(mmc); 1544 1545 if (gpio_is_valid(slot->detect_pin)) { 1546 present = !(gpio_get_value(slot->detect_pin) ^ 1547 slot->detect_is_active_high); 1548 dev_dbg(&mmc->class_dev, "card is %spresent\n", 1549 present ? "" : "not "); 1550 } 1551 1552 return present; 1553 } 1554 1555 static void atmci_enable_sdio_irq(struct mmc_host *mmc, int enable) 1556 { 1557 struct atmel_mci_slot *slot = mmc_priv(mmc); 1558 struct atmel_mci *host = slot->host; 1559 1560 if (enable) 1561 atmci_writel(host, ATMCI_IER, slot->sdio_irq); 1562 else 1563 atmci_writel(host, ATMCI_IDR, slot->sdio_irq); 1564 } 1565 1566 static const struct mmc_host_ops atmci_ops = { 1567 .request = atmci_request, 1568 .set_ios = atmci_set_ios, 1569 .get_ro = atmci_get_ro, 1570 .get_cd = atmci_get_cd, 1571 .enable_sdio_irq = atmci_enable_sdio_irq, 1572 }; 1573 1574 /* Called with host->lock held */ 1575 static void atmci_request_end(struct atmel_mci *host, struct mmc_request *mrq) 1576 __releases(&host->lock) 1577 __acquires(&host->lock) 1578 { 1579 struct atmel_mci_slot *slot = NULL; 1580 struct mmc_host *prev_mmc = host->cur_slot->mmc; 1581 1582 WARN_ON(host->cmd || host->data); 1583 1584 /* 1585 * Update the MMC clock rate if necessary. This may be 1586 * necessary if set_ios() is called when a different slot is 1587 * busy transferring data. 1588 */ 1589 if (host->need_clock_update) { 1590 atmci_writel(host, ATMCI_MR, host->mode_reg); 1591 if (host->caps.has_cfg_reg) 1592 atmci_writel(host, ATMCI_CFG, host->cfg_reg); 1593 } 1594 1595 host->cur_slot->mrq = NULL; 1596 host->mrq = NULL; 1597 if (!list_empty(&host->queue)) { 1598 slot = list_entry(host->queue.next, 1599 struct atmel_mci_slot, queue_node); 1600 list_del(&slot->queue_node); 1601 dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n", 1602 mmc_hostname(slot->mmc)); 1603 host->state = STATE_SENDING_CMD; 1604 atmci_start_request(host, slot); 1605 } else { 1606 dev_vdbg(&host->pdev->dev, "list empty\n"); 1607 host->state = STATE_IDLE; 1608 } 1609 1610 del_timer(&host->timer); 1611 1612 spin_unlock(&host->lock); 1613 mmc_request_done(prev_mmc, mrq); 1614 spin_lock(&host->lock); 1615 } 1616 1617 static void atmci_command_complete(struct atmel_mci *host, 1618 struct mmc_command *cmd) 1619 { 1620 u32 status = host->cmd_status; 1621 1622 /* Read the response from the card (up to 16 bytes) */ 1623 cmd->resp[0] = atmci_readl(host, ATMCI_RSPR); 1624 cmd->resp[1] = atmci_readl(host, ATMCI_RSPR); 1625 cmd->resp[2] = atmci_readl(host, ATMCI_RSPR); 1626 cmd->resp[3] = atmci_readl(host, ATMCI_RSPR); 1627 1628 if (status & ATMCI_RTOE) 1629 cmd->error = -ETIMEDOUT; 1630 else if ((cmd->flags & MMC_RSP_CRC) && (status & ATMCI_RCRCE)) 1631 cmd->error = -EILSEQ; 1632 else if (status & (ATMCI_RINDE | ATMCI_RDIRE | ATMCI_RENDE)) 1633 cmd->error = -EIO; 1634 else if (host->mrq->data && (host->mrq->data->blksz & 3)) { 1635 if (host->caps.need_blksz_mul_4) { 1636 cmd->error = -EINVAL; 1637 host->need_reset = 1; 1638 } 1639 } else 1640 cmd->error = 0; 1641 } 1642 1643 static void atmci_detect_change(struct timer_list *t) 1644 { 1645 struct atmel_mci_slot *slot = from_timer(slot, t, detect_timer); 1646 bool present; 1647 bool present_old; 1648 1649 /* 1650 * atmci_cleanup_slot() sets the ATMCI_SHUTDOWN flag before 1651 * freeing the interrupt. We must not re-enable the interrupt 1652 * if it has been freed, and if we're shutting down, it 1653 * doesn't really matter whether the card is present or not. 1654 */ 1655 smp_rmb(); 1656 if (test_bit(ATMCI_SHUTDOWN, &slot->flags)) 1657 return; 1658 1659 enable_irq(gpio_to_irq(slot->detect_pin)); 1660 present = !(gpio_get_value(slot->detect_pin) ^ 1661 slot->detect_is_active_high); 1662 present_old = test_bit(ATMCI_CARD_PRESENT, &slot->flags); 1663 1664 dev_vdbg(&slot->mmc->class_dev, "detect change: %d (was %d)\n", 1665 present, present_old); 1666 1667 if (present != present_old) { 1668 struct atmel_mci *host = slot->host; 1669 struct mmc_request *mrq; 1670 1671 dev_dbg(&slot->mmc->class_dev, "card %s\n", 1672 present ? "inserted" : "removed"); 1673 1674 spin_lock(&host->lock); 1675 1676 if (!present) 1677 clear_bit(ATMCI_CARD_PRESENT, &slot->flags); 1678 else 1679 set_bit(ATMCI_CARD_PRESENT, &slot->flags); 1680 1681 /* Clean up queue if present */ 1682 mrq = slot->mrq; 1683 if (mrq) { 1684 if (mrq == host->mrq) { 1685 /* 1686 * Reset controller to terminate any ongoing 1687 * commands or data transfers. 1688 */ 1689 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST); 1690 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN); 1691 atmci_writel(host, ATMCI_MR, host->mode_reg); 1692 if (host->caps.has_cfg_reg) 1693 atmci_writel(host, ATMCI_CFG, host->cfg_reg); 1694 1695 host->data = NULL; 1696 host->cmd = NULL; 1697 1698 switch (host->state) { 1699 case STATE_IDLE: 1700 break; 1701 case STATE_SENDING_CMD: 1702 mrq->cmd->error = -ENOMEDIUM; 1703 if (mrq->data) 1704 host->stop_transfer(host); 1705 break; 1706 case STATE_DATA_XFER: 1707 mrq->data->error = -ENOMEDIUM; 1708 host->stop_transfer(host); 1709 break; 1710 case STATE_WAITING_NOTBUSY: 1711 mrq->data->error = -ENOMEDIUM; 1712 break; 1713 case STATE_SENDING_STOP: 1714 mrq->stop->error = -ENOMEDIUM; 1715 break; 1716 case STATE_END_REQUEST: 1717 break; 1718 } 1719 1720 atmci_request_end(host, mrq); 1721 } else { 1722 list_del(&slot->queue_node); 1723 mrq->cmd->error = -ENOMEDIUM; 1724 if (mrq->data) 1725 mrq->data->error = -ENOMEDIUM; 1726 if (mrq->stop) 1727 mrq->stop->error = -ENOMEDIUM; 1728 1729 spin_unlock(&host->lock); 1730 mmc_request_done(slot->mmc, mrq); 1731 spin_lock(&host->lock); 1732 } 1733 } 1734 spin_unlock(&host->lock); 1735 1736 mmc_detect_change(slot->mmc, 0); 1737 } 1738 } 1739 1740 static void atmci_tasklet_func(unsigned long priv) 1741 { 1742 struct atmel_mci *host = (struct atmel_mci *)priv; 1743 struct mmc_request *mrq = host->mrq; 1744 struct mmc_data *data = host->data; 1745 enum atmel_mci_state state = host->state; 1746 enum atmel_mci_state prev_state; 1747 u32 status; 1748 1749 spin_lock(&host->lock); 1750 1751 state = host->state; 1752 1753 dev_vdbg(&host->pdev->dev, 1754 "tasklet: state %u pending/completed/mask %lx/%lx/%x\n", 1755 state, host->pending_events, host->completed_events, 1756 atmci_readl(host, ATMCI_IMR)); 1757 1758 do { 1759 prev_state = state; 1760 dev_dbg(&host->pdev->dev, "FSM: state=%d\n", state); 1761 1762 switch (state) { 1763 case STATE_IDLE: 1764 break; 1765 1766 case STATE_SENDING_CMD: 1767 /* 1768 * Command has been sent, we are waiting for command 1769 * ready. Then we have three next states possible: 1770 * END_REQUEST by default, WAITING_NOTBUSY if it's a 1771 * command needing it or DATA_XFER if there is data. 1772 */ 1773 dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n"); 1774 if (!atmci_test_and_clear_pending(host, 1775 EVENT_CMD_RDY)) 1776 break; 1777 1778 dev_dbg(&host->pdev->dev, "set completed cmd ready\n"); 1779 host->cmd = NULL; 1780 atmci_set_completed(host, EVENT_CMD_RDY); 1781 atmci_command_complete(host, mrq->cmd); 1782 if (mrq->data) { 1783 dev_dbg(&host->pdev->dev, 1784 "command with data transfer"); 1785 /* 1786 * If there is a command error don't start 1787 * data transfer. 1788 */ 1789 if (mrq->cmd->error) { 1790 host->stop_transfer(host); 1791 host->data = NULL; 1792 atmci_writel(host, ATMCI_IDR, 1793 ATMCI_TXRDY | ATMCI_RXRDY 1794 | ATMCI_DATA_ERROR_FLAGS); 1795 state = STATE_END_REQUEST; 1796 } else 1797 state = STATE_DATA_XFER; 1798 } else if ((!mrq->data) && (mrq->cmd->flags & MMC_RSP_BUSY)) { 1799 dev_dbg(&host->pdev->dev, 1800 "command response need waiting notbusy"); 1801 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); 1802 state = STATE_WAITING_NOTBUSY; 1803 } else 1804 state = STATE_END_REQUEST; 1805 1806 break; 1807 1808 case STATE_DATA_XFER: 1809 if (atmci_test_and_clear_pending(host, 1810 EVENT_DATA_ERROR)) { 1811 dev_dbg(&host->pdev->dev, "set completed data error\n"); 1812 atmci_set_completed(host, EVENT_DATA_ERROR); 1813 state = STATE_END_REQUEST; 1814 break; 1815 } 1816 1817 /* 1818 * A data transfer is in progress. The event expected 1819 * to move to the next state depends of data transfer 1820 * type (PDC or DMA). Once transfer done we can move 1821 * to the next step which is WAITING_NOTBUSY in write 1822 * case and directly SENDING_STOP in read case. 1823 */ 1824 dev_dbg(&host->pdev->dev, "FSM: xfer complete?\n"); 1825 if (!atmci_test_and_clear_pending(host, 1826 EVENT_XFER_COMPLETE)) 1827 break; 1828 1829 dev_dbg(&host->pdev->dev, 1830 "(%s) set completed xfer complete\n", 1831 __func__); 1832 atmci_set_completed(host, EVENT_XFER_COMPLETE); 1833 1834 if (host->caps.need_notbusy_for_read_ops || 1835 (host->data->flags & MMC_DATA_WRITE)) { 1836 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); 1837 state = STATE_WAITING_NOTBUSY; 1838 } else if (host->mrq->stop) { 1839 atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY); 1840 atmci_send_stop_cmd(host, data); 1841 state = STATE_SENDING_STOP; 1842 } else { 1843 host->data = NULL; 1844 data->bytes_xfered = data->blocks * data->blksz; 1845 data->error = 0; 1846 state = STATE_END_REQUEST; 1847 } 1848 break; 1849 1850 case STATE_WAITING_NOTBUSY: 1851 /* 1852 * We can be in the state for two reasons: a command 1853 * requiring waiting not busy signal (stop command 1854 * included) or a write operation. In the latest case, 1855 * we need to send a stop command. 1856 */ 1857 dev_dbg(&host->pdev->dev, "FSM: not busy?\n"); 1858 if (!atmci_test_and_clear_pending(host, 1859 EVENT_NOTBUSY)) 1860 break; 1861 1862 dev_dbg(&host->pdev->dev, "set completed not busy\n"); 1863 atmci_set_completed(host, EVENT_NOTBUSY); 1864 1865 if (host->data) { 1866 /* 1867 * For some commands such as CMD53, even if 1868 * there is data transfer, there is no stop 1869 * command to send. 1870 */ 1871 if (host->mrq->stop) { 1872 atmci_writel(host, ATMCI_IER, 1873 ATMCI_CMDRDY); 1874 atmci_send_stop_cmd(host, data); 1875 state = STATE_SENDING_STOP; 1876 } else { 1877 host->data = NULL; 1878 data->bytes_xfered = data->blocks 1879 * data->blksz; 1880 data->error = 0; 1881 state = STATE_END_REQUEST; 1882 } 1883 } else 1884 state = STATE_END_REQUEST; 1885 break; 1886 1887 case STATE_SENDING_STOP: 1888 /* 1889 * In this state, it is important to set host->data to 1890 * NULL (which is tested in the waiting notbusy state) 1891 * in order to go to the end request state instead of 1892 * sending stop again. 1893 */ 1894 dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n"); 1895 if (!atmci_test_and_clear_pending(host, 1896 EVENT_CMD_RDY)) 1897 break; 1898 1899 dev_dbg(&host->pdev->dev, "FSM: cmd ready\n"); 1900 host->cmd = NULL; 1901 data->bytes_xfered = data->blocks * data->blksz; 1902 data->error = 0; 1903 atmci_command_complete(host, mrq->stop); 1904 if (mrq->stop->error) { 1905 host->stop_transfer(host); 1906 atmci_writel(host, ATMCI_IDR, 1907 ATMCI_TXRDY | ATMCI_RXRDY 1908 | ATMCI_DATA_ERROR_FLAGS); 1909 state = STATE_END_REQUEST; 1910 } else { 1911 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); 1912 state = STATE_WAITING_NOTBUSY; 1913 } 1914 host->data = NULL; 1915 break; 1916 1917 case STATE_END_REQUEST: 1918 atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY | ATMCI_RXRDY 1919 | ATMCI_DATA_ERROR_FLAGS); 1920 status = host->data_status; 1921 if (unlikely(status)) { 1922 host->stop_transfer(host); 1923 host->data = NULL; 1924 if (data) { 1925 if (status & ATMCI_DTOE) { 1926 data->error = -ETIMEDOUT; 1927 } else if (status & ATMCI_DCRCE) { 1928 data->error = -EILSEQ; 1929 } else { 1930 data->error = -EIO; 1931 } 1932 } 1933 } 1934 1935 atmci_request_end(host, host->mrq); 1936 goto unlock; /* atmci_request_end() sets host->state */ 1937 break; 1938 } 1939 } while (state != prev_state); 1940 1941 host->state = state; 1942 1943 unlock: 1944 spin_unlock(&host->lock); 1945 } 1946 1947 static void atmci_read_data_pio(struct atmel_mci *host) 1948 { 1949 struct scatterlist *sg = host->sg; 1950 unsigned int offset = host->pio_offset; 1951 struct mmc_data *data = host->data; 1952 u32 value; 1953 u32 status; 1954 unsigned int nbytes = 0; 1955 1956 do { 1957 value = atmci_readl(host, ATMCI_RDR); 1958 if (likely(offset + 4 <= sg->length)) { 1959 sg_pcopy_from_buffer(sg, 1, &value, sizeof(u32), offset); 1960 1961 offset += 4; 1962 nbytes += 4; 1963 1964 if (offset == sg->length) { 1965 flush_dcache_page(sg_page(sg)); 1966 host->sg = sg = sg_next(sg); 1967 host->sg_len--; 1968 if (!sg || !host->sg_len) 1969 goto done; 1970 1971 offset = 0; 1972 } 1973 } else { 1974 unsigned int remaining = sg->length - offset; 1975 1976 sg_pcopy_from_buffer(sg, 1, &value, remaining, offset); 1977 nbytes += remaining; 1978 1979 flush_dcache_page(sg_page(sg)); 1980 host->sg = sg = sg_next(sg); 1981 host->sg_len--; 1982 if (!sg || !host->sg_len) 1983 goto done; 1984 1985 offset = 4 - remaining; 1986 sg_pcopy_from_buffer(sg, 1, (u8 *)&value + remaining, 1987 offset, 0); 1988 nbytes += offset; 1989 } 1990 1991 status = atmci_readl(host, ATMCI_SR); 1992 if (status & ATMCI_DATA_ERROR_FLAGS) { 1993 atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_RXRDY 1994 | ATMCI_DATA_ERROR_FLAGS)); 1995 host->data_status = status; 1996 data->bytes_xfered += nbytes; 1997 return; 1998 } 1999 } while (status & ATMCI_RXRDY); 2000 2001 host->pio_offset = offset; 2002 data->bytes_xfered += nbytes; 2003 2004 return; 2005 2006 done: 2007 atmci_writel(host, ATMCI_IDR, ATMCI_RXRDY); 2008 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); 2009 data->bytes_xfered += nbytes; 2010 smp_wmb(); 2011 atmci_set_pending(host, EVENT_XFER_COMPLETE); 2012 } 2013 2014 static void atmci_write_data_pio(struct atmel_mci *host) 2015 { 2016 struct scatterlist *sg = host->sg; 2017 unsigned int offset = host->pio_offset; 2018 struct mmc_data *data = host->data; 2019 u32 value; 2020 u32 status; 2021 unsigned int nbytes = 0; 2022 2023 do { 2024 if (likely(offset + 4 <= sg->length)) { 2025 sg_pcopy_to_buffer(sg, 1, &value, sizeof(u32), offset); 2026 atmci_writel(host, ATMCI_TDR, value); 2027 2028 offset += 4; 2029 nbytes += 4; 2030 if (offset == sg->length) { 2031 host->sg = sg = sg_next(sg); 2032 host->sg_len--; 2033 if (!sg || !host->sg_len) 2034 goto done; 2035 2036 offset = 0; 2037 } 2038 } else { 2039 unsigned int remaining = sg->length - offset; 2040 2041 value = 0; 2042 sg_pcopy_to_buffer(sg, 1, &value, remaining, offset); 2043 nbytes += remaining; 2044 2045 host->sg = sg = sg_next(sg); 2046 host->sg_len--; 2047 if (!sg || !host->sg_len) { 2048 atmci_writel(host, ATMCI_TDR, value); 2049 goto done; 2050 } 2051 2052 offset = 4 - remaining; 2053 sg_pcopy_to_buffer(sg, 1, (u8 *)&value + remaining, 2054 offset, 0); 2055 atmci_writel(host, ATMCI_TDR, value); 2056 nbytes += offset; 2057 } 2058 2059 status = atmci_readl(host, ATMCI_SR); 2060 if (status & ATMCI_DATA_ERROR_FLAGS) { 2061 atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_TXRDY 2062 | ATMCI_DATA_ERROR_FLAGS)); 2063 host->data_status = status; 2064 data->bytes_xfered += nbytes; 2065 return; 2066 } 2067 } while (status & ATMCI_TXRDY); 2068 2069 host->pio_offset = offset; 2070 data->bytes_xfered += nbytes; 2071 2072 return; 2073 2074 done: 2075 atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY); 2076 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); 2077 data->bytes_xfered += nbytes; 2078 smp_wmb(); 2079 atmci_set_pending(host, EVENT_XFER_COMPLETE); 2080 } 2081 2082 static void atmci_sdio_interrupt(struct atmel_mci *host, u32 status) 2083 { 2084 int i; 2085 2086 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) { 2087 struct atmel_mci_slot *slot = host->slot[i]; 2088 if (slot && (status & slot->sdio_irq)) { 2089 mmc_signal_sdio_irq(slot->mmc); 2090 } 2091 } 2092 } 2093 2094 2095 static irqreturn_t atmci_interrupt(int irq, void *dev_id) 2096 { 2097 struct atmel_mci *host = dev_id; 2098 u32 status, mask, pending; 2099 unsigned int pass_count = 0; 2100 2101 do { 2102 status = atmci_readl(host, ATMCI_SR); 2103 mask = atmci_readl(host, ATMCI_IMR); 2104 pending = status & mask; 2105 if (!pending) 2106 break; 2107 2108 if (pending & ATMCI_DATA_ERROR_FLAGS) { 2109 dev_dbg(&host->pdev->dev, "IRQ: data error\n"); 2110 atmci_writel(host, ATMCI_IDR, ATMCI_DATA_ERROR_FLAGS 2111 | ATMCI_RXRDY | ATMCI_TXRDY 2112 | ATMCI_ENDRX | ATMCI_ENDTX 2113 | ATMCI_RXBUFF | ATMCI_TXBUFE); 2114 2115 host->data_status = status; 2116 dev_dbg(&host->pdev->dev, "set pending data error\n"); 2117 smp_wmb(); 2118 atmci_set_pending(host, EVENT_DATA_ERROR); 2119 tasklet_schedule(&host->tasklet); 2120 } 2121 2122 if (pending & ATMCI_TXBUFE) { 2123 dev_dbg(&host->pdev->dev, "IRQ: tx buffer empty\n"); 2124 atmci_writel(host, ATMCI_IDR, ATMCI_TXBUFE); 2125 atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX); 2126 /* 2127 * We can receive this interruption before having configured 2128 * the second pdc buffer, so we need to reconfigure first and 2129 * second buffers again 2130 */ 2131 if (host->data_size) { 2132 atmci_pdc_set_both_buf(host, XFER_TRANSMIT); 2133 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX); 2134 atmci_writel(host, ATMCI_IER, ATMCI_TXBUFE); 2135 } else { 2136 atmci_pdc_complete(host); 2137 } 2138 } else if (pending & ATMCI_ENDTX) { 2139 dev_dbg(&host->pdev->dev, "IRQ: end of tx buffer\n"); 2140 atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX); 2141 2142 if (host->data_size) { 2143 atmci_pdc_set_single_buf(host, 2144 XFER_TRANSMIT, PDC_SECOND_BUF); 2145 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX); 2146 } 2147 } 2148 2149 if (pending & ATMCI_RXBUFF) { 2150 dev_dbg(&host->pdev->dev, "IRQ: rx buffer full\n"); 2151 atmci_writel(host, ATMCI_IDR, ATMCI_RXBUFF); 2152 atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX); 2153 /* 2154 * We can receive this interruption before having configured 2155 * the second pdc buffer, so we need to reconfigure first and 2156 * second buffers again 2157 */ 2158 if (host->data_size) { 2159 atmci_pdc_set_both_buf(host, XFER_RECEIVE); 2160 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX); 2161 atmci_writel(host, ATMCI_IER, ATMCI_RXBUFF); 2162 } else { 2163 atmci_pdc_complete(host); 2164 } 2165 } else if (pending & ATMCI_ENDRX) { 2166 dev_dbg(&host->pdev->dev, "IRQ: end of rx buffer\n"); 2167 atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX); 2168 2169 if (host->data_size) { 2170 atmci_pdc_set_single_buf(host, 2171 XFER_RECEIVE, PDC_SECOND_BUF); 2172 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX); 2173 } 2174 } 2175 2176 /* 2177 * First mci IPs, so mainly the ones having pdc, have some 2178 * issues with the notbusy signal. You can't get it after 2179 * data transmission if you have not sent a stop command. 2180 * The appropriate workaround is to use the BLKE signal. 2181 */ 2182 if (pending & ATMCI_BLKE) { 2183 dev_dbg(&host->pdev->dev, "IRQ: blke\n"); 2184 atmci_writel(host, ATMCI_IDR, ATMCI_BLKE); 2185 smp_wmb(); 2186 dev_dbg(&host->pdev->dev, "set pending notbusy\n"); 2187 atmci_set_pending(host, EVENT_NOTBUSY); 2188 tasklet_schedule(&host->tasklet); 2189 } 2190 2191 if (pending & ATMCI_NOTBUSY) { 2192 dev_dbg(&host->pdev->dev, "IRQ: not_busy\n"); 2193 atmci_writel(host, ATMCI_IDR, ATMCI_NOTBUSY); 2194 smp_wmb(); 2195 dev_dbg(&host->pdev->dev, "set pending notbusy\n"); 2196 atmci_set_pending(host, EVENT_NOTBUSY); 2197 tasklet_schedule(&host->tasklet); 2198 } 2199 2200 if (pending & ATMCI_RXRDY) 2201 atmci_read_data_pio(host); 2202 if (pending & ATMCI_TXRDY) 2203 atmci_write_data_pio(host); 2204 2205 if (pending & ATMCI_CMDRDY) { 2206 dev_dbg(&host->pdev->dev, "IRQ: cmd ready\n"); 2207 atmci_writel(host, ATMCI_IDR, ATMCI_CMDRDY); 2208 host->cmd_status = status; 2209 smp_wmb(); 2210 dev_dbg(&host->pdev->dev, "set pending cmd rdy\n"); 2211 atmci_set_pending(host, EVENT_CMD_RDY); 2212 tasklet_schedule(&host->tasklet); 2213 } 2214 2215 if (pending & (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB)) 2216 atmci_sdio_interrupt(host, status); 2217 2218 } while (pass_count++ < 5); 2219 2220 return pass_count ? IRQ_HANDLED : IRQ_NONE; 2221 } 2222 2223 static irqreturn_t atmci_detect_interrupt(int irq, void *dev_id) 2224 { 2225 struct atmel_mci_slot *slot = dev_id; 2226 2227 /* 2228 * Disable interrupts until the pin has stabilized and check 2229 * the state then. Use mod_timer() since we may be in the 2230 * middle of the timer routine when this interrupt triggers. 2231 */ 2232 disable_irq_nosync(irq); 2233 mod_timer(&slot->detect_timer, jiffies + msecs_to_jiffies(20)); 2234 2235 return IRQ_HANDLED; 2236 } 2237 2238 static int atmci_init_slot(struct atmel_mci *host, 2239 struct mci_slot_pdata *slot_data, unsigned int id, 2240 u32 sdc_reg, u32 sdio_irq) 2241 { 2242 struct mmc_host *mmc; 2243 struct atmel_mci_slot *slot; 2244 2245 mmc = mmc_alloc_host(sizeof(struct atmel_mci_slot), &host->pdev->dev); 2246 if (!mmc) 2247 return -ENOMEM; 2248 2249 slot = mmc_priv(mmc); 2250 slot->mmc = mmc; 2251 slot->host = host; 2252 slot->detect_pin = slot_data->detect_pin; 2253 slot->wp_pin = slot_data->wp_pin; 2254 slot->detect_is_active_high = slot_data->detect_is_active_high; 2255 slot->sdc_reg = sdc_reg; 2256 slot->sdio_irq = sdio_irq; 2257 2258 dev_dbg(&mmc->class_dev, 2259 "slot[%u]: bus_width=%u, detect_pin=%d, " 2260 "detect_is_active_high=%s, wp_pin=%d\n", 2261 id, slot_data->bus_width, slot_data->detect_pin, 2262 slot_data->detect_is_active_high ? "true" : "false", 2263 slot_data->wp_pin); 2264 2265 mmc->ops = &atmci_ops; 2266 mmc->f_min = DIV_ROUND_UP(host->bus_hz, 512); 2267 mmc->f_max = host->bus_hz / 2; 2268 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 2269 if (sdio_irq) 2270 mmc->caps |= MMC_CAP_SDIO_IRQ; 2271 if (host->caps.has_highspeed) 2272 mmc->caps |= MMC_CAP_SD_HIGHSPEED; 2273 /* 2274 * Without the read/write proof capability, it is strongly suggested to 2275 * use only one bit for data to prevent fifo underruns and overruns 2276 * which will corrupt data. 2277 */ 2278 if ((slot_data->bus_width >= 4) && host->caps.has_rwproof) { 2279 mmc->caps |= MMC_CAP_4_BIT_DATA; 2280 if (slot_data->bus_width >= 8) 2281 mmc->caps |= MMC_CAP_8_BIT_DATA; 2282 } 2283 2284 if (atmci_get_version(host) < 0x200) { 2285 mmc->max_segs = 256; 2286 mmc->max_blk_size = 4095; 2287 mmc->max_blk_count = 256; 2288 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 2289 mmc->max_seg_size = mmc->max_blk_size * mmc->max_segs; 2290 } else { 2291 mmc->max_segs = 64; 2292 mmc->max_req_size = 32768 * 512; 2293 mmc->max_blk_size = 32768; 2294 mmc->max_blk_count = 512; 2295 } 2296 2297 /* Assume card is present initially */ 2298 set_bit(ATMCI_CARD_PRESENT, &slot->flags); 2299 if (gpio_is_valid(slot->detect_pin)) { 2300 if (devm_gpio_request(&host->pdev->dev, slot->detect_pin, 2301 "mmc_detect")) { 2302 dev_dbg(&mmc->class_dev, "no detect pin available\n"); 2303 slot->detect_pin = -EBUSY; 2304 } else if (gpio_get_value(slot->detect_pin) ^ 2305 slot->detect_is_active_high) { 2306 clear_bit(ATMCI_CARD_PRESENT, &slot->flags); 2307 } 2308 } 2309 2310 if (!gpio_is_valid(slot->detect_pin)) { 2311 if (slot_data->non_removable) 2312 mmc->caps |= MMC_CAP_NONREMOVABLE; 2313 else 2314 mmc->caps |= MMC_CAP_NEEDS_POLL; 2315 } 2316 2317 if (gpio_is_valid(slot->wp_pin)) { 2318 if (devm_gpio_request(&host->pdev->dev, slot->wp_pin, 2319 "mmc_wp")) { 2320 dev_dbg(&mmc->class_dev, "no WP pin available\n"); 2321 slot->wp_pin = -EBUSY; 2322 } 2323 } 2324 2325 host->slot[id] = slot; 2326 mmc_regulator_get_supply(mmc); 2327 mmc_add_host(mmc); 2328 2329 if (gpio_is_valid(slot->detect_pin)) { 2330 int ret; 2331 2332 timer_setup(&slot->detect_timer, atmci_detect_change, 0); 2333 2334 ret = request_irq(gpio_to_irq(slot->detect_pin), 2335 atmci_detect_interrupt, 2336 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, 2337 "mmc-detect", slot); 2338 if (ret) { 2339 dev_dbg(&mmc->class_dev, 2340 "could not request IRQ %d for detect pin\n", 2341 gpio_to_irq(slot->detect_pin)); 2342 slot->detect_pin = -EBUSY; 2343 } 2344 } 2345 2346 atmci_init_debugfs(slot); 2347 2348 return 0; 2349 } 2350 2351 static void atmci_cleanup_slot(struct atmel_mci_slot *slot, 2352 unsigned int id) 2353 { 2354 /* Debugfs stuff is cleaned up by mmc core */ 2355 2356 set_bit(ATMCI_SHUTDOWN, &slot->flags); 2357 smp_wmb(); 2358 2359 mmc_remove_host(slot->mmc); 2360 2361 if (gpio_is_valid(slot->detect_pin)) { 2362 int pin = slot->detect_pin; 2363 2364 free_irq(gpio_to_irq(pin), slot); 2365 del_timer_sync(&slot->detect_timer); 2366 } 2367 2368 slot->host->slot[id] = NULL; 2369 mmc_free_host(slot->mmc); 2370 } 2371 2372 static int atmci_configure_dma(struct atmel_mci *host) 2373 { 2374 host->dma.chan = dma_request_slave_channel_reason(&host->pdev->dev, 2375 "rxtx"); 2376 2377 if (PTR_ERR(host->dma.chan) == -ENODEV) { 2378 struct mci_platform_data *pdata = host->pdev->dev.platform_data; 2379 dma_cap_mask_t mask; 2380 2381 if (!pdata || !pdata->dma_filter) 2382 return -ENODEV; 2383 2384 dma_cap_zero(mask); 2385 dma_cap_set(DMA_SLAVE, mask); 2386 2387 host->dma.chan = dma_request_channel(mask, pdata->dma_filter, 2388 pdata->dma_slave); 2389 if (!host->dma.chan) 2390 host->dma.chan = ERR_PTR(-ENODEV); 2391 } 2392 2393 if (IS_ERR(host->dma.chan)) 2394 return PTR_ERR(host->dma.chan); 2395 2396 dev_info(&host->pdev->dev, "using %s for DMA transfers\n", 2397 dma_chan_name(host->dma.chan)); 2398 2399 host->dma_conf.src_addr = host->mapbase + ATMCI_RDR; 2400 host->dma_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 2401 host->dma_conf.src_maxburst = 1; 2402 host->dma_conf.dst_addr = host->mapbase + ATMCI_TDR; 2403 host->dma_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 2404 host->dma_conf.dst_maxburst = 1; 2405 host->dma_conf.device_fc = false; 2406 2407 return 0; 2408 } 2409 2410 /* 2411 * HSMCI (High Speed MCI) module is not fully compatible with MCI module. 2412 * HSMCI provides DMA support and a new config register but no more supports 2413 * PDC. 2414 */ 2415 static void atmci_get_cap(struct atmel_mci *host) 2416 { 2417 unsigned int version; 2418 2419 version = atmci_get_version(host); 2420 dev_info(&host->pdev->dev, 2421 "version: 0x%x\n", version); 2422 2423 host->caps.has_dma_conf_reg = 0; 2424 host->caps.has_pdc = 1; 2425 host->caps.has_cfg_reg = 0; 2426 host->caps.has_cstor_reg = 0; 2427 host->caps.has_highspeed = 0; 2428 host->caps.has_rwproof = 0; 2429 host->caps.has_odd_clk_div = 0; 2430 host->caps.has_bad_data_ordering = 1; 2431 host->caps.need_reset_after_xfer = 1; 2432 host->caps.need_blksz_mul_4 = 1; 2433 host->caps.need_notbusy_for_read_ops = 0; 2434 2435 /* keep only major version number */ 2436 switch (version & 0xf00) { 2437 case 0x600: 2438 case 0x500: 2439 host->caps.has_odd_clk_div = 1; 2440 case 0x400: 2441 case 0x300: 2442 host->caps.has_dma_conf_reg = 1; 2443 host->caps.has_pdc = 0; 2444 host->caps.has_cfg_reg = 1; 2445 host->caps.has_cstor_reg = 1; 2446 host->caps.has_highspeed = 1; 2447 case 0x200: 2448 host->caps.has_rwproof = 1; 2449 host->caps.need_blksz_mul_4 = 0; 2450 host->caps.need_notbusy_for_read_ops = 1; 2451 case 0x100: 2452 host->caps.has_bad_data_ordering = 0; 2453 host->caps.need_reset_after_xfer = 0; 2454 case 0x0: 2455 break; 2456 default: 2457 host->caps.has_pdc = 0; 2458 dev_warn(&host->pdev->dev, 2459 "Unmanaged mci version, set minimum capabilities\n"); 2460 break; 2461 } 2462 } 2463 2464 static int atmci_probe(struct platform_device *pdev) 2465 { 2466 struct mci_platform_data *pdata; 2467 struct atmel_mci *host; 2468 struct resource *regs; 2469 unsigned int nr_slots; 2470 int irq; 2471 int ret, i; 2472 2473 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2474 if (!regs) 2475 return -ENXIO; 2476 pdata = pdev->dev.platform_data; 2477 if (!pdata) { 2478 pdata = atmci_of_init(pdev); 2479 if (IS_ERR(pdata)) { 2480 dev_err(&pdev->dev, "platform data not available\n"); 2481 return PTR_ERR(pdata); 2482 } 2483 } 2484 2485 irq = platform_get_irq(pdev, 0); 2486 if (irq < 0) 2487 return irq; 2488 2489 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL); 2490 if (!host) 2491 return -ENOMEM; 2492 2493 host->pdev = pdev; 2494 spin_lock_init(&host->lock); 2495 INIT_LIST_HEAD(&host->queue); 2496 2497 host->mck = devm_clk_get(&pdev->dev, "mci_clk"); 2498 if (IS_ERR(host->mck)) 2499 return PTR_ERR(host->mck); 2500 2501 host->regs = devm_ioremap(&pdev->dev, regs->start, resource_size(regs)); 2502 if (!host->regs) 2503 return -ENOMEM; 2504 2505 ret = clk_prepare_enable(host->mck); 2506 if (ret) 2507 return ret; 2508 2509 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST); 2510 host->bus_hz = clk_get_rate(host->mck); 2511 2512 host->mapbase = regs->start; 2513 2514 tasklet_init(&host->tasklet, atmci_tasklet_func, (unsigned long)host); 2515 2516 ret = request_irq(irq, atmci_interrupt, 0, dev_name(&pdev->dev), host); 2517 if (ret) { 2518 clk_disable_unprepare(host->mck); 2519 return ret; 2520 } 2521 2522 /* Get MCI capabilities and set operations according to it */ 2523 atmci_get_cap(host); 2524 ret = atmci_configure_dma(host); 2525 if (ret == -EPROBE_DEFER) 2526 goto err_dma_probe_defer; 2527 if (ret == 0) { 2528 host->prepare_data = &atmci_prepare_data_dma; 2529 host->submit_data = &atmci_submit_data_dma; 2530 host->stop_transfer = &atmci_stop_transfer_dma; 2531 } else if (host->caps.has_pdc) { 2532 dev_info(&pdev->dev, "using PDC\n"); 2533 host->prepare_data = &atmci_prepare_data_pdc; 2534 host->submit_data = &atmci_submit_data_pdc; 2535 host->stop_transfer = &atmci_stop_transfer_pdc; 2536 } else { 2537 dev_info(&pdev->dev, "using PIO\n"); 2538 host->prepare_data = &atmci_prepare_data; 2539 host->submit_data = &atmci_submit_data; 2540 host->stop_transfer = &atmci_stop_transfer; 2541 } 2542 2543 platform_set_drvdata(pdev, host); 2544 2545 timer_setup(&host->timer, atmci_timeout_timer, 0); 2546 2547 pm_runtime_get_noresume(&pdev->dev); 2548 pm_runtime_set_active(&pdev->dev); 2549 pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_DELAY); 2550 pm_runtime_use_autosuspend(&pdev->dev); 2551 pm_runtime_enable(&pdev->dev); 2552 2553 /* We need at least one slot to succeed */ 2554 nr_slots = 0; 2555 ret = -ENODEV; 2556 if (pdata->slot[0].bus_width) { 2557 ret = atmci_init_slot(host, &pdata->slot[0], 2558 0, ATMCI_SDCSEL_SLOT_A, ATMCI_SDIOIRQA); 2559 if (!ret) { 2560 nr_slots++; 2561 host->buf_size = host->slot[0]->mmc->max_req_size; 2562 } 2563 } 2564 if (pdata->slot[1].bus_width) { 2565 ret = atmci_init_slot(host, &pdata->slot[1], 2566 1, ATMCI_SDCSEL_SLOT_B, ATMCI_SDIOIRQB); 2567 if (!ret) { 2568 nr_slots++; 2569 if (host->slot[1]->mmc->max_req_size > host->buf_size) 2570 host->buf_size = 2571 host->slot[1]->mmc->max_req_size; 2572 } 2573 } 2574 2575 if (!nr_slots) { 2576 dev_err(&pdev->dev, "init failed: no slot defined\n"); 2577 goto err_init_slot; 2578 } 2579 2580 if (!host->caps.has_rwproof) { 2581 host->buffer = dma_alloc_coherent(&pdev->dev, host->buf_size, 2582 &host->buf_phys_addr, 2583 GFP_KERNEL); 2584 if (!host->buffer) { 2585 ret = -ENOMEM; 2586 dev_err(&pdev->dev, "buffer allocation failed\n"); 2587 goto err_dma_alloc; 2588 } 2589 } 2590 2591 dev_info(&pdev->dev, 2592 "Atmel MCI controller at 0x%08lx irq %d, %u slots\n", 2593 host->mapbase, irq, nr_slots); 2594 2595 pm_runtime_mark_last_busy(&host->pdev->dev); 2596 pm_runtime_put_autosuspend(&pdev->dev); 2597 2598 return 0; 2599 2600 err_dma_alloc: 2601 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) { 2602 if (host->slot[i]) 2603 atmci_cleanup_slot(host->slot[i], i); 2604 } 2605 err_init_slot: 2606 clk_disable_unprepare(host->mck); 2607 2608 pm_runtime_disable(&pdev->dev); 2609 pm_runtime_put_noidle(&pdev->dev); 2610 2611 del_timer_sync(&host->timer); 2612 if (!IS_ERR(host->dma.chan)) 2613 dma_release_channel(host->dma.chan); 2614 err_dma_probe_defer: 2615 free_irq(irq, host); 2616 return ret; 2617 } 2618 2619 static int atmci_remove(struct platform_device *pdev) 2620 { 2621 struct atmel_mci *host = platform_get_drvdata(pdev); 2622 unsigned int i; 2623 2624 pm_runtime_get_sync(&pdev->dev); 2625 2626 if (host->buffer) 2627 dma_free_coherent(&pdev->dev, host->buf_size, 2628 host->buffer, host->buf_phys_addr); 2629 2630 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) { 2631 if (host->slot[i]) 2632 atmci_cleanup_slot(host->slot[i], i); 2633 } 2634 2635 atmci_writel(host, ATMCI_IDR, ~0UL); 2636 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS); 2637 atmci_readl(host, ATMCI_SR); 2638 2639 del_timer_sync(&host->timer); 2640 if (!IS_ERR(host->dma.chan)) 2641 dma_release_channel(host->dma.chan); 2642 2643 free_irq(platform_get_irq(pdev, 0), host); 2644 2645 clk_disable_unprepare(host->mck); 2646 2647 pm_runtime_disable(&pdev->dev); 2648 pm_runtime_put_noidle(&pdev->dev); 2649 2650 return 0; 2651 } 2652 2653 #ifdef CONFIG_PM 2654 static int atmci_runtime_suspend(struct device *dev) 2655 { 2656 struct atmel_mci *host = dev_get_drvdata(dev); 2657 2658 clk_disable_unprepare(host->mck); 2659 2660 pinctrl_pm_select_sleep_state(dev); 2661 2662 return 0; 2663 } 2664 2665 static int atmci_runtime_resume(struct device *dev) 2666 { 2667 struct atmel_mci *host = dev_get_drvdata(dev); 2668 2669 pinctrl_pm_select_default_state(dev); 2670 2671 return clk_prepare_enable(host->mck); 2672 } 2673 #endif 2674 2675 static const struct dev_pm_ops atmci_dev_pm_ops = { 2676 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 2677 pm_runtime_force_resume) 2678 SET_RUNTIME_PM_OPS(atmci_runtime_suspend, atmci_runtime_resume, NULL) 2679 }; 2680 2681 static struct platform_driver atmci_driver = { 2682 .probe = atmci_probe, 2683 .remove = atmci_remove, 2684 .driver = { 2685 .name = "atmel_mci", 2686 .of_match_table = of_match_ptr(atmci_dt_ids), 2687 .pm = &atmci_dev_pm_ops, 2688 }, 2689 }; 2690 module_platform_driver(atmci_driver); 2691 2692 MODULE_DESCRIPTION("Atmel Multimedia Card Interface driver"); 2693 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); 2694 MODULE_LICENSE("GPL v2"); 2695