1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell. 5 * 6 */ 7 8 #ifndef RVU_H 9 #define RVU_H 10 11 #include <linux/pci.h> 12 #include <net/devlink.h> 13 14 #include "rvu_struct.h" 15 #include "rvu_devlink.h" 16 #include "common.h" 17 #include "mbox.h" 18 #include "npc.h" 19 #include "rvu_reg.h" 20 21 /* PCI device IDs */ 22 #define PCI_DEVID_OCTEONTX2_RVU_AF 0xA065 23 #define PCI_DEVID_OCTEONTX2_LBK 0xA061 24 25 /* Subsystem Device ID */ 26 #define PCI_SUBSYS_DEVID_98XX 0xB100 27 #define PCI_SUBSYS_DEVID_96XX 0xB200 28 #define PCI_SUBSYS_DEVID_CN10K_A 0xB900 29 #define PCI_SUBSYS_DEVID_CNF10K_B 0xBC00 30 #define PCI_SUBSYS_DEVID_CN10K_B 0xBD00 31 32 /* PCI BAR nos */ 33 #define PCI_AF_REG_BAR_NUM 0 34 #define PCI_PF_REG_BAR_NUM 2 35 #define PCI_MBOX_BAR_NUM 4 36 37 #define NAME_SIZE 32 38 #define MAX_NIX_BLKS 2 39 #define MAX_CPT_BLKS 2 40 41 /* PF_FUNC */ 42 #define RVU_PFVF_PF_SHIFT 10 43 #define RVU_PFVF_PF_MASK 0x3F 44 #define RVU_PFVF_FUNC_SHIFT 0 45 #define RVU_PFVF_FUNC_MASK 0x3FF 46 47 #ifdef CONFIG_DEBUG_FS 48 struct dump_ctx { 49 int lf; 50 int id; 51 bool all; 52 }; 53 54 struct cpt_ctx { 55 int blkaddr; 56 struct rvu *rvu; 57 }; 58 59 struct rvu_debugfs { 60 struct dentry *root; 61 struct dentry *cgx_root; 62 struct dentry *cgx; 63 struct dentry *lmac; 64 struct dentry *npa; 65 struct dentry *nix; 66 struct dentry *npc; 67 struct dentry *cpt; 68 struct dentry *mcs_root; 69 struct dentry *mcs; 70 struct dentry *mcs_rx; 71 struct dentry *mcs_tx; 72 struct dump_ctx npa_aura_ctx; 73 struct dump_ctx npa_pool_ctx; 74 struct dump_ctx nix_cq_ctx; 75 struct dump_ctx nix_rq_ctx; 76 struct dump_ctx nix_sq_ctx; 77 struct cpt_ctx cpt_ctx[MAX_CPT_BLKS]; 78 int npa_qsize_id; 79 int nix_qsize_id; 80 }; 81 #endif 82 83 struct rvu_work { 84 struct work_struct work; 85 struct rvu *rvu; 86 int num_msgs; 87 int up_num_msgs; 88 }; 89 90 struct rsrc_bmap { 91 unsigned long *bmap; /* Pointer to resource bitmap */ 92 u16 max; /* Max resource id or count */ 93 }; 94 95 struct rvu_block { 96 struct rsrc_bmap lf; 97 struct admin_queue *aq; /* NIX/NPA AQ */ 98 u16 *fn_map; /* LF to pcifunc mapping */ 99 bool multislot; 100 bool implemented; 101 u8 addr; /* RVU_BLOCK_ADDR_E */ 102 u8 type; /* RVU_BLOCK_TYPE_E */ 103 u8 lfshift; 104 u64 lookup_reg; 105 u64 pf_lfcnt_reg; 106 u64 vf_lfcnt_reg; 107 u64 lfcfg_reg; 108 u64 msixcfg_reg; 109 u64 lfreset_reg; 110 unsigned char name[NAME_SIZE]; 111 struct rvu *rvu; 112 u64 cpt_flt_eng_map[3]; 113 u64 cpt_rcvrd_eng_map[3]; 114 }; 115 116 struct nix_mcast { 117 struct qmem *mce_ctx; 118 struct qmem *mcast_buf; 119 int replay_pkind; 120 int next_free_mce; 121 struct mutex mce_lock; /* Serialize MCE updates */ 122 }; 123 124 struct nix_mce_list { 125 struct hlist_head head; 126 int count; 127 int max; 128 }; 129 130 /* layer metadata to uniquely identify a packet header field */ 131 struct npc_layer_mdata { 132 u8 lid; 133 u8 ltype; 134 u8 hdr; 135 u8 key; 136 u8 len; 137 }; 138 139 /* Structure to represent a field present in the 140 * generated key. A key field may present anywhere and can 141 * be of any size in the generated key. Once this structure 142 * is populated for fields of interest then field's presence 143 * and location (if present) can be known. 144 */ 145 struct npc_key_field { 146 /* Masks where all set bits indicate position 147 * of a field in the key 148 */ 149 u64 kw_mask[NPC_MAX_KWS_IN_KEY]; 150 /* Number of words in the key a field spans. If a field is 151 * of 16 bytes and key offset is 4 then the field will use 152 * 4 bytes in KW0, 8 bytes in KW1 and 4 bytes in KW2 and 153 * nr_kws will be 3(KW0, KW1 and KW2). 154 */ 155 int nr_kws; 156 /* used by packet header fields */ 157 struct npc_layer_mdata layer_mdata; 158 }; 159 160 struct npc_mcam { 161 struct rsrc_bmap counters; 162 struct mutex lock; /* MCAM entries and counters update lock */ 163 unsigned long *bmap; /* bitmap, 0 => bmap_entries */ 164 unsigned long *bmap_reverse; /* Reverse bitmap, bmap_entries => 0 */ 165 u16 bmap_entries; /* Number of unreserved MCAM entries */ 166 u16 bmap_fcnt; /* MCAM entries free count */ 167 u16 *entry2pfvf_map; 168 u16 *entry2cntr_map; 169 u16 *cntr2pfvf_map; 170 u16 *cntr_refcnt; 171 u16 *entry2target_pffunc; 172 u8 keysize; /* MCAM keysize 112/224/448 bits */ 173 u8 banks; /* Number of MCAM banks */ 174 u8 banks_per_entry;/* Number of keywords in key */ 175 u16 banksize; /* Number of MCAM entries in each bank */ 176 u16 total_entries; /* Total number of MCAM entries */ 177 u16 nixlf_offset; /* Offset of nixlf rsvd uncast entries */ 178 u16 pf_offset; /* Offset of PF's rsvd bcast, promisc entries */ 179 u16 lprio_count; 180 u16 lprio_start; 181 u16 hprio_count; 182 u16 hprio_end; 183 u16 rx_miss_act_cntr; /* Counter for RX MISS action */ 184 /* fields present in the generated key */ 185 struct npc_key_field tx_key_fields[NPC_KEY_FIELDS_MAX]; 186 struct npc_key_field rx_key_fields[NPC_KEY_FIELDS_MAX]; 187 u64 tx_features; 188 u64 rx_features; 189 struct list_head mcam_rules; 190 }; 191 192 /* Structure for per RVU func info ie PF/VF */ 193 struct rvu_pfvf { 194 bool npalf; /* Only one NPALF per RVU_FUNC */ 195 bool nixlf; /* Only one NIXLF per RVU_FUNC */ 196 u16 sso; 197 u16 ssow; 198 u16 cptlfs; 199 u16 timlfs; 200 u16 cpt1_lfs; 201 u8 cgx_lmac; 202 203 /* Block LF's MSIX vector info */ 204 struct rsrc_bmap msix; /* Bitmap for MSIX vector alloc */ 205 #define MSIX_BLKLF(blkaddr, lf) (((blkaddr) << 8) | ((lf) & 0xFF)) 206 u16 *msix_lfmap; /* Vector to block LF mapping */ 207 208 /* NPA contexts */ 209 struct qmem *aura_ctx; 210 struct qmem *pool_ctx; 211 struct qmem *npa_qints_ctx; 212 unsigned long *aura_bmap; 213 unsigned long *pool_bmap; 214 215 /* NIX contexts */ 216 struct qmem *rq_ctx; 217 struct qmem *sq_ctx; 218 struct qmem *cq_ctx; 219 struct qmem *rss_ctx; 220 struct qmem *cq_ints_ctx; 221 struct qmem *nix_qints_ctx; 222 unsigned long *sq_bmap; 223 unsigned long *rq_bmap; 224 unsigned long *cq_bmap; 225 226 u16 rx_chan_base; 227 u16 tx_chan_base; 228 u8 rx_chan_cnt; /* total number of RX channels */ 229 u8 tx_chan_cnt; /* total number of TX channels */ 230 u16 maxlen; 231 u16 minlen; 232 233 bool hw_rx_tstamp_en; /* Is rx_tstamp enabled */ 234 u8 mac_addr[ETH_ALEN]; /* MAC address of this PF/VF */ 235 u8 default_mac[ETH_ALEN]; /* MAC address from FWdata */ 236 237 /* Broadcast/Multicast/Promisc pkt replication info */ 238 u16 bcast_mce_idx; 239 u16 mcast_mce_idx; 240 u16 promisc_mce_idx; 241 struct nix_mce_list bcast_mce_list; 242 struct nix_mce_list mcast_mce_list; 243 struct nix_mce_list promisc_mce_list; 244 bool use_mce_list; 245 246 struct rvu_npc_mcam_rule *def_ucast_rule; 247 248 bool cgx_in_use; /* this PF/VF using CGX? */ 249 int cgx_users; /* number of cgx users - used only by PFs */ 250 251 int intf_mode; 252 u8 nix_blkaddr; /* BLKADDR_NIX0/1 assigned to this PF */ 253 u8 nix_rx_intf; /* NIX0_RX/NIX1_RX interface to NPC */ 254 u8 nix_tx_intf; /* NIX0_TX/NIX1_TX interface to NPC */ 255 u8 lbkid; /* NIX0/1 lbk link ID */ 256 u64 lmt_base_addr; /* Preseving the pcifunc's lmtst base addr*/ 257 u64 lmt_map_ent_w1; /* Preseving the word1 of lmtst map table entry*/ 258 unsigned long flags; 259 struct sdp_node_info *sdp_info; 260 }; 261 262 enum rvu_pfvf_flags { 263 NIXLF_INITIALIZED = 0, 264 PF_SET_VF_MAC, 265 PF_SET_VF_CFG, 266 PF_SET_VF_TRUSTED, 267 }; 268 269 #define RVU_CLEAR_VF_PERM ~GENMASK(PF_SET_VF_TRUSTED, PF_SET_VF_MAC) 270 271 struct nix_txsch { 272 struct rsrc_bmap schq; 273 u8 lvl; 274 #define NIX_TXSCHQ_FREE BIT_ULL(1) 275 #define NIX_TXSCHQ_CFG_DONE BIT_ULL(0) 276 #define TXSCH_MAP_FUNC(__pfvf_map) ((__pfvf_map) & 0xFFFF) 277 #define TXSCH_MAP_FLAGS(__pfvf_map) ((__pfvf_map) >> 16) 278 #define TXSCH_MAP(__func, __flags) (((__func) & 0xFFFF) | ((__flags) << 16)) 279 #define TXSCH_SET_FLAG(__pfvf_map, flag) ((__pfvf_map) | ((flag) << 16)) 280 u32 *pfvf_map; 281 }; 282 283 struct nix_mark_format { 284 u8 total; 285 u8 in_use; 286 u32 *cfg; 287 }; 288 289 /* smq(flush) to tl1 cir/pir info */ 290 struct nix_smq_tree_ctx { 291 u64 cir_off; 292 u64 cir_val; 293 u64 pir_off; 294 u64 pir_val; 295 }; 296 297 /* smq flush context */ 298 struct nix_smq_flush_ctx { 299 int smq; 300 u16 tl1_schq; 301 u16 tl2_schq; 302 struct nix_smq_tree_ctx smq_tree_ctx[NIX_TXSCH_LVL_CNT]; 303 }; 304 305 struct npc_pkind { 306 struct rsrc_bmap rsrc; 307 u32 *pfchan_map; 308 }; 309 310 struct nix_flowkey { 311 #define NIX_FLOW_KEY_ALG_MAX 32 312 u32 flowkey[NIX_FLOW_KEY_ALG_MAX]; 313 int in_use; 314 }; 315 316 struct nix_lso { 317 u8 total; 318 u8 in_use; 319 }; 320 321 struct nix_txvlan { 322 #define NIX_TX_VTAG_DEF_MAX 0x400 323 struct rsrc_bmap rsrc; 324 u16 *entry2pfvf_map; 325 struct mutex rsrc_lock; /* Serialize resource alloc/free */ 326 }; 327 328 struct nix_ipolicer { 329 struct rsrc_bmap band_prof; 330 u16 *pfvf_map; 331 u16 *match_id; 332 u16 *ref_count; 333 }; 334 335 struct nix_hw { 336 int blkaddr; 337 struct rvu *rvu; 338 struct nix_txsch txsch[NIX_TXSCH_LVL_CNT]; /* Tx schedulers */ 339 struct nix_mcast mcast; 340 struct nix_flowkey flowkey; 341 struct nix_mark_format mark_format; 342 struct nix_lso lso; 343 struct nix_txvlan txvlan; 344 struct nix_ipolicer *ipolicer; 345 u64 *tx_credits; 346 }; 347 348 /* RVU block's capabilities or functionality, 349 * which vary by silicon version/skew. 350 */ 351 struct hw_cap { 352 /* Transmit side supported functionality */ 353 u8 nix_tx_aggr_lvl; /* Tx link's traffic aggregation level */ 354 u16 nix_txsch_per_cgx_lmac; /* Max Q's transmitting to CGX LMAC */ 355 u16 nix_txsch_per_lbk_lmac; /* Max Q's transmitting to LBK LMAC */ 356 u16 nix_txsch_per_sdp_lmac; /* Max Q's transmitting to SDP LMAC */ 357 bool nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */ 358 bool nix_shaping; /* Is shaping and coloring supported */ 359 bool nix_shaper_toggle_wait; /* Shaping toggle needs poll/wait */ 360 bool nix_tx_link_bp; /* Can link backpressure TL queues ? */ 361 bool nix_rx_multicast; /* Rx packet replication support */ 362 bool nix_common_dwrr_mtu; /* Common DWRR MTU for quantum config */ 363 bool per_pf_mbox_regs; /* PF mbox specified in per PF registers ? */ 364 bool programmable_chans; /* Channels programmable ? */ 365 bool ipolicer; 366 bool nix_multiple_dwrr_mtu; /* Multiple DWRR_MTU to choose from */ 367 bool npc_hash_extract; /* Hash extract enabled ? */ 368 bool npc_exact_match_enabled; /* Exact match supported ? */ 369 }; 370 371 struct rvu_hwinfo { 372 u8 total_pfs; /* MAX RVU PFs HW supports */ 373 u16 total_vfs; /* Max RVU VFs HW supports */ 374 u16 max_vfs_per_pf; /* Max VFs that can be attached to a PF */ 375 u8 cgx; 376 u8 lmac_per_cgx; 377 u16 cgx_chan_base; /* CGX base channel number */ 378 u16 lbk_chan_base; /* LBK base channel number */ 379 u16 sdp_chan_base; /* SDP base channel number */ 380 u16 cpt_chan_base; /* CPT base channel number */ 381 u8 cgx_links; 382 u8 lbk_links; 383 u8 sdp_links; 384 u8 cpt_links; /* Number of CPT links */ 385 u8 npc_kpus; /* No of parser units */ 386 u8 npc_pkinds; /* No of port kinds */ 387 u8 npc_intfs; /* No of interfaces */ 388 u8 npc_kpu_entries; /* No of KPU entries */ 389 u16 npc_counters; /* No of match stats counters */ 390 u32 lbk_bufsize; /* FIFO size supported by LBK */ 391 bool npc_ext_set; /* Extended register set */ 392 u64 npc_stat_ena; /* Match stats enable bit */ 393 394 struct hw_cap cap; 395 struct rvu_block block[BLK_COUNT]; /* Block info */ 396 struct nix_hw *nix; 397 struct rvu *rvu; 398 struct npc_pkind pkind; 399 struct npc_mcam mcam; 400 struct npc_exact_table *table; 401 }; 402 403 struct mbox_wq_info { 404 struct otx2_mbox mbox; 405 struct rvu_work *mbox_wrk; 406 407 struct otx2_mbox mbox_up; 408 struct rvu_work *mbox_wrk_up; 409 410 struct workqueue_struct *mbox_wq; 411 }; 412 413 struct rvu_fwdata { 414 #define RVU_FWDATA_HEADER_MAGIC 0xCFDA /* Custom Firmware Data*/ 415 #define RVU_FWDATA_VERSION 0x0001 416 u32 header_magic; 417 u32 version; /* version id */ 418 419 /* MAC address */ 420 #define PF_MACNUM_MAX 32 421 #define VF_MACNUM_MAX 256 422 u64 pf_macs[PF_MACNUM_MAX]; 423 u64 vf_macs[VF_MACNUM_MAX]; 424 u64 sclk; 425 u64 rclk; 426 u64 mcam_addr; 427 u64 mcam_sz; 428 u64 msixtr_base; 429 u32 ptp_ext_clk_rate; 430 u32 ptp_ext_tstamp; 431 #define FWDATA_RESERVED_MEM 1022 432 u64 reserved[FWDATA_RESERVED_MEM]; 433 #define CGX_MAX 9 434 #define CGX_LMACS_MAX 4 435 #define CGX_LMACS_USX 8 436 union { 437 struct cgx_lmac_fwdata_s 438 cgx_fw_data[CGX_MAX][CGX_LMACS_MAX]; 439 struct cgx_lmac_fwdata_s 440 cgx_fw_data_usx[CGX_MAX][CGX_LMACS_USX]; 441 }; 442 /* Do not add new fields below this line */ 443 }; 444 445 struct ptp; 446 447 /* KPU profile adapter structure gathering all KPU configuration data and abstracting out the 448 * source where it came from. 449 */ 450 struct npc_kpu_profile_adapter { 451 const char *name; 452 u64 version; 453 const struct npc_lt_def_cfg *lt_def; 454 const struct npc_kpu_profile_action *ikpu; /* array[pkinds] */ 455 const struct npc_kpu_profile *kpu; /* array[kpus] */ 456 struct npc_mcam_kex *mkex; 457 struct npc_mcam_kex_hash *mkex_hash; 458 bool custom; 459 size_t pkinds; 460 size_t kpus; 461 }; 462 463 #define RVU_SWITCH_LBK_CHAN 63 464 465 struct rvu_switch { 466 struct mutex switch_lock; /* Serialize flow installation */ 467 u32 used_entries; 468 u16 *entry2pcifunc; 469 u16 mode; 470 u16 start_entry; 471 }; 472 473 struct rvu { 474 void __iomem *afreg_base; 475 void __iomem *pfreg_base; 476 struct pci_dev *pdev; 477 struct device *dev; 478 struct rvu_hwinfo *hw; 479 struct rvu_pfvf *pf; 480 struct rvu_pfvf *hwvf; 481 struct mutex rsrc_lock; /* Serialize resource alloc/free */ 482 struct mutex alias_lock; /* Serialize bar2 alias access */ 483 int vfs; /* Number of VFs attached to RVU */ 484 int nix_blkaddr[MAX_NIX_BLKS]; 485 486 /* Mbox */ 487 struct mbox_wq_info afpf_wq_info; 488 struct mbox_wq_info afvf_wq_info; 489 490 /* PF FLR */ 491 struct rvu_work *flr_wrk; 492 struct workqueue_struct *flr_wq; 493 struct mutex flr_lock; /* Serialize FLRs */ 494 495 /* MSI-X */ 496 u16 num_vec; 497 char *irq_name; 498 bool *irq_allocated; 499 dma_addr_t msix_base_iova; 500 u64 msixtr_base_phy; /* Register reset value */ 501 502 /* CGX */ 503 #define PF_CGXMAP_BASE 1 /* PF 0 is reserved for RVU PF */ 504 u16 cgx_mapped_vfs; /* maximum CGX mapped VFs */ 505 u8 cgx_mapped_pfs; 506 u8 cgx_cnt_max; /* CGX port count max */ 507 u8 *pf2cgxlmac_map; /* pf to cgx_lmac map */ 508 u64 *cgxlmac2pf_map; /* bitmap of mapped pfs for 509 * every cgx lmac port 510 */ 511 unsigned long pf_notify_bmap; /* Flags for PF notification */ 512 void **cgx_idmap; /* cgx id to cgx data map table */ 513 struct work_struct cgx_evh_work; 514 struct workqueue_struct *cgx_evh_wq; 515 spinlock_t cgx_evq_lock; /* cgx event queue lock */ 516 struct list_head cgx_evq_head; /* cgx event queue head */ 517 struct mutex cgx_cfg_lock; /* serialize cgx configuration */ 518 519 char mkex_pfl_name[MKEX_NAME_LEN]; /* Configured MKEX profile name */ 520 char kpu_pfl_name[KPU_NAME_LEN]; /* Configured KPU profile name */ 521 522 /* Firmware data */ 523 struct rvu_fwdata *fwdata; 524 void *kpu_fwdata; 525 size_t kpu_fwdata_sz; 526 void __iomem *kpu_prfl_addr; 527 528 /* NPC KPU data */ 529 struct npc_kpu_profile_adapter kpu; 530 531 struct ptp *ptp; 532 533 int mcs_blk_cnt; 534 int cpt_pf_num; 535 536 #ifdef CONFIG_DEBUG_FS 537 struct rvu_debugfs rvu_dbg; 538 #endif 539 struct rvu_devlink *rvu_dl; 540 541 /* RVU switch implementation over NPC with DMAC rules */ 542 struct rvu_switch rswitch; 543 544 struct work_struct mcs_intr_work; 545 struct workqueue_struct *mcs_intr_wq; 546 struct list_head mcs_intrq_head; 547 /* mcs interrupt queue lock */ 548 spinlock_t mcs_intrq_lock; 549 /* CPT interrupt lock */ 550 spinlock_t cpt_intr_lock; 551 }; 552 553 static inline void rvu_write64(struct rvu *rvu, u64 block, u64 offset, u64 val) 554 { 555 writeq(val, rvu->afreg_base + ((block << 28) | offset)); 556 } 557 558 static inline u64 rvu_read64(struct rvu *rvu, u64 block, u64 offset) 559 { 560 return readq(rvu->afreg_base + ((block << 28) | offset)); 561 } 562 563 static inline void rvupf_write64(struct rvu *rvu, u64 offset, u64 val) 564 { 565 writeq(val, rvu->pfreg_base + offset); 566 } 567 568 static inline u64 rvupf_read64(struct rvu *rvu, u64 offset) 569 { 570 return readq(rvu->pfreg_base + offset); 571 } 572 573 static inline void rvu_bar2_sel_write64(struct rvu *rvu, u64 block, u64 offset, u64 val) 574 { 575 /* HW requires read back of RVU_AF_BAR2_SEL register to make sure completion of 576 * write operation. 577 */ 578 rvu_write64(rvu, block, offset, val); 579 rvu_read64(rvu, block, offset); 580 /* Barrier to ensure read completes before accessing LF registers */ 581 mb(); 582 } 583 584 /* Silicon revisions */ 585 static inline bool is_rvu_pre_96xx_C0(struct rvu *rvu) 586 { 587 struct pci_dev *pdev = rvu->pdev; 588 /* 96XX A0/B0, 95XX A0/A1/B0 chips */ 589 return ((pdev->revision == 0x00) || (pdev->revision == 0x01) || 590 (pdev->revision == 0x10) || (pdev->revision == 0x11) || 591 (pdev->revision == 0x14)); 592 } 593 594 static inline bool is_rvu_96xx_A0(struct rvu *rvu) 595 { 596 struct pci_dev *pdev = rvu->pdev; 597 598 return (pdev->revision == 0x00); 599 } 600 601 static inline bool is_rvu_96xx_B0(struct rvu *rvu) 602 { 603 struct pci_dev *pdev = rvu->pdev; 604 605 return (pdev->revision == 0x00) || (pdev->revision == 0x01); 606 } 607 608 static inline bool is_rvu_95xx_A0(struct rvu *rvu) 609 { 610 struct pci_dev *pdev = rvu->pdev; 611 612 return (pdev->revision == 0x10) || (pdev->revision == 0x11); 613 } 614 615 /* REVID for PCIe devices. 616 * Bits 0..1: minor pass, bit 3..2: major pass 617 * bits 7..4: midr id 618 */ 619 #define PCI_REVISION_ID_96XX 0x00 620 #define PCI_REVISION_ID_95XX 0x10 621 #define PCI_REVISION_ID_95XXN 0x20 622 #define PCI_REVISION_ID_98XX 0x30 623 #define PCI_REVISION_ID_95XXMM 0x40 624 #define PCI_REVISION_ID_95XXO 0xE0 625 626 static inline bool is_rvu_otx2(struct rvu *rvu) 627 { 628 struct pci_dev *pdev = rvu->pdev; 629 630 u8 midr = pdev->revision & 0xF0; 631 632 return (midr == PCI_REVISION_ID_96XX || midr == PCI_REVISION_ID_95XX || 633 midr == PCI_REVISION_ID_95XXN || midr == PCI_REVISION_ID_98XX || 634 midr == PCI_REVISION_ID_95XXMM || midr == PCI_REVISION_ID_95XXO); 635 } 636 637 static inline bool is_rvu_npc_hash_extract_en(struct rvu *rvu) 638 { 639 u64 npc_const3; 640 641 npc_const3 = rvu_read64(rvu, BLKADDR_NPC, NPC_AF_CONST3); 642 if (!(npc_const3 & BIT_ULL(62))) 643 return false; 644 645 return true; 646 } 647 648 static inline u16 rvu_nix_chan_cgx(struct rvu *rvu, u8 cgxid, 649 u8 lmacid, u8 chan) 650 { 651 u64 nix_const = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_CONST); 652 u16 cgx_chans = nix_const & 0xFFULL; 653 struct rvu_hwinfo *hw = rvu->hw; 654 655 if (!hw->cap.programmable_chans) 656 return NIX_CHAN_CGX_LMAC_CHX(cgxid, lmacid, chan); 657 658 return rvu->hw->cgx_chan_base + 659 (cgxid * hw->lmac_per_cgx + lmacid) * cgx_chans + chan; 660 } 661 662 static inline u16 rvu_nix_chan_lbk(struct rvu *rvu, u8 lbkid, 663 u8 chan) 664 { 665 u64 nix_const = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_CONST); 666 u16 lbk_chans = (nix_const >> 16) & 0xFFULL; 667 struct rvu_hwinfo *hw = rvu->hw; 668 669 if (!hw->cap.programmable_chans) 670 return NIX_CHAN_LBK_CHX(lbkid, chan); 671 672 return rvu->hw->lbk_chan_base + lbkid * lbk_chans + chan; 673 } 674 675 static inline u16 rvu_nix_chan_sdp(struct rvu *rvu, u8 chan) 676 { 677 struct rvu_hwinfo *hw = rvu->hw; 678 679 if (!hw->cap.programmable_chans) 680 return NIX_CHAN_SDP_CHX(chan); 681 682 return hw->sdp_chan_base + chan; 683 } 684 685 static inline u16 rvu_nix_chan_cpt(struct rvu *rvu, u8 chan) 686 { 687 return rvu->hw->cpt_chan_base + chan; 688 } 689 690 static inline bool is_rvu_supports_nix1(struct rvu *rvu) 691 { 692 struct pci_dev *pdev = rvu->pdev; 693 694 if (pdev->subsystem_device == PCI_SUBSYS_DEVID_98XX) 695 return true; 696 697 return false; 698 } 699 700 /* Function Prototypes 701 * RVU 702 */ 703 static inline bool is_afvf(u16 pcifunc) 704 { 705 return !(pcifunc & ~RVU_PFVF_FUNC_MASK); 706 } 707 708 static inline bool is_vf(u16 pcifunc) 709 { 710 return !!(pcifunc & RVU_PFVF_FUNC_MASK); 711 } 712 713 /* check if PF_FUNC is AF */ 714 static inline bool is_pffunc_af(u16 pcifunc) 715 { 716 return !pcifunc; 717 } 718 719 static inline bool is_rvu_fwdata_valid(struct rvu *rvu) 720 { 721 return (rvu->fwdata->header_magic == RVU_FWDATA_HEADER_MAGIC) && 722 (rvu->fwdata->version == RVU_FWDATA_VERSION); 723 } 724 725 int rvu_alloc_bitmap(struct rsrc_bmap *rsrc); 726 void rvu_free_bitmap(struct rsrc_bmap *rsrc); 727 int rvu_alloc_rsrc(struct rsrc_bmap *rsrc); 728 void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id); 729 bool is_rsrc_free(struct rsrc_bmap *rsrc, int id); 730 int rvu_rsrc_free_count(struct rsrc_bmap *rsrc); 731 int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc); 732 bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc); 733 u16 rvu_get_rsrc_mapcount(struct rvu_pfvf *pfvf, int blkaddr); 734 int rvu_get_pf(u16 pcifunc); 735 struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc); 736 void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf); 737 bool is_block_implemented(struct rvu_hwinfo *hw, int blkaddr); 738 bool is_pffunc_map_valid(struct rvu *rvu, u16 pcifunc, int blktype); 739 int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot); 740 int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf); 741 int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc); 742 int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero); 743 int rvu_get_num_lbk_chans(void); 744 int rvu_get_blkaddr_from_slot(struct rvu *rvu, int blktype, u16 pcifunc, 745 u16 global_slot, u16 *slot_in_block); 746 747 /* RVU HW reg validation */ 748 enum regmap_block { 749 TXSCHQ_HWREGMAP = 0, 750 MAX_HWREGMAP, 751 }; 752 753 bool rvu_check_valid_reg(int regmap, int regblk, u64 reg); 754 755 /* NPA/NIX AQ APIs */ 756 int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue, 757 int qsize, int inst_size, int res_size); 758 void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq); 759 760 /* SDP APIs */ 761 int rvu_sdp_init(struct rvu *rvu); 762 bool is_sdp_pfvf(u16 pcifunc); 763 bool is_sdp_pf(u16 pcifunc); 764 bool is_sdp_vf(u16 pcifunc); 765 766 /* CGX APIs */ 767 static inline bool is_pf_cgxmapped(struct rvu *rvu, u8 pf) 768 { 769 return (pf >= PF_CGXMAP_BASE && pf <= rvu->cgx_mapped_pfs) && 770 !is_sdp_pf(pf << RVU_PFVF_PF_SHIFT); 771 } 772 773 static inline void rvu_get_cgx_lmac_id(u8 map, u8 *cgx_id, u8 *lmac_id) 774 { 775 *cgx_id = (map >> 4) & 0xF; 776 *lmac_id = (map & 0xF); 777 } 778 779 static inline bool is_cgx_vf(struct rvu *rvu, u16 pcifunc) 780 { 781 return ((pcifunc & RVU_PFVF_FUNC_MASK) && 782 is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc))); 783 } 784 785 #define M(_name, _id, fn_name, req, rsp) \ 786 int rvu_mbox_handler_ ## fn_name(struct rvu *, struct req *, struct rsp *); 787 MBOX_MESSAGES 788 #undef M 789 790 int rvu_cgx_init(struct rvu *rvu); 791 int rvu_cgx_exit(struct rvu *rvu); 792 void *rvu_cgx_pdata(u8 cgx_id, struct rvu *rvu); 793 int rvu_cgx_config_rxtx(struct rvu *rvu, u16 pcifunc, bool start); 794 void rvu_cgx_enadis_rx_bp(struct rvu *rvu, int pf, bool enable); 795 int rvu_cgx_start_stop_io(struct rvu *rvu, u16 pcifunc, bool start); 796 int rvu_cgx_nix_cuml_stats(struct rvu *rvu, void *cgxd, int lmac_id, int index, 797 int rxtxflag, u64 *stat); 798 void rvu_cgx_disable_dmac_entries(struct rvu *rvu, u16 pcifunc); 799 800 /* NPA APIs */ 801 int rvu_npa_init(struct rvu *rvu); 802 void rvu_npa_freemem(struct rvu *rvu); 803 void rvu_npa_lf_teardown(struct rvu *rvu, u16 pcifunc, int npalf); 804 int rvu_npa_aq_enq_inst(struct rvu *rvu, struct npa_aq_enq_req *req, 805 struct npa_aq_enq_rsp *rsp); 806 807 /* NIX APIs */ 808 bool is_nixlf_attached(struct rvu *rvu, u16 pcifunc); 809 int rvu_nix_init(struct rvu *rvu); 810 int rvu_nix_reserve_mark_format(struct rvu *rvu, struct nix_hw *nix_hw, 811 int blkaddr, u32 cfg); 812 void rvu_nix_freemem(struct rvu *rvu); 813 int rvu_get_nixlf_count(struct rvu *rvu); 814 void rvu_nix_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int npalf); 815 int nix_get_nixlf(struct rvu *rvu, u16 pcifunc, int *nixlf, int *nix_blkaddr); 816 int nix_update_mce_list(struct rvu *rvu, u16 pcifunc, 817 struct nix_mce_list *mce_list, 818 int mce_idx, int mcam_index, bool add); 819 void nix_get_mce_list(struct rvu *rvu, u16 pcifunc, int type, 820 struct nix_mce_list **mce_list, int *mce_idx); 821 struct nix_hw *get_nix_hw(struct rvu_hwinfo *hw, int blkaddr); 822 int rvu_get_next_nix_blkaddr(struct rvu *rvu, int blkaddr); 823 void rvu_nix_reset_mac(struct rvu_pfvf *pfvf, int pcifunc); 824 int nix_get_struct_ptrs(struct rvu *rvu, u16 pcifunc, 825 struct nix_hw **nix_hw, int *blkaddr); 826 int rvu_nix_setup_ratelimit_aggr(struct rvu *rvu, u16 pcifunc, 827 u16 rq_idx, u16 match_id); 828 int nix_aq_context_read(struct rvu *rvu, struct nix_hw *nix_hw, 829 struct nix_cn10k_aq_enq_req *aq_req, 830 struct nix_cn10k_aq_enq_rsp *aq_rsp, 831 u16 pcifunc, u8 ctype, u32 qidx); 832 int rvu_get_nix_blkaddr(struct rvu *rvu, u16 pcifunc); 833 int nix_get_dwrr_mtu_reg(struct rvu_hwinfo *hw, int smq_link_type); 834 u32 convert_dwrr_mtu_to_bytes(u8 dwrr_mtu); 835 u32 convert_bytes_to_dwrr_mtu(u32 bytes); 836 void rvu_nix_tx_tl2_cfg(struct rvu *rvu, int blkaddr, u16 pcifunc, 837 struct nix_txsch *txsch, bool enable); 838 839 /* NPC APIs */ 840 void rvu_npc_freemem(struct rvu *rvu); 841 int rvu_npc_get_pkind(struct rvu *rvu, u16 pf); 842 void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf); 843 int npc_config_ts_kpuaction(struct rvu *rvu, int pf, u16 pcifunc, bool en); 844 void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc, 845 int nixlf, u64 chan, u8 *mac_addr); 846 void rvu_npc_install_promisc_entry(struct rvu *rvu, u16 pcifunc, 847 int nixlf, u64 chan, u8 chan_cnt); 848 void rvu_npc_enable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf, 849 bool enable); 850 void rvu_npc_install_bcast_match_entry(struct rvu *rvu, u16 pcifunc, 851 int nixlf, u64 chan); 852 void rvu_npc_enable_bcast_entry(struct rvu *rvu, u16 pcifunc, int nixlf, 853 bool enable); 854 void rvu_npc_install_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf, 855 u64 chan); 856 void rvu_npc_enable_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf, 857 bool enable); 858 859 void npc_enadis_default_mce_entry(struct rvu *rvu, u16 pcifunc, 860 int nixlf, int type, bool enable); 861 void rvu_npc_disable_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 862 bool rvu_npc_enable_mcam_by_entry_index(struct rvu *rvu, int entry, int intf, bool enable); 863 void rvu_npc_free_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 864 void rvu_npc_disable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 865 void rvu_npc_enable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 866 void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, u16 pcifunc, int nixlf, 867 int group, int alg_idx, int mcam_index); 868 869 void rvu_npc_get_mcam_entry_alloc_info(struct rvu *rvu, u16 pcifunc, 870 int blkaddr, int *alloc_cnt, 871 int *enable_cnt); 872 void rvu_npc_get_mcam_counter_alloc_info(struct rvu *rvu, u16 pcifunc, 873 int blkaddr, int *alloc_cnt, 874 int *enable_cnt); 875 bool is_npc_intf_tx(u8 intf); 876 bool is_npc_intf_rx(u8 intf); 877 bool is_npc_interface_valid(struct rvu *rvu, u8 intf); 878 int rvu_npc_get_tx_nibble_cfg(struct rvu *rvu, u64 nibble_ena); 879 int npc_flow_steering_init(struct rvu *rvu, int blkaddr); 880 const char *npc_get_field_name(u8 hdr); 881 int npc_get_bank(struct npc_mcam *mcam, int index); 882 void npc_mcam_enable_flows(struct rvu *rvu, u16 target); 883 void npc_mcam_disable_flows(struct rvu *rvu, u16 target); 884 void npc_enable_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, 885 int blkaddr, int index, bool enable); 886 void npc_read_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, 887 int blkaddr, u16 src, struct mcam_entry *entry, 888 u8 *intf, u8 *ena); 889 bool is_cgx_config_permitted(struct rvu *rvu, u16 pcifunc); 890 bool is_mac_feature_supported(struct rvu *rvu, int pf, int feature); 891 u32 rvu_cgx_get_fifolen(struct rvu *rvu); 892 void *rvu_first_cgx_pdata(struct rvu *rvu); 893 int cgxlmac_to_pf(struct rvu *rvu, int cgx_id, int lmac_id); 894 int rvu_cgx_config_tx(void *cgxd, int lmac_id, bool enable); 895 int rvu_cgx_prio_flow_ctrl_cfg(struct rvu *rvu, u16 pcifunc, u8 tx_pause, u8 rx_pause, 896 u16 pfc_en); 897 int rvu_cgx_cfg_pause_frm(struct rvu *rvu, u16 pcifunc, u8 tx_pause, u8 rx_pause); 898 void rvu_mac_reset(struct rvu *rvu, u16 pcifunc); 899 u32 rvu_cgx_get_lmac_fifolen(struct rvu *rvu, int cgx, int lmac); 900 int npc_get_nixlf_mcam_index(struct npc_mcam *mcam, u16 pcifunc, int nixlf, 901 int type); 902 bool is_mcam_entry_enabled(struct rvu *rvu, struct npc_mcam *mcam, int blkaddr, 903 int index); 904 int rvu_npc_init(struct rvu *rvu); 905 int npc_install_mcam_drop_rule(struct rvu *rvu, int mcam_idx, u16 *counter_idx, 906 u64 chan_val, u64 chan_mask, u64 exact_val, u64 exact_mask, 907 u64 bcast_mcast_val, u64 bcast_mcast_mask); 908 void npc_mcam_rsrcs_reserve(struct rvu *rvu, int blkaddr, int entry_idx); 909 bool npc_is_feature_supported(struct rvu *rvu, u64 features, u8 intf); 910 911 /* CPT APIs */ 912 int rvu_cpt_register_interrupts(struct rvu *rvu); 913 void rvu_cpt_unregister_interrupts(struct rvu *rvu); 914 int rvu_cpt_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int lf, 915 int slot); 916 int rvu_cpt_ctx_flush(struct rvu *rvu, u16 pcifunc); 917 int rvu_cpt_init(struct rvu *rvu); 918 919 #define NDC_AF_BANK_MASK GENMASK_ULL(7, 0) 920 #define NDC_AF_BANK_LINE_MASK GENMASK_ULL(31, 16) 921 922 /* CN10K RVU */ 923 int rvu_set_channels_base(struct rvu *rvu); 924 void rvu_program_channels(struct rvu *rvu); 925 926 /* CN10K NIX */ 927 void rvu_nix_block_cn10k_init(struct rvu *rvu, struct nix_hw *nix_hw); 928 929 /* CN10K RVU - LMT*/ 930 void rvu_reset_lmt_map_tbl(struct rvu *rvu, u16 pcifunc); 931 932 #ifdef CONFIG_DEBUG_FS 933 void rvu_dbg_init(struct rvu *rvu); 934 void rvu_dbg_exit(struct rvu *rvu); 935 #else 936 static inline void rvu_dbg_init(struct rvu *rvu) {} 937 static inline void rvu_dbg_exit(struct rvu *rvu) {} 938 #endif 939 940 int rvu_ndc_fix_locked_cacheline(struct rvu *rvu, int blkaddr); 941 942 /* RVU Switch */ 943 void rvu_switch_enable(struct rvu *rvu); 944 void rvu_switch_disable(struct rvu *rvu); 945 void rvu_switch_update_rules(struct rvu *rvu, u16 pcifunc); 946 947 int rvu_npc_set_parse_mode(struct rvu *rvu, u16 pcifunc, u64 mode, u8 dir, 948 u64 pkind, u8 var_len_off, u8 var_len_off_mask, 949 u8 shift_dir); 950 int rvu_get_hwvf(struct rvu *rvu, int pcifunc); 951 952 /* CN10K MCS */ 953 int rvu_mcs_init(struct rvu *rvu); 954 int rvu_mcs_flr_handler(struct rvu *rvu, u16 pcifunc); 955 void rvu_mcs_ptp_cfg(struct rvu *rvu, u8 rpm_id, u8 lmac_id, bool ena); 956 void rvu_mcs_exit(struct rvu *rvu); 957 958 #endif /* RVU_H */ 959