1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88e6xxx Ethernet switch single-chip support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 8 * 9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 11 */ 12 13 #include <linux/bitfield.h> 14 #include <linux/delay.h> 15 #include <linux/dsa/mv88e6xxx.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/if_bridge.h> 19 #include <linux/interrupt.h> 20 #include <linux/irq.h> 21 #include <linux/irqdomain.h> 22 #include <linux/jiffies.h> 23 #include <linux/list.h> 24 #include <linux/mdio.h> 25 #include <linux/module.h> 26 #include <linux/of_device.h> 27 #include <linux/of_irq.h> 28 #include <linux/of_mdio.h> 29 #include <linux/platform_data/mv88e6xxx.h> 30 #include <linux/netdevice.h> 31 #include <linux/gpio/consumer.h> 32 #include <linux/phylink.h> 33 #include <net/dsa.h> 34 35 #include "chip.h" 36 #include "devlink.h" 37 #include "global1.h" 38 #include "global2.h" 39 #include "hwtstamp.h" 40 #include "phy.h" 41 #include "port.h" 42 #include "ptp.h" 43 #include "serdes.h" 44 #include "smi.h" 45 46 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 47 { 48 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 49 dev_err(chip->dev, "Switch registers lock not held!\n"); 50 dump_stack(); 51 } 52 } 53 54 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 55 { 56 int err; 57 58 assert_reg_lock(chip); 59 60 err = mv88e6xxx_smi_read(chip, addr, reg, val); 61 if (err) 62 return err; 63 64 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 65 addr, reg, *val); 66 67 return 0; 68 } 69 70 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 71 { 72 int err; 73 74 assert_reg_lock(chip); 75 76 err = mv88e6xxx_smi_write(chip, addr, reg, val); 77 if (err) 78 return err; 79 80 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 81 addr, reg, val); 82 83 return 0; 84 } 85 86 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 87 u16 mask, u16 val) 88 { 89 const unsigned long timeout = jiffies + msecs_to_jiffies(50); 90 u16 data; 91 int err; 92 int i; 93 94 /* There's no bus specific operation to wait for a mask. Even 95 * if the initial poll takes longer than 50ms, always do at 96 * least one more attempt. 97 */ 98 for (i = 0; time_before(jiffies, timeout) || (i < 2); i++) { 99 err = mv88e6xxx_read(chip, addr, reg, &data); 100 if (err) 101 return err; 102 103 if ((data & mask) == val) 104 return 0; 105 106 if (i < 2) 107 cpu_relax(); 108 else 109 usleep_range(1000, 2000); 110 } 111 112 err = mv88e6xxx_read(chip, addr, reg, &data); 113 if (err) 114 return err; 115 116 if ((data & mask) == val) 117 return 0; 118 119 dev_err(chip->dev, "Timeout while waiting for switch\n"); 120 return -ETIMEDOUT; 121 } 122 123 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 124 int bit, int val) 125 { 126 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit), 127 val ? BIT(bit) : 0x0000); 128 } 129 130 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 131 { 132 struct mv88e6xxx_mdio_bus *mdio_bus; 133 134 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 135 list); 136 if (!mdio_bus) 137 return NULL; 138 139 return mdio_bus->bus; 140 } 141 142 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 143 { 144 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 145 unsigned int n = d->hwirq; 146 147 chip->g1_irq.masked |= (1 << n); 148 } 149 150 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 151 { 152 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 153 unsigned int n = d->hwirq; 154 155 chip->g1_irq.masked &= ~(1 << n); 156 } 157 158 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 159 { 160 unsigned int nhandled = 0; 161 unsigned int sub_irq; 162 unsigned int n; 163 u16 reg; 164 u16 ctl1; 165 int err; 166 167 mv88e6xxx_reg_lock(chip); 168 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 169 mv88e6xxx_reg_unlock(chip); 170 171 if (err) 172 goto out; 173 174 do { 175 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 176 if (reg & (1 << n)) { 177 sub_irq = irq_find_mapping(chip->g1_irq.domain, 178 n); 179 handle_nested_irq(sub_irq); 180 ++nhandled; 181 } 182 } 183 184 mv88e6xxx_reg_lock(chip); 185 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1); 186 if (err) 187 goto unlock; 188 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 189 unlock: 190 mv88e6xxx_reg_unlock(chip); 191 if (err) 192 goto out; 193 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0); 194 } while (reg & ctl1); 195 196 out: 197 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 198 } 199 200 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 201 { 202 struct mv88e6xxx_chip *chip = dev_id; 203 204 return mv88e6xxx_g1_irq_thread_work(chip); 205 } 206 207 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 208 { 209 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 210 211 mv88e6xxx_reg_lock(chip); 212 } 213 214 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 215 { 216 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 217 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 218 u16 reg; 219 int err; 220 221 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 222 if (err) 223 goto out; 224 225 reg &= ~mask; 226 reg |= (~chip->g1_irq.masked & mask); 227 228 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 229 if (err) 230 goto out; 231 232 out: 233 mv88e6xxx_reg_unlock(chip); 234 } 235 236 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 237 .name = "mv88e6xxx-g1", 238 .irq_mask = mv88e6xxx_g1_irq_mask, 239 .irq_unmask = mv88e6xxx_g1_irq_unmask, 240 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 241 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 242 }; 243 244 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 245 unsigned int irq, 246 irq_hw_number_t hwirq) 247 { 248 struct mv88e6xxx_chip *chip = d->host_data; 249 250 irq_set_chip_data(irq, d->host_data); 251 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 252 irq_set_noprobe(irq); 253 254 return 0; 255 } 256 257 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 258 .map = mv88e6xxx_g1_irq_domain_map, 259 .xlate = irq_domain_xlate_twocell, 260 }; 261 262 /* To be called with reg_lock held */ 263 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 264 { 265 int irq, virq; 266 u16 mask; 267 268 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 269 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 270 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 271 272 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 273 virq = irq_find_mapping(chip->g1_irq.domain, irq); 274 irq_dispose_mapping(virq); 275 } 276 277 irq_domain_remove(chip->g1_irq.domain); 278 } 279 280 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 281 { 282 /* 283 * free_irq must be called without reg_lock taken because the irq 284 * handler takes this lock, too. 285 */ 286 free_irq(chip->irq, chip); 287 288 mv88e6xxx_reg_lock(chip); 289 mv88e6xxx_g1_irq_free_common(chip); 290 mv88e6xxx_reg_unlock(chip); 291 } 292 293 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 294 { 295 int err, irq, virq; 296 u16 reg, mask; 297 298 chip->g1_irq.nirqs = chip->info->g1_irqs; 299 chip->g1_irq.domain = irq_domain_add_simple( 300 NULL, chip->g1_irq.nirqs, 0, 301 &mv88e6xxx_g1_irq_domain_ops, chip); 302 if (!chip->g1_irq.domain) 303 return -ENOMEM; 304 305 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 306 irq_create_mapping(chip->g1_irq.domain, irq); 307 308 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 309 chip->g1_irq.masked = ~0; 310 311 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 312 if (err) 313 goto out_mapping; 314 315 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 316 317 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 318 if (err) 319 goto out_disable; 320 321 /* Reading the interrupt status clears (most of) them */ 322 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 323 if (err) 324 goto out_disable; 325 326 return 0; 327 328 out_disable: 329 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 330 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 331 332 out_mapping: 333 for (irq = 0; irq < 16; irq++) { 334 virq = irq_find_mapping(chip->g1_irq.domain, irq); 335 irq_dispose_mapping(virq); 336 } 337 338 irq_domain_remove(chip->g1_irq.domain); 339 340 return err; 341 } 342 343 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 344 { 345 static struct lock_class_key lock_key; 346 static struct lock_class_key request_key; 347 int err; 348 349 err = mv88e6xxx_g1_irq_setup_common(chip); 350 if (err) 351 return err; 352 353 /* These lock classes tells lockdep that global 1 irqs are in 354 * a different category than their parent GPIO, so it won't 355 * report false recursion. 356 */ 357 irq_set_lockdep_class(chip->irq, &lock_key, &request_key); 358 359 snprintf(chip->irq_name, sizeof(chip->irq_name), 360 "mv88e6xxx-%s", dev_name(chip->dev)); 361 362 mv88e6xxx_reg_unlock(chip); 363 err = request_threaded_irq(chip->irq, NULL, 364 mv88e6xxx_g1_irq_thread_fn, 365 IRQF_ONESHOT | IRQF_SHARED, 366 chip->irq_name, chip); 367 mv88e6xxx_reg_lock(chip); 368 if (err) 369 mv88e6xxx_g1_irq_free_common(chip); 370 371 return err; 372 } 373 374 static void mv88e6xxx_irq_poll(struct kthread_work *work) 375 { 376 struct mv88e6xxx_chip *chip = container_of(work, 377 struct mv88e6xxx_chip, 378 irq_poll_work.work); 379 mv88e6xxx_g1_irq_thread_work(chip); 380 381 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 382 msecs_to_jiffies(100)); 383 } 384 385 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 386 { 387 int err; 388 389 err = mv88e6xxx_g1_irq_setup_common(chip); 390 if (err) 391 return err; 392 393 kthread_init_delayed_work(&chip->irq_poll_work, 394 mv88e6xxx_irq_poll); 395 396 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev)); 397 if (IS_ERR(chip->kworker)) 398 return PTR_ERR(chip->kworker); 399 400 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 401 msecs_to_jiffies(100)); 402 403 return 0; 404 } 405 406 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 407 { 408 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 409 kthread_destroy_worker(chip->kworker); 410 411 mv88e6xxx_reg_lock(chip); 412 mv88e6xxx_g1_irq_free_common(chip); 413 mv88e6xxx_reg_unlock(chip); 414 } 415 416 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip, 417 int port, phy_interface_t interface) 418 { 419 int err; 420 421 if (chip->info->ops->port_set_rgmii_delay) { 422 err = chip->info->ops->port_set_rgmii_delay(chip, port, 423 interface); 424 if (err && err != -EOPNOTSUPP) 425 return err; 426 } 427 428 if (chip->info->ops->port_set_cmode) { 429 err = chip->info->ops->port_set_cmode(chip, port, 430 interface); 431 if (err && err != -EOPNOTSUPP) 432 return err; 433 } 434 435 return 0; 436 } 437 438 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 439 int link, int speed, int duplex, int pause, 440 phy_interface_t mode) 441 { 442 int err; 443 444 if (!chip->info->ops->port_set_link) 445 return 0; 446 447 /* Port's MAC control must not be changed unless the link is down */ 448 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 449 if (err) 450 return err; 451 452 if (chip->info->ops->port_set_speed_duplex) { 453 err = chip->info->ops->port_set_speed_duplex(chip, port, 454 speed, duplex); 455 if (err && err != -EOPNOTSUPP) 456 goto restore_link; 457 } 458 459 if (chip->info->ops->port_set_pause) { 460 err = chip->info->ops->port_set_pause(chip, port, pause); 461 if (err) 462 goto restore_link; 463 } 464 465 err = mv88e6xxx_port_config_interface(chip, port, mode); 466 restore_link: 467 if (chip->info->ops->port_set_link(chip, port, link)) 468 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 469 470 return err; 471 } 472 473 static int mv88e6xxx_phy_is_internal(struct mv88e6xxx_chip *chip, int port) 474 { 475 return port >= chip->info->internal_phys_offset && 476 port < chip->info->num_internal_phys + 477 chip->info->internal_phys_offset; 478 } 479 480 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port) 481 { 482 u16 reg; 483 int err; 484 485 /* The 88e6250 family does not have the PHY detect bit. Instead, 486 * report whether the port is internal. 487 */ 488 if (chip->info->family == MV88E6XXX_FAMILY_6250) 489 return mv88e6xxx_phy_is_internal(chip, port); 490 491 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 492 if (err) { 493 dev_err(chip->dev, 494 "p%d: %s: failed to read port status\n", 495 port, __func__); 496 return err; 497 } 498 499 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT); 500 } 501 502 static int mv88e6xxx_serdes_pcs_get_state(struct dsa_switch *ds, int port, 503 struct phylink_link_state *state) 504 { 505 struct mv88e6xxx_chip *chip = ds->priv; 506 int lane; 507 int err; 508 509 mv88e6xxx_reg_lock(chip); 510 lane = mv88e6xxx_serdes_get_lane(chip, port); 511 if (lane >= 0 && chip->info->ops->serdes_pcs_get_state) 512 err = chip->info->ops->serdes_pcs_get_state(chip, port, lane, 513 state); 514 else 515 err = -EOPNOTSUPP; 516 mv88e6xxx_reg_unlock(chip); 517 518 return err; 519 } 520 521 static int mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port, 522 unsigned int mode, 523 phy_interface_t interface, 524 const unsigned long *advertise) 525 { 526 const struct mv88e6xxx_ops *ops = chip->info->ops; 527 int lane; 528 529 if (ops->serdes_pcs_config) { 530 lane = mv88e6xxx_serdes_get_lane(chip, port); 531 if (lane >= 0) 532 return ops->serdes_pcs_config(chip, port, lane, mode, 533 interface, advertise); 534 } 535 536 return 0; 537 } 538 539 static void mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch *ds, int port) 540 { 541 struct mv88e6xxx_chip *chip = ds->priv; 542 const struct mv88e6xxx_ops *ops; 543 int err = 0; 544 int lane; 545 546 ops = chip->info->ops; 547 548 if (ops->serdes_pcs_an_restart) { 549 mv88e6xxx_reg_lock(chip); 550 lane = mv88e6xxx_serdes_get_lane(chip, port); 551 if (lane >= 0) 552 err = ops->serdes_pcs_an_restart(chip, port, lane); 553 mv88e6xxx_reg_unlock(chip); 554 555 if (err) 556 dev_err(ds->dev, "p%d: failed to restart AN\n", port); 557 } 558 } 559 560 static int mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port, 561 unsigned int mode, 562 int speed, int duplex) 563 { 564 const struct mv88e6xxx_ops *ops = chip->info->ops; 565 int lane; 566 567 if (!phylink_autoneg_inband(mode) && ops->serdes_pcs_link_up) { 568 lane = mv88e6xxx_serdes_get_lane(chip, port); 569 if (lane >= 0) 570 return ops->serdes_pcs_link_up(chip, port, lane, 571 speed, duplex); 572 } 573 574 return 0; 575 } 576 577 static const u8 mv88e6185_phy_interface_modes[] = { 578 [MV88E6185_PORT_STS_CMODE_GMII_FD] = PHY_INTERFACE_MODE_GMII, 579 [MV88E6185_PORT_STS_CMODE_MII_100_FD_PS] = PHY_INTERFACE_MODE_MII, 580 [MV88E6185_PORT_STS_CMODE_MII_100] = PHY_INTERFACE_MODE_MII, 581 [MV88E6185_PORT_STS_CMODE_MII_10] = PHY_INTERFACE_MODE_MII, 582 [MV88E6185_PORT_STS_CMODE_SERDES] = PHY_INTERFACE_MODE_1000BASEX, 583 [MV88E6185_PORT_STS_CMODE_1000BASE_X] = PHY_INTERFACE_MODE_1000BASEX, 584 [MV88E6185_PORT_STS_CMODE_PHY] = PHY_INTERFACE_MODE_SGMII, 585 }; 586 587 static void mv88e6095_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 588 struct phylink_config *config) 589 { 590 u8 cmode = chip->ports[port].cmode; 591 592 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100; 593 594 if (mv88e6xxx_phy_is_internal(chip, port)) { 595 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 596 } else { 597 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) && 598 mv88e6185_phy_interface_modes[cmode]) 599 __set_bit(mv88e6185_phy_interface_modes[cmode], 600 config->supported_interfaces); 601 602 config->mac_capabilities |= MAC_1000FD; 603 } 604 } 605 606 static void mv88e6185_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 607 struct phylink_config *config) 608 { 609 u8 cmode = chip->ports[port].cmode; 610 611 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) && 612 mv88e6185_phy_interface_modes[cmode]) 613 __set_bit(mv88e6185_phy_interface_modes[cmode], 614 config->supported_interfaces); 615 616 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 617 MAC_1000FD; 618 } 619 620 static const u8 mv88e6xxx_phy_interface_modes[] = { 621 [MV88E6XXX_PORT_STS_CMODE_MII_PHY] = PHY_INTERFACE_MODE_REVMII, 622 [MV88E6XXX_PORT_STS_CMODE_MII] = PHY_INTERFACE_MODE_MII, 623 [MV88E6XXX_PORT_STS_CMODE_GMII] = PHY_INTERFACE_MODE_GMII, 624 [MV88E6XXX_PORT_STS_CMODE_RMII_PHY] = PHY_INTERFACE_MODE_REVRMII, 625 [MV88E6XXX_PORT_STS_CMODE_RMII] = PHY_INTERFACE_MODE_RMII, 626 [MV88E6XXX_PORT_STS_CMODE_100BASEX] = PHY_INTERFACE_MODE_100BASEX, 627 [MV88E6XXX_PORT_STS_CMODE_1000BASEX] = PHY_INTERFACE_MODE_1000BASEX, 628 [MV88E6XXX_PORT_STS_CMODE_SGMII] = PHY_INTERFACE_MODE_SGMII, 629 /* higher interface modes are not needed here, since ports supporting 630 * them are writable, and so the supported interfaces are filled in the 631 * corresponding .phylink_set_interfaces() implementation below 632 */ 633 }; 634 635 static void mv88e6xxx_translate_cmode(u8 cmode, unsigned long *supported) 636 { 637 if (cmode < ARRAY_SIZE(mv88e6xxx_phy_interface_modes) && 638 mv88e6xxx_phy_interface_modes[cmode]) 639 __set_bit(mv88e6xxx_phy_interface_modes[cmode], supported); 640 else if (cmode == MV88E6XXX_PORT_STS_CMODE_RGMII) 641 phy_interface_set_rgmii(supported); 642 } 643 644 static void mv88e6250_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 645 struct phylink_config *config) 646 { 647 unsigned long *supported = config->supported_interfaces; 648 649 /* Translate the default cmode */ 650 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 651 652 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100; 653 } 654 655 static int mv88e6352_get_port4_serdes_cmode(struct mv88e6xxx_chip *chip) 656 { 657 u16 reg, val; 658 int err; 659 660 err = mv88e6xxx_port_read(chip, 4, MV88E6XXX_PORT_STS, ®); 661 if (err) 662 return err; 663 664 /* If PHY_DETECT is zero, then we are not in auto-media mode */ 665 if (!(reg & MV88E6XXX_PORT_STS_PHY_DETECT)) 666 return 0xf; 667 668 val = reg & ~MV88E6XXX_PORT_STS_PHY_DETECT; 669 err = mv88e6xxx_port_write(chip, 4, MV88E6XXX_PORT_STS, val); 670 if (err) 671 return err; 672 673 err = mv88e6xxx_port_read(chip, 4, MV88E6XXX_PORT_STS, &val); 674 if (err) 675 return err; 676 677 /* Restore PHY_DETECT value */ 678 err = mv88e6xxx_port_write(chip, 4, MV88E6XXX_PORT_STS, reg); 679 if (err) 680 return err; 681 682 return val & MV88E6XXX_PORT_STS_CMODE_MASK; 683 } 684 685 static void mv88e6352_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 686 struct phylink_config *config) 687 { 688 unsigned long *supported = config->supported_interfaces; 689 int err, cmode; 690 691 /* Translate the default cmode */ 692 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 693 694 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 695 MAC_1000FD; 696 697 /* Port 4 supports automedia if the serdes is associated with it. */ 698 if (port == 4) { 699 err = mv88e6352_g2_scratch_port_has_serdes(chip, port); 700 if (err < 0) 701 dev_err(chip->dev, "p%d: failed to read scratch\n", 702 port); 703 if (err <= 0) 704 return; 705 706 cmode = mv88e6352_get_port4_serdes_cmode(chip); 707 if (cmode < 0) 708 dev_err(chip->dev, "p%d: failed to read serdes cmode\n", 709 port); 710 else 711 mv88e6xxx_translate_cmode(cmode, supported); 712 } 713 } 714 715 static void mv88e6341_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 716 struct phylink_config *config) 717 { 718 unsigned long *supported = config->supported_interfaces; 719 720 /* Translate the default cmode */ 721 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 722 723 /* No ethtool bits for 200Mbps */ 724 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 725 MAC_1000FD; 726 727 /* The C_Mode field is programmable on port 5 */ 728 if (port == 5) { 729 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 730 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 731 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 732 733 config->mac_capabilities |= MAC_2500FD; 734 } 735 } 736 737 static void mv88e6390_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 738 struct phylink_config *config) 739 { 740 unsigned long *supported = config->supported_interfaces; 741 742 /* Translate the default cmode */ 743 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 744 745 /* No ethtool bits for 200Mbps */ 746 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 747 MAC_1000FD; 748 749 /* The C_Mode field is programmable on ports 9 and 10 */ 750 if (port == 9 || port == 10) { 751 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 752 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 753 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 754 755 config->mac_capabilities |= MAC_2500FD; 756 } 757 } 758 759 static void mv88e6390x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 760 struct phylink_config *config) 761 { 762 unsigned long *supported = config->supported_interfaces; 763 764 mv88e6390_phylink_get_caps(chip, port, config); 765 766 /* For the 6x90X, ports 2-7 can be in automedia mode. 767 * (Note that 6x90 doesn't support RXAUI nor XAUI). 768 * 769 * Port 2 can also support 1000BASE-X in automedia mode if port 9 is 770 * configured for 1000BASE-X, SGMII or 2500BASE-X. 771 * Port 3-4 can also support 1000BASE-X in automedia mode if port 9 is 772 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X. 773 * 774 * Port 5 can also support 1000BASE-X in automedia mode if port 10 is 775 * configured for 1000BASE-X, SGMII or 2500BASE-X. 776 * Port 6-7 can also support 1000BASE-X in automedia mode if port 10 is 777 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X. 778 * 779 * For now, be permissive (as the old code was) and allow 1000BASE-X 780 * on ports 2..7. 781 */ 782 if (port >= 2 && port <= 7) 783 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 784 785 /* The C_Mode field can also be programmed for 10G speeds */ 786 if (port == 9 || port == 10) { 787 __set_bit(PHY_INTERFACE_MODE_XAUI, supported); 788 __set_bit(PHY_INTERFACE_MODE_RXAUI, supported); 789 790 config->mac_capabilities |= MAC_10000FD; 791 } 792 } 793 794 static void mv88e6393x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 795 struct phylink_config *config) 796 { 797 unsigned long *supported = config->supported_interfaces; 798 bool is_6191x = 799 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X; 800 bool is_6361 = 801 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361; 802 803 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 804 805 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 806 MAC_1000FD; 807 808 /* The C_Mode field can be programmed for ports 0, 9 and 10 */ 809 if (port == 0 || port == 9 || port == 10) { 810 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 811 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 812 813 /* 6191X supports >1G modes only on port 10 */ 814 if (!is_6191x || port == 10) { 815 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 816 config->mac_capabilities |= MAC_2500FD; 817 818 /* 6361 only supports up to 2500BaseX */ 819 if (!is_6361) { 820 __set_bit(PHY_INTERFACE_MODE_5GBASER, supported); 821 __set_bit(PHY_INTERFACE_MODE_10GBASER, supported); 822 __set_bit(PHY_INTERFACE_MODE_USXGMII, supported); 823 config->mac_capabilities |= MAC_5000FD | 824 MAC_10000FD; 825 } 826 } 827 } 828 829 if (port == 0) { 830 __set_bit(PHY_INTERFACE_MODE_RMII, supported); 831 __set_bit(PHY_INTERFACE_MODE_RGMII, supported); 832 __set_bit(PHY_INTERFACE_MODE_RGMII_ID, supported); 833 __set_bit(PHY_INTERFACE_MODE_RGMII_RXID, supported); 834 __set_bit(PHY_INTERFACE_MODE_RGMII_TXID, supported); 835 } 836 } 837 838 static void mv88e6xxx_get_caps(struct dsa_switch *ds, int port, 839 struct phylink_config *config) 840 { 841 struct mv88e6xxx_chip *chip = ds->priv; 842 843 mv88e6xxx_reg_lock(chip); 844 chip->info->ops->phylink_get_caps(chip, port, config); 845 mv88e6xxx_reg_unlock(chip); 846 847 if (mv88e6xxx_phy_is_internal(chip, port)) { 848 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 849 config->supported_interfaces); 850 /* Internal ports with no phy-mode need GMII for PHYLIB */ 851 __set_bit(PHY_INTERFACE_MODE_GMII, 852 config->supported_interfaces); 853 } 854 } 855 856 static int mv88e6xxx_mac_prepare(struct dsa_switch *ds, int port, 857 unsigned int mode, phy_interface_t interface) 858 { 859 struct mv88e6xxx_chip *chip = ds->priv; 860 int err = 0; 861 862 /* In inband mode, the link may come up at any time while the link 863 * is not forced down. Force the link down while we reconfigure the 864 * interface mode. 865 */ 866 if (mode == MLO_AN_INBAND && 867 chip->ports[port].interface != interface && 868 chip->info->ops->port_set_link) { 869 mv88e6xxx_reg_lock(chip); 870 err = chip->info->ops->port_set_link(chip, port, 871 LINK_FORCED_DOWN); 872 mv88e6xxx_reg_unlock(chip); 873 } 874 875 return err; 876 } 877 878 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port, 879 unsigned int mode, 880 const struct phylink_link_state *state) 881 { 882 struct mv88e6xxx_chip *chip = ds->priv; 883 int err = 0; 884 885 mv88e6xxx_reg_lock(chip); 886 887 if (mode != MLO_AN_PHY || !mv88e6xxx_phy_is_internal(chip, port)) { 888 err = mv88e6xxx_port_config_interface(chip, port, 889 state->interface); 890 if (err && err != -EOPNOTSUPP) 891 goto err_unlock; 892 893 err = mv88e6xxx_serdes_pcs_config(chip, port, mode, 894 state->interface, 895 state->advertising); 896 /* FIXME: we should restart negotiation if something changed - 897 * which is something we get if we convert to using phylinks 898 * PCS operations. 899 */ 900 if (err > 0) 901 err = 0; 902 } 903 904 err_unlock: 905 mv88e6xxx_reg_unlock(chip); 906 907 if (err && err != -EOPNOTSUPP) 908 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port); 909 } 910 911 static int mv88e6xxx_mac_finish(struct dsa_switch *ds, int port, 912 unsigned int mode, phy_interface_t interface) 913 { 914 struct mv88e6xxx_chip *chip = ds->priv; 915 int err = 0; 916 917 /* Undo the forced down state above after completing configuration 918 * irrespective of its state on entry, which allows the link to come 919 * up in the in-band case where there is no separate SERDES. Also 920 * ensure that the link can come up if the PPU is in use and we are 921 * in PHY mode (we treat the PPU as an effective in-band mechanism.) 922 */ 923 mv88e6xxx_reg_lock(chip); 924 925 if (chip->info->ops->port_set_link && 926 ((mode == MLO_AN_INBAND && 927 chip->ports[port].interface != interface) || 928 (mode == MLO_AN_PHY && mv88e6xxx_port_ppu_updates(chip, port)))) 929 err = chip->info->ops->port_set_link(chip, port, LINK_UNFORCED); 930 931 mv88e6xxx_reg_unlock(chip); 932 933 chip->ports[port].interface = interface; 934 935 return err; 936 } 937 938 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port, 939 unsigned int mode, 940 phy_interface_t interface) 941 { 942 struct mv88e6xxx_chip *chip = ds->priv; 943 const struct mv88e6xxx_ops *ops; 944 int err = 0; 945 946 ops = chip->info->ops; 947 948 mv88e6xxx_reg_lock(chip); 949 /* Force the link down if we know the port may not be automatically 950 * updated by the switch or if we are using fixed-link mode. 951 */ 952 if ((!mv88e6xxx_port_ppu_updates(chip, port) || 953 mode == MLO_AN_FIXED) && ops->port_sync_link) 954 err = ops->port_sync_link(chip, port, mode, false); 955 956 if (!err && ops->port_set_speed_duplex) 957 err = ops->port_set_speed_duplex(chip, port, SPEED_UNFORCED, 958 DUPLEX_UNFORCED); 959 mv88e6xxx_reg_unlock(chip); 960 961 if (err) 962 dev_err(chip->dev, 963 "p%d: failed to force MAC link down\n", port); 964 } 965 966 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port, 967 unsigned int mode, phy_interface_t interface, 968 struct phy_device *phydev, 969 int speed, int duplex, 970 bool tx_pause, bool rx_pause) 971 { 972 struct mv88e6xxx_chip *chip = ds->priv; 973 const struct mv88e6xxx_ops *ops; 974 int err = 0; 975 976 ops = chip->info->ops; 977 978 mv88e6xxx_reg_lock(chip); 979 /* Configure and force the link up if we know that the port may not 980 * automatically updated by the switch or if we are using fixed-link 981 * mode. 982 */ 983 if (!mv88e6xxx_port_ppu_updates(chip, port) || 984 mode == MLO_AN_FIXED) { 985 /* FIXME: for an automedia port, should we force the link 986 * down here - what if the link comes up due to "other" media 987 * while we're bringing the port up, how is the exclusivity 988 * handled in the Marvell hardware? E.g. port 2 on 88E6390 989 * shared between internal PHY and Serdes. 990 */ 991 err = mv88e6xxx_serdes_pcs_link_up(chip, port, mode, speed, 992 duplex); 993 if (err) 994 goto error; 995 996 if (ops->port_set_speed_duplex) { 997 err = ops->port_set_speed_duplex(chip, port, 998 speed, duplex); 999 if (err && err != -EOPNOTSUPP) 1000 goto error; 1001 } 1002 1003 if (ops->port_sync_link) 1004 err = ops->port_sync_link(chip, port, mode, true); 1005 } 1006 error: 1007 mv88e6xxx_reg_unlock(chip); 1008 1009 if (err && err != -EOPNOTSUPP) 1010 dev_err(ds->dev, 1011 "p%d: failed to configure MAC link up\n", port); 1012 } 1013 1014 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 1015 { 1016 if (!chip->info->ops->stats_snapshot) 1017 return -EOPNOTSUPP; 1018 1019 return chip->info->ops->stats_snapshot(chip, port); 1020 } 1021 1022 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 1023 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 1024 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 1025 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 1026 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 1027 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 1028 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 1029 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 1030 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 1031 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 1032 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 1033 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 1034 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 1035 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 1036 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 1037 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 1038 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 1039 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 1040 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 1041 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 1042 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 1043 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 1044 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 1045 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 1046 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 1047 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 1048 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 1049 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 1050 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 1051 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 1052 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 1053 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 1054 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 1055 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 1056 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 1057 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 1058 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 1059 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 1060 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 1061 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 1062 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 1063 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 1064 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 1065 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 1066 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 1067 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 1068 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 1069 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 1070 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 1071 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 1072 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 1073 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 1074 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 1075 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 1076 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 1077 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 1078 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 1079 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 1080 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 1081 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 1082 }; 1083 1084 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 1085 struct mv88e6xxx_hw_stat *s, 1086 int port, u16 bank1_select, 1087 u16 histogram) 1088 { 1089 u32 low; 1090 u32 high = 0; 1091 u16 reg = 0; 1092 int err; 1093 u64 value; 1094 1095 switch (s->type) { 1096 case STATS_TYPE_PORT: 1097 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 1098 if (err) 1099 return U64_MAX; 1100 1101 low = reg; 1102 if (s->size == 4) { 1103 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 1104 if (err) 1105 return U64_MAX; 1106 low |= ((u32)reg) << 16; 1107 } 1108 break; 1109 case STATS_TYPE_BANK1: 1110 reg = bank1_select; 1111 fallthrough; 1112 case STATS_TYPE_BANK0: 1113 reg |= s->reg | histogram; 1114 mv88e6xxx_g1_stats_read(chip, reg, &low); 1115 if (s->size == 8) 1116 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 1117 break; 1118 default: 1119 return U64_MAX; 1120 } 1121 value = (((u64)high) << 32) | low; 1122 return value; 1123 } 1124 1125 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 1126 uint8_t *data, int types) 1127 { 1128 struct mv88e6xxx_hw_stat *stat; 1129 int i, j; 1130 1131 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1132 stat = &mv88e6xxx_hw_stats[i]; 1133 if (stat->type & types) { 1134 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 1135 ETH_GSTRING_LEN); 1136 j++; 1137 } 1138 } 1139 1140 return j; 1141 } 1142 1143 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 1144 uint8_t *data) 1145 { 1146 return mv88e6xxx_stats_get_strings(chip, data, 1147 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 1148 } 1149 1150 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip, 1151 uint8_t *data) 1152 { 1153 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0); 1154 } 1155 1156 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 1157 uint8_t *data) 1158 { 1159 return mv88e6xxx_stats_get_strings(chip, data, 1160 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 1161 } 1162 1163 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { 1164 "atu_member_violation", 1165 "atu_miss_violation", 1166 "atu_full_violation", 1167 "vtu_member_violation", 1168 "vtu_miss_violation", 1169 }; 1170 1171 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data) 1172 { 1173 unsigned int i; 1174 1175 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) 1176 strscpy(data + i * ETH_GSTRING_LEN, 1177 mv88e6xxx_atu_vtu_stats_strings[i], 1178 ETH_GSTRING_LEN); 1179 } 1180 1181 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 1182 u32 stringset, uint8_t *data) 1183 { 1184 struct mv88e6xxx_chip *chip = ds->priv; 1185 int count = 0; 1186 1187 if (stringset != ETH_SS_STATS) 1188 return; 1189 1190 mv88e6xxx_reg_lock(chip); 1191 1192 if (chip->info->ops->stats_get_strings) 1193 count = chip->info->ops->stats_get_strings(chip, data); 1194 1195 if (chip->info->ops->serdes_get_strings) { 1196 data += count * ETH_GSTRING_LEN; 1197 count = chip->info->ops->serdes_get_strings(chip, port, data); 1198 } 1199 1200 data += count * ETH_GSTRING_LEN; 1201 mv88e6xxx_atu_vtu_get_strings(data); 1202 1203 mv88e6xxx_reg_unlock(chip); 1204 } 1205 1206 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 1207 int types) 1208 { 1209 struct mv88e6xxx_hw_stat *stat; 1210 int i, j; 1211 1212 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1213 stat = &mv88e6xxx_hw_stats[i]; 1214 if (stat->type & types) 1215 j++; 1216 } 1217 return j; 1218 } 1219 1220 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1221 { 1222 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1223 STATS_TYPE_PORT); 1224 } 1225 1226 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1227 { 1228 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0); 1229 } 1230 1231 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1232 { 1233 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1234 STATS_TYPE_BANK1); 1235 } 1236 1237 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) 1238 { 1239 struct mv88e6xxx_chip *chip = ds->priv; 1240 int serdes_count = 0; 1241 int count = 0; 1242 1243 if (sset != ETH_SS_STATS) 1244 return 0; 1245 1246 mv88e6xxx_reg_lock(chip); 1247 if (chip->info->ops->stats_get_sset_count) 1248 count = chip->info->ops->stats_get_sset_count(chip); 1249 if (count < 0) 1250 goto out; 1251 1252 if (chip->info->ops->serdes_get_sset_count) 1253 serdes_count = chip->info->ops->serdes_get_sset_count(chip, 1254 port); 1255 if (serdes_count < 0) { 1256 count = serdes_count; 1257 goto out; 1258 } 1259 count += serdes_count; 1260 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); 1261 1262 out: 1263 mv88e6xxx_reg_unlock(chip); 1264 1265 return count; 1266 } 1267 1268 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1269 uint64_t *data, int types, 1270 u16 bank1_select, u16 histogram) 1271 { 1272 struct mv88e6xxx_hw_stat *stat; 1273 int i, j; 1274 1275 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1276 stat = &mv88e6xxx_hw_stats[i]; 1277 if (stat->type & types) { 1278 mv88e6xxx_reg_lock(chip); 1279 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1280 bank1_select, 1281 histogram); 1282 mv88e6xxx_reg_unlock(chip); 1283 1284 j++; 1285 } 1286 } 1287 return j; 1288 } 1289 1290 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1291 uint64_t *data) 1292 { 1293 return mv88e6xxx_stats_get_stats(chip, port, data, 1294 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 1295 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1296 } 1297 1298 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1299 uint64_t *data) 1300 { 1301 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0, 1302 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1303 } 1304 1305 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1306 uint64_t *data) 1307 { 1308 return mv88e6xxx_stats_get_stats(chip, port, data, 1309 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1310 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 1311 MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1312 } 1313 1314 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1315 uint64_t *data) 1316 { 1317 return mv88e6xxx_stats_get_stats(chip, port, data, 1318 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1319 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 1320 0); 1321 } 1322 1323 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, 1324 uint64_t *data) 1325 { 1326 *data++ = chip->ports[port].atu_member_violation; 1327 *data++ = chip->ports[port].atu_miss_violation; 1328 *data++ = chip->ports[port].atu_full_violation; 1329 *data++ = chip->ports[port].vtu_member_violation; 1330 *data++ = chip->ports[port].vtu_miss_violation; 1331 } 1332 1333 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 1334 uint64_t *data) 1335 { 1336 int count = 0; 1337 1338 if (chip->info->ops->stats_get_stats) 1339 count = chip->info->ops->stats_get_stats(chip, port, data); 1340 1341 mv88e6xxx_reg_lock(chip); 1342 if (chip->info->ops->serdes_get_stats) { 1343 data += count; 1344 count = chip->info->ops->serdes_get_stats(chip, port, data); 1345 } 1346 data += count; 1347 mv88e6xxx_atu_vtu_get_stats(chip, port, data); 1348 mv88e6xxx_reg_unlock(chip); 1349 } 1350 1351 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 1352 uint64_t *data) 1353 { 1354 struct mv88e6xxx_chip *chip = ds->priv; 1355 int ret; 1356 1357 mv88e6xxx_reg_lock(chip); 1358 1359 ret = mv88e6xxx_stats_snapshot(chip, port); 1360 mv88e6xxx_reg_unlock(chip); 1361 1362 if (ret < 0) 1363 return; 1364 1365 mv88e6xxx_get_stats(chip, port, data); 1366 1367 } 1368 1369 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1370 { 1371 struct mv88e6xxx_chip *chip = ds->priv; 1372 int len; 1373 1374 len = 32 * sizeof(u16); 1375 if (chip->info->ops->serdes_get_regs_len) 1376 len += chip->info->ops->serdes_get_regs_len(chip, port); 1377 1378 return len; 1379 } 1380 1381 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1382 struct ethtool_regs *regs, void *_p) 1383 { 1384 struct mv88e6xxx_chip *chip = ds->priv; 1385 int err; 1386 u16 reg; 1387 u16 *p = _p; 1388 int i; 1389 1390 regs->version = chip->info->prod_num; 1391 1392 memset(p, 0xff, 32 * sizeof(u16)); 1393 1394 mv88e6xxx_reg_lock(chip); 1395 1396 for (i = 0; i < 32; i++) { 1397 1398 err = mv88e6xxx_port_read(chip, port, i, ®); 1399 if (!err) 1400 p[i] = reg; 1401 } 1402 1403 if (chip->info->ops->serdes_get_regs) 1404 chip->info->ops->serdes_get_regs(chip, port, &p[i]); 1405 1406 mv88e6xxx_reg_unlock(chip); 1407 } 1408 1409 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 1410 struct ethtool_eee *e) 1411 { 1412 /* Nothing to do on the port's MAC */ 1413 return 0; 1414 } 1415 1416 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 1417 struct ethtool_eee *e) 1418 { 1419 /* Nothing to do on the port's MAC */ 1420 return 0; 1421 } 1422 1423 /* Mask of the local ports allowed to receive frames from a given fabric port */ 1424 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 1425 { 1426 struct dsa_switch *ds = chip->ds; 1427 struct dsa_switch_tree *dst = ds->dst; 1428 struct dsa_port *dp, *other_dp; 1429 bool found = false; 1430 u16 pvlan; 1431 1432 /* dev is a physical switch */ 1433 if (dev <= dst->last_switch) { 1434 list_for_each_entry(dp, &dst->ports, list) { 1435 if (dp->ds->index == dev && dp->index == port) { 1436 /* dp might be a DSA link or a user port, so it 1437 * might or might not have a bridge. 1438 * Use the "found" variable for both cases. 1439 */ 1440 found = true; 1441 break; 1442 } 1443 } 1444 /* dev is a virtual bridge */ 1445 } else { 1446 list_for_each_entry(dp, &dst->ports, list) { 1447 unsigned int bridge_num = dsa_port_bridge_num_get(dp); 1448 1449 if (!bridge_num) 1450 continue; 1451 1452 if (bridge_num + dst->last_switch != dev) 1453 continue; 1454 1455 found = true; 1456 break; 1457 } 1458 } 1459 1460 /* Prevent frames from unknown switch or virtual bridge */ 1461 if (!found) 1462 return 0; 1463 1464 /* Frames from DSA links and CPU ports can egress any local port */ 1465 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA) 1466 return mv88e6xxx_port_mask(chip); 1467 1468 pvlan = 0; 1469 1470 /* Frames from standalone user ports can only egress on the 1471 * upstream port. 1472 */ 1473 if (!dsa_port_bridge_dev_get(dp)) 1474 return BIT(dsa_switch_upstream_port(ds)); 1475 1476 /* Frames from bridged user ports can egress any local DSA 1477 * links and CPU ports, as well as any local member of their 1478 * bridge group. 1479 */ 1480 dsa_switch_for_each_port(other_dp, ds) 1481 if (other_dp->type == DSA_PORT_TYPE_CPU || 1482 other_dp->type == DSA_PORT_TYPE_DSA || 1483 dsa_port_bridge_same(dp, other_dp)) 1484 pvlan |= BIT(other_dp->index); 1485 1486 return pvlan; 1487 } 1488 1489 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 1490 { 1491 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 1492 1493 /* prevent frames from going back out of the port they came in on */ 1494 output_ports &= ~BIT(port); 1495 1496 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1497 } 1498 1499 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1500 u8 state) 1501 { 1502 struct mv88e6xxx_chip *chip = ds->priv; 1503 int err; 1504 1505 mv88e6xxx_reg_lock(chip); 1506 err = mv88e6xxx_port_set_state(chip, port, state); 1507 mv88e6xxx_reg_unlock(chip); 1508 1509 if (err) 1510 dev_err(ds->dev, "p%d: failed to update state\n", port); 1511 } 1512 1513 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) 1514 { 1515 int err; 1516 1517 if (chip->info->ops->ieee_pri_map) { 1518 err = chip->info->ops->ieee_pri_map(chip); 1519 if (err) 1520 return err; 1521 } 1522 1523 if (chip->info->ops->ip_pri_map) { 1524 err = chip->info->ops->ip_pri_map(chip); 1525 if (err) 1526 return err; 1527 } 1528 1529 return 0; 1530 } 1531 1532 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) 1533 { 1534 struct dsa_switch *ds = chip->ds; 1535 int target, port; 1536 int err; 1537 1538 if (!chip->info->global2_addr) 1539 return 0; 1540 1541 /* Initialize the routing port to the 32 possible target devices */ 1542 for (target = 0; target < 32; target++) { 1543 port = dsa_routing_port(ds, target); 1544 if (port == ds->num_ports) 1545 port = 0x1f; 1546 1547 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 1548 if (err) 1549 return err; 1550 } 1551 1552 if (chip->info->ops->set_cascade_port) { 1553 port = MV88E6XXX_CASCADE_PORT_MULTIPLE; 1554 err = chip->info->ops->set_cascade_port(chip, port); 1555 if (err) 1556 return err; 1557 } 1558 1559 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); 1560 if (err) 1561 return err; 1562 1563 return 0; 1564 } 1565 1566 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) 1567 { 1568 /* Clear all trunk masks and mapping */ 1569 if (chip->info->global2_addr) 1570 return mv88e6xxx_g2_trunk_clear(chip); 1571 1572 return 0; 1573 } 1574 1575 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) 1576 { 1577 if (chip->info->ops->rmu_disable) 1578 return chip->info->ops->rmu_disable(chip); 1579 1580 return 0; 1581 } 1582 1583 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 1584 { 1585 if (chip->info->ops->pot_clear) 1586 return chip->info->ops->pot_clear(chip); 1587 1588 return 0; 1589 } 1590 1591 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 1592 { 1593 if (chip->info->ops->mgmt_rsvd2cpu) 1594 return chip->info->ops->mgmt_rsvd2cpu(chip); 1595 1596 return 0; 1597 } 1598 1599 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 1600 { 1601 int err; 1602 1603 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 1604 if (err) 1605 return err; 1606 1607 /* The chips that have a "learn2all" bit in Global1, ATU 1608 * Control are precisely those whose port registers have a 1609 * Message Port bit in Port Control 1 and hence implement 1610 * ->port_setup_message_port. 1611 */ 1612 if (chip->info->ops->port_setup_message_port) { 1613 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 1614 if (err) 1615 return err; 1616 } 1617 1618 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 1619 } 1620 1621 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 1622 { 1623 int port; 1624 int err; 1625 1626 if (!chip->info->ops->irl_init_all) 1627 return 0; 1628 1629 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1630 /* Disable ingress rate limiting by resetting all per port 1631 * ingress rate limit resources to their initial state. 1632 */ 1633 err = chip->info->ops->irl_init_all(chip, port); 1634 if (err) 1635 return err; 1636 } 1637 1638 return 0; 1639 } 1640 1641 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1642 { 1643 if (chip->info->ops->set_switch_mac) { 1644 u8 addr[ETH_ALEN]; 1645 1646 eth_random_addr(addr); 1647 1648 return chip->info->ops->set_switch_mac(chip, addr); 1649 } 1650 1651 return 0; 1652 } 1653 1654 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1655 { 1656 struct dsa_switch_tree *dst = chip->ds->dst; 1657 struct dsa_switch *ds; 1658 struct dsa_port *dp; 1659 u16 pvlan = 0; 1660 1661 if (!mv88e6xxx_has_pvt(chip)) 1662 return 0; 1663 1664 /* Skip the local source device, which uses in-chip port VLAN */ 1665 if (dev != chip->ds->index) { 1666 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1667 1668 ds = dsa_switch_find(dst->index, dev); 1669 dp = ds ? dsa_to_port(ds, port) : NULL; 1670 if (dp && dp->lag) { 1671 /* As the PVT is used to limit flooding of 1672 * FORWARD frames, which use the LAG ID as the 1673 * source port, we must translate dev/port to 1674 * the special "LAG device" in the PVT, using 1675 * the LAG ID (one-based) as the port number 1676 * (zero-based). 1677 */ 1678 dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK; 1679 port = dsa_port_lag_id_get(dp) - 1; 1680 } 1681 } 1682 1683 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1684 } 1685 1686 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1687 { 1688 int dev, port; 1689 int err; 1690 1691 if (!mv88e6xxx_has_pvt(chip)) 1692 return 0; 1693 1694 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1695 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1696 */ 1697 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1698 if (err) 1699 return err; 1700 1701 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1702 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1703 err = mv88e6xxx_pvt_map(chip, dev, port); 1704 if (err) 1705 return err; 1706 } 1707 } 1708 1709 return 0; 1710 } 1711 1712 static int mv88e6xxx_port_fast_age_fid(struct mv88e6xxx_chip *chip, int port, 1713 u16 fid) 1714 { 1715 if (dsa_to_port(chip->ds, port)->lag) 1716 /* Hardware is incapable of fast-aging a LAG through a 1717 * regular ATU move operation. Until we have something 1718 * more fancy in place this is a no-op. 1719 */ 1720 return -EOPNOTSUPP; 1721 1722 return mv88e6xxx_g1_atu_remove(chip, fid, port, false); 1723 } 1724 1725 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1726 { 1727 struct mv88e6xxx_chip *chip = ds->priv; 1728 int err; 1729 1730 mv88e6xxx_reg_lock(chip); 1731 err = mv88e6xxx_port_fast_age_fid(chip, port, 0); 1732 mv88e6xxx_reg_unlock(chip); 1733 1734 if (err) 1735 dev_err(chip->ds->dev, "p%d: failed to flush ATU: %d\n", 1736 port, err); 1737 } 1738 1739 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1740 { 1741 if (!mv88e6xxx_max_vid(chip)) 1742 return 0; 1743 1744 return mv88e6xxx_g1_vtu_flush(chip); 1745 } 1746 1747 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, 1748 struct mv88e6xxx_vtu_entry *entry) 1749 { 1750 int err; 1751 1752 if (!chip->info->ops->vtu_getnext) 1753 return -EOPNOTSUPP; 1754 1755 entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip); 1756 entry->valid = false; 1757 1758 err = chip->info->ops->vtu_getnext(chip, entry); 1759 1760 if (entry->vid != vid) 1761 entry->valid = false; 1762 1763 return err; 1764 } 1765 1766 int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip, 1767 int (*cb)(struct mv88e6xxx_chip *chip, 1768 const struct mv88e6xxx_vtu_entry *entry, 1769 void *priv), 1770 void *priv) 1771 { 1772 struct mv88e6xxx_vtu_entry entry = { 1773 .vid = mv88e6xxx_max_vid(chip), 1774 .valid = false, 1775 }; 1776 int err; 1777 1778 if (!chip->info->ops->vtu_getnext) 1779 return -EOPNOTSUPP; 1780 1781 do { 1782 err = chip->info->ops->vtu_getnext(chip, &entry); 1783 if (err) 1784 return err; 1785 1786 if (!entry.valid) 1787 break; 1788 1789 err = cb(chip, &entry, priv); 1790 if (err) 1791 return err; 1792 } while (entry.vid < mv88e6xxx_max_vid(chip)); 1793 1794 return 0; 1795 } 1796 1797 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1798 struct mv88e6xxx_vtu_entry *entry) 1799 { 1800 if (!chip->info->ops->vtu_loadpurge) 1801 return -EOPNOTSUPP; 1802 1803 return chip->info->ops->vtu_loadpurge(chip, entry); 1804 } 1805 1806 static int mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip *chip, 1807 const struct mv88e6xxx_vtu_entry *entry, 1808 void *_fid_bitmap) 1809 { 1810 unsigned long *fid_bitmap = _fid_bitmap; 1811 1812 set_bit(entry->fid, fid_bitmap); 1813 return 0; 1814 } 1815 1816 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap) 1817 { 1818 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1819 1820 /* Every FID has an associated VID, so walking the VTU 1821 * will discover the full set of FIDs in use. 1822 */ 1823 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_fid_map_vlan, fid_bitmap); 1824 } 1825 1826 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1827 { 1828 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1829 int err; 1830 1831 err = mv88e6xxx_fid_map(chip, fid_bitmap); 1832 if (err) 1833 return err; 1834 1835 *fid = find_first_zero_bit(fid_bitmap, MV88E6XXX_N_FID); 1836 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1837 return -ENOSPC; 1838 1839 /* Clear the database */ 1840 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1841 } 1842 1843 static int mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip, 1844 struct mv88e6xxx_stu_entry *entry) 1845 { 1846 if (!chip->info->ops->stu_loadpurge) 1847 return -EOPNOTSUPP; 1848 1849 return chip->info->ops->stu_loadpurge(chip, entry); 1850 } 1851 1852 static int mv88e6xxx_stu_setup(struct mv88e6xxx_chip *chip) 1853 { 1854 struct mv88e6xxx_stu_entry stu = { 1855 .valid = true, 1856 .sid = 0 1857 }; 1858 1859 if (!mv88e6xxx_has_stu(chip)) 1860 return 0; 1861 1862 /* Make sure that SID 0 is always valid. This is used by VTU 1863 * entries that do not make use of the STU, e.g. when creating 1864 * a VLAN upper on a port that is also part of a VLAN 1865 * filtering bridge. 1866 */ 1867 return mv88e6xxx_stu_loadpurge(chip, &stu); 1868 } 1869 1870 static int mv88e6xxx_sid_get(struct mv88e6xxx_chip *chip, u8 *sid) 1871 { 1872 DECLARE_BITMAP(busy, MV88E6XXX_N_SID) = { 0 }; 1873 struct mv88e6xxx_mst *mst; 1874 1875 __set_bit(0, busy); 1876 1877 list_for_each_entry(mst, &chip->msts, node) 1878 __set_bit(mst->stu.sid, busy); 1879 1880 *sid = find_first_zero_bit(busy, MV88E6XXX_N_SID); 1881 1882 return (*sid >= mv88e6xxx_max_sid(chip)) ? -ENOSPC : 0; 1883 } 1884 1885 static int mv88e6xxx_mst_put(struct mv88e6xxx_chip *chip, u8 sid) 1886 { 1887 struct mv88e6xxx_mst *mst, *tmp; 1888 int err; 1889 1890 if (!sid) 1891 return 0; 1892 1893 list_for_each_entry_safe(mst, tmp, &chip->msts, node) { 1894 if (mst->stu.sid != sid) 1895 continue; 1896 1897 if (!refcount_dec_and_test(&mst->refcnt)) 1898 return 0; 1899 1900 mst->stu.valid = false; 1901 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 1902 if (err) { 1903 refcount_set(&mst->refcnt, 1); 1904 return err; 1905 } 1906 1907 list_del(&mst->node); 1908 kfree(mst); 1909 return 0; 1910 } 1911 1912 return -ENOENT; 1913 } 1914 1915 static int mv88e6xxx_mst_get(struct mv88e6xxx_chip *chip, struct net_device *br, 1916 u16 msti, u8 *sid) 1917 { 1918 struct mv88e6xxx_mst *mst; 1919 int err, i; 1920 1921 if (!mv88e6xxx_has_stu(chip)) { 1922 err = -EOPNOTSUPP; 1923 goto err; 1924 } 1925 1926 if (!msti) { 1927 *sid = 0; 1928 return 0; 1929 } 1930 1931 list_for_each_entry(mst, &chip->msts, node) { 1932 if (mst->br == br && mst->msti == msti) { 1933 refcount_inc(&mst->refcnt); 1934 *sid = mst->stu.sid; 1935 return 0; 1936 } 1937 } 1938 1939 err = mv88e6xxx_sid_get(chip, sid); 1940 if (err) 1941 goto err; 1942 1943 mst = kzalloc(sizeof(*mst), GFP_KERNEL); 1944 if (!mst) { 1945 err = -ENOMEM; 1946 goto err; 1947 } 1948 1949 INIT_LIST_HEAD(&mst->node); 1950 refcount_set(&mst->refcnt, 1); 1951 mst->br = br; 1952 mst->msti = msti; 1953 mst->stu.valid = true; 1954 mst->stu.sid = *sid; 1955 1956 /* The bridge starts out all ports in the disabled state. But 1957 * a STU state of disabled means to go by the port-global 1958 * state. So we set all user port's initial state to blocking, 1959 * to match the bridge's behavior. 1960 */ 1961 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 1962 mst->stu.state[i] = dsa_is_user_port(chip->ds, i) ? 1963 MV88E6XXX_PORT_CTL0_STATE_BLOCKING : 1964 MV88E6XXX_PORT_CTL0_STATE_DISABLED; 1965 1966 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 1967 if (err) 1968 goto err_free; 1969 1970 list_add_tail(&mst->node, &chip->msts); 1971 return 0; 1972 1973 err_free: 1974 kfree(mst); 1975 err: 1976 return err; 1977 } 1978 1979 static int mv88e6xxx_port_mst_state_set(struct dsa_switch *ds, int port, 1980 const struct switchdev_mst_state *st) 1981 { 1982 struct dsa_port *dp = dsa_to_port(ds, port); 1983 struct mv88e6xxx_chip *chip = ds->priv; 1984 struct mv88e6xxx_mst *mst; 1985 u8 state; 1986 int err; 1987 1988 if (!mv88e6xxx_has_stu(chip)) 1989 return -EOPNOTSUPP; 1990 1991 switch (st->state) { 1992 case BR_STATE_DISABLED: 1993 case BR_STATE_BLOCKING: 1994 case BR_STATE_LISTENING: 1995 state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING; 1996 break; 1997 case BR_STATE_LEARNING: 1998 state = MV88E6XXX_PORT_CTL0_STATE_LEARNING; 1999 break; 2000 case BR_STATE_FORWARDING: 2001 state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 2002 break; 2003 default: 2004 return -EINVAL; 2005 } 2006 2007 list_for_each_entry(mst, &chip->msts, node) { 2008 if (mst->br == dsa_port_bridge_dev_get(dp) && 2009 mst->msti == st->msti) { 2010 if (mst->stu.state[port] == state) 2011 return 0; 2012 2013 mst->stu.state[port] = state; 2014 mv88e6xxx_reg_lock(chip); 2015 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 2016 mv88e6xxx_reg_unlock(chip); 2017 return err; 2018 } 2019 } 2020 2021 return -ENOENT; 2022 } 2023 2024 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 2025 u16 vid) 2026 { 2027 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 2028 struct mv88e6xxx_chip *chip = ds->priv; 2029 struct mv88e6xxx_vtu_entry vlan; 2030 int err; 2031 2032 /* DSA and CPU ports have to be members of multiple vlans */ 2033 if (dsa_port_is_dsa(dp) || dsa_port_is_cpu(dp)) 2034 return 0; 2035 2036 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2037 if (err) 2038 return err; 2039 2040 if (!vlan.valid) 2041 return 0; 2042 2043 dsa_switch_for_each_user_port(other_dp, ds) { 2044 struct net_device *other_br; 2045 2046 if (vlan.member[other_dp->index] == 2047 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2048 continue; 2049 2050 if (dsa_port_bridge_same(dp, other_dp)) 2051 break; /* same bridge, check next VLAN */ 2052 2053 other_br = dsa_port_bridge_dev_get(other_dp); 2054 if (!other_br) 2055 continue; 2056 2057 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 2058 port, vlan.vid, other_dp->index, netdev_name(other_br)); 2059 return -EOPNOTSUPP; 2060 } 2061 2062 return 0; 2063 } 2064 2065 static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port) 2066 { 2067 struct dsa_port *dp = dsa_to_port(chip->ds, port); 2068 struct net_device *br = dsa_port_bridge_dev_get(dp); 2069 struct mv88e6xxx_port *p = &chip->ports[port]; 2070 u16 pvid = MV88E6XXX_VID_STANDALONE; 2071 bool drop_untagged = false; 2072 int err; 2073 2074 if (br) { 2075 if (br_vlan_enabled(br)) { 2076 pvid = p->bridge_pvid.vid; 2077 drop_untagged = !p->bridge_pvid.valid; 2078 } else { 2079 pvid = MV88E6XXX_VID_BRIDGED; 2080 } 2081 } 2082 2083 err = mv88e6xxx_port_set_pvid(chip, port, pvid); 2084 if (err) 2085 return err; 2086 2087 return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged); 2088 } 2089 2090 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 2091 bool vlan_filtering, 2092 struct netlink_ext_ack *extack) 2093 { 2094 struct mv88e6xxx_chip *chip = ds->priv; 2095 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 2096 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 2097 int err; 2098 2099 if (!mv88e6xxx_max_vid(chip)) 2100 return -EOPNOTSUPP; 2101 2102 mv88e6xxx_reg_lock(chip); 2103 2104 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 2105 if (err) 2106 goto unlock; 2107 2108 err = mv88e6xxx_port_commit_pvid(chip, port); 2109 if (err) 2110 goto unlock; 2111 2112 unlock: 2113 mv88e6xxx_reg_unlock(chip); 2114 2115 return err; 2116 } 2117 2118 static int 2119 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 2120 const struct switchdev_obj_port_vlan *vlan) 2121 { 2122 struct mv88e6xxx_chip *chip = ds->priv; 2123 int err; 2124 2125 if (!mv88e6xxx_max_vid(chip)) 2126 return -EOPNOTSUPP; 2127 2128 /* If the requested port doesn't belong to the same bridge as the VLAN 2129 * members, do not support it (yet) and fallback to software VLAN. 2130 */ 2131 mv88e6xxx_reg_lock(chip); 2132 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid); 2133 mv88e6xxx_reg_unlock(chip); 2134 2135 return err; 2136 } 2137 2138 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 2139 const unsigned char *addr, u16 vid, 2140 u8 state) 2141 { 2142 struct mv88e6xxx_atu_entry entry; 2143 struct mv88e6xxx_vtu_entry vlan; 2144 u16 fid; 2145 int err; 2146 2147 /* Ports have two private address databases: one for when the port is 2148 * standalone and one for when the port is under a bridge and the 2149 * 802.1Q mode is disabled. When the port is standalone, DSA wants its 2150 * address database to remain 100% empty, so we never load an ATU entry 2151 * into a standalone port's database. Therefore, translate the null 2152 * VLAN ID into the port's database used for VLAN-unaware bridging. 2153 */ 2154 if (vid == 0) { 2155 fid = MV88E6XXX_FID_BRIDGED; 2156 } else { 2157 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2158 if (err) 2159 return err; 2160 2161 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 2162 if (!vlan.valid) 2163 return -EOPNOTSUPP; 2164 2165 fid = vlan.fid; 2166 } 2167 2168 entry.state = 0; 2169 ether_addr_copy(entry.mac, addr); 2170 eth_addr_dec(entry.mac); 2171 2172 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry); 2173 if (err) 2174 return err; 2175 2176 /* Initialize a fresh ATU entry if it isn't found */ 2177 if (!entry.state || !ether_addr_equal(entry.mac, addr)) { 2178 memset(&entry, 0, sizeof(entry)); 2179 ether_addr_copy(entry.mac, addr); 2180 } 2181 2182 /* Purge the ATU entry only if no port is using it anymore */ 2183 if (!state) { 2184 entry.portvec &= ~BIT(port); 2185 if (!entry.portvec) 2186 entry.state = 0; 2187 } else { 2188 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC) 2189 entry.portvec = BIT(port); 2190 else 2191 entry.portvec |= BIT(port); 2192 2193 entry.state = state; 2194 } 2195 2196 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry); 2197 } 2198 2199 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port, 2200 const struct mv88e6xxx_policy *policy) 2201 { 2202 enum mv88e6xxx_policy_mapping mapping = policy->mapping; 2203 enum mv88e6xxx_policy_action action = policy->action; 2204 const u8 *addr = policy->addr; 2205 u16 vid = policy->vid; 2206 u8 state; 2207 int err; 2208 int id; 2209 2210 if (!chip->info->ops->port_set_policy) 2211 return -EOPNOTSUPP; 2212 2213 switch (mapping) { 2214 case MV88E6XXX_POLICY_MAPPING_DA: 2215 case MV88E6XXX_POLICY_MAPPING_SA: 2216 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 2217 state = 0; /* Dissociate the port and address */ 2218 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 2219 is_multicast_ether_addr(addr)) 2220 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY; 2221 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 2222 is_unicast_ether_addr(addr)) 2223 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY; 2224 else 2225 return -EOPNOTSUPP; 2226 2227 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2228 state); 2229 if (err) 2230 return err; 2231 break; 2232 default: 2233 return -EOPNOTSUPP; 2234 } 2235 2236 /* Skip the port's policy clearing if the mapping is still in use */ 2237 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 2238 idr_for_each_entry(&chip->policies, policy, id) 2239 if (policy->port == port && 2240 policy->mapping == mapping && 2241 policy->action != action) 2242 return 0; 2243 2244 return chip->info->ops->port_set_policy(chip, port, mapping, action); 2245 } 2246 2247 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port, 2248 struct ethtool_rx_flow_spec *fs) 2249 { 2250 struct ethhdr *mac_entry = &fs->h_u.ether_spec; 2251 struct ethhdr *mac_mask = &fs->m_u.ether_spec; 2252 enum mv88e6xxx_policy_mapping mapping; 2253 enum mv88e6xxx_policy_action action; 2254 struct mv88e6xxx_policy *policy; 2255 u16 vid = 0; 2256 u8 *addr; 2257 int err; 2258 int id; 2259 2260 if (fs->location != RX_CLS_LOC_ANY) 2261 return -EINVAL; 2262 2263 if (fs->ring_cookie == RX_CLS_FLOW_DISC) 2264 action = MV88E6XXX_POLICY_ACTION_DISCARD; 2265 else 2266 return -EOPNOTSUPP; 2267 2268 switch (fs->flow_type & ~FLOW_EXT) { 2269 case ETHER_FLOW: 2270 if (!is_zero_ether_addr(mac_mask->h_dest) && 2271 is_zero_ether_addr(mac_mask->h_source)) { 2272 mapping = MV88E6XXX_POLICY_MAPPING_DA; 2273 addr = mac_entry->h_dest; 2274 } else if (is_zero_ether_addr(mac_mask->h_dest) && 2275 !is_zero_ether_addr(mac_mask->h_source)) { 2276 mapping = MV88E6XXX_POLICY_MAPPING_SA; 2277 addr = mac_entry->h_source; 2278 } else { 2279 /* Cannot support DA and SA mapping in the same rule */ 2280 return -EOPNOTSUPP; 2281 } 2282 break; 2283 default: 2284 return -EOPNOTSUPP; 2285 } 2286 2287 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) { 2288 if (fs->m_ext.vlan_tci != htons(0xffff)) 2289 return -EOPNOTSUPP; 2290 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK; 2291 } 2292 2293 idr_for_each_entry(&chip->policies, policy, id) { 2294 if (policy->port == port && policy->mapping == mapping && 2295 policy->action == action && policy->vid == vid && 2296 ether_addr_equal(policy->addr, addr)) 2297 return -EEXIST; 2298 } 2299 2300 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL); 2301 if (!policy) 2302 return -ENOMEM; 2303 2304 fs->location = 0; 2305 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff, 2306 GFP_KERNEL); 2307 if (err) { 2308 devm_kfree(chip->dev, policy); 2309 return err; 2310 } 2311 2312 memcpy(&policy->fs, fs, sizeof(*fs)); 2313 ether_addr_copy(policy->addr, addr); 2314 policy->mapping = mapping; 2315 policy->action = action; 2316 policy->port = port; 2317 policy->vid = vid; 2318 2319 err = mv88e6xxx_policy_apply(chip, port, policy); 2320 if (err) { 2321 idr_remove(&chip->policies, fs->location); 2322 devm_kfree(chip->dev, policy); 2323 return err; 2324 } 2325 2326 return 0; 2327 } 2328 2329 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port, 2330 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 2331 { 2332 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 2333 struct mv88e6xxx_chip *chip = ds->priv; 2334 struct mv88e6xxx_policy *policy; 2335 int err; 2336 int id; 2337 2338 mv88e6xxx_reg_lock(chip); 2339 2340 switch (rxnfc->cmd) { 2341 case ETHTOOL_GRXCLSRLCNT: 2342 rxnfc->data = 0; 2343 rxnfc->data |= RX_CLS_LOC_SPECIAL; 2344 rxnfc->rule_cnt = 0; 2345 idr_for_each_entry(&chip->policies, policy, id) 2346 if (policy->port == port) 2347 rxnfc->rule_cnt++; 2348 err = 0; 2349 break; 2350 case ETHTOOL_GRXCLSRULE: 2351 err = -ENOENT; 2352 policy = idr_find(&chip->policies, fs->location); 2353 if (policy) { 2354 memcpy(fs, &policy->fs, sizeof(*fs)); 2355 err = 0; 2356 } 2357 break; 2358 case ETHTOOL_GRXCLSRLALL: 2359 rxnfc->data = 0; 2360 rxnfc->rule_cnt = 0; 2361 idr_for_each_entry(&chip->policies, policy, id) 2362 if (policy->port == port) 2363 rule_locs[rxnfc->rule_cnt++] = id; 2364 err = 0; 2365 break; 2366 default: 2367 err = -EOPNOTSUPP; 2368 break; 2369 } 2370 2371 mv88e6xxx_reg_unlock(chip); 2372 2373 return err; 2374 } 2375 2376 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port, 2377 struct ethtool_rxnfc *rxnfc) 2378 { 2379 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 2380 struct mv88e6xxx_chip *chip = ds->priv; 2381 struct mv88e6xxx_policy *policy; 2382 int err; 2383 2384 mv88e6xxx_reg_lock(chip); 2385 2386 switch (rxnfc->cmd) { 2387 case ETHTOOL_SRXCLSRLINS: 2388 err = mv88e6xxx_policy_insert(chip, port, fs); 2389 break; 2390 case ETHTOOL_SRXCLSRLDEL: 2391 err = -ENOENT; 2392 policy = idr_remove(&chip->policies, fs->location); 2393 if (policy) { 2394 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL; 2395 err = mv88e6xxx_policy_apply(chip, port, policy); 2396 devm_kfree(chip->dev, policy); 2397 } 2398 break; 2399 default: 2400 err = -EOPNOTSUPP; 2401 break; 2402 } 2403 2404 mv88e6xxx_reg_unlock(chip); 2405 2406 return err; 2407 } 2408 2409 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 2410 u16 vid) 2411 { 2412 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2413 u8 broadcast[ETH_ALEN]; 2414 2415 eth_broadcast_addr(broadcast); 2416 2417 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 2418 } 2419 2420 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 2421 { 2422 int port; 2423 int err; 2424 2425 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2426 struct dsa_port *dp = dsa_to_port(chip->ds, port); 2427 struct net_device *brport; 2428 2429 if (dsa_is_unused_port(chip->ds, port)) 2430 continue; 2431 2432 brport = dsa_port_to_bridge_port(dp); 2433 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD)) 2434 /* Skip bridged user ports where broadcast 2435 * flooding is disabled. 2436 */ 2437 continue; 2438 2439 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 2440 if (err) 2441 return err; 2442 } 2443 2444 return 0; 2445 } 2446 2447 struct mv88e6xxx_port_broadcast_sync_ctx { 2448 int port; 2449 bool flood; 2450 }; 2451 2452 static int 2453 mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip, 2454 const struct mv88e6xxx_vtu_entry *vlan, 2455 void *_ctx) 2456 { 2457 struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx; 2458 u8 broadcast[ETH_ALEN]; 2459 u8 state; 2460 2461 if (ctx->flood) 2462 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2463 else 2464 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED; 2465 2466 eth_broadcast_addr(broadcast); 2467 2468 return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast, 2469 vlan->vid, state); 2470 } 2471 2472 static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port, 2473 bool flood) 2474 { 2475 struct mv88e6xxx_port_broadcast_sync_ctx ctx = { 2476 .port = port, 2477 .flood = flood, 2478 }; 2479 struct mv88e6xxx_vtu_entry vid0 = { 2480 .vid = 0, 2481 }; 2482 int err; 2483 2484 /* Update the port's private database... */ 2485 err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx); 2486 if (err) 2487 return err; 2488 2489 /* ...and the database for all VLANs. */ 2490 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan, 2491 &ctx); 2492 } 2493 2494 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port, 2495 u16 vid, u8 member, bool warn) 2496 { 2497 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2498 struct mv88e6xxx_vtu_entry vlan; 2499 int i, err; 2500 2501 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2502 if (err) 2503 return err; 2504 2505 if (!vlan.valid) { 2506 memset(&vlan, 0, sizeof(vlan)); 2507 2508 if (vid == MV88E6XXX_VID_STANDALONE) 2509 vlan.policy = true; 2510 2511 err = mv88e6xxx_atu_new(chip, &vlan.fid); 2512 if (err) 2513 return err; 2514 2515 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 2516 if (i == port) 2517 vlan.member[i] = member; 2518 else 2519 vlan.member[i] = non_member; 2520 2521 vlan.vid = vid; 2522 vlan.valid = true; 2523 2524 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2525 if (err) 2526 return err; 2527 2528 err = mv88e6xxx_broadcast_setup(chip, vlan.vid); 2529 if (err) 2530 return err; 2531 } else if (vlan.member[port] != member) { 2532 vlan.member[port] = member; 2533 2534 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2535 if (err) 2536 return err; 2537 } else if (warn) { 2538 dev_info(chip->dev, "p%d: already a member of VLAN %d\n", 2539 port, vid); 2540 } 2541 2542 return 0; 2543 } 2544 2545 static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 2546 const struct switchdev_obj_port_vlan *vlan, 2547 struct netlink_ext_ack *extack) 2548 { 2549 struct mv88e6xxx_chip *chip = ds->priv; 2550 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 2551 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 2552 struct mv88e6xxx_port *p = &chip->ports[port]; 2553 bool warn; 2554 u8 member; 2555 int err; 2556 2557 if (!vlan->vid) 2558 return 0; 2559 2560 err = mv88e6xxx_port_vlan_prepare(ds, port, vlan); 2561 if (err) 2562 return err; 2563 2564 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 2565 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 2566 else if (untagged) 2567 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 2568 else 2569 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 2570 2571 /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port 2572 * and then the CPU port. Do not warn for duplicates for the CPU port. 2573 */ 2574 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port); 2575 2576 mv88e6xxx_reg_lock(chip); 2577 2578 err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn); 2579 if (err) { 2580 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 2581 vlan->vid, untagged ? 'u' : 't'); 2582 goto out; 2583 } 2584 2585 if (pvid) { 2586 p->bridge_pvid.vid = vlan->vid; 2587 p->bridge_pvid.valid = true; 2588 2589 err = mv88e6xxx_port_commit_pvid(chip, port); 2590 if (err) 2591 goto out; 2592 } else if (vlan->vid && p->bridge_pvid.vid == vlan->vid) { 2593 /* The old pvid was reinstalled as a non-pvid VLAN */ 2594 p->bridge_pvid.valid = false; 2595 2596 err = mv88e6xxx_port_commit_pvid(chip, port); 2597 if (err) 2598 goto out; 2599 } 2600 2601 out: 2602 mv88e6xxx_reg_unlock(chip); 2603 2604 return err; 2605 } 2606 2607 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip, 2608 int port, u16 vid) 2609 { 2610 struct mv88e6xxx_vtu_entry vlan; 2611 int i, err; 2612 2613 if (!vid) 2614 return 0; 2615 2616 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2617 if (err) 2618 return err; 2619 2620 /* If the VLAN doesn't exist in hardware or the port isn't a member, 2621 * tell switchdev that this VLAN is likely handled in software. 2622 */ 2623 if (!vlan.valid || 2624 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2625 return -EOPNOTSUPP; 2626 2627 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2628 2629 /* keep the VLAN unless all ports are excluded */ 2630 vlan.valid = false; 2631 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 2632 if (vlan.member[i] != 2633 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 2634 vlan.valid = true; 2635 break; 2636 } 2637 } 2638 2639 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2640 if (err) 2641 return err; 2642 2643 if (!vlan.valid) { 2644 err = mv88e6xxx_mst_put(chip, vlan.sid); 2645 if (err) 2646 return err; 2647 } 2648 2649 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 2650 } 2651 2652 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 2653 const struct switchdev_obj_port_vlan *vlan) 2654 { 2655 struct mv88e6xxx_chip *chip = ds->priv; 2656 struct mv88e6xxx_port *p = &chip->ports[port]; 2657 int err = 0; 2658 u16 pvid; 2659 2660 if (!mv88e6xxx_max_vid(chip)) 2661 return -EOPNOTSUPP; 2662 2663 /* The ATU removal procedure needs the FID to be mapped in the VTU, 2664 * but FDB deletion runs concurrently with VLAN deletion. Flush the DSA 2665 * switchdev workqueue to ensure that all FDB entries are deleted 2666 * before we remove the VLAN. 2667 */ 2668 dsa_flush_workqueue(); 2669 2670 mv88e6xxx_reg_lock(chip); 2671 2672 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 2673 if (err) 2674 goto unlock; 2675 2676 err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid); 2677 if (err) 2678 goto unlock; 2679 2680 if (vlan->vid == pvid) { 2681 p->bridge_pvid.valid = false; 2682 2683 err = mv88e6xxx_port_commit_pvid(chip, port); 2684 if (err) 2685 goto unlock; 2686 } 2687 2688 unlock: 2689 mv88e6xxx_reg_unlock(chip); 2690 2691 return err; 2692 } 2693 2694 static int mv88e6xxx_port_vlan_fast_age(struct dsa_switch *ds, int port, u16 vid) 2695 { 2696 struct mv88e6xxx_chip *chip = ds->priv; 2697 struct mv88e6xxx_vtu_entry vlan; 2698 int err; 2699 2700 mv88e6xxx_reg_lock(chip); 2701 2702 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2703 if (err) 2704 goto unlock; 2705 2706 err = mv88e6xxx_port_fast_age_fid(chip, port, vlan.fid); 2707 2708 unlock: 2709 mv88e6xxx_reg_unlock(chip); 2710 2711 return err; 2712 } 2713 2714 static int mv88e6xxx_vlan_msti_set(struct dsa_switch *ds, 2715 struct dsa_bridge bridge, 2716 const struct switchdev_vlan_msti *msti) 2717 { 2718 struct mv88e6xxx_chip *chip = ds->priv; 2719 struct mv88e6xxx_vtu_entry vlan; 2720 u8 old_sid, new_sid; 2721 int err; 2722 2723 if (!mv88e6xxx_has_stu(chip)) 2724 return -EOPNOTSUPP; 2725 2726 mv88e6xxx_reg_lock(chip); 2727 2728 err = mv88e6xxx_vtu_get(chip, msti->vid, &vlan); 2729 if (err) 2730 goto unlock; 2731 2732 if (!vlan.valid) { 2733 err = -EINVAL; 2734 goto unlock; 2735 } 2736 2737 old_sid = vlan.sid; 2738 2739 err = mv88e6xxx_mst_get(chip, bridge.dev, msti->msti, &new_sid); 2740 if (err) 2741 goto unlock; 2742 2743 if (new_sid != old_sid) { 2744 vlan.sid = new_sid; 2745 2746 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2747 if (err) { 2748 mv88e6xxx_mst_put(chip, new_sid); 2749 goto unlock; 2750 } 2751 } 2752 2753 err = mv88e6xxx_mst_put(chip, old_sid); 2754 2755 unlock: 2756 mv88e6xxx_reg_unlock(chip); 2757 return err; 2758 } 2759 2760 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 2761 const unsigned char *addr, u16 vid, 2762 struct dsa_db db) 2763 { 2764 struct mv88e6xxx_chip *chip = ds->priv; 2765 int err; 2766 2767 mv88e6xxx_reg_lock(chip); 2768 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2769 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2770 mv88e6xxx_reg_unlock(chip); 2771 2772 return err; 2773 } 2774 2775 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 2776 const unsigned char *addr, u16 vid, 2777 struct dsa_db db) 2778 { 2779 struct mv88e6xxx_chip *chip = ds->priv; 2780 int err; 2781 2782 mv88e6xxx_reg_lock(chip); 2783 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0); 2784 mv88e6xxx_reg_unlock(chip); 2785 2786 return err; 2787 } 2788 2789 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 2790 u16 fid, u16 vid, int port, 2791 dsa_fdb_dump_cb_t *cb, void *data) 2792 { 2793 struct mv88e6xxx_atu_entry addr; 2794 bool is_static; 2795 int err; 2796 2797 addr.state = 0; 2798 eth_broadcast_addr(addr.mac); 2799 2800 do { 2801 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 2802 if (err) 2803 return err; 2804 2805 if (!addr.state) 2806 break; 2807 2808 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 2809 continue; 2810 2811 if (!is_unicast_ether_addr(addr.mac)) 2812 continue; 2813 2814 is_static = (addr.state == 2815 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2816 err = cb(addr.mac, vid, is_static, data); 2817 if (err) 2818 return err; 2819 } while (!is_broadcast_ether_addr(addr.mac)); 2820 2821 return err; 2822 } 2823 2824 struct mv88e6xxx_port_db_dump_vlan_ctx { 2825 int port; 2826 dsa_fdb_dump_cb_t *cb; 2827 void *data; 2828 }; 2829 2830 static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip, 2831 const struct mv88e6xxx_vtu_entry *entry, 2832 void *_data) 2833 { 2834 struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data; 2835 2836 return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid, 2837 ctx->port, ctx->cb, ctx->data); 2838 } 2839 2840 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 2841 dsa_fdb_dump_cb_t *cb, void *data) 2842 { 2843 struct mv88e6xxx_port_db_dump_vlan_ctx ctx = { 2844 .port = port, 2845 .cb = cb, 2846 .data = data, 2847 }; 2848 u16 fid; 2849 int err; 2850 2851 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 2852 err = mv88e6xxx_port_get_fid(chip, port, &fid); 2853 if (err) 2854 return err; 2855 2856 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 2857 if (err) 2858 return err; 2859 2860 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx); 2861 } 2862 2863 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 2864 dsa_fdb_dump_cb_t *cb, void *data) 2865 { 2866 struct mv88e6xxx_chip *chip = ds->priv; 2867 int err; 2868 2869 mv88e6xxx_reg_lock(chip); 2870 err = mv88e6xxx_port_db_dump(chip, port, cb, data); 2871 mv88e6xxx_reg_unlock(chip); 2872 2873 return err; 2874 } 2875 2876 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 2877 struct dsa_bridge bridge) 2878 { 2879 struct dsa_switch *ds = chip->ds; 2880 struct dsa_switch_tree *dst = ds->dst; 2881 struct dsa_port *dp; 2882 int err; 2883 2884 list_for_each_entry(dp, &dst->ports, list) { 2885 if (dsa_port_offloads_bridge(dp, &bridge)) { 2886 if (dp->ds == ds) { 2887 /* This is a local bridge group member, 2888 * remap its Port VLAN Map. 2889 */ 2890 err = mv88e6xxx_port_vlan_map(chip, dp->index); 2891 if (err) 2892 return err; 2893 } else { 2894 /* This is an external bridge group member, 2895 * remap its cross-chip Port VLAN Table entry. 2896 */ 2897 err = mv88e6xxx_pvt_map(chip, dp->ds->index, 2898 dp->index); 2899 if (err) 2900 return err; 2901 } 2902 } 2903 } 2904 2905 return 0; 2906 } 2907 2908 /* Treat the software bridge as a virtual single-port switch behind the 2909 * CPU and map in the PVT. First dst->last_switch elements are taken by 2910 * physical switches, so start from beyond that range. 2911 */ 2912 static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds, 2913 unsigned int bridge_num) 2914 { 2915 u8 dev = bridge_num + ds->dst->last_switch; 2916 struct mv88e6xxx_chip *chip = ds->priv; 2917 2918 return mv88e6xxx_pvt_map(chip, dev, 0); 2919 } 2920 2921 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 2922 struct dsa_bridge bridge, 2923 bool *tx_fwd_offload, 2924 struct netlink_ext_ack *extack) 2925 { 2926 struct mv88e6xxx_chip *chip = ds->priv; 2927 int err; 2928 2929 mv88e6xxx_reg_lock(chip); 2930 2931 err = mv88e6xxx_bridge_map(chip, bridge); 2932 if (err) 2933 goto unlock; 2934 2935 err = mv88e6xxx_port_set_map_da(chip, port, true); 2936 if (err) 2937 goto unlock; 2938 2939 err = mv88e6xxx_port_commit_pvid(chip, port); 2940 if (err) 2941 goto unlock; 2942 2943 if (mv88e6xxx_has_pvt(chip)) { 2944 err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num); 2945 if (err) 2946 goto unlock; 2947 2948 *tx_fwd_offload = true; 2949 } 2950 2951 unlock: 2952 mv88e6xxx_reg_unlock(chip); 2953 2954 return err; 2955 } 2956 2957 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 2958 struct dsa_bridge bridge) 2959 { 2960 struct mv88e6xxx_chip *chip = ds->priv; 2961 int err; 2962 2963 mv88e6xxx_reg_lock(chip); 2964 2965 if (bridge.tx_fwd_offload && 2966 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num)) 2967 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 2968 2969 if (mv88e6xxx_bridge_map(chip, bridge) || 2970 mv88e6xxx_port_vlan_map(chip, port)) 2971 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 2972 2973 err = mv88e6xxx_port_set_map_da(chip, port, false); 2974 if (err) 2975 dev_err(ds->dev, 2976 "port %d failed to restore map-DA: %pe\n", 2977 port, ERR_PTR(err)); 2978 2979 err = mv88e6xxx_port_commit_pvid(chip, port); 2980 if (err) 2981 dev_err(ds->dev, 2982 "port %d failed to restore standalone pvid: %pe\n", 2983 port, ERR_PTR(err)); 2984 2985 mv88e6xxx_reg_unlock(chip); 2986 } 2987 2988 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, 2989 int tree_index, int sw_index, 2990 int port, struct dsa_bridge bridge, 2991 struct netlink_ext_ack *extack) 2992 { 2993 struct mv88e6xxx_chip *chip = ds->priv; 2994 int err; 2995 2996 if (tree_index != ds->dst->index) 2997 return 0; 2998 2999 mv88e6xxx_reg_lock(chip); 3000 err = mv88e6xxx_pvt_map(chip, sw_index, port); 3001 err = err ? : mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num); 3002 mv88e6xxx_reg_unlock(chip); 3003 3004 return err; 3005 } 3006 3007 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, 3008 int tree_index, int sw_index, 3009 int port, struct dsa_bridge bridge) 3010 { 3011 struct mv88e6xxx_chip *chip = ds->priv; 3012 3013 if (tree_index != ds->dst->index) 3014 return; 3015 3016 mv88e6xxx_reg_lock(chip); 3017 if (mv88e6xxx_pvt_map(chip, sw_index, port) || 3018 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num)) 3019 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 3020 mv88e6xxx_reg_unlock(chip); 3021 } 3022 3023 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 3024 { 3025 if (chip->info->ops->reset) 3026 return chip->info->ops->reset(chip); 3027 3028 return 0; 3029 } 3030 3031 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 3032 { 3033 struct gpio_desc *gpiod = chip->reset; 3034 3035 /* If there is a GPIO connected to the reset pin, toggle it */ 3036 if (gpiod) { 3037 gpiod_set_value_cansleep(gpiod, 1); 3038 usleep_range(10000, 20000); 3039 gpiod_set_value_cansleep(gpiod, 0); 3040 usleep_range(10000, 20000); 3041 3042 mv88e6xxx_g1_wait_eeprom_done(chip); 3043 } 3044 } 3045 3046 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 3047 { 3048 int i, err; 3049 3050 /* Set all ports to the Disabled state */ 3051 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3052 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 3053 if (err) 3054 return err; 3055 } 3056 3057 /* Wait for transmit queues to drain, 3058 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 3059 */ 3060 usleep_range(2000, 4000); 3061 3062 return 0; 3063 } 3064 3065 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 3066 { 3067 int err; 3068 3069 err = mv88e6xxx_disable_ports(chip); 3070 if (err) 3071 return err; 3072 3073 mv88e6xxx_hardware_reset(chip); 3074 3075 return mv88e6xxx_software_reset(chip); 3076 } 3077 3078 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 3079 enum mv88e6xxx_frame_mode frame, 3080 enum mv88e6xxx_egress_mode egress, u16 etype) 3081 { 3082 int err; 3083 3084 if (!chip->info->ops->port_set_frame_mode) 3085 return -EOPNOTSUPP; 3086 3087 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 3088 if (err) 3089 return err; 3090 3091 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 3092 if (err) 3093 return err; 3094 3095 if (chip->info->ops->port_set_ether_type) 3096 return chip->info->ops->port_set_ether_type(chip, port, etype); 3097 3098 return 0; 3099 } 3100 3101 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 3102 { 3103 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 3104 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 3105 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 3106 } 3107 3108 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 3109 { 3110 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 3111 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 3112 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 3113 } 3114 3115 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 3116 { 3117 return mv88e6xxx_set_port_mode(chip, port, 3118 MV88E6XXX_FRAME_MODE_ETHERTYPE, 3119 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 3120 ETH_P_EDSA); 3121 } 3122 3123 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 3124 { 3125 if (dsa_is_dsa_port(chip->ds, port)) 3126 return mv88e6xxx_set_port_mode_dsa(chip, port); 3127 3128 if (dsa_is_user_port(chip->ds, port)) 3129 return mv88e6xxx_set_port_mode_normal(chip, port); 3130 3131 /* Setup CPU port mode depending on its supported tag format */ 3132 if (chip->tag_protocol == DSA_TAG_PROTO_DSA) 3133 return mv88e6xxx_set_port_mode_dsa(chip, port); 3134 3135 if (chip->tag_protocol == DSA_TAG_PROTO_EDSA) 3136 return mv88e6xxx_set_port_mode_edsa(chip, port); 3137 3138 return -EINVAL; 3139 } 3140 3141 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 3142 { 3143 bool message = dsa_is_dsa_port(chip->ds, port); 3144 3145 return mv88e6xxx_port_set_message_port(chip, port, message); 3146 } 3147 3148 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 3149 { 3150 int err; 3151 3152 if (chip->info->ops->port_set_ucast_flood) { 3153 err = chip->info->ops->port_set_ucast_flood(chip, port, true); 3154 if (err) 3155 return err; 3156 } 3157 if (chip->info->ops->port_set_mcast_flood) { 3158 err = chip->info->ops->port_set_mcast_flood(chip, port, true); 3159 if (err) 3160 return err; 3161 } 3162 3163 return 0; 3164 } 3165 3166 static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id) 3167 { 3168 struct mv88e6xxx_port *mvp = dev_id; 3169 struct mv88e6xxx_chip *chip = mvp->chip; 3170 irqreturn_t ret = IRQ_NONE; 3171 int port = mvp->port; 3172 int lane; 3173 3174 mv88e6xxx_reg_lock(chip); 3175 lane = mv88e6xxx_serdes_get_lane(chip, port); 3176 if (lane >= 0) 3177 ret = mv88e6xxx_serdes_irq_status(chip, port, lane); 3178 mv88e6xxx_reg_unlock(chip); 3179 3180 return ret; 3181 } 3182 3183 static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port, 3184 int lane) 3185 { 3186 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 3187 unsigned int irq; 3188 int err; 3189 3190 /* Nothing to request if this SERDES port has no IRQ */ 3191 irq = mv88e6xxx_serdes_irq_mapping(chip, port); 3192 if (!irq) 3193 return 0; 3194 3195 snprintf(dev_id->serdes_irq_name, sizeof(dev_id->serdes_irq_name), 3196 "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port); 3197 3198 /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */ 3199 mv88e6xxx_reg_unlock(chip); 3200 err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn, 3201 IRQF_ONESHOT, dev_id->serdes_irq_name, 3202 dev_id); 3203 mv88e6xxx_reg_lock(chip); 3204 if (err) 3205 return err; 3206 3207 dev_id->serdes_irq = irq; 3208 3209 return mv88e6xxx_serdes_irq_enable(chip, port, lane); 3210 } 3211 3212 static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port, 3213 int lane) 3214 { 3215 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 3216 unsigned int irq = dev_id->serdes_irq; 3217 int err; 3218 3219 /* Nothing to free if no IRQ has been requested */ 3220 if (!irq) 3221 return 0; 3222 3223 err = mv88e6xxx_serdes_irq_disable(chip, port, lane); 3224 3225 /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */ 3226 mv88e6xxx_reg_unlock(chip); 3227 free_irq(irq, dev_id); 3228 mv88e6xxx_reg_lock(chip); 3229 3230 dev_id->serdes_irq = 0; 3231 3232 return err; 3233 } 3234 3235 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port, 3236 bool on) 3237 { 3238 int lane; 3239 int err; 3240 3241 lane = mv88e6xxx_serdes_get_lane(chip, port); 3242 if (lane < 0) 3243 return 0; 3244 3245 if (on) { 3246 err = mv88e6xxx_serdes_power_up(chip, port, lane); 3247 if (err) 3248 return err; 3249 3250 err = mv88e6xxx_serdes_irq_request(chip, port, lane); 3251 } else { 3252 err = mv88e6xxx_serdes_irq_free(chip, port, lane); 3253 if (err) 3254 return err; 3255 3256 err = mv88e6xxx_serdes_power_down(chip, port, lane); 3257 } 3258 3259 return err; 3260 } 3261 3262 static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip, 3263 enum mv88e6xxx_egress_direction direction, 3264 int port) 3265 { 3266 int err; 3267 3268 if (!chip->info->ops->set_egress_port) 3269 return -EOPNOTSUPP; 3270 3271 err = chip->info->ops->set_egress_port(chip, direction, port); 3272 if (err) 3273 return err; 3274 3275 if (direction == MV88E6XXX_EGRESS_DIR_INGRESS) 3276 chip->ingress_dest_port = port; 3277 else 3278 chip->egress_dest_port = port; 3279 3280 return 0; 3281 } 3282 3283 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 3284 { 3285 struct dsa_switch *ds = chip->ds; 3286 int upstream_port; 3287 int err; 3288 3289 upstream_port = dsa_upstream_port(ds, port); 3290 if (chip->info->ops->port_set_upstream_port) { 3291 err = chip->info->ops->port_set_upstream_port(chip, port, 3292 upstream_port); 3293 if (err) 3294 return err; 3295 } 3296 3297 if (port == upstream_port) { 3298 if (chip->info->ops->set_cpu_port) { 3299 err = chip->info->ops->set_cpu_port(chip, 3300 upstream_port); 3301 if (err) 3302 return err; 3303 } 3304 3305 err = mv88e6xxx_set_egress_port(chip, 3306 MV88E6XXX_EGRESS_DIR_INGRESS, 3307 upstream_port); 3308 if (err && err != -EOPNOTSUPP) 3309 return err; 3310 3311 err = mv88e6xxx_set_egress_port(chip, 3312 MV88E6XXX_EGRESS_DIR_EGRESS, 3313 upstream_port); 3314 if (err && err != -EOPNOTSUPP) 3315 return err; 3316 } 3317 3318 return 0; 3319 } 3320 3321 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 3322 { 3323 struct device_node *phy_handle = NULL; 3324 struct dsa_switch *ds = chip->ds; 3325 phy_interface_t mode; 3326 struct dsa_port *dp; 3327 int tx_amp, speed; 3328 int err; 3329 u16 reg; 3330 3331 chip->ports[port].chip = chip; 3332 chip->ports[port].port = port; 3333 3334 dp = dsa_to_port(ds, port); 3335 3336 /* MAC Forcing register: don't force link, speed, duplex or flow control 3337 * state to any particular values on physical ports, but force the CPU 3338 * port and all DSA ports to their maximum bandwidth and full duplex. 3339 */ 3340 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) { 3341 struct phylink_config pl_config = {}; 3342 unsigned long caps; 3343 3344 chip->info->ops->phylink_get_caps(chip, port, &pl_config); 3345 3346 caps = pl_config.mac_capabilities; 3347 3348 if (chip->info->ops->port_max_speed_mode) 3349 mode = chip->info->ops->port_max_speed_mode(chip, port); 3350 else 3351 mode = PHY_INTERFACE_MODE_NA; 3352 3353 if (caps & MAC_10000FD) 3354 speed = SPEED_10000; 3355 else if (caps & MAC_5000FD) 3356 speed = SPEED_5000; 3357 else if (caps & MAC_2500FD) 3358 speed = SPEED_2500; 3359 else if (caps & MAC_1000) 3360 speed = SPEED_1000; 3361 else if (caps & MAC_100) 3362 speed = SPEED_100; 3363 else 3364 speed = SPEED_10; 3365 3366 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, 3367 speed, DUPLEX_FULL, 3368 PAUSE_OFF, mode); 3369 } else { 3370 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 3371 SPEED_UNFORCED, DUPLEX_UNFORCED, 3372 PAUSE_ON, 3373 PHY_INTERFACE_MODE_NA); 3374 } 3375 if (err) 3376 return err; 3377 3378 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 3379 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 3380 * tunneling, determine priority by looking at 802.1p and IP 3381 * priority fields (IP prio has precedence), and set STP state 3382 * to Forwarding. 3383 * 3384 * If this is the CPU link, use DSA or EDSA tagging depending 3385 * on which tagging mode was configured. 3386 * 3387 * If this is a link to another switch, use DSA tagging mode. 3388 * 3389 * If this is the upstream port for this switch, enable 3390 * forwarding of unknown unicasts and multicasts. 3391 */ 3392 reg = MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 3393 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 3394 /* Forward any IPv4 IGMP or IPv6 MLD frames received 3395 * by a USER port to the CPU port to allow snooping. 3396 */ 3397 if (dsa_is_user_port(ds, port)) 3398 reg |= MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP; 3399 3400 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 3401 if (err) 3402 return err; 3403 3404 err = mv88e6xxx_setup_port_mode(chip, port); 3405 if (err) 3406 return err; 3407 3408 err = mv88e6xxx_setup_egress_floods(chip, port); 3409 if (err) 3410 return err; 3411 3412 /* Port Control 2: don't force a good FCS, set the MTU size to 3413 * 10222 bytes, disable 802.1q tags checking, don't discard 3414 * tagged or untagged frames on this port, skip destination 3415 * address lookup on user ports, disable ARP mirroring and don't 3416 * send a copy of all transmitted/received frames on this port 3417 * to the CPU. 3418 */ 3419 err = mv88e6xxx_port_set_map_da(chip, port, !dsa_is_user_port(ds, port)); 3420 if (err) 3421 return err; 3422 3423 err = mv88e6xxx_setup_upstream_port(chip, port); 3424 if (err) 3425 return err; 3426 3427 /* On chips that support it, set all downstream DSA ports' 3428 * VLAN policy to TRAP. In combination with loading 3429 * MV88E6XXX_VID_STANDALONE as a policy entry in the VTU, this 3430 * provides a better isolation barrier between standalone 3431 * ports, as the ATU is bypassed on any intermediate switches 3432 * between the incoming port and the CPU. 3433 */ 3434 if (dsa_is_downstream_port(ds, port) && 3435 chip->info->ops->port_set_policy) { 3436 err = chip->info->ops->port_set_policy(chip, port, 3437 MV88E6XXX_POLICY_MAPPING_VTU, 3438 MV88E6XXX_POLICY_ACTION_TRAP); 3439 if (err) 3440 return err; 3441 } 3442 3443 /* User ports start out in standalone mode and 802.1Q is 3444 * therefore disabled. On DSA ports, all valid VIDs are always 3445 * loaded in the VTU - therefore, enable 802.1Q in order to take 3446 * advantage of VLAN policy on chips that supports it. 3447 */ 3448 err = mv88e6xxx_port_set_8021q_mode(chip, port, 3449 dsa_is_user_port(ds, port) ? 3450 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED : 3451 MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE); 3452 if (err) 3453 return err; 3454 3455 /* Bind MV88E6XXX_VID_STANDALONE to MV88E6XXX_FID_STANDALONE by 3456 * virtue of the fact that mv88e6xxx_atu_new() will pick it as 3457 * the first free FID. This will be used as the private PVID for 3458 * unbridged ports. Shared (DSA and CPU) ports must also be 3459 * members of this VID, in order to trap all frames assigned to 3460 * it to the CPU. 3461 */ 3462 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_STANDALONE, 3463 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED, 3464 false); 3465 if (err) 3466 return err; 3467 3468 /* Associate MV88E6XXX_VID_BRIDGED with MV88E6XXX_FID_BRIDGED in the 3469 * ATU by virtue of the fact that mv88e6xxx_atu_new() will pick it as 3470 * the first free FID after MV88E6XXX_FID_STANDALONE. This will be used 3471 * as the private PVID on ports under a VLAN-unaware bridge. 3472 * Shared (DSA and CPU) ports must also be members of it, to translate 3473 * the VID from the DSA tag into MV88E6XXX_FID_BRIDGED, instead of 3474 * relying on their port default FID. 3475 */ 3476 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_BRIDGED, 3477 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED, 3478 false); 3479 if (err) 3480 return err; 3481 3482 if (chip->info->ops->port_set_jumbo_size) { 3483 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218); 3484 if (err) 3485 return err; 3486 } 3487 3488 /* Port Association Vector: disable automatic address learning 3489 * on all user ports since they start out in standalone 3490 * mode. When joining a bridge, learning will be configured to 3491 * match the bridge port settings. Enable learning on all 3492 * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the 3493 * learning process. 3494 * 3495 * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData, 3496 * and RefreshLocked. I.e. setup standard automatic learning. 3497 */ 3498 if (dsa_is_user_port(ds, port)) 3499 reg = 0; 3500 else 3501 reg = 1 << port; 3502 3503 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 3504 reg); 3505 if (err) 3506 return err; 3507 3508 /* Egress rate control 2: disable egress rate control. */ 3509 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 3510 0x0000); 3511 if (err) 3512 return err; 3513 3514 if (chip->info->ops->port_pause_limit) { 3515 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 3516 if (err) 3517 return err; 3518 } 3519 3520 if (chip->info->ops->port_disable_learn_limit) { 3521 err = chip->info->ops->port_disable_learn_limit(chip, port); 3522 if (err) 3523 return err; 3524 } 3525 3526 if (chip->info->ops->port_disable_pri_override) { 3527 err = chip->info->ops->port_disable_pri_override(chip, port); 3528 if (err) 3529 return err; 3530 } 3531 3532 if (chip->info->ops->port_tag_remap) { 3533 err = chip->info->ops->port_tag_remap(chip, port); 3534 if (err) 3535 return err; 3536 } 3537 3538 if (chip->info->ops->port_egress_rate_limiting) { 3539 err = chip->info->ops->port_egress_rate_limiting(chip, port); 3540 if (err) 3541 return err; 3542 } 3543 3544 if (chip->info->ops->port_setup_message_port) { 3545 err = chip->info->ops->port_setup_message_port(chip, port); 3546 if (err) 3547 return err; 3548 } 3549 3550 if (chip->info->ops->serdes_set_tx_amplitude) { 3551 if (dp) 3552 phy_handle = of_parse_phandle(dp->dn, "phy-handle", 0); 3553 3554 if (phy_handle && !of_property_read_u32(phy_handle, 3555 "tx-p2p-microvolt", 3556 &tx_amp)) 3557 err = chip->info->ops->serdes_set_tx_amplitude(chip, 3558 port, tx_amp); 3559 if (phy_handle) { 3560 of_node_put(phy_handle); 3561 if (err) 3562 return err; 3563 } 3564 } 3565 3566 /* Port based VLAN map: give each port the same default address 3567 * database, and allow bidirectional communication between the 3568 * CPU and DSA port(s), and the other ports. 3569 */ 3570 err = mv88e6xxx_port_set_fid(chip, port, MV88E6XXX_FID_STANDALONE); 3571 if (err) 3572 return err; 3573 3574 err = mv88e6xxx_port_vlan_map(chip, port); 3575 if (err) 3576 return err; 3577 3578 /* Default VLAN ID and priority: don't set a default VLAN 3579 * ID, and set the default packet priority to zero. 3580 */ 3581 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 3582 } 3583 3584 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port) 3585 { 3586 struct mv88e6xxx_chip *chip = ds->priv; 3587 3588 if (chip->info->ops->port_set_jumbo_size) 3589 return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3590 else if (chip->info->ops->set_max_frame_size) 3591 return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3592 return ETH_DATA_LEN; 3593 } 3594 3595 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 3596 { 3597 struct mv88e6xxx_chip *chip = ds->priv; 3598 int ret = 0; 3599 3600 /* For families where we don't know how to alter the MTU, 3601 * just accept any value up to ETH_DATA_LEN 3602 */ 3603 if (!chip->info->ops->port_set_jumbo_size && 3604 !chip->info->ops->set_max_frame_size) { 3605 if (new_mtu > ETH_DATA_LEN) 3606 return -EINVAL; 3607 3608 return 0; 3609 } 3610 3611 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 3612 new_mtu += EDSA_HLEN; 3613 3614 mv88e6xxx_reg_lock(chip); 3615 if (chip->info->ops->port_set_jumbo_size) 3616 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu); 3617 else if (chip->info->ops->set_max_frame_size) 3618 ret = chip->info->ops->set_max_frame_size(chip, new_mtu); 3619 mv88e6xxx_reg_unlock(chip); 3620 3621 return ret; 3622 } 3623 3624 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port, 3625 struct phy_device *phydev) 3626 { 3627 struct mv88e6xxx_chip *chip = ds->priv; 3628 int err; 3629 3630 mv88e6xxx_reg_lock(chip); 3631 err = mv88e6xxx_serdes_power(chip, port, true); 3632 mv88e6xxx_reg_unlock(chip); 3633 3634 return err; 3635 } 3636 3637 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port) 3638 { 3639 struct mv88e6xxx_chip *chip = ds->priv; 3640 3641 mv88e6xxx_reg_lock(chip); 3642 if (mv88e6xxx_serdes_power(chip, port, false)) 3643 dev_err(chip->dev, "failed to power off SERDES\n"); 3644 mv88e6xxx_reg_unlock(chip); 3645 } 3646 3647 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 3648 unsigned int ageing_time) 3649 { 3650 struct mv88e6xxx_chip *chip = ds->priv; 3651 int err; 3652 3653 mv88e6xxx_reg_lock(chip); 3654 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 3655 mv88e6xxx_reg_unlock(chip); 3656 3657 return err; 3658 } 3659 3660 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 3661 { 3662 int err; 3663 3664 /* Initialize the statistics unit */ 3665 if (chip->info->ops->stats_set_histogram) { 3666 err = chip->info->ops->stats_set_histogram(chip); 3667 if (err) 3668 return err; 3669 } 3670 3671 return mv88e6xxx_g1_stats_clear(chip); 3672 } 3673 3674 /* Check if the errata has already been applied. */ 3675 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip) 3676 { 3677 int port; 3678 int err; 3679 u16 val; 3680 3681 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3682 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val); 3683 if (err) { 3684 dev_err(chip->dev, 3685 "Error reading hidden register: %d\n", err); 3686 return false; 3687 } 3688 if (val != 0x01c0) 3689 return false; 3690 } 3691 3692 return true; 3693 } 3694 3695 /* The 6390 copper ports have an errata which require poking magic 3696 * values into undocumented hidden registers and then performing a 3697 * software reset. 3698 */ 3699 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) 3700 { 3701 int port; 3702 int err; 3703 3704 if (mv88e6390_setup_errata_applied(chip)) 3705 return 0; 3706 3707 /* Set the ports into blocking mode */ 3708 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3709 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED); 3710 if (err) 3711 return err; 3712 } 3713 3714 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3715 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0); 3716 if (err) 3717 return err; 3718 } 3719 3720 return mv88e6xxx_software_reset(chip); 3721 } 3722 3723 /* prod_id for switch families which do not have a PHY model number */ 3724 static const u16 family_prod_id_table[] = { 3725 [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 3726 [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 3727 [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 3728 }; 3729 3730 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 3731 { 3732 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3733 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3734 u16 prod_id; 3735 u16 val; 3736 int err; 3737 3738 if (!chip->info->ops->phy_read) 3739 return -EOPNOTSUPP; 3740 3741 mv88e6xxx_reg_lock(chip); 3742 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 3743 mv88e6xxx_reg_unlock(chip); 3744 3745 /* Some internal PHYs don't have a model number. */ 3746 if (reg == MII_PHYSID2 && !(val & 0x3f0) && 3747 chip->info->family < ARRAY_SIZE(family_prod_id_table)) { 3748 prod_id = family_prod_id_table[chip->info->family]; 3749 if (prod_id) 3750 val |= prod_id >> 4; 3751 } 3752 3753 return err ? err : val; 3754 } 3755 3756 static int mv88e6xxx_mdio_read_c45(struct mii_bus *bus, int phy, int devad, 3757 int reg) 3758 { 3759 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3760 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3761 u16 val; 3762 int err; 3763 3764 if (!chip->info->ops->phy_read_c45) 3765 return -EOPNOTSUPP; 3766 3767 mv88e6xxx_reg_lock(chip); 3768 err = chip->info->ops->phy_read_c45(chip, bus, phy, devad, reg, &val); 3769 mv88e6xxx_reg_unlock(chip); 3770 3771 return err ? err : val; 3772 } 3773 3774 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 3775 { 3776 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3777 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3778 int err; 3779 3780 if (!chip->info->ops->phy_write) 3781 return -EOPNOTSUPP; 3782 3783 mv88e6xxx_reg_lock(chip); 3784 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 3785 mv88e6xxx_reg_unlock(chip); 3786 3787 return err; 3788 } 3789 3790 static int mv88e6xxx_mdio_write_c45(struct mii_bus *bus, int phy, int devad, 3791 int reg, u16 val) 3792 { 3793 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3794 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3795 int err; 3796 3797 if (!chip->info->ops->phy_write_c45) 3798 return -EOPNOTSUPP; 3799 3800 mv88e6xxx_reg_lock(chip); 3801 err = chip->info->ops->phy_write_c45(chip, bus, phy, devad, reg, val); 3802 mv88e6xxx_reg_unlock(chip); 3803 3804 return err; 3805 } 3806 3807 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 3808 struct device_node *np, 3809 bool external) 3810 { 3811 static int index; 3812 struct mv88e6xxx_mdio_bus *mdio_bus; 3813 struct mii_bus *bus; 3814 int err; 3815 3816 if (external) { 3817 mv88e6xxx_reg_lock(chip); 3818 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true); 3819 mv88e6xxx_reg_unlock(chip); 3820 3821 if (err) 3822 return err; 3823 } 3824 3825 bus = mdiobus_alloc_size(sizeof(*mdio_bus)); 3826 if (!bus) 3827 return -ENOMEM; 3828 3829 mdio_bus = bus->priv; 3830 mdio_bus->bus = bus; 3831 mdio_bus->chip = chip; 3832 INIT_LIST_HEAD(&mdio_bus->list); 3833 mdio_bus->external = external; 3834 3835 if (np) { 3836 bus->name = np->full_name; 3837 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 3838 } else { 3839 bus->name = "mv88e6xxx SMI"; 3840 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 3841 } 3842 3843 bus->read = mv88e6xxx_mdio_read; 3844 bus->write = mv88e6xxx_mdio_write; 3845 bus->read_c45 = mv88e6xxx_mdio_read_c45; 3846 bus->write_c45 = mv88e6xxx_mdio_write_c45; 3847 bus->parent = chip->dev; 3848 bus->phy_mask = ~GENMASK(chip->info->phy_base_addr + 3849 mv88e6xxx_num_ports(chip) - 1, 3850 chip->info->phy_base_addr); 3851 3852 if (!external) { 3853 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); 3854 if (err) 3855 goto out; 3856 } 3857 3858 err = of_mdiobus_register(bus, np); 3859 if (err) { 3860 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 3861 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3862 goto out; 3863 } 3864 3865 if (external) 3866 list_add_tail(&mdio_bus->list, &chip->mdios); 3867 else 3868 list_add(&mdio_bus->list, &chip->mdios); 3869 3870 return 0; 3871 3872 out: 3873 mdiobus_free(bus); 3874 return err; 3875 } 3876 3877 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 3878 3879 { 3880 struct mv88e6xxx_mdio_bus *mdio_bus, *p; 3881 struct mii_bus *bus; 3882 3883 list_for_each_entry_safe(mdio_bus, p, &chip->mdios, list) { 3884 bus = mdio_bus->bus; 3885 3886 if (!mdio_bus->external) 3887 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3888 3889 mdiobus_unregister(bus); 3890 mdiobus_free(bus); 3891 } 3892 } 3893 3894 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip) 3895 { 3896 struct device_node *np = chip->dev->of_node; 3897 struct device_node *child; 3898 int err; 3899 3900 /* Always register one mdio bus for the internal/default mdio 3901 * bus. This maybe represented in the device tree, but is 3902 * optional. 3903 */ 3904 child = of_get_child_by_name(np, "mdio"); 3905 err = mv88e6xxx_mdio_register(chip, child, false); 3906 of_node_put(child); 3907 if (err) 3908 return err; 3909 3910 /* Walk the device tree, and see if there are any other nodes 3911 * which say they are compatible with the external mdio 3912 * bus. 3913 */ 3914 for_each_available_child_of_node(np, child) { 3915 if (of_device_is_compatible( 3916 child, "marvell,mv88e6xxx-mdio-external")) { 3917 err = mv88e6xxx_mdio_register(chip, child, true); 3918 if (err) { 3919 mv88e6xxx_mdios_unregister(chip); 3920 of_node_put(child); 3921 return err; 3922 } 3923 } 3924 } 3925 3926 return 0; 3927 } 3928 3929 static void mv88e6xxx_teardown(struct dsa_switch *ds) 3930 { 3931 struct mv88e6xxx_chip *chip = ds->priv; 3932 3933 mv88e6xxx_teardown_devlink_params(ds); 3934 dsa_devlink_resources_unregister(ds); 3935 mv88e6xxx_teardown_devlink_regions_global(ds); 3936 mv88e6xxx_mdios_unregister(chip); 3937 } 3938 3939 static int mv88e6xxx_setup(struct dsa_switch *ds) 3940 { 3941 struct mv88e6xxx_chip *chip = ds->priv; 3942 u8 cmode; 3943 int err; 3944 int i; 3945 3946 err = mv88e6xxx_mdios_register(chip); 3947 if (err) 3948 return err; 3949 3950 chip->ds = ds; 3951 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); 3952 3953 /* Since virtual bridges are mapped in the PVT, the number we support 3954 * depends on the physical switch topology. We need to let DSA figure 3955 * that out and therefore we cannot set this at dsa_register_switch() 3956 * time. 3957 */ 3958 if (mv88e6xxx_has_pvt(chip)) 3959 ds->max_num_bridges = MV88E6XXX_MAX_PVT_SWITCHES - 3960 ds->dst->last_switch - 1; 3961 3962 mv88e6xxx_reg_lock(chip); 3963 3964 if (chip->info->ops->setup_errata) { 3965 err = chip->info->ops->setup_errata(chip); 3966 if (err) 3967 goto unlock; 3968 } 3969 3970 /* Cache the cmode of each port. */ 3971 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3972 if (chip->info->ops->port_get_cmode) { 3973 err = chip->info->ops->port_get_cmode(chip, i, &cmode); 3974 if (err) 3975 goto unlock; 3976 3977 chip->ports[i].cmode = cmode; 3978 } 3979 } 3980 3981 err = mv88e6xxx_vtu_setup(chip); 3982 if (err) 3983 goto unlock; 3984 3985 /* Must be called after mv88e6xxx_vtu_setup (which flushes the 3986 * VTU, thereby also flushing the STU). 3987 */ 3988 err = mv88e6xxx_stu_setup(chip); 3989 if (err) 3990 goto unlock; 3991 3992 /* Setup Switch Port Registers */ 3993 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3994 if (dsa_is_unused_port(ds, i)) 3995 continue; 3996 3997 /* Prevent the use of an invalid port. */ 3998 if (mv88e6xxx_is_invalid_port(chip, i)) { 3999 dev_err(chip->dev, "port %d is invalid\n", i); 4000 err = -EINVAL; 4001 goto unlock; 4002 } 4003 4004 err = mv88e6xxx_setup_port(chip, i); 4005 if (err) 4006 goto unlock; 4007 } 4008 4009 err = mv88e6xxx_irl_setup(chip); 4010 if (err) 4011 goto unlock; 4012 4013 err = mv88e6xxx_mac_setup(chip); 4014 if (err) 4015 goto unlock; 4016 4017 err = mv88e6xxx_phy_setup(chip); 4018 if (err) 4019 goto unlock; 4020 4021 err = mv88e6xxx_pvt_setup(chip); 4022 if (err) 4023 goto unlock; 4024 4025 err = mv88e6xxx_atu_setup(chip); 4026 if (err) 4027 goto unlock; 4028 4029 err = mv88e6xxx_broadcast_setup(chip, 0); 4030 if (err) 4031 goto unlock; 4032 4033 err = mv88e6xxx_pot_setup(chip); 4034 if (err) 4035 goto unlock; 4036 4037 err = mv88e6xxx_rmu_setup(chip); 4038 if (err) 4039 goto unlock; 4040 4041 err = mv88e6xxx_rsvd2cpu_setup(chip); 4042 if (err) 4043 goto unlock; 4044 4045 err = mv88e6xxx_trunk_setup(chip); 4046 if (err) 4047 goto unlock; 4048 4049 err = mv88e6xxx_devmap_setup(chip); 4050 if (err) 4051 goto unlock; 4052 4053 err = mv88e6xxx_pri_setup(chip); 4054 if (err) 4055 goto unlock; 4056 4057 /* Setup PTP Hardware Clock and timestamping */ 4058 if (chip->info->ptp_support) { 4059 err = mv88e6xxx_ptp_setup(chip); 4060 if (err) 4061 goto unlock; 4062 4063 err = mv88e6xxx_hwtstamp_setup(chip); 4064 if (err) 4065 goto unlock; 4066 } 4067 4068 err = mv88e6xxx_stats_setup(chip); 4069 if (err) 4070 goto unlock; 4071 4072 unlock: 4073 mv88e6xxx_reg_unlock(chip); 4074 4075 if (err) 4076 goto out_mdios; 4077 4078 /* Have to be called without holding the register lock, since 4079 * they take the devlink lock, and we later take the locks in 4080 * the reverse order when getting/setting parameters or 4081 * resource occupancy. 4082 */ 4083 err = mv88e6xxx_setup_devlink_resources(ds); 4084 if (err) 4085 goto out_mdios; 4086 4087 err = mv88e6xxx_setup_devlink_params(ds); 4088 if (err) 4089 goto out_resources; 4090 4091 err = mv88e6xxx_setup_devlink_regions_global(ds); 4092 if (err) 4093 goto out_params; 4094 4095 return 0; 4096 4097 out_params: 4098 mv88e6xxx_teardown_devlink_params(ds); 4099 out_resources: 4100 dsa_devlink_resources_unregister(ds); 4101 out_mdios: 4102 mv88e6xxx_mdios_unregister(chip); 4103 4104 return err; 4105 } 4106 4107 static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port) 4108 { 4109 return mv88e6xxx_setup_devlink_regions_port(ds, port); 4110 } 4111 4112 static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port) 4113 { 4114 mv88e6xxx_teardown_devlink_regions_port(ds, port); 4115 } 4116 4117 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 4118 { 4119 struct mv88e6xxx_chip *chip = ds->priv; 4120 4121 return chip->eeprom_len; 4122 } 4123 4124 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 4125 struct ethtool_eeprom *eeprom, u8 *data) 4126 { 4127 struct mv88e6xxx_chip *chip = ds->priv; 4128 int err; 4129 4130 if (!chip->info->ops->get_eeprom) 4131 return -EOPNOTSUPP; 4132 4133 mv88e6xxx_reg_lock(chip); 4134 err = chip->info->ops->get_eeprom(chip, eeprom, data); 4135 mv88e6xxx_reg_unlock(chip); 4136 4137 if (err) 4138 return err; 4139 4140 eeprom->magic = 0xc3ec4951; 4141 4142 return 0; 4143 } 4144 4145 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 4146 struct ethtool_eeprom *eeprom, u8 *data) 4147 { 4148 struct mv88e6xxx_chip *chip = ds->priv; 4149 int err; 4150 4151 if (!chip->info->ops->set_eeprom) 4152 return -EOPNOTSUPP; 4153 4154 if (eeprom->magic != 0xc3ec4951) 4155 return -EINVAL; 4156 4157 mv88e6xxx_reg_lock(chip); 4158 err = chip->info->ops->set_eeprom(chip, eeprom, data); 4159 mv88e6xxx_reg_unlock(chip); 4160 4161 return err; 4162 } 4163 4164 static const struct mv88e6xxx_ops mv88e6085_ops = { 4165 /* MV88E6XXX_FAMILY_6097 */ 4166 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4167 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4168 .irl_init_all = mv88e6352_g2_irl_init_all, 4169 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4170 .phy_read = mv88e6185_phy_ppu_read, 4171 .phy_write = mv88e6185_phy_ppu_write, 4172 .port_set_link = mv88e6xxx_port_set_link, 4173 .port_sync_link = mv88e6xxx_port_sync_link, 4174 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4175 .port_tag_remap = mv88e6095_port_tag_remap, 4176 .port_set_policy = mv88e6352_port_set_policy, 4177 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4178 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4179 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4180 .port_set_ether_type = mv88e6351_port_set_ether_type, 4181 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4182 .port_pause_limit = mv88e6097_port_pause_limit, 4183 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4184 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4185 .port_get_cmode = mv88e6185_port_get_cmode, 4186 .port_setup_message_port = mv88e6xxx_setup_message_port, 4187 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4188 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4189 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4190 .stats_get_strings = mv88e6095_stats_get_strings, 4191 .stats_get_stats = mv88e6095_stats_get_stats, 4192 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4193 .set_egress_port = mv88e6095_g1_set_egress_port, 4194 .watchdog_ops = &mv88e6097_watchdog_ops, 4195 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4196 .pot_clear = mv88e6xxx_g2_pot_clear, 4197 .ppu_enable = mv88e6185_g1_ppu_enable, 4198 .ppu_disable = mv88e6185_g1_ppu_disable, 4199 .reset = mv88e6185_g1_reset, 4200 .rmu_disable = mv88e6085_g1_rmu_disable, 4201 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4202 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4203 .stu_getnext = mv88e6352_g1_stu_getnext, 4204 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4205 .phylink_get_caps = mv88e6185_phylink_get_caps, 4206 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4207 }; 4208 4209 static const struct mv88e6xxx_ops mv88e6095_ops = { 4210 /* MV88E6XXX_FAMILY_6095 */ 4211 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4212 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4213 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4214 .phy_read = mv88e6185_phy_ppu_read, 4215 .phy_write = mv88e6185_phy_ppu_write, 4216 .port_set_link = mv88e6xxx_port_set_link, 4217 .port_sync_link = mv88e6185_port_sync_link, 4218 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4219 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4220 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4221 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4222 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4223 .port_get_cmode = mv88e6185_port_get_cmode, 4224 .port_setup_message_port = mv88e6xxx_setup_message_port, 4225 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4226 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4227 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4228 .stats_get_strings = mv88e6095_stats_get_strings, 4229 .stats_get_stats = mv88e6095_stats_get_stats, 4230 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4231 .serdes_power = mv88e6185_serdes_power, 4232 .serdes_get_lane = mv88e6185_serdes_get_lane, 4233 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 4234 .ppu_enable = mv88e6185_g1_ppu_enable, 4235 .ppu_disable = mv88e6185_g1_ppu_disable, 4236 .reset = mv88e6185_g1_reset, 4237 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4238 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4239 .phylink_get_caps = mv88e6095_phylink_get_caps, 4240 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4241 }; 4242 4243 static const struct mv88e6xxx_ops mv88e6097_ops = { 4244 /* MV88E6XXX_FAMILY_6097 */ 4245 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4246 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4247 .irl_init_all = mv88e6352_g2_irl_init_all, 4248 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4249 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4250 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4251 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4252 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4253 .port_set_link = mv88e6xxx_port_set_link, 4254 .port_sync_link = mv88e6185_port_sync_link, 4255 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4256 .port_tag_remap = mv88e6095_port_tag_remap, 4257 .port_set_policy = mv88e6352_port_set_policy, 4258 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4259 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4260 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4261 .port_set_ether_type = mv88e6351_port_set_ether_type, 4262 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 4263 .port_pause_limit = mv88e6097_port_pause_limit, 4264 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4265 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4266 .port_get_cmode = mv88e6185_port_get_cmode, 4267 .port_setup_message_port = mv88e6xxx_setup_message_port, 4268 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4269 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4270 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4271 .stats_get_strings = mv88e6095_stats_get_strings, 4272 .stats_get_stats = mv88e6095_stats_get_stats, 4273 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4274 .set_egress_port = mv88e6095_g1_set_egress_port, 4275 .watchdog_ops = &mv88e6097_watchdog_ops, 4276 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4277 .serdes_power = mv88e6185_serdes_power, 4278 .serdes_get_lane = mv88e6185_serdes_get_lane, 4279 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 4280 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4281 .serdes_irq_enable = mv88e6097_serdes_irq_enable, 4282 .serdes_irq_status = mv88e6097_serdes_irq_status, 4283 .pot_clear = mv88e6xxx_g2_pot_clear, 4284 .reset = mv88e6352_g1_reset, 4285 .rmu_disable = mv88e6085_g1_rmu_disable, 4286 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4287 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4288 .phylink_get_caps = mv88e6095_phylink_get_caps, 4289 .stu_getnext = mv88e6352_g1_stu_getnext, 4290 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4291 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4292 }; 4293 4294 static const struct mv88e6xxx_ops mv88e6123_ops = { 4295 /* MV88E6XXX_FAMILY_6165 */ 4296 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4297 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4298 .irl_init_all = mv88e6352_g2_irl_init_all, 4299 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4300 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4301 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4302 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4303 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4304 .port_set_link = mv88e6xxx_port_set_link, 4305 .port_sync_link = mv88e6xxx_port_sync_link, 4306 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4307 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4308 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4309 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4310 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4311 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4312 .port_get_cmode = mv88e6185_port_get_cmode, 4313 .port_setup_message_port = mv88e6xxx_setup_message_port, 4314 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4315 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4316 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4317 .stats_get_strings = mv88e6095_stats_get_strings, 4318 .stats_get_stats = mv88e6095_stats_get_stats, 4319 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4320 .set_egress_port = mv88e6095_g1_set_egress_port, 4321 .watchdog_ops = &mv88e6097_watchdog_ops, 4322 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4323 .pot_clear = mv88e6xxx_g2_pot_clear, 4324 .reset = mv88e6352_g1_reset, 4325 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4326 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4327 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4328 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4329 .stu_getnext = mv88e6352_g1_stu_getnext, 4330 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4331 .phylink_get_caps = mv88e6185_phylink_get_caps, 4332 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4333 }; 4334 4335 static const struct mv88e6xxx_ops mv88e6131_ops = { 4336 /* MV88E6XXX_FAMILY_6185 */ 4337 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4338 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4339 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4340 .phy_read = mv88e6185_phy_ppu_read, 4341 .phy_write = mv88e6185_phy_ppu_write, 4342 .port_set_link = mv88e6xxx_port_set_link, 4343 .port_sync_link = mv88e6xxx_port_sync_link, 4344 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4345 .port_tag_remap = mv88e6095_port_tag_remap, 4346 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4347 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4348 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4349 .port_set_ether_type = mv88e6351_port_set_ether_type, 4350 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4351 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4352 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4353 .port_pause_limit = mv88e6097_port_pause_limit, 4354 .port_set_pause = mv88e6185_port_set_pause, 4355 .port_get_cmode = mv88e6185_port_get_cmode, 4356 .port_setup_message_port = mv88e6xxx_setup_message_port, 4357 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4358 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4359 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4360 .stats_get_strings = mv88e6095_stats_get_strings, 4361 .stats_get_stats = mv88e6095_stats_get_stats, 4362 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4363 .set_egress_port = mv88e6095_g1_set_egress_port, 4364 .watchdog_ops = &mv88e6097_watchdog_ops, 4365 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4366 .ppu_enable = mv88e6185_g1_ppu_enable, 4367 .set_cascade_port = mv88e6185_g1_set_cascade_port, 4368 .ppu_disable = mv88e6185_g1_ppu_disable, 4369 .reset = mv88e6185_g1_reset, 4370 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4371 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4372 .phylink_get_caps = mv88e6185_phylink_get_caps, 4373 }; 4374 4375 static const struct mv88e6xxx_ops mv88e6141_ops = { 4376 /* MV88E6XXX_FAMILY_6341 */ 4377 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4378 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4379 .irl_init_all = mv88e6352_g2_irl_init_all, 4380 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4381 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4382 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4383 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4384 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4385 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4386 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4387 .port_set_link = mv88e6xxx_port_set_link, 4388 .port_sync_link = mv88e6xxx_port_sync_link, 4389 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4390 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 4391 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 4392 .port_tag_remap = mv88e6095_port_tag_remap, 4393 .port_set_policy = mv88e6352_port_set_policy, 4394 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4395 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4396 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4397 .port_set_ether_type = mv88e6351_port_set_ether_type, 4398 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4399 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4400 .port_pause_limit = mv88e6097_port_pause_limit, 4401 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4402 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4403 .port_get_cmode = mv88e6352_port_get_cmode, 4404 .port_set_cmode = mv88e6341_port_set_cmode, 4405 .port_setup_message_port = mv88e6xxx_setup_message_port, 4406 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4407 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4408 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4409 .stats_get_strings = mv88e6320_stats_get_strings, 4410 .stats_get_stats = mv88e6390_stats_get_stats, 4411 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4412 .set_egress_port = mv88e6390_g1_set_egress_port, 4413 .watchdog_ops = &mv88e6390_watchdog_ops, 4414 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4415 .pot_clear = mv88e6xxx_g2_pot_clear, 4416 .reset = mv88e6352_g1_reset, 4417 .rmu_disable = mv88e6390_g1_rmu_disable, 4418 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4419 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4420 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4421 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4422 .stu_getnext = mv88e6352_g1_stu_getnext, 4423 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4424 .serdes_power = mv88e6390_serdes_power, 4425 .serdes_get_lane = mv88e6341_serdes_get_lane, 4426 /* Check status register pause & lpa register */ 4427 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4428 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4429 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4430 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4431 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4432 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4433 .serdes_irq_status = mv88e6390_serdes_irq_status, 4434 .gpio_ops = &mv88e6352_gpio_ops, 4435 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4436 .serdes_get_strings = mv88e6390_serdes_get_strings, 4437 .serdes_get_stats = mv88e6390_serdes_get_stats, 4438 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4439 .serdes_get_regs = mv88e6390_serdes_get_regs, 4440 .phylink_get_caps = mv88e6341_phylink_get_caps, 4441 }; 4442 4443 static const struct mv88e6xxx_ops mv88e6161_ops = { 4444 /* MV88E6XXX_FAMILY_6165 */ 4445 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4446 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4447 .irl_init_all = mv88e6352_g2_irl_init_all, 4448 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4449 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4450 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4451 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4452 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4453 .port_set_link = mv88e6xxx_port_set_link, 4454 .port_sync_link = mv88e6xxx_port_sync_link, 4455 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4456 .port_tag_remap = mv88e6095_port_tag_remap, 4457 .port_set_policy = mv88e6352_port_set_policy, 4458 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4459 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4460 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4461 .port_set_ether_type = mv88e6351_port_set_ether_type, 4462 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4463 .port_pause_limit = mv88e6097_port_pause_limit, 4464 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4465 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4466 .port_get_cmode = mv88e6185_port_get_cmode, 4467 .port_setup_message_port = mv88e6xxx_setup_message_port, 4468 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4469 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4470 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4471 .stats_get_strings = mv88e6095_stats_get_strings, 4472 .stats_get_stats = mv88e6095_stats_get_stats, 4473 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4474 .set_egress_port = mv88e6095_g1_set_egress_port, 4475 .watchdog_ops = &mv88e6097_watchdog_ops, 4476 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4477 .pot_clear = mv88e6xxx_g2_pot_clear, 4478 .reset = mv88e6352_g1_reset, 4479 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4480 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4481 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4482 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4483 .stu_getnext = mv88e6352_g1_stu_getnext, 4484 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4485 .avb_ops = &mv88e6165_avb_ops, 4486 .ptp_ops = &mv88e6165_ptp_ops, 4487 .phylink_get_caps = mv88e6185_phylink_get_caps, 4488 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4489 }; 4490 4491 static const struct mv88e6xxx_ops mv88e6165_ops = { 4492 /* MV88E6XXX_FAMILY_6165 */ 4493 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4494 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4495 .irl_init_all = mv88e6352_g2_irl_init_all, 4496 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4497 .phy_read = mv88e6165_phy_read, 4498 .phy_write = mv88e6165_phy_write, 4499 .port_set_link = mv88e6xxx_port_set_link, 4500 .port_sync_link = mv88e6xxx_port_sync_link, 4501 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4502 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4503 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4504 .port_get_cmode = mv88e6185_port_get_cmode, 4505 .port_setup_message_port = mv88e6xxx_setup_message_port, 4506 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4507 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4508 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4509 .stats_get_strings = mv88e6095_stats_get_strings, 4510 .stats_get_stats = mv88e6095_stats_get_stats, 4511 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4512 .set_egress_port = mv88e6095_g1_set_egress_port, 4513 .watchdog_ops = &mv88e6097_watchdog_ops, 4514 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4515 .pot_clear = mv88e6xxx_g2_pot_clear, 4516 .reset = mv88e6352_g1_reset, 4517 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4518 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4519 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4520 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4521 .stu_getnext = mv88e6352_g1_stu_getnext, 4522 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4523 .avb_ops = &mv88e6165_avb_ops, 4524 .ptp_ops = &mv88e6165_ptp_ops, 4525 .phylink_get_caps = mv88e6185_phylink_get_caps, 4526 }; 4527 4528 static const struct mv88e6xxx_ops mv88e6171_ops = { 4529 /* MV88E6XXX_FAMILY_6351 */ 4530 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4531 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4532 .irl_init_all = mv88e6352_g2_irl_init_all, 4533 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4534 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4535 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4536 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4537 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4538 .port_set_link = mv88e6xxx_port_set_link, 4539 .port_sync_link = mv88e6xxx_port_sync_link, 4540 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4541 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4542 .port_tag_remap = mv88e6095_port_tag_remap, 4543 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4544 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4545 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4546 .port_set_ether_type = mv88e6351_port_set_ether_type, 4547 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4548 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4549 .port_pause_limit = mv88e6097_port_pause_limit, 4550 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4551 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4552 .port_get_cmode = mv88e6352_port_get_cmode, 4553 .port_setup_message_port = mv88e6xxx_setup_message_port, 4554 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4555 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4556 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4557 .stats_get_strings = mv88e6095_stats_get_strings, 4558 .stats_get_stats = mv88e6095_stats_get_stats, 4559 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4560 .set_egress_port = mv88e6095_g1_set_egress_port, 4561 .watchdog_ops = &mv88e6097_watchdog_ops, 4562 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4563 .pot_clear = mv88e6xxx_g2_pot_clear, 4564 .reset = mv88e6352_g1_reset, 4565 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4566 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4567 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4568 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4569 .stu_getnext = mv88e6352_g1_stu_getnext, 4570 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4571 .phylink_get_caps = mv88e6185_phylink_get_caps, 4572 }; 4573 4574 static const struct mv88e6xxx_ops mv88e6172_ops = { 4575 /* MV88E6XXX_FAMILY_6352 */ 4576 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4577 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4578 .irl_init_all = mv88e6352_g2_irl_init_all, 4579 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4580 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4581 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4582 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4583 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4584 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4585 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4586 .port_set_link = mv88e6xxx_port_set_link, 4587 .port_sync_link = mv88e6xxx_port_sync_link, 4588 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4589 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4590 .port_tag_remap = mv88e6095_port_tag_remap, 4591 .port_set_policy = mv88e6352_port_set_policy, 4592 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4593 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4594 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4595 .port_set_ether_type = mv88e6351_port_set_ether_type, 4596 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4597 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4598 .port_pause_limit = mv88e6097_port_pause_limit, 4599 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4600 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4601 .port_get_cmode = mv88e6352_port_get_cmode, 4602 .port_setup_message_port = mv88e6xxx_setup_message_port, 4603 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4604 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4605 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4606 .stats_get_strings = mv88e6095_stats_get_strings, 4607 .stats_get_stats = mv88e6095_stats_get_stats, 4608 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4609 .set_egress_port = mv88e6095_g1_set_egress_port, 4610 .watchdog_ops = &mv88e6097_watchdog_ops, 4611 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4612 .pot_clear = mv88e6xxx_g2_pot_clear, 4613 .reset = mv88e6352_g1_reset, 4614 .rmu_disable = mv88e6352_g1_rmu_disable, 4615 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4616 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4617 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4618 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4619 .stu_getnext = mv88e6352_g1_stu_getnext, 4620 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4621 .serdes_get_lane = mv88e6352_serdes_get_lane, 4622 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4623 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4624 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4625 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4626 .serdes_power = mv88e6352_serdes_power, 4627 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4628 .serdes_get_regs = mv88e6352_serdes_get_regs, 4629 .gpio_ops = &mv88e6352_gpio_ops, 4630 .phylink_get_caps = mv88e6352_phylink_get_caps, 4631 }; 4632 4633 static const struct mv88e6xxx_ops mv88e6175_ops = { 4634 /* MV88E6XXX_FAMILY_6351 */ 4635 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4636 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4637 .irl_init_all = mv88e6352_g2_irl_init_all, 4638 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4639 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4640 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4641 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4642 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4643 .port_set_link = mv88e6xxx_port_set_link, 4644 .port_sync_link = mv88e6xxx_port_sync_link, 4645 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4646 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4647 .port_tag_remap = mv88e6095_port_tag_remap, 4648 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4649 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4650 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4651 .port_set_ether_type = mv88e6351_port_set_ether_type, 4652 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4653 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4654 .port_pause_limit = mv88e6097_port_pause_limit, 4655 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4656 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4657 .port_get_cmode = mv88e6352_port_get_cmode, 4658 .port_setup_message_port = mv88e6xxx_setup_message_port, 4659 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4660 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4661 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4662 .stats_get_strings = mv88e6095_stats_get_strings, 4663 .stats_get_stats = mv88e6095_stats_get_stats, 4664 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4665 .set_egress_port = mv88e6095_g1_set_egress_port, 4666 .watchdog_ops = &mv88e6097_watchdog_ops, 4667 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4668 .pot_clear = mv88e6xxx_g2_pot_clear, 4669 .reset = mv88e6352_g1_reset, 4670 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4671 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4672 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4673 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4674 .stu_getnext = mv88e6352_g1_stu_getnext, 4675 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4676 .phylink_get_caps = mv88e6185_phylink_get_caps, 4677 }; 4678 4679 static const struct mv88e6xxx_ops mv88e6176_ops = { 4680 /* MV88E6XXX_FAMILY_6352 */ 4681 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4682 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4683 .irl_init_all = mv88e6352_g2_irl_init_all, 4684 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4685 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4686 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4687 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4688 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4689 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4690 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4691 .port_set_link = mv88e6xxx_port_set_link, 4692 .port_sync_link = mv88e6xxx_port_sync_link, 4693 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4694 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4695 .port_tag_remap = mv88e6095_port_tag_remap, 4696 .port_set_policy = mv88e6352_port_set_policy, 4697 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4698 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4699 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4700 .port_set_ether_type = mv88e6351_port_set_ether_type, 4701 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4702 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4703 .port_pause_limit = mv88e6097_port_pause_limit, 4704 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4705 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4706 .port_get_cmode = mv88e6352_port_get_cmode, 4707 .port_setup_message_port = mv88e6xxx_setup_message_port, 4708 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4709 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4710 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4711 .stats_get_strings = mv88e6095_stats_get_strings, 4712 .stats_get_stats = mv88e6095_stats_get_stats, 4713 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4714 .set_egress_port = mv88e6095_g1_set_egress_port, 4715 .watchdog_ops = &mv88e6097_watchdog_ops, 4716 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4717 .pot_clear = mv88e6xxx_g2_pot_clear, 4718 .reset = mv88e6352_g1_reset, 4719 .rmu_disable = mv88e6352_g1_rmu_disable, 4720 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4721 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4722 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4723 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4724 .stu_getnext = mv88e6352_g1_stu_getnext, 4725 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4726 .serdes_get_lane = mv88e6352_serdes_get_lane, 4727 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4728 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4729 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4730 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4731 .serdes_power = mv88e6352_serdes_power, 4732 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4733 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4734 .serdes_irq_status = mv88e6352_serdes_irq_status, 4735 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4736 .serdes_get_regs = mv88e6352_serdes_get_regs, 4737 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 4738 .gpio_ops = &mv88e6352_gpio_ops, 4739 .phylink_get_caps = mv88e6352_phylink_get_caps, 4740 }; 4741 4742 static const struct mv88e6xxx_ops mv88e6185_ops = { 4743 /* MV88E6XXX_FAMILY_6185 */ 4744 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4745 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4746 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4747 .phy_read = mv88e6185_phy_ppu_read, 4748 .phy_write = mv88e6185_phy_ppu_write, 4749 .port_set_link = mv88e6xxx_port_set_link, 4750 .port_sync_link = mv88e6185_port_sync_link, 4751 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4752 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4753 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4754 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4755 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 4756 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4757 .port_set_pause = mv88e6185_port_set_pause, 4758 .port_get_cmode = mv88e6185_port_get_cmode, 4759 .port_setup_message_port = mv88e6xxx_setup_message_port, 4760 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4761 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4762 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4763 .stats_get_strings = mv88e6095_stats_get_strings, 4764 .stats_get_stats = mv88e6095_stats_get_stats, 4765 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4766 .set_egress_port = mv88e6095_g1_set_egress_port, 4767 .watchdog_ops = &mv88e6097_watchdog_ops, 4768 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4769 .serdes_power = mv88e6185_serdes_power, 4770 .serdes_get_lane = mv88e6185_serdes_get_lane, 4771 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 4772 .set_cascade_port = mv88e6185_g1_set_cascade_port, 4773 .ppu_enable = mv88e6185_g1_ppu_enable, 4774 .ppu_disable = mv88e6185_g1_ppu_disable, 4775 .reset = mv88e6185_g1_reset, 4776 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4777 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4778 .phylink_get_caps = mv88e6185_phylink_get_caps, 4779 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4780 }; 4781 4782 static const struct mv88e6xxx_ops mv88e6190_ops = { 4783 /* MV88E6XXX_FAMILY_6390 */ 4784 .setup_errata = mv88e6390_setup_errata, 4785 .irl_init_all = mv88e6390_g2_irl_init_all, 4786 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4787 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4788 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4789 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4790 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4791 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4792 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4793 .port_set_link = mv88e6xxx_port_set_link, 4794 .port_sync_link = mv88e6xxx_port_sync_link, 4795 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4796 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4797 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4798 .port_tag_remap = mv88e6390_port_tag_remap, 4799 .port_set_policy = mv88e6352_port_set_policy, 4800 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4801 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4802 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4803 .port_set_ether_type = mv88e6351_port_set_ether_type, 4804 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4805 .port_pause_limit = mv88e6390_port_pause_limit, 4806 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4807 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4808 .port_get_cmode = mv88e6352_port_get_cmode, 4809 .port_set_cmode = mv88e6390_port_set_cmode, 4810 .port_setup_message_port = mv88e6xxx_setup_message_port, 4811 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4812 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4813 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4814 .stats_get_strings = mv88e6320_stats_get_strings, 4815 .stats_get_stats = mv88e6390_stats_get_stats, 4816 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4817 .set_egress_port = mv88e6390_g1_set_egress_port, 4818 .watchdog_ops = &mv88e6390_watchdog_ops, 4819 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4820 .pot_clear = mv88e6xxx_g2_pot_clear, 4821 .reset = mv88e6352_g1_reset, 4822 .rmu_disable = mv88e6390_g1_rmu_disable, 4823 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4824 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4825 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4826 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4827 .stu_getnext = mv88e6390_g1_stu_getnext, 4828 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4829 .serdes_power = mv88e6390_serdes_power, 4830 .serdes_get_lane = mv88e6390_serdes_get_lane, 4831 /* Check status register pause & lpa register */ 4832 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4833 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4834 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4835 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4836 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4837 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4838 .serdes_irq_status = mv88e6390_serdes_irq_status, 4839 .serdes_get_strings = mv88e6390_serdes_get_strings, 4840 .serdes_get_stats = mv88e6390_serdes_get_stats, 4841 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4842 .serdes_get_regs = mv88e6390_serdes_get_regs, 4843 .gpio_ops = &mv88e6352_gpio_ops, 4844 .phylink_get_caps = mv88e6390_phylink_get_caps, 4845 }; 4846 4847 static const struct mv88e6xxx_ops mv88e6190x_ops = { 4848 /* MV88E6XXX_FAMILY_6390 */ 4849 .setup_errata = mv88e6390_setup_errata, 4850 .irl_init_all = mv88e6390_g2_irl_init_all, 4851 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4852 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4853 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4854 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4855 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4856 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4857 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4858 .port_set_link = mv88e6xxx_port_set_link, 4859 .port_sync_link = mv88e6xxx_port_sync_link, 4860 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4861 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 4862 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4863 .port_tag_remap = mv88e6390_port_tag_remap, 4864 .port_set_policy = mv88e6352_port_set_policy, 4865 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4866 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4867 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4868 .port_set_ether_type = mv88e6351_port_set_ether_type, 4869 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4870 .port_pause_limit = mv88e6390_port_pause_limit, 4871 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4872 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4873 .port_get_cmode = mv88e6352_port_get_cmode, 4874 .port_set_cmode = mv88e6390x_port_set_cmode, 4875 .port_setup_message_port = mv88e6xxx_setup_message_port, 4876 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4877 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4878 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4879 .stats_get_strings = mv88e6320_stats_get_strings, 4880 .stats_get_stats = mv88e6390_stats_get_stats, 4881 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4882 .set_egress_port = mv88e6390_g1_set_egress_port, 4883 .watchdog_ops = &mv88e6390_watchdog_ops, 4884 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4885 .pot_clear = mv88e6xxx_g2_pot_clear, 4886 .reset = mv88e6352_g1_reset, 4887 .rmu_disable = mv88e6390_g1_rmu_disable, 4888 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4889 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4890 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4891 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4892 .stu_getnext = mv88e6390_g1_stu_getnext, 4893 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4894 .serdes_power = mv88e6390_serdes_power, 4895 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4896 /* Check status register pause & lpa register */ 4897 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4898 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4899 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4900 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4901 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4902 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4903 .serdes_irq_status = mv88e6390_serdes_irq_status, 4904 .serdes_get_strings = mv88e6390_serdes_get_strings, 4905 .serdes_get_stats = mv88e6390_serdes_get_stats, 4906 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4907 .serdes_get_regs = mv88e6390_serdes_get_regs, 4908 .gpio_ops = &mv88e6352_gpio_ops, 4909 .phylink_get_caps = mv88e6390x_phylink_get_caps, 4910 }; 4911 4912 static const struct mv88e6xxx_ops mv88e6191_ops = { 4913 /* MV88E6XXX_FAMILY_6390 */ 4914 .setup_errata = mv88e6390_setup_errata, 4915 .irl_init_all = mv88e6390_g2_irl_init_all, 4916 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4917 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4918 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4919 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4920 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4921 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4922 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4923 .port_set_link = mv88e6xxx_port_set_link, 4924 .port_sync_link = mv88e6xxx_port_sync_link, 4925 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4926 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4927 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4928 .port_tag_remap = mv88e6390_port_tag_remap, 4929 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4930 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4931 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4932 .port_set_ether_type = mv88e6351_port_set_ether_type, 4933 .port_pause_limit = mv88e6390_port_pause_limit, 4934 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4935 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4936 .port_get_cmode = mv88e6352_port_get_cmode, 4937 .port_set_cmode = mv88e6390_port_set_cmode, 4938 .port_setup_message_port = mv88e6xxx_setup_message_port, 4939 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4940 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4941 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4942 .stats_get_strings = mv88e6320_stats_get_strings, 4943 .stats_get_stats = mv88e6390_stats_get_stats, 4944 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4945 .set_egress_port = mv88e6390_g1_set_egress_port, 4946 .watchdog_ops = &mv88e6390_watchdog_ops, 4947 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4948 .pot_clear = mv88e6xxx_g2_pot_clear, 4949 .reset = mv88e6352_g1_reset, 4950 .rmu_disable = mv88e6390_g1_rmu_disable, 4951 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4952 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4953 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4954 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4955 .stu_getnext = mv88e6390_g1_stu_getnext, 4956 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4957 .serdes_power = mv88e6390_serdes_power, 4958 .serdes_get_lane = mv88e6390_serdes_get_lane, 4959 /* Check status register pause & lpa register */ 4960 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4961 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4962 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4963 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4964 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4965 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4966 .serdes_irq_status = mv88e6390_serdes_irq_status, 4967 .serdes_get_strings = mv88e6390_serdes_get_strings, 4968 .serdes_get_stats = mv88e6390_serdes_get_stats, 4969 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4970 .serdes_get_regs = mv88e6390_serdes_get_regs, 4971 .avb_ops = &mv88e6390_avb_ops, 4972 .ptp_ops = &mv88e6352_ptp_ops, 4973 .phylink_get_caps = mv88e6390_phylink_get_caps, 4974 }; 4975 4976 static const struct mv88e6xxx_ops mv88e6240_ops = { 4977 /* MV88E6XXX_FAMILY_6352 */ 4978 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4979 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4980 .irl_init_all = mv88e6352_g2_irl_init_all, 4981 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4982 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4983 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4984 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4985 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4986 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4987 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4988 .port_set_link = mv88e6xxx_port_set_link, 4989 .port_sync_link = mv88e6xxx_port_sync_link, 4990 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4991 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4992 .port_tag_remap = mv88e6095_port_tag_remap, 4993 .port_set_policy = mv88e6352_port_set_policy, 4994 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4995 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4996 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4997 .port_set_ether_type = mv88e6351_port_set_ether_type, 4998 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4999 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5000 .port_pause_limit = mv88e6097_port_pause_limit, 5001 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5002 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5003 .port_get_cmode = mv88e6352_port_get_cmode, 5004 .port_setup_message_port = mv88e6xxx_setup_message_port, 5005 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5006 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5007 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5008 .stats_get_strings = mv88e6095_stats_get_strings, 5009 .stats_get_stats = mv88e6095_stats_get_stats, 5010 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5011 .set_egress_port = mv88e6095_g1_set_egress_port, 5012 .watchdog_ops = &mv88e6097_watchdog_ops, 5013 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5014 .pot_clear = mv88e6xxx_g2_pot_clear, 5015 .reset = mv88e6352_g1_reset, 5016 .rmu_disable = mv88e6352_g1_rmu_disable, 5017 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5018 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5019 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5020 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5021 .stu_getnext = mv88e6352_g1_stu_getnext, 5022 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5023 .serdes_get_lane = mv88e6352_serdes_get_lane, 5024 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 5025 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 5026 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 5027 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 5028 .serdes_power = mv88e6352_serdes_power, 5029 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 5030 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 5031 .serdes_irq_status = mv88e6352_serdes_irq_status, 5032 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 5033 .serdes_get_regs = mv88e6352_serdes_get_regs, 5034 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 5035 .gpio_ops = &mv88e6352_gpio_ops, 5036 .avb_ops = &mv88e6352_avb_ops, 5037 .ptp_ops = &mv88e6352_ptp_ops, 5038 .phylink_get_caps = mv88e6352_phylink_get_caps, 5039 }; 5040 5041 static const struct mv88e6xxx_ops mv88e6250_ops = { 5042 /* MV88E6XXX_FAMILY_6250 */ 5043 .ieee_pri_map = mv88e6250_g1_ieee_pri_map, 5044 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5045 .irl_init_all = mv88e6352_g2_irl_init_all, 5046 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5047 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5048 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5049 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5050 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5051 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5052 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5053 .port_set_link = mv88e6xxx_port_set_link, 5054 .port_sync_link = mv88e6xxx_port_sync_link, 5055 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5056 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex, 5057 .port_tag_remap = mv88e6095_port_tag_remap, 5058 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5059 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5060 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5061 .port_set_ether_type = mv88e6351_port_set_ether_type, 5062 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5063 .port_pause_limit = mv88e6097_port_pause_limit, 5064 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5065 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5066 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5067 .stats_get_sset_count = mv88e6250_stats_get_sset_count, 5068 .stats_get_strings = mv88e6250_stats_get_strings, 5069 .stats_get_stats = mv88e6250_stats_get_stats, 5070 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5071 .set_egress_port = mv88e6095_g1_set_egress_port, 5072 .watchdog_ops = &mv88e6250_watchdog_ops, 5073 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5074 .pot_clear = mv88e6xxx_g2_pot_clear, 5075 .reset = mv88e6250_g1_reset, 5076 .vtu_getnext = mv88e6185_g1_vtu_getnext, 5077 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 5078 .avb_ops = &mv88e6352_avb_ops, 5079 .ptp_ops = &mv88e6250_ptp_ops, 5080 .phylink_get_caps = mv88e6250_phylink_get_caps, 5081 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 5082 }; 5083 5084 static const struct mv88e6xxx_ops mv88e6290_ops = { 5085 /* MV88E6XXX_FAMILY_6390 */ 5086 .setup_errata = mv88e6390_setup_errata, 5087 .irl_init_all = mv88e6390_g2_irl_init_all, 5088 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5089 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5090 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5091 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5092 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5093 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5094 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5095 .port_set_link = mv88e6xxx_port_set_link, 5096 .port_sync_link = mv88e6xxx_port_sync_link, 5097 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5098 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 5099 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 5100 .port_tag_remap = mv88e6390_port_tag_remap, 5101 .port_set_policy = mv88e6352_port_set_policy, 5102 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5103 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5104 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5105 .port_set_ether_type = mv88e6351_port_set_ether_type, 5106 .port_pause_limit = mv88e6390_port_pause_limit, 5107 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5108 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5109 .port_get_cmode = mv88e6352_port_get_cmode, 5110 .port_set_cmode = mv88e6390_port_set_cmode, 5111 .port_setup_message_port = mv88e6xxx_setup_message_port, 5112 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5113 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5114 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5115 .stats_get_strings = mv88e6320_stats_get_strings, 5116 .stats_get_stats = mv88e6390_stats_get_stats, 5117 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5118 .set_egress_port = mv88e6390_g1_set_egress_port, 5119 .watchdog_ops = &mv88e6390_watchdog_ops, 5120 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5121 .pot_clear = mv88e6xxx_g2_pot_clear, 5122 .reset = mv88e6352_g1_reset, 5123 .rmu_disable = mv88e6390_g1_rmu_disable, 5124 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5125 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5126 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5127 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5128 .stu_getnext = mv88e6390_g1_stu_getnext, 5129 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5130 .serdes_power = mv88e6390_serdes_power, 5131 .serdes_get_lane = mv88e6390_serdes_get_lane, 5132 /* Check status register pause & lpa register */ 5133 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 5134 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 5135 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 5136 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 5137 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5138 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 5139 .serdes_irq_status = mv88e6390_serdes_irq_status, 5140 .serdes_get_strings = mv88e6390_serdes_get_strings, 5141 .serdes_get_stats = mv88e6390_serdes_get_stats, 5142 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5143 .serdes_get_regs = mv88e6390_serdes_get_regs, 5144 .gpio_ops = &mv88e6352_gpio_ops, 5145 .avb_ops = &mv88e6390_avb_ops, 5146 .ptp_ops = &mv88e6390_ptp_ops, 5147 .phylink_get_caps = mv88e6390_phylink_get_caps, 5148 }; 5149 5150 static const struct mv88e6xxx_ops mv88e6320_ops = { 5151 /* MV88E6XXX_FAMILY_6320 */ 5152 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5153 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5154 .irl_init_all = mv88e6352_g2_irl_init_all, 5155 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5156 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5157 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5158 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5159 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5160 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5161 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5162 .port_set_link = mv88e6xxx_port_set_link, 5163 .port_sync_link = mv88e6xxx_port_sync_link, 5164 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay, 5165 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5166 .port_tag_remap = mv88e6095_port_tag_remap, 5167 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5168 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5169 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5170 .port_set_ether_type = mv88e6351_port_set_ether_type, 5171 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5172 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5173 .port_pause_limit = mv88e6097_port_pause_limit, 5174 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5175 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5176 .port_get_cmode = mv88e6352_port_get_cmode, 5177 .port_setup_message_port = mv88e6xxx_setup_message_port, 5178 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5179 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5180 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5181 .stats_get_strings = mv88e6320_stats_get_strings, 5182 .stats_get_stats = mv88e6320_stats_get_stats, 5183 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5184 .set_egress_port = mv88e6095_g1_set_egress_port, 5185 .watchdog_ops = &mv88e6390_watchdog_ops, 5186 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5187 .pot_clear = mv88e6xxx_g2_pot_clear, 5188 .reset = mv88e6352_g1_reset, 5189 .vtu_getnext = mv88e6185_g1_vtu_getnext, 5190 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 5191 .gpio_ops = &mv88e6352_gpio_ops, 5192 .avb_ops = &mv88e6352_avb_ops, 5193 .ptp_ops = &mv88e6352_ptp_ops, 5194 .phylink_get_caps = mv88e6185_phylink_get_caps, 5195 }; 5196 5197 static const struct mv88e6xxx_ops mv88e6321_ops = { 5198 /* MV88E6XXX_FAMILY_6320 */ 5199 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5200 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5201 .irl_init_all = mv88e6352_g2_irl_init_all, 5202 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5203 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5204 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5205 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5206 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5207 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5208 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5209 .port_set_link = mv88e6xxx_port_set_link, 5210 .port_sync_link = mv88e6xxx_port_sync_link, 5211 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay, 5212 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5213 .port_tag_remap = mv88e6095_port_tag_remap, 5214 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5215 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5216 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5217 .port_set_ether_type = mv88e6351_port_set_ether_type, 5218 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5219 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5220 .port_pause_limit = mv88e6097_port_pause_limit, 5221 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5222 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5223 .port_get_cmode = mv88e6352_port_get_cmode, 5224 .port_setup_message_port = mv88e6xxx_setup_message_port, 5225 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5226 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5227 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5228 .stats_get_strings = mv88e6320_stats_get_strings, 5229 .stats_get_stats = mv88e6320_stats_get_stats, 5230 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5231 .set_egress_port = mv88e6095_g1_set_egress_port, 5232 .watchdog_ops = &mv88e6390_watchdog_ops, 5233 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5234 .reset = mv88e6352_g1_reset, 5235 .vtu_getnext = mv88e6185_g1_vtu_getnext, 5236 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 5237 .gpio_ops = &mv88e6352_gpio_ops, 5238 .avb_ops = &mv88e6352_avb_ops, 5239 .ptp_ops = &mv88e6352_ptp_ops, 5240 .phylink_get_caps = mv88e6185_phylink_get_caps, 5241 }; 5242 5243 static const struct mv88e6xxx_ops mv88e6341_ops = { 5244 /* MV88E6XXX_FAMILY_6341 */ 5245 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5246 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5247 .irl_init_all = mv88e6352_g2_irl_init_all, 5248 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5249 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5250 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5251 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5252 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5253 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5254 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5255 .port_set_link = mv88e6xxx_port_set_link, 5256 .port_sync_link = mv88e6xxx_port_sync_link, 5257 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5258 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 5259 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 5260 .port_tag_remap = mv88e6095_port_tag_remap, 5261 .port_set_policy = mv88e6352_port_set_policy, 5262 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5263 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5264 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5265 .port_set_ether_type = mv88e6351_port_set_ether_type, 5266 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5267 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5268 .port_pause_limit = mv88e6097_port_pause_limit, 5269 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5270 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5271 .port_get_cmode = mv88e6352_port_get_cmode, 5272 .port_set_cmode = mv88e6341_port_set_cmode, 5273 .port_setup_message_port = mv88e6xxx_setup_message_port, 5274 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5275 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5276 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5277 .stats_get_strings = mv88e6320_stats_get_strings, 5278 .stats_get_stats = mv88e6390_stats_get_stats, 5279 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5280 .set_egress_port = mv88e6390_g1_set_egress_port, 5281 .watchdog_ops = &mv88e6390_watchdog_ops, 5282 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5283 .pot_clear = mv88e6xxx_g2_pot_clear, 5284 .reset = mv88e6352_g1_reset, 5285 .rmu_disable = mv88e6390_g1_rmu_disable, 5286 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5287 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5288 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5289 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5290 .stu_getnext = mv88e6352_g1_stu_getnext, 5291 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5292 .serdes_power = mv88e6390_serdes_power, 5293 .serdes_get_lane = mv88e6341_serdes_get_lane, 5294 /* Check status register pause & lpa register */ 5295 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 5296 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 5297 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 5298 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 5299 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5300 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 5301 .serdes_irq_status = mv88e6390_serdes_irq_status, 5302 .gpio_ops = &mv88e6352_gpio_ops, 5303 .avb_ops = &mv88e6390_avb_ops, 5304 .ptp_ops = &mv88e6352_ptp_ops, 5305 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5306 .serdes_get_strings = mv88e6390_serdes_get_strings, 5307 .serdes_get_stats = mv88e6390_serdes_get_stats, 5308 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5309 .serdes_get_regs = mv88e6390_serdes_get_regs, 5310 .phylink_get_caps = mv88e6341_phylink_get_caps, 5311 }; 5312 5313 static const struct mv88e6xxx_ops mv88e6350_ops = { 5314 /* MV88E6XXX_FAMILY_6351 */ 5315 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5316 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5317 .irl_init_all = mv88e6352_g2_irl_init_all, 5318 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5319 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5320 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5321 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5322 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5323 .port_set_link = mv88e6xxx_port_set_link, 5324 .port_sync_link = mv88e6xxx_port_sync_link, 5325 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5326 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5327 .port_tag_remap = mv88e6095_port_tag_remap, 5328 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5329 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5330 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5331 .port_set_ether_type = mv88e6351_port_set_ether_type, 5332 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5333 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5334 .port_pause_limit = mv88e6097_port_pause_limit, 5335 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5336 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5337 .port_get_cmode = mv88e6352_port_get_cmode, 5338 .port_setup_message_port = mv88e6xxx_setup_message_port, 5339 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5340 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5341 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5342 .stats_get_strings = mv88e6095_stats_get_strings, 5343 .stats_get_stats = mv88e6095_stats_get_stats, 5344 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5345 .set_egress_port = mv88e6095_g1_set_egress_port, 5346 .watchdog_ops = &mv88e6097_watchdog_ops, 5347 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5348 .pot_clear = mv88e6xxx_g2_pot_clear, 5349 .reset = mv88e6352_g1_reset, 5350 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5351 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5352 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5353 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5354 .stu_getnext = mv88e6352_g1_stu_getnext, 5355 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5356 .phylink_get_caps = mv88e6185_phylink_get_caps, 5357 }; 5358 5359 static const struct mv88e6xxx_ops mv88e6351_ops = { 5360 /* MV88E6XXX_FAMILY_6351 */ 5361 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5362 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5363 .irl_init_all = mv88e6352_g2_irl_init_all, 5364 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5365 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5366 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5367 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5368 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5369 .port_set_link = mv88e6xxx_port_set_link, 5370 .port_sync_link = mv88e6xxx_port_sync_link, 5371 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5372 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5373 .port_tag_remap = mv88e6095_port_tag_remap, 5374 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5375 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5376 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5377 .port_set_ether_type = mv88e6351_port_set_ether_type, 5378 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5379 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5380 .port_pause_limit = mv88e6097_port_pause_limit, 5381 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5382 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5383 .port_get_cmode = mv88e6352_port_get_cmode, 5384 .port_setup_message_port = mv88e6xxx_setup_message_port, 5385 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5386 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5387 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5388 .stats_get_strings = mv88e6095_stats_get_strings, 5389 .stats_get_stats = mv88e6095_stats_get_stats, 5390 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5391 .set_egress_port = mv88e6095_g1_set_egress_port, 5392 .watchdog_ops = &mv88e6097_watchdog_ops, 5393 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5394 .pot_clear = mv88e6xxx_g2_pot_clear, 5395 .reset = mv88e6352_g1_reset, 5396 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5397 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5398 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5399 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5400 .stu_getnext = mv88e6352_g1_stu_getnext, 5401 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5402 .avb_ops = &mv88e6352_avb_ops, 5403 .ptp_ops = &mv88e6352_ptp_ops, 5404 .phylink_get_caps = mv88e6185_phylink_get_caps, 5405 }; 5406 5407 static const struct mv88e6xxx_ops mv88e6352_ops = { 5408 /* MV88E6XXX_FAMILY_6352 */ 5409 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5410 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5411 .irl_init_all = mv88e6352_g2_irl_init_all, 5412 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5413 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5414 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5415 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5416 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5417 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5418 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5419 .port_set_link = mv88e6xxx_port_set_link, 5420 .port_sync_link = mv88e6xxx_port_sync_link, 5421 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5422 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 5423 .port_tag_remap = mv88e6095_port_tag_remap, 5424 .port_set_policy = mv88e6352_port_set_policy, 5425 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5426 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5427 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5428 .port_set_ether_type = mv88e6351_port_set_ether_type, 5429 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5430 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5431 .port_pause_limit = mv88e6097_port_pause_limit, 5432 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5433 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5434 .port_get_cmode = mv88e6352_port_get_cmode, 5435 .port_setup_message_port = mv88e6xxx_setup_message_port, 5436 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5437 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5438 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5439 .stats_get_strings = mv88e6095_stats_get_strings, 5440 .stats_get_stats = mv88e6095_stats_get_stats, 5441 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5442 .set_egress_port = mv88e6095_g1_set_egress_port, 5443 .watchdog_ops = &mv88e6097_watchdog_ops, 5444 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5445 .pot_clear = mv88e6xxx_g2_pot_clear, 5446 .reset = mv88e6352_g1_reset, 5447 .rmu_disable = mv88e6352_g1_rmu_disable, 5448 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5449 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5450 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5451 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5452 .stu_getnext = mv88e6352_g1_stu_getnext, 5453 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5454 .serdes_get_lane = mv88e6352_serdes_get_lane, 5455 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 5456 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 5457 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 5458 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 5459 .serdes_power = mv88e6352_serdes_power, 5460 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 5461 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 5462 .serdes_irq_status = mv88e6352_serdes_irq_status, 5463 .gpio_ops = &mv88e6352_gpio_ops, 5464 .avb_ops = &mv88e6352_avb_ops, 5465 .ptp_ops = &mv88e6352_ptp_ops, 5466 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, 5467 .serdes_get_strings = mv88e6352_serdes_get_strings, 5468 .serdes_get_stats = mv88e6352_serdes_get_stats, 5469 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 5470 .serdes_get_regs = mv88e6352_serdes_get_regs, 5471 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 5472 .phylink_get_caps = mv88e6352_phylink_get_caps, 5473 }; 5474 5475 static const struct mv88e6xxx_ops mv88e6390_ops = { 5476 /* MV88E6XXX_FAMILY_6390 */ 5477 .setup_errata = mv88e6390_setup_errata, 5478 .irl_init_all = mv88e6390_g2_irl_init_all, 5479 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5480 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5481 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5482 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5483 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5484 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5485 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5486 .port_set_link = mv88e6xxx_port_set_link, 5487 .port_sync_link = mv88e6xxx_port_sync_link, 5488 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5489 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 5490 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 5491 .port_tag_remap = mv88e6390_port_tag_remap, 5492 .port_set_policy = mv88e6352_port_set_policy, 5493 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5494 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5495 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5496 .port_set_ether_type = mv88e6351_port_set_ether_type, 5497 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5498 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5499 .port_pause_limit = mv88e6390_port_pause_limit, 5500 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5501 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5502 .port_get_cmode = mv88e6352_port_get_cmode, 5503 .port_set_cmode = mv88e6390_port_set_cmode, 5504 .port_setup_message_port = mv88e6xxx_setup_message_port, 5505 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5506 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5507 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5508 .stats_get_strings = mv88e6320_stats_get_strings, 5509 .stats_get_stats = mv88e6390_stats_get_stats, 5510 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5511 .set_egress_port = mv88e6390_g1_set_egress_port, 5512 .watchdog_ops = &mv88e6390_watchdog_ops, 5513 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5514 .pot_clear = mv88e6xxx_g2_pot_clear, 5515 .reset = mv88e6352_g1_reset, 5516 .rmu_disable = mv88e6390_g1_rmu_disable, 5517 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5518 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5519 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5520 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5521 .stu_getnext = mv88e6390_g1_stu_getnext, 5522 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5523 .serdes_power = mv88e6390_serdes_power, 5524 .serdes_get_lane = mv88e6390_serdes_get_lane, 5525 /* Check status register pause & lpa register */ 5526 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 5527 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 5528 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 5529 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 5530 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5531 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 5532 .serdes_irq_status = mv88e6390_serdes_irq_status, 5533 .gpio_ops = &mv88e6352_gpio_ops, 5534 .avb_ops = &mv88e6390_avb_ops, 5535 .ptp_ops = &mv88e6390_ptp_ops, 5536 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5537 .serdes_get_strings = mv88e6390_serdes_get_strings, 5538 .serdes_get_stats = mv88e6390_serdes_get_stats, 5539 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5540 .serdes_get_regs = mv88e6390_serdes_get_regs, 5541 .phylink_get_caps = mv88e6390_phylink_get_caps, 5542 }; 5543 5544 static const struct mv88e6xxx_ops mv88e6390x_ops = { 5545 /* MV88E6XXX_FAMILY_6390 */ 5546 .setup_errata = mv88e6390_setup_errata, 5547 .irl_init_all = mv88e6390_g2_irl_init_all, 5548 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5549 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5550 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5551 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5552 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5553 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5554 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5555 .port_set_link = mv88e6xxx_port_set_link, 5556 .port_sync_link = mv88e6xxx_port_sync_link, 5557 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5558 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 5559 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 5560 .port_tag_remap = mv88e6390_port_tag_remap, 5561 .port_set_policy = mv88e6352_port_set_policy, 5562 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5563 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5564 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5565 .port_set_ether_type = mv88e6351_port_set_ether_type, 5566 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5567 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5568 .port_pause_limit = mv88e6390_port_pause_limit, 5569 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5570 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5571 .port_get_cmode = mv88e6352_port_get_cmode, 5572 .port_set_cmode = mv88e6390x_port_set_cmode, 5573 .port_setup_message_port = mv88e6xxx_setup_message_port, 5574 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5575 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5576 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5577 .stats_get_strings = mv88e6320_stats_get_strings, 5578 .stats_get_stats = mv88e6390_stats_get_stats, 5579 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5580 .set_egress_port = mv88e6390_g1_set_egress_port, 5581 .watchdog_ops = &mv88e6390_watchdog_ops, 5582 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5583 .pot_clear = mv88e6xxx_g2_pot_clear, 5584 .reset = mv88e6352_g1_reset, 5585 .rmu_disable = mv88e6390_g1_rmu_disable, 5586 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5587 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5588 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5589 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5590 .stu_getnext = mv88e6390_g1_stu_getnext, 5591 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5592 .serdes_power = mv88e6390_serdes_power, 5593 .serdes_get_lane = mv88e6390x_serdes_get_lane, 5594 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 5595 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 5596 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 5597 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 5598 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5599 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 5600 .serdes_irq_status = mv88e6390_serdes_irq_status, 5601 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5602 .serdes_get_strings = mv88e6390_serdes_get_strings, 5603 .serdes_get_stats = mv88e6390_serdes_get_stats, 5604 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5605 .serdes_get_regs = mv88e6390_serdes_get_regs, 5606 .gpio_ops = &mv88e6352_gpio_ops, 5607 .avb_ops = &mv88e6390_avb_ops, 5608 .ptp_ops = &mv88e6390_ptp_ops, 5609 .phylink_get_caps = mv88e6390x_phylink_get_caps, 5610 }; 5611 5612 static const struct mv88e6xxx_ops mv88e6393x_ops = { 5613 /* MV88E6XXX_FAMILY_6393 */ 5614 .setup_errata = mv88e6393x_serdes_setup_errata, 5615 .irl_init_all = mv88e6390_g2_irl_init_all, 5616 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5617 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5618 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5619 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5620 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5621 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5622 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5623 .port_set_link = mv88e6xxx_port_set_link, 5624 .port_sync_link = mv88e6xxx_port_sync_link, 5625 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5626 .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex, 5627 .port_max_speed_mode = mv88e6393x_port_max_speed_mode, 5628 .port_tag_remap = mv88e6390_port_tag_remap, 5629 .port_set_policy = mv88e6393x_port_set_policy, 5630 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5631 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5632 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5633 .port_set_ether_type = mv88e6393x_port_set_ether_type, 5634 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5635 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5636 .port_pause_limit = mv88e6390_port_pause_limit, 5637 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5638 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5639 .port_get_cmode = mv88e6352_port_get_cmode, 5640 .port_set_cmode = mv88e6393x_port_set_cmode, 5641 .port_setup_message_port = mv88e6xxx_setup_message_port, 5642 .port_set_upstream_port = mv88e6393x_port_set_upstream_port, 5643 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5644 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5645 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5646 .stats_get_strings = mv88e6320_stats_get_strings, 5647 .stats_get_stats = mv88e6390_stats_get_stats, 5648 /* .set_cpu_port is missing because this family does not support a global 5649 * CPU port, only per port CPU port which is set via 5650 * .port_set_upstream_port method. 5651 */ 5652 .set_egress_port = mv88e6393x_set_egress_port, 5653 .watchdog_ops = &mv88e6393x_watchdog_ops, 5654 .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu, 5655 .pot_clear = mv88e6xxx_g2_pot_clear, 5656 .reset = mv88e6352_g1_reset, 5657 .rmu_disable = mv88e6390_g1_rmu_disable, 5658 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5659 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5660 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5661 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5662 .stu_getnext = mv88e6390_g1_stu_getnext, 5663 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5664 .serdes_power = mv88e6393x_serdes_power, 5665 .serdes_get_lane = mv88e6393x_serdes_get_lane, 5666 .serdes_pcs_get_state = mv88e6393x_serdes_pcs_get_state, 5667 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 5668 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 5669 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 5670 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5671 .serdes_irq_enable = mv88e6393x_serdes_irq_enable, 5672 .serdes_irq_status = mv88e6393x_serdes_irq_status, 5673 /* TODO: serdes stats */ 5674 .gpio_ops = &mv88e6352_gpio_ops, 5675 .avb_ops = &mv88e6390_avb_ops, 5676 .ptp_ops = &mv88e6352_ptp_ops, 5677 .phylink_get_caps = mv88e6393x_phylink_get_caps, 5678 }; 5679 5680 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 5681 [MV88E6020] = { 5682 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6020, 5683 .family = MV88E6XXX_FAMILY_6250, 5684 .name = "Marvell 88E6020", 5685 .num_databases = 64, 5686 .num_ports = 4, 5687 .num_internal_phys = 2, 5688 .max_vid = 4095, 5689 .port_base_addr = 0x8, 5690 .phy_base_addr = 0x0, 5691 .global1_addr = 0xf, 5692 .global2_addr = 0x7, 5693 .age_time_coeff = 15000, 5694 .g1_irqs = 9, 5695 .g2_irqs = 5, 5696 .atu_move_port_mask = 0xf, 5697 .dual_chip = true, 5698 .ops = &mv88e6250_ops, 5699 }, 5700 5701 [MV88E6071] = { 5702 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6071, 5703 .family = MV88E6XXX_FAMILY_6250, 5704 .name = "Marvell 88E6071", 5705 .num_databases = 64, 5706 .num_ports = 7, 5707 .num_internal_phys = 5, 5708 .max_vid = 4095, 5709 .port_base_addr = 0x08, 5710 .phy_base_addr = 0x00, 5711 .global1_addr = 0x0f, 5712 .global2_addr = 0x07, 5713 .age_time_coeff = 15000, 5714 .g1_irqs = 9, 5715 .g2_irqs = 5, 5716 .atu_move_port_mask = 0xf, 5717 .dual_chip = true, 5718 .ops = &mv88e6250_ops, 5719 }, 5720 5721 [MV88E6085] = { 5722 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 5723 .family = MV88E6XXX_FAMILY_6097, 5724 .name = "Marvell 88E6085", 5725 .num_databases = 4096, 5726 .num_macs = 8192, 5727 .num_ports = 10, 5728 .num_internal_phys = 5, 5729 .max_vid = 4095, 5730 .max_sid = 63, 5731 .port_base_addr = 0x10, 5732 .phy_base_addr = 0x0, 5733 .global1_addr = 0x1b, 5734 .global2_addr = 0x1c, 5735 .age_time_coeff = 15000, 5736 .g1_irqs = 8, 5737 .g2_irqs = 10, 5738 .atu_move_port_mask = 0xf, 5739 .pvt = true, 5740 .multi_chip = true, 5741 .ops = &mv88e6085_ops, 5742 }, 5743 5744 [MV88E6095] = { 5745 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 5746 .family = MV88E6XXX_FAMILY_6095, 5747 .name = "Marvell 88E6095/88E6095F", 5748 .num_databases = 256, 5749 .num_macs = 8192, 5750 .num_ports = 11, 5751 .num_internal_phys = 0, 5752 .max_vid = 4095, 5753 .port_base_addr = 0x10, 5754 .phy_base_addr = 0x0, 5755 .global1_addr = 0x1b, 5756 .global2_addr = 0x1c, 5757 .age_time_coeff = 15000, 5758 .g1_irqs = 8, 5759 .atu_move_port_mask = 0xf, 5760 .multi_chip = true, 5761 .ops = &mv88e6095_ops, 5762 }, 5763 5764 [MV88E6097] = { 5765 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 5766 .family = MV88E6XXX_FAMILY_6097, 5767 .name = "Marvell 88E6097/88E6097F", 5768 .num_databases = 4096, 5769 .num_macs = 8192, 5770 .num_ports = 11, 5771 .num_internal_phys = 8, 5772 .max_vid = 4095, 5773 .max_sid = 63, 5774 .port_base_addr = 0x10, 5775 .phy_base_addr = 0x0, 5776 .global1_addr = 0x1b, 5777 .global2_addr = 0x1c, 5778 .age_time_coeff = 15000, 5779 .g1_irqs = 8, 5780 .g2_irqs = 10, 5781 .atu_move_port_mask = 0xf, 5782 .pvt = true, 5783 .multi_chip = true, 5784 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5785 .ops = &mv88e6097_ops, 5786 }, 5787 5788 [MV88E6123] = { 5789 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 5790 .family = MV88E6XXX_FAMILY_6165, 5791 .name = "Marvell 88E6123", 5792 .num_databases = 4096, 5793 .num_macs = 1024, 5794 .num_ports = 3, 5795 .num_internal_phys = 5, 5796 .max_vid = 4095, 5797 .max_sid = 63, 5798 .port_base_addr = 0x10, 5799 .phy_base_addr = 0x0, 5800 .global1_addr = 0x1b, 5801 .global2_addr = 0x1c, 5802 .age_time_coeff = 15000, 5803 .g1_irqs = 9, 5804 .g2_irqs = 10, 5805 .atu_move_port_mask = 0xf, 5806 .pvt = true, 5807 .multi_chip = true, 5808 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5809 .ops = &mv88e6123_ops, 5810 }, 5811 5812 [MV88E6131] = { 5813 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 5814 .family = MV88E6XXX_FAMILY_6185, 5815 .name = "Marvell 88E6131", 5816 .num_databases = 256, 5817 .num_macs = 8192, 5818 .num_ports = 8, 5819 .num_internal_phys = 0, 5820 .max_vid = 4095, 5821 .port_base_addr = 0x10, 5822 .phy_base_addr = 0x0, 5823 .global1_addr = 0x1b, 5824 .global2_addr = 0x1c, 5825 .age_time_coeff = 15000, 5826 .g1_irqs = 9, 5827 .atu_move_port_mask = 0xf, 5828 .multi_chip = true, 5829 .ops = &mv88e6131_ops, 5830 }, 5831 5832 [MV88E6141] = { 5833 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 5834 .family = MV88E6XXX_FAMILY_6341, 5835 .name = "Marvell 88E6141", 5836 .num_databases = 4096, 5837 .num_macs = 2048, 5838 .num_ports = 6, 5839 .num_internal_phys = 5, 5840 .num_gpio = 11, 5841 .max_vid = 4095, 5842 .max_sid = 63, 5843 .port_base_addr = 0x10, 5844 .phy_base_addr = 0x10, 5845 .global1_addr = 0x1b, 5846 .global2_addr = 0x1c, 5847 .age_time_coeff = 3750, 5848 .atu_move_port_mask = 0x1f, 5849 .g1_irqs = 9, 5850 .g2_irqs = 10, 5851 .pvt = true, 5852 .multi_chip = true, 5853 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5854 .ops = &mv88e6141_ops, 5855 }, 5856 5857 [MV88E6161] = { 5858 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 5859 .family = MV88E6XXX_FAMILY_6165, 5860 .name = "Marvell 88E6161", 5861 .num_databases = 4096, 5862 .num_macs = 1024, 5863 .num_ports = 6, 5864 .num_internal_phys = 5, 5865 .max_vid = 4095, 5866 .max_sid = 63, 5867 .port_base_addr = 0x10, 5868 .phy_base_addr = 0x0, 5869 .global1_addr = 0x1b, 5870 .global2_addr = 0x1c, 5871 .age_time_coeff = 15000, 5872 .g1_irqs = 9, 5873 .g2_irqs = 10, 5874 .atu_move_port_mask = 0xf, 5875 .pvt = true, 5876 .multi_chip = true, 5877 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5878 .ptp_support = true, 5879 .ops = &mv88e6161_ops, 5880 }, 5881 5882 [MV88E6165] = { 5883 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 5884 .family = MV88E6XXX_FAMILY_6165, 5885 .name = "Marvell 88E6165", 5886 .num_databases = 4096, 5887 .num_macs = 8192, 5888 .num_ports = 6, 5889 .num_internal_phys = 0, 5890 .max_vid = 4095, 5891 .max_sid = 63, 5892 .port_base_addr = 0x10, 5893 .phy_base_addr = 0x0, 5894 .global1_addr = 0x1b, 5895 .global2_addr = 0x1c, 5896 .age_time_coeff = 15000, 5897 .g1_irqs = 9, 5898 .g2_irqs = 10, 5899 .atu_move_port_mask = 0xf, 5900 .pvt = true, 5901 .multi_chip = true, 5902 .ptp_support = true, 5903 .ops = &mv88e6165_ops, 5904 }, 5905 5906 [MV88E6171] = { 5907 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 5908 .family = MV88E6XXX_FAMILY_6351, 5909 .name = "Marvell 88E6171", 5910 .num_databases = 4096, 5911 .num_macs = 8192, 5912 .num_ports = 7, 5913 .num_internal_phys = 5, 5914 .max_vid = 4095, 5915 .max_sid = 63, 5916 .port_base_addr = 0x10, 5917 .phy_base_addr = 0x0, 5918 .global1_addr = 0x1b, 5919 .global2_addr = 0x1c, 5920 .age_time_coeff = 15000, 5921 .g1_irqs = 9, 5922 .g2_irqs = 10, 5923 .atu_move_port_mask = 0xf, 5924 .pvt = true, 5925 .multi_chip = true, 5926 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5927 .ops = &mv88e6171_ops, 5928 }, 5929 5930 [MV88E6172] = { 5931 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 5932 .family = MV88E6XXX_FAMILY_6352, 5933 .name = "Marvell 88E6172", 5934 .num_databases = 4096, 5935 .num_macs = 8192, 5936 .num_ports = 7, 5937 .num_internal_phys = 5, 5938 .num_gpio = 15, 5939 .max_vid = 4095, 5940 .max_sid = 63, 5941 .port_base_addr = 0x10, 5942 .phy_base_addr = 0x0, 5943 .global1_addr = 0x1b, 5944 .global2_addr = 0x1c, 5945 .age_time_coeff = 15000, 5946 .g1_irqs = 9, 5947 .g2_irqs = 10, 5948 .atu_move_port_mask = 0xf, 5949 .pvt = true, 5950 .multi_chip = true, 5951 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5952 .ops = &mv88e6172_ops, 5953 }, 5954 5955 [MV88E6175] = { 5956 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 5957 .family = MV88E6XXX_FAMILY_6351, 5958 .name = "Marvell 88E6175", 5959 .num_databases = 4096, 5960 .num_macs = 8192, 5961 .num_ports = 7, 5962 .num_internal_phys = 5, 5963 .max_vid = 4095, 5964 .max_sid = 63, 5965 .port_base_addr = 0x10, 5966 .phy_base_addr = 0x0, 5967 .global1_addr = 0x1b, 5968 .global2_addr = 0x1c, 5969 .age_time_coeff = 15000, 5970 .g1_irqs = 9, 5971 .g2_irqs = 10, 5972 .atu_move_port_mask = 0xf, 5973 .pvt = true, 5974 .multi_chip = true, 5975 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5976 .ops = &mv88e6175_ops, 5977 }, 5978 5979 [MV88E6176] = { 5980 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 5981 .family = MV88E6XXX_FAMILY_6352, 5982 .name = "Marvell 88E6176", 5983 .num_databases = 4096, 5984 .num_macs = 8192, 5985 .num_ports = 7, 5986 .num_internal_phys = 5, 5987 .num_gpio = 15, 5988 .max_vid = 4095, 5989 .max_sid = 63, 5990 .port_base_addr = 0x10, 5991 .phy_base_addr = 0x0, 5992 .global1_addr = 0x1b, 5993 .global2_addr = 0x1c, 5994 .age_time_coeff = 15000, 5995 .g1_irqs = 9, 5996 .g2_irqs = 10, 5997 .atu_move_port_mask = 0xf, 5998 .pvt = true, 5999 .multi_chip = true, 6000 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6001 .ops = &mv88e6176_ops, 6002 }, 6003 6004 [MV88E6185] = { 6005 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 6006 .family = MV88E6XXX_FAMILY_6185, 6007 .name = "Marvell 88E6185", 6008 .num_databases = 256, 6009 .num_macs = 8192, 6010 .num_ports = 10, 6011 .num_internal_phys = 0, 6012 .max_vid = 4095, 6013 .port_base_addr = 0x10, 6014 .phy_base_addr = 0x0, 6015 .global1_addr = 0x1b, 6016 .global2_addr = 0x1c, 6017 .age_time_coeff = 15000, 6018 .g1_irqs = 8, 6019 .atu_move_port_mask = 0xf, 6020 .multi_chip = true, 6021 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6022 .ops = &mv88e6185_ops, 6023 }, 6024 6025 [MV88E6190] = { 6026 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 6027 .family = MV88E6XXX_FAMILY_6390, 6028 .name = "Marvell 88E6190", 6029 .num_databases = 4096, 6030 .num_macs = 16384, 6031 .num_ports = 11, /* 10 + Z80 */ 6032 .num_internal_phys = 9, 6033 .num_gpio = 16, 6034 .max_vid = 8191, 6035 .max_sid = 63, 6036 .port_base_addr = 0x0, 6037 .phy_base_addr = 0x0, 6038 .global1_addr = 0x1b, 6039 .global2_addr = 0x1c, 6040 .age_time_coeff = 3750, 6041 .g1_irqs = 9, 6042 .g2_irqs = 14, 6043 .pvt = true, 6044 .multi_chip = true, 6045 .atu_move_port_mask = 0x1f, 6046 .ops = &mv88e6190_ops, 6047 }, 6048 6049 [MV88E6190X] = { 6050 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 6051 .family = MV88E6XXX_FAMILY_6390, 6052 .name = "Marvell 88E6190X", 6053 .num_databases = 4096, 6054 .num_macs = 16384, 6055 .num_ports = 11, /* 10 + Z80 */ 6056 .num_internal_phys = 9, 6057 .num_gpio = 16, 6058 .max_vid = 8191, 6059 .max_sid = 63, 6060 .port_base_addr = 0x0, 6061 .phy_base_addr = 0x0, 6062 .global1_addr = 0x1b, 6063 .global2_addr = 0x1c, 6064 .age_time_coeff = 3750, 6065 .g1_irqs = 9, 6066 .g2_irqs = 14, 6067 .atu_move_port_mask = 0x1f, 6068 .pvt = true, 6069 .multi_chip = true, 6070 .ops = &mv88e6190x_ops, 6071 }, 6072 6073 [MV88E6191] = { 6074 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 6075 .family = MV88E6XXX_FAMILY_6390, 6076 .name = "Marvell 88E6191", 6077 .num_databases = 4096, 6078 .num_macs = 16384, 6079 .num_ports = 11, /* 10 + Z80 */ 6080 .num_internal_phys = 9, 6081 .max_vid = 8191, 6082 .max_sid = 63, 6083 .port_base_addr = 0x0, 6084 .phy_base_addr = 0x0, 6085 .global1_addr = 0x1b, 6086 .global2_addr = 0x1c, 6087 .age_time_coeff = 3750, 6088 .g1_irqs = 9, 6089 .g2_irqs = 14, 6090 .atu_move_port_mask = 0x1f, 6091 .pvt = true, 6092 .multi_chip = true, 6093 .ptp_support = true, 6094 .ops = &mv88e6191_ops, 6095 }, 6096 6097 [MV88E6191X] = { 6098 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X, 6099 .family = MV88E6XXX_FAMILY_6393, 6100 .name = "Marvell 88E6191X", 6101 .num_databases = 4096, 6102 .num_ports = 11, /* 10 + Z80 */ 6103 .num_internal_phys = 8, 6104 .internal_phys_offset = 1, 6105 .max_vid = 8191, 6106 .max_sid = 63, 6107 .port_base_addr = 0x0, 6108 .phy_base_addr = 0x0, 6109 .global1_addr = 0x1b, 6110 .global2_addr = 0x1c, 6111 .age_time_coeff = 3750, 6112 .g1_irqs = 10, 6113 .g2_irqs = 14, 6114 .atu_move_port_mask = 0x1f, 6115 .pvt = true, 6116 .multi_chip = true, 6117 .ptp_support = true, 6118 .ops = &mv88e6393x_ops, 6119 }, 6120 6121 [MV88E6193X] = { 6122 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X, 6123 .family = MV88E6XXX_FAMILY_6393, 6124 .name = "Marvell 88E6193X", 6125 .num_databases = 4096, 6126 .num_ports = 11, /* 10 + Z80 */ 6127 .num_internal_phys = 8, 6128 .internal_phys_offset = 1, 6129 .max_vid = 8191, 6130 .max_sid = 63, 6131 .port_base_addr = 0x0, 6132 .phy_base_addr = 0x0, 6133 .global1_addr = 0x1b, 6134 .global2_addr = 0x1c, 6135 .age_time_coeff = 3750, 6136 .g1_irqs = 10, 6137 .g2_irqs = 14, 6138 .atu_move_port_mask = 0x1f, 6139 .pvt = true, 6140 .multi_chip = true, 6141 .ptp_support = true, 6142 .ops = &mv88e6393x_ops, 6143 }, 6144 6145 [MV88E6220] = { 6146 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220, 6147 .family = MV88E6XXX_FAMILY_6250, 6148 .name = "Marvell 88E6220", 6149 .num_databases = 64, 6150 6151 /* Ports 2-4 are not routed to pins 6152 * => usable ports 0, 1, 5, 6 6153 */ 6154 .num_ports = 7, 6155 .num_internal_phys = 2, 6156 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 6157 .max_vid = 4095, 6158 .port_base_addr = 0x08, 6159 .phy_base_addr = 0x00, 6160 .global1_addr = 0x0f, 6161 .global2_addr = 0x07, 6162 .age_time_coeff = 15000, 6163 .g1_irqs = 9, 6164 .g2_irqs = 10, 6165 .atu_move_port_mask = 0xf, 6166 .dual_chip = true, 6167 .ptp_support = true, 6168 .ops = &mv88e6250_ops, 6169 }, 6170 6171 [MV88E6240] = { 6172 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 6173 .family = MV88E6XXX_FAMILY_6352, 6174 .name = "Marvell 88E6240", 6175 .num_databases = 4096, 6176 .num_macs = 8192, 6177 .num_ports = 7, 6178 .num_internal_phys = 5, 6179 .num_gpio = 15, 6180 .max_vid = 4095, 6181 .max_sid = 63, 6182 .port_base_addr = 0x10, 6183 .phy_base_addr = 0x0, 6184 .global1_addr = 0x1b, 6185 .global2_addr = 0x1c, 6186 .age_time_coeff = 15000, 6187 .g1_irqs = 9, 6188 .g2_irqs = 10, 6189 .atu_move_port_mask = 0xf, 6190 .pvt = true, 6191 .multi_chip = true, 6192 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6193 .ptp_support = true, 6194 .ops = &mv88e6240_ops, 6195 }, 6196 6197 [MV88E6250] = { 6198 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250, 6199 .family = MV88E6XXX_FAMILY_6250, 6200 .name = "Marvell 88E6250", 6201 .num_databases = 64, 6202 .num_ports = 7, 6203 .num_internal_phys = 5, 6204 .max_vid = 4095, 6205 .port_base_addr = 0x08, 6206 .phy_base_addr = 0x00, 6207 .global1_addr = 0x0f, 6208 .global2_addr = 0x07, 6209 .age_time_coeff = 15000, 6210 .g1_irqs = 9, 6211 .g2_irqs = 10, 6212 .atu_move_port_mask = 0xf, 6213 .dual_chip = true, 6214 .ptp_support = true, 6215 .ops = &mv88e6250_ops, 6216 }, 6217 6218 [MV88E6290] = { 6219 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 6220 .family = MV88E6XXX_FAMILY_6390, 6221 .name = "Marvell 88E6290", 6222 .num_databases = 4096, 6223 .num_ports = 11, /* 10 + Z80 */ 6224 .num_internal_phys = 9, 6225 .num_gpio = 16, 6226 .max_vid = 8191, 6227 .max_sid = 63, 6228 .port_base_addr = 0x0, 6229 .phy_base_addr = 0x0, 6230 .global1_addr = 0x1b, 6231 .global2_addr = 0x1c, 6232 .age_time_coeff = 3750, 6233 .g1_irqs = 9, 6234 .g2_irqs = 14, 6235 .atu_move_port_mask = 0x1f, 6236 .pvt = true, 6237 .multi_chip = true, 6238 .ptp_support = true, 6239 .ops = &mv88e6290_ops, 6240 }, 6241 6242 [MV88E6320] = { 6243 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 6244 .family = MV88E6XXX_FAMILY_6320, 6245 .name = "Marvell 88E6320", 6246 .num_databases = 4096, 6247 .num_macs = 8192, 6248 .num_ports = 7, 6249 .num_internal_phys = 5, 6250 .num_gpio = 15, 6251 .max_vid = 4095, 6252 .port_base_addr = 0x10, 6253 .phy_base_addr = 0x0, 6254 .global1_addr = 0x1b, 6255 .global2_addr = 0x1c, 6256 .age_time_coeff = 15000, 6257 .g1_irqs = 8, 6258 .g2_irqs = 10, 6259 .atu_move_port_mask = 0xf, 6260 .pvt = true, 6261 .multi_chip = true, 6262 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6263 .ptp_support = true, 6264 .ops = &mv88e6320_ops, 6265 }, 6266 6267 [MV88E6321] = { 6268 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 6269 .family = MV88E6XXX_FAMILY_6320, 6270 .name = "Marvell 88E6321", 6271 .num_databases = 4096, 6272 .num_macs = 8192, 6273 .num_ports = 7, 6274 .num_internal_phys = 5, 6275 .num_gpio = 15, 6276 .max_vid = 4095, 6277 .port_base_addr = 0x10, 6278 .phy_base_addr = 0x0, 6279 .global1_addr = 0x1b, 6280 .global2_addr = 0x1c, 6281 .age_time_coeff = 15000, 6282 .g1_irqs = 8, 6283 .g2_irqs = 10, 6284 .atu_move_port_mask = 0xf, 6285 .multi_chip = true, 6286 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6287 .ptp_support = true, 6288 .ops = &mv88e6321_ops, 6289 }, 6290 6291 [MV88E6341] = { 6292 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 6293 .family = MV88E6XXX_FAMILY_6341, 6294 .name = "Marvell 88E6341", 6295 .num_databases = 4096, 6296 .num_macs = 2048, 6297 .num_internal_phys = 5, 6298 .num_ports = 6, 6299 .num_gpio = 11, 6300 .max_vid = 4095, 6301 .max_sid = 63, 6302 .port_base_addr = 0x10, 6303 .phy_base_addr = 0x10, 6304 .global1_addr = 0x1b, 6305 .global2_addr = 0x1c, 6306 .age_time_coeff = 3750, 6307 .atu_move_port_mask = 0x1f, 6308 .g1_irqs = 9, 6309 .g2_irqs = 10, 6310 .pvt = true, 6311 .multi_chip = true, 6312 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6313 .ptp_support = true, 6314 .ops = &mv88e6341_ops, 6315 }, 6316 6317 [MV88E6350] = { 6318 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 6319 .family = MV88E6XXX_FAMILY_6351, 6320 .name = "Marvell 88E6350", 6321 .num_databases = 4096, 6322 .num_macs = 8192, 6323 .num_ports = 7, 6324 .num_internal_phys = 5, 6325 .max_vid = 4095, 6326 .max_sid = 63, 6327 .port_base_addr = 0x10, 6328 .phy_base_addr = 0x0, 6329 .global1_addr = 0x1b, 6330 .global2_addr = 0x1c, 6331 .age_time_coeff = 15000, 6332 .g1_irqs = 9, 6333 .g2_irqs = 10, 6334 .atu_move_port_mask = 0xf, 6335 .pvt = true, 6336 .multi_chip = true, 6337 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6338 .ops = &mv88e6350_ops, 6339 }, 6340 6341 [MV88E6351] = { 6342 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 6343 .family = MV88E6XXX_FAMILY_6351, 6344 .name = "Marvell 88E6351", 6345 .num_databases = 4096, 6346 .num_macs = 8192, 6347 .num_ports = 7, 6348 .num_internal_phys = 5, 6349 .max_vid = 4095, 6350 .max_sid = 63, 6351 .port_base_addr = 0x10, 6352 .phy_base_addr = 0x0, 6353 .global1_addr = 0x1b, 6354 .global2_addr = 0x1c, 6355 .age_time_coeff = 15000, 6356 .g1_irqs = 9, 6357 .g2_irqs = 10, 6358 .atu_move_port_mask = 0xf, 6359 .pvt = true, 6360 .multi_chip = true, 6361 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6362 .ops = &mv88e6351_ops, 6363 }, 6364 6365 [MV88E6352] = { 6366 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 6367 .family = MV88E6XXX_FAMILY_6352, 6368 .name = "Marvell 88E6352", 6369 .num_databases = 4096, 6370 .num_macs = 8192, 6371 .num_ports = 7, 6372 .num_internal_phys = 5, 6373 .num_gpio = 15, 6374 .max_vid = 4095, 6375 .max_sid = 63, 6376 .port_base_addr = 0x10, 6377 .phy_base_addr = 0x0, 6378 .global1_addr = 0x1b, 6379 .global2_addr = 0x1c, 6380 .age_time_coeff = 15000, 6381 .g1_irqs = 9, 6382 .g2_irqs = 10, 6383 .atu_move_port_mask = 0xf, 6384 .pvt = true, 6385 .multi_chip = true, 6386 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6387 .ptp_support = true, 6388 .ops = &mv88e6352_ops, 6389 }, 6390 [MV88E6361] = { 6391 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6361, 6392 .family = MV88E6XXX_FAMILY_6393, 6393 .name = "Marvell 88E6361", 6394 .num_databases = 4096, 6395 .num_macs = 16384, 6396 .num_ports = 11, 6397 /* Ports 1, 2 and 8 are not routed */ 6398 .invalid_port_mask = BIT(1) | BIT(2) | BIT(8), 6399 .num_internal_phys = 5, 6400 .internal_phys_offset = 3, 6401 .max_vid = 4095, 6402 .max_sid = 63, 6403 .port_base_addr = 0x0, 6404 .phy_base_addr = 0x0, 6405 .global1_addr = 0x1b, 6406 .global2_addr = 0x1c, 6407 .age_time_coeff = 3750, 6408 .g1_irqs = 10, 6409 .g2_irqs = 14, 6410 .atu_move_port_mask = 0x1f, 6411 .pvt = true, 6412 .multi_chip = true, 6413 .ptp_support = true, 6414 .ops = &mv88e6393x_ops, 6415 }, 6416 [MV88E6390] = { 6417 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 6418 .family = MV88E6XXX_FAMILY_6390, 6419 .name = "Marvell 88E6390", 6420 .num_databases = 4096, 6421 .num_macs = 16384, 6422 .num_ports = 11, /* 10 + Z80 */ 6423 .num_internal_phys = 9, 6424 .num_gpio = 16, 6425 .max_vid = 8191, 6426 .max_sid = 63, 6427 .port_base_addr = 0x0, 6428 .phy_base_addr = 0x0, 6429 .global1_addr = 0x1b, 6430 .global2_addr = 0x1c, 6431 .age_time_coeff = 3750, 6432 .g1_irqs = 9, 6433 .g2_irqs = 14, 6434 .atu_move_port_mask = 0x1f, 6435 .pvt = true, 6436 .multi_chip = true, 6437 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 6438 .ptp_support = true, 6439 .ops = &mv88e6390_ops, 6440 }, 6441 [MV88E6390X] = { 6442 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 6443 .family = MV88E6XXX_FAMILY_6390, 6444 .name = "Marvell 88E6390X", 6445 .num_databases = 4096, 6446 .num_macs = 16384, 6447 .num_ports = 11, /* 10 + Z80 */ 6448 .num_internal_phys = 9, 6449 .num_gpio = 16, 6450 .max_vid = 8191, 6451 .max_sid = 63, 6452 .port_base_addr = 0x0, 6453 .phy_base_addr = 0x0, 6454 .global1_addr = 0x1b, 6455 .global2_addr = 0x1c, 6456 .age_time_coeff = 3750, 6457 .g1_irqs = 9, 6458 .g2_irqs = 14, 6459 .atu_move_port_mask = 0x1f, 6460 .pvt = true, 6461 .multi_chip = true, 6462 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 6463 .ptp_support = true, 6464 .ops = &mv88e6390x_ops, 6465 }, 6466 6467 [MV88E6393X] = { 6468 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 6469 .family = MV88E6XXX_FAMILY_6393, 6470 .name = "Marvell 88E6393X", 6471 .num_databases = 4096, 6472 .num_ports = 11, /* 10 + Z80 */ 6473 .num_internal_phys = 8, 6474 .internal_phys_offset = 1, 6475 .max_vid = 8191, 6476 .max_sid = 63, 6477 .port_base_addr = 0x0, 6478 .phy_base_addr = 0x0, 6479 .global1_addr = 0x1b, 6480 .global2_addr = 0x1c, 6481 .age_time_coeff = 3750, 6482 .g1_irqs = 10, 6483 .g2_irqs = 14, 6484 .atu_move_port_mask = 0x1f, 6485 .pvt = true, 6486 .multi_chip = true, 6487 .ptp_support = true, 6488 .ops = &mv88e6393x_ops, 6489 }, 6490 }; 6491 6492 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 6493 { 6494 int i; 6495 6496 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 6497 if (mv88e6xxx_table[i].prod_num == prod_num) 6498 return &mv88e6xxx_table[i]; 6499 6500 return NULL; 6501 } 6502 6503 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 6504 { 6505 const struct mv88e6xxx_info *info; 6506 unsigned int prod_num, rev; 6507 u16 id; 6508 int err; 6509 6510 mv88e6xxx_reg_lock(chip); 6511 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 6512 mv88e6xxx_reg_unlock(chip); 6513 if (err) 6514 return err; 6515 6516 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 6517 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 6518 6519 info = mv88e6xxx_lookup_info(prod_num); 6520 if (!info) 6521 return -ENODEV; 6522 6523 /* Update the compatible info with the probed one */ 6524 chip->info = info; 6525 6526 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 6527 chip->info->prod_num, chip->info->name, rev); 6528 6529 return 0; 6530 } 6531 6532 static int mv88e6xxx_single_chip_detect(struct mv88e6xxx_chip *chip, 6533 struct mdio_device *mdiodev) 6534 { 6535 int err; 6536 6537 /* dual_chip takes precedence over single/multi-chip modes */ 6538 if (chip->info->dual_chip) 6539 return -EINVAL; 6540 6541 /* If the mdio addr is 16 indicating the first port address of a switch 6542 * (e.g. mv88e6*41) in single chip addressing mode the device may be 6543 * configured in single chip addressing mode. Setup the smi access as 6544 * single chip addressing mode and attempt to detect the model of the 6545 * switch, if this fails the device is not configured in single chip 6546 * addressing mode. 6547 */ 6548 if (mdiodev->addr != 16) 6549 return -EINVAL; 6550 6551 err = mv88e6xxx_smi_init(chip, mdiodev->bus, 0); 6552 if (err) 6553 return err; 6554 6555 return mv88e6xxx_detect(chip); 6556 } 6557 6558 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 6559 { 6560 struct mv88e6xxx_chip *chip; 6561 6562 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 6563 if (!chip) 6564 return NULL; 6565 6566 chip->dev = dev; 6567 6568 mutex_init(&chip->reg_lock); 6569 INIT_LIST_HEAD(&chip->mdios); 6570 idr_init(&chip->policies); 6571 INIT_LIST_HEAD(&chip->msts); 6572 6573 return chip; 6574 } 6575 6576 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 6577 int port, 6578 enum dsa_tag_protocol m) 6579 { 6580 struct mv88e6xxx_chip *chip = ds->priv; 6581 6582 return chip->tag_protocol; 6583 } 6584 6585 static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds, 6586 enum dsa_tag_protocol proto) 6587 { 6588 struct mv88e6xxx_chip *chip = ds->priv; 6589 enum dsa_tag_protocol old_protocol; 6590 struct dsa_port *cpu_dp; 6591 int err; 6592 6593 switch (proto) { 6594 case DSA_TAG_PROTO_EDSA: 6595 switch (chip->info->edsa_support) { 6596 case MV88E6XXX_EDSA_UNSUPPORTED: 6597 return -EPROTONOSUPPORT; 6598 case MV88E6XXX_EDSA_UNDOCUMENTED: 6599 dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n"); 6600 fallthrough; 6601 case MV88E6XXX_EDSA_SUPPORTED: 6602 break; 6603 } 6604 break; 6605 case DSA_TAG_PROTO_DSA: 6606 break; 6607 default: 6608 return -EPROTONOSUPPORT; 6609 } 6610 6611 old_protocol = chip->tag_protocol; 6612 chip->tag_protocol = proto; 6613 6614 mv88e6xxx_reg_lock(chip); 6615 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 6616 err = mv88e6xxx_setup_port_mode(chip, cpu_dp->index); 6617 if (err) { 6618 mv88e6xxx_reg_unlock(chip); 6619 goto unwind; 6620 } 6621 } 6622 mv88e6xxx_reg_unlock(chip); 6623 6624 return 0; 6625 6626 unwind: 6627 chip->tag_protocol = old_protocol; 6628 6629 mv88e6xxx_reg_lock(chip); 6630 dsa_switch_for_each_cpu_port_continue_reverse(cpu_dp, ds) 6631 mv88e6xxx_setup_port_mode(chip, cpu_dp->index); 6632 mv88e6xxx_reg_unlock(chip); 6633 6634 return err; 6635 } 6636 6637 static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 6638 const struct switchdev_obj_port_mdb *mdb, 6639 struct dsa_db db) 6640 { 6641 struct mv88e6xxx_chip *chip = ds->priv; 6642 int err; 6643 6644 mv88e6xxx_reg_lock(chip); 6645 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 6646 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC); 6647 mv88e6xxx_reg_unlock(chip); 6648 6649 return err; 6650 } 6651 6652 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 6653 const struct switchdev_obj_port_mdb *mdb, 6654 struct dsa_db db) 6655 { 6656 struct mv88e6xxx_chip *chip = ds->priv; 6657 int err; 6658 6659 mv88e6xxx_reg_lock(chip); 6660 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0); 6661 mv88e6xxx_reg_unlock(chip); 6662 6663 return err; 6664 } 6665 6666 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port, 6667 struct dsa_mall_mirror_tc_entry *mirror, 6668 bool ingress, 6669 struct netlink_ext_ack *extack) 6670 { 6671 enum mv88e6xxx_egress_direction direction = ingress ? 6672 MV88E6XXX_EGRESS_DIR_INGRESS : 6673 MV88E6XXX_EGRESS_DIR_EGRESS; 6674 struct mv88e6xxx_chip *chip = ds->priv; 6675 bool other_mirrors = false; 6676 int i; 6677 int err; 6678 6679 mutex_lock(&chip->reg_lock); 6680 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) != 6681 mirror->to_local_port) { 6682 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 6683 other_mirrors |= ingress ? 6684 chip->ports[i].mirror_ingress : 6685 chip->ports[i].mirror_egress; 6686 6687 /* Can't change egress port when other mirror is active */ 6688 if (other_mirrors) { 6689 err = -EBUSY; 6690 goto out; 6691 } 6692 6693 err = mv88e6xxx_set_egress_port(chip, direction, 6694 mirror->to_local_port); 6695 if (err) 6696 goto out; 6697 } 6698 6699 err = mv88e6xxx_port_set_mirror(chip, port, direction, true); 6700 out: 6701 mutex_unlock(&chip->reg_lock); 6702 6703 return err; 6704 } 6705 6706 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port, 6707 struct dsa_mall_mirror_tc_entry *mirror) 6708 { 6709 enum mv88e6xxx_egress_direction direction = mirror->ingress ? 6710 MV88E6XXX_EGRESS_DIR_INGRESS : 6711 MV88E6XXX_EGRESS_DIR_EGRESS; 6712 struct mv88e6xxx_chip *chip = ds->priv; 6713 bool other_mirrors = false; 6714 int i; 6715 6716 mutex_lock(&chip->reg_lock); 6717 if (mv88e6xxx_port_set_mirror(chip, port, direction, false)) 6718 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port); 6719 6720 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 6721 other_mirrors |= mirror->ingress ? 6722 chip->ports[i].mirror_ingress : 6723 chip->ports[i].mirror_egress; 6724 6725 /* Reset egress port when no other mirror is active */ 6726 if (!other_mirrors) { 6727 if (mv88e6xxx_set_egress_port(chip, direction, 6728 dsa_upstream_port(ds, port))) 6729 dev_err(ds->dev, "failed to set egress port\n"); 6730 } 6731 6732 mutex_unlock(&chip->reg_lock); 6733 } 6734 6735 static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port, 6736 struct switchdev_brport_flags flags, 6737 struct netlink_ext_ack *extack) 6738 { 6739 struct mv88e6xxx_chip *chip = ds->priv; 6740 const struct mv88e6xxx_ops *ops; 6741 6742 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 6743 BR_BCAST_FLOOD | BR_PORT_LOCKED | BR_PORT_MAB)) 6744 return -EINVAL; 6745 6746 ops = chip->info->ops; 6747 6748 if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood) 6749 return -EINVAL; 6750 6751 if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood) 6752 return -EINVAL; 6753 6754 return 0; 6755 } 6756 6757 static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port, 6758 struct switchdev_brport_flags flags, 6759 struct netlink_ext_ack *extack) 6760 { 6761 struct mv88e6xxx_chip *chip = ds->priv; 6762 int err = 0; 6763 6764 mv88e6xxx_reg_lock(chip); 6765 6766 if (flags.mask & BR_LEARNING) { 6767 bool learning = !!(flags.val & BR_LEARNING); 6768 u16 pav = learning ? (1 << port) : 0; 6769 6770 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav); 6771 if (err) 6772 goto out; 6773 } 6774 6775 if (flags.mask & BR_FLOOD) { 6776 bool unicast = !!(flags.val & BR_FLOOD); 6777 6778 err = chip->info->ops->port_set_ucast_flood(chip, port, 6779 unicast); 6780 if (err) 6781 goto out; 6782 } 6783 6784 if (flags.mask & BR_MCAST_FLOOD) { 6785 bool multicast = !!(flags.val & BR_MCAST_FLOOD); 6786 6787 err = chip->info->ops->port_set_mcast_flood(chip, port, 6788 multicast); 6789 if (err) 6790 goto out; 6791 } 6792 6793 if (flags.mask & BR_BCAST_FLOOD) { 6794 bool broadcast = !!(flags.val & BR_BCAST_FLOOD); 6795 6796 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast); 6797 if (err) 6798 goto out; 6799 } 6800 6801 if (flags.mask & BR_PORT_MAB) { 6802 bool mab = !!(flags.val & BR_PORT_MAB); 6803 6804 mv88e6xxx_port_set_mab(chip, port, mab); 6805 } 6806 6807 if (flags.mask & BR_PORT_LOCKED) { 6808 bool locked = !!(flags.val & BR_PORT_LOCKED); 6809 6810 err = mv88e6xxx_port_set_lock(chip, port, locked); 6811 if (err) 6812 goto out; 6813 } 6814 out: 6815 mv88e6xxx_reg_unlock(chip); 6816 6817 return err; 6818 } 6819 6820 static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds, 6821 struct dsa_lag lag, 6822 struct netdev_lag_upper_info *info, 6823 struct netlink_ext_ack *extack) 6824 { 6825 struct mv88e6xxx_chip *chip = ds->priv; 6826 struct dsa_port *dp; 6827 int members = 0; 6828 6829 if (!mv88e6xxx_has_lag(chip)) { 6830 NL_SET_ERR_MSG_MOD(extack, "Chip does not support LAG offload"); 6831 return false; 6832 } 6833 6834 if (!lag.id) 6835 return false; 6836 6837 dsa_lag_foreach_port(dp, ds->dst, &lag) 6838 /* Includes the port joining the LAG */ 6839 members++; 6840 6841 if (members > 8) { 6842 NL_SET_ERR_MSG_MOD(extack, 6843 "Cannot offload more than 8 LAG ports"); 6844 return false; 6845 } 6846 6847 /* We could potentially relax this to include active 6848 * backup in the future. 6849 */ 6850 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) { 6851 NL_SET_ERR_MSG_MOD(extack, 6852 "Can only offload LAG using hash TX type"); 6853 return false; 6854 } 6855 6856 /* Ideally we would also validate that the hash type matches 6857 * the hardware. Alas, this is always set to unknown on team 6858 * interfaces. 6859 */ 6860 return true; 6861 } 6862 6863 static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct dsa_lag lag) 6864 { 6865 struct mv88e6xxx_chip *chip = ds->priv; 6866 struct dsa_port *dp; 6867 u16 map = 0; 6868 int id; 6869 6870 /* DSA LAG IDs are one-based, hardware is zero-based */ 6871 id = lag.id - 1; 6872 6873 /* Build the map of all ports to distribute flows destined for 6874 * this LAG. This can be either a local user port, or a DSA 6875 * port if the LAG port is on a remote chip. 6876 */ 6877 dsa_lag_foreach_port(dp, ds->dst, &lag) 6878 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index)); 6879 6880 return mv88e6xxx_g2_trunk_mapping_write(chip, id, map); 6881 } 6882 6883 static const u8 mv88e6xxx_lag_mask_table[8][8] = { 6884 /* Row number corresponds to the number of active members in a 6885 * LAG. Each column states which of the eight hash buckets are 6886 * mapped to the column:th port in the LAG. 6887 * 6888 * Example: In a LAG with three active ports, the second port 6889 * ([2][1]) would be selected for traffic mapped to buckets 6890 * 3,4,5 (0x38). 6891 */ 6892 { 0xff, 0, 0, 0, 0, 0, 0, 0 }, 6893 { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 }, 6894 { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 }, 6895 { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 }, 6896 { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 }, 6897 { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 }, 6898 { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 }, 6899 { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 }, 6900 }; 6901 6902 static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port, 6903 int num_tx, int nth) 6904 { 6905 u8 active = 0; 6906 int i; 6907 6908 num_tx = num_tx <= 8 ? num_tx : 8; 6909 if (nth < num_tx) 6910 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth]; 6911 6912 for (i = 0; i < 8; i++) { 6913 if (BIT(i) & active) 6914 mask[i] |= BIT(port); 6915 } 6916 } 6917 6918 static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds) 6919 { 6920 struct mv88e6xxx_chip *chip = ds->priv; 6921 unsigned int id, num_tx; 6922 struct dsa_port *dp; 6923 struct dsa_lag *lag; 6924 int i, err, nth; 6925 u16 mask[8]; 6926 u16 ivec; 6927 6928 /* Assume no port is a member of any LAG. */ 6929 ivec = BIT(mv88e6xxx_num_ports(chip)) - 1; 6930 6931 /* Disable all masks for ports that _are_ members of a LAG. */ 6932 dsa_switch_for_each_port(dp, ds) { 6933 if (!dp->lag) 6934 continue; 6935 6936 ivec &= ~BIT(dp->index); 6937 } 6938 6939 for (i = 0; i < 8; i++) 6940 mask[i] = ivec; 6941 6942 /* Enable the correct subset of masks for all LAG ports that 6943 * are in the Tx set. 6944 */ 6945 dsa_lags_foreach_id(id, ds->dst) { 6946 lag = dsa_lag_by_id(ds->dst, id); 6947 if (!lag) 6948 continue; 6949 6950 num_tx = 0; 6951 dsa_lag_foreach_port(dp, ds->dst, lag) { 6952 if (dp->lag_tx_enabled) 6953 num_tx++; 6954 } 6955 6956 if (!num_tx) 6957 continue; 6958 6959 nth = 0; 6960 dsa_lag_foreach_port(dp, ds->dst, lag) { 6961 if (!dp->lag_tx_enabled) 6962 continue; 6963 6964 if (dp->ds == ds) 6965 mv88e6xxx_lag_set_port_mask(mask, dp->index, 6966 num_tx, nth); 6967 6968 nth++; 6969 } 6970 } 6971 6972 for (i = 0; i < 8; i++) { 6973 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]); 6974 if (err) 6975 return err; 6976 } 6977 6978 return 0; 6979 } 6980 6981 static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds, 6982 struct dsa_lag lag) 6983 { 6984 int err; 6985 6986 err = mv88e6xxx_lag_sync_masks(ds); 6987 6988 if (!err) 6989 err = mv88e6xxx_lag_sync_map(ds, lag); 6990 6991 return err; 6992 } 6993 6994 static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port) 6995 { 6996 struct mv88e6xxx_chip *chip = ds->priv; 6997 int err; 6998 6999 mv88e6xxx_reg_lock(chip); 7000 err = mv88e6xxx_lag_sync_masks(ds); 7001 mv88e6xxx_reg_unlock(chip); 7002 return err; 7003 } 7004 7005 static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port, 7006 struct dsa_lag lag, 7007 struct netdev_lag_upper_info *info, 7008 struct netlink_ext_ack *extack) 7009 { 7010 struct mv88e6xxx_chip *chip = ds->priv; 7011 int err, id; 7012 7013 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack)) 7014 return -EOPNOTSUPP; 7015 7016 /* DSA LAG IDs are one-based */ 7017 id = lag.id - 1; 7018 7019 mv88e6xxx_reg_lock(chip); 7020 7021 err = mv88e6xxx_port_set_trunk(chip, port, true, id); 7022 if (err) 7023 goto err_unlock; 7024 7025 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 7026 if (err) 7027 goto err_clear_trunk; 7028 7029 mv88e6xxx_reg_unlock(chip); 7030 return 0; 7031 7032 err_clear_trunk: 7033 mv88e6xxx_port_set_trunk(chip, port, false, 0); 7034 err_unlock: 7035 mv88e6xxx_reg_unlock(chip); 7036 return err; 7037 } 7038 7039 static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port, 7040 struct dsa_lag lag) 7041 { 7042 struct mv88e6xxx_chip *chip = ds->priv; 7043 int err_sync, err_trunk; 7044 7045 mv88e6xxx_reg_lock(chip); 7046 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 7047 err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0); 7048 mv88e6xxx_reg_unlock(chip); 7049 return err_sync ? : err_trunk; 7050 } 7051 7052 static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index, 7053 int port) 7054 { 7055 struct mv88e6xxx_chip *chip = ds->priv; 7056 int err; 7057 7058 mv88e6xxx_reg_lock(chip); 7059 err = mv88e6xxx_lag_sync_masks(ds); 7060 mv88e6xxx_reg_unlock(chip); 7061 return err; 7062 } 7063 7064 static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index, 7065 int port, struct dsa_lag lag, 7066 struct netdev_lag_upper_info *info, 7067 struct netlink_ext_ack *extack) 7068 { 7069 struct mv88e6xxx_chip *chip = ds->priv; 7070 int err; 7071 7072 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack)) 7073 return -EOPNOTSUPP; 7074 7075 mv88e6xxx_reg_lock(chip); 7076 7077 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 7078 if (err) 7079 goto unlock; 7080 7081 err = mv88e6xxx_pvt_map(chip, sw_index, port); 7082 7083 unlock: 7084 mv88e6xxx_reg_unlock(chip); 7085 return err; 7086 } 7087 7088 static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index, 7089 int port, struct dsa_lag lag) 7090 { 7091 struct mv88e6xxx_chip *chip = ds->priv; 7092 int err_sync, err_pvt; 7093 7094 mv88e6xxx_reg_lock(chip); 7095 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 7096 err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port); 7097 mv88e6xxx_reg_unlock(chip); 7098 return err_sync ? : err_pvt; 7099 } 7100 7101 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 7102 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 7103 .change_tag_protocol = mv88e6xxx_change_tag_protocol, 7104 .setup = mv88e6xxx_setup, 7105 .teardown = mv88e6xxx_teardown, 7106 .port_setup = mv88e6xxx_port_setup, 7107 .port_teardown = mv88e6xxx_port_teardown, 7108 .phylink_get_caps = mv88e6xxx_get_caps, 7109 .phylink_mac_link_state = mv88e6xxx_serdes_pcs_get_state, 7110 .phylink_mac_prepare = mv88e6xxx_mac_prepare, 7111 .phylink_mac_config = mv88e6xxx_mac_config, 7112 .phylink_mac_finish = mv88e6xxx_mac_finish, 7113 .phylink_mac_an_restart = mv88e6xxx_serdes_pcs_an_restart, 7114 .phylink_mac_link_down = mv88e6xxx_mac_link_down, 7115 .phylink_mac_link_up = mv88e6xxx_mac_link_up, 7116 .get_strings = mv88e6xxx_get_strings, 7117 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 7118 .get_sset_count = mv88e6xxx_get_sset_count, 7119 .port_enable = mv88e6xxx_port_enable, 7120 .port_disable = mv88e6xxx_port_disable, 7121 .port_max_mtu = mv88e6xxx_get_max_mtu, 7122 .port_change_mtu = mv88e6xxx_change_mtu, 7123 .get_mac_eee = mv88e6xxx_get_mac_eee, 7124 .set_mac_eee = mv88e6xxx_set_mac_eee, 7125 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 7126 .get_eeprom = mv88e6xxx_get_eeprom, 7127 .set_eeprom = mv88e6xxx_set_eeprom, 7128 .get_regs_len = mv88e6xxx_get_regs_len, 7129 .get_regs = mv88e6xxx_get_regs, 7130 .get_rxnfc = mv88e6xxx_get_rxnfc, 7131 .set_rxnfc = mv88e6xxx_set_rxnfc, 7132 .set_ageing_time = mv88e6xxx_set_ageing_time, 7133 .port_bridge_join = mv88e6xxx_port_bridge_join, 7134 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 7135 .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags, 7136 .port_bridge_flags = mv88e6xxx_port_bridge_flags, 7137 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 7138 .port_mst_state_set = mv88e6xxx_port_mst_state_set, 7139 .port_fast_age = mv88e6xxx_port_fast_age, 7140 .port_vlan_fast_age = mv88e6xxx_port_vlan_fast_age, 7141 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 7142 .port_vlan_add = mv88e6xxx_port_vlan_add, 7143 .port_vlan_del = mv88e6xxx_port_vlan_del, 7144 .vlan_msti_set = mv88e6xxx_vlan_msti_set, 7145 .port_fdb_add = mv88e6xxx_port_fdb_add, 7146 .port_fdb_del = mv88e6xxx_port_fdb_del, 7147 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 7148 .port_mdb_add = mv88e6xxx_port_mdb_add, 7149 .port_mdb_del = mv88e6xxx_port_mdb_del, 7150 .port_mirror_add = mv88e6xxx_port_mirror_add, 7151 .port_mirror_del = mv88e6xxx_port_mirror_del, 7152 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 7153 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 7154 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 7155 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 7156 .port_txtstamp = mv88e6xxx_port_txtstamp, 7157 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 7158 .get_ts_info = mv88e6xxx_get_ts_info, 7159 .devlink_param_get = mv88e6xxx_devlink_param_get, 7160 .devlink_param_set = mv88e6xxx_devlink_param_set, 7161 .devlink_info_get = mv88e6xxx_devlink_info_get, 7162 .port_lag_change = mv88e6xxx_port_lag_change, 7163 .port_lag_join = mv88e6xxx_port_lag_join, 7164 .port_lag_leave = mv88e6xxx_port_lag_leave, 7165 .crosschip_lag_change = mv88e6xxx_crosschip_lag_change, 7166 .crosschip_lag_join = mv88e6xxx_crosschip_lag_join, 7167 .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave, 7168 }; 7169 7170 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 7171 { 7172 struct device *dev = chip->dev; 7173 struct dsa_switch *ds; 7174 7175 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); 7176 if (!ds) 7177 return -ENOMEM; 7178 7179 ds->dev = dev; 7180 ds->num_ports = mv88e6xxx_num_ports(chip); 7181 ds->priv = chip; 7182 ds->dev = dev; 7183 ds->ops = &mv88e6xxx_switch_ops; 7184 ds->ageing_time_min = chip->info->age_time_coeff; 7185 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 7186 7187 /* Some chips support up to 32, but that requires enabling the 7188 * 5-bit port mode, which we do not support. 640k^W16 ought to 7189 * be enough for anyone. 7190 */ 7191 ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0; 7192 7193 dev_set_drvdata(dev, ds); 7194 7195 return dsa_register_switch(ds); 7196 } 7197 7198 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 7199 { 7200 dsa_unregister_switch(chip->ds); 7201 } 7202 7203 static const void *pdata_device_get_match_data(struct device *dev) 7204 { 7205 const struct of_device_id *matches = dev->driver->of_match_table; 7206 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; 7207 7208 for (; matches->name[0] || matches->type[0] || matches->compatible[0]; 7209 matches++) { 7210 if (!strcmp(pdata->compatible, matches->compatible)) 7211 return matches->data; 7212 } 7213 return NULL; 7214 } 7215 7216 /* There is no suspend to RAM support at DSA level yet, the switch configuration 7217 * would be lost after a power cycle so prevent it to be suspended. 7218 */ 7219 static int __maybe_unused mv88e6xxx_suspend(struct device *dev) 7220 { 7221 return -EOPNOTSUPP; 7222 } 7223 7224 static int __maybe_unused mv88e6xxx_resume(struct device *dev) 7225 { 7226 return 0; 7227 } 7228 7229 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume); 7230 7231 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 7232 { 7233 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; 7234 const struct mv88e6xxx_info *compat_info = NULL; 7235 struct device *dev = &mdiodev->dev; 7236 struct device_node *np = dev->of_node; 7237 struct mv88e6xxx_chip *chip; 7238 int port; 7239 int err; 7240 7241 if (!np && !pdata) 7242 return -EINVAL; 7243 7244 if (np) 7245 compat_info = of_device_get_match_data(dev); 7246 7247 if (pdata) { 7248 compat_info = pdata_device_get_match_data(dev); 7249 7250 if (!pdata->netdev) 7251 return -EINVAL; 7252 7253 for (port = 0; port < DSA_MAX_PORTS; port++) { 7254 if (!(pdata->enabled_ports & (1 << port))) 7255 continue; 7256 if (strcmp(pdata->cd.port_names[port], "cpu")) 7257 continue; 7258 pdata->cd.netdev[port] = &pdata->netdev->dev; 7259 break; 7260 } 7261 } 7262 7263 if (!compat_info) 7264 return -EINVAL; 7265 7266 chip = mv88e6xxx_alloc_chip(dev); 7267 if (!chip) { 7268 err = -ENOMEM; 7269 goto out; 7270 } 7271 7272 chip->info = compat_info; 7273 7274 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 7275 if (IS_ERR(chip->reset)) { 7276 err = PTR_ERR(chip->reset); 7277 goto out; 7278 } 7279 if (chip->reset) 7280 usleep_range(10000, 20000); 7281 7282 /* Detect if the device is configured in single chip addressing mode, 7283 * otherwise continue with address specific smi init/detection. 7284 */ 7285 err = mv88e6xxx_single_chip_detect(chip, mdiodev); 7286 if (err) { 7287 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 7288 if (err) 7289 goto out; 7290 7291 err = mv88e6xxx_detect(chip); 7292 if (err) 7293 goto out; 7294 } 7295 7296 if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED) 7297 chip->tag_protocol = DSA_TAG_PROTO_EDSA; 7298 else 7299 chip->tag_protocol = DSA_TAG_PROTO_DSA; 7300 7301 mv88e6xxx_phy_init(chip); 7302 7303 if (chip->info->ops->get_eeprom) { 7304 if (np) 7305 of_property_read_u32(np, "eeprom-length", 7306 &chip->eeprom_len); 7307 else 7308 chip->eeprom_len = pdata->eeprom_len; 7309 } 7310 7311 mv88e6xxx_reg_lock(chip); 7312 err = mv88e6xxx_switch_reset(chip); 7313 mv88e6xxx_reg_unlock(chip); 7314 if (err) 7315 goto out; 7316 7317 if (np) { 7318 chip->irq = of_irq_get(np, 0); 7319 if (chip->irq == -EPROBE_DEFER) { 7320 err = chip->irq; 7321 goto out; 7322 } 7323 } 7324 7325 if (pdata) 7326 chip->irq = pdata->irq; 7327 7328 /* Has to be performed before the MDIO bus is created, because 7329 * the PHYs will link their interrupts to these interrupt 7330 * controllers 7331 */ 7332 mv88e6xxx_reg_lock(chip); 7333 if (chip->irq > 0) 7334 err = mv88e6xxx_g1_irq_setup(chip); 7335 else 7336 err = mv88e6xxx_irq_poll_setup(chip); 7337 mv88e6xxx_reg_unlock(chip); 7338 7339 if (err) 7340 goto out; 7341 7342 if (chip->info->g2_irqs > 0) { 7343 err = mv88e6xxx_g2_irq_setup(chip); 7344 if (err) 7345 goto out_g1_irq; 7346 } 7347 7348 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 7349 if (err) 7350 goto out_g2_irq; 7351 7352 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 7353 if (err) 7354 goto out_g1_atu_prob_irq; 7355 7356 err = mv88e6xxx_register_switch(chip); 7357 if (err) 7358 goto out_g1_vtu_prob_irq; 7359 7360 return 0; 7361 7362 out_g1_vtu_prob_irq: 7363 mv88e6xxx_g1_vtu_prob_irq_free(chip); 7364 out_g1_atu_prob_irq: 7365 mv88e6xxx_g1_atu_prob_irq_free(chip); 7366 out_g2_irq: 7367 if (chip->info->g2_irqs > 0) 7368 mv88e6xxx_g2_irq_free(chip); 7369 out_g1_irq: 7370 if (chip->irq > 0) 7371 mv88e6xxx_g1_irq_free(chip); 7372 else 7373 mv88e6xxx_irq_poll_free(chip); 7374 out: 7375 if (pdata) 7376 dev_put(pdata->netdev); 7377 7378 return err; 7379 } 7380 7381 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 7382 { 7383 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 7384 struct mv88e6xxx_chip *chip; 7385 7386 if (!ds) 7387 return; 7388 7389 chip = ds->priv; 7390 7391 if (chip->info->ptp_support) { 7392 mv88e6xxx_hwtstamp_free(chip); 7393 mv88e6xxx_ptp_free(chip); 7394 } 7395 7396 mv88e6xxx_phy_destroy(chip); 7397 mv88e6xxx_unregister_switch(chip); 7398 7399 mv88e6xxx_g1_vtu_prob_irq_free(chip); 7400 mv88e6xxx_g1_atu_prob_irq_free(chip); 7401 7402 if (chip->info->g2_irqs > 0) 7403 mv88e6xxx_g2_irq_free(chip); 7404 7405 if (chip->irq > 0) 7406 mv88e6xxx_g1_irq_free(chip); 7407 else 7408 mv88e6xxx_irq_poll_free(chip); 7409 } 7410 7411 static void mv88e6xxx_shutdown(struct mdio_device *mdiodev) 7412 { 7413 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 7414 7415 if (!ds) 7416 return; 7417 7418 dsa_switch_shutdown(ds); 7419 7420 dev_set_drvdata(&mdiodev->dev, NULL); 7421 } 7422 7423 static const struct of_device_id mv88e6xxx_of_match[] = { 7424 { 7425 .compatible = "marvell,mv88e6085", 7426 .data = &mv88e6xxx_table[MV88E6085], 7427 }, 7428 { 7429 .compatible = "marvell,mv88e6190", 7430 .data = &mv88e6xxx_table[MV88E6190], 7431 }, 7432 { 7433 .compatible = "marvell,mv88e6250", 7434 .data = &mv88e6xxx_table[MV88E6250], 7435 }, 7436 { /* sentinel */ }, 7437 }; 7438 7439 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 7440 7441 static struct mdio_driver mv88e6xxx_driver = { 7442 .probe = mv88e6xxx_probe, 7443 .remove = mv88e6xxx_remove, 7444 .shutdown = mv88e6xxx_shutdown, 7445 .mdiodrv.driver = { 7446 .name = "mv88e6085", 7447 .of_match_table = mv88e6xxx_of_match, 7448 .pm = &mv88e6xxx_pm_ops, 7449 }, 7450 }; 7451 7452 mdio_module_driver(mv88e6xxx_driver); 7453 7454 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 7455 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 7456 MODULE_LICENSE("GPL"); 7457