1 /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- 2 * 3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * Copyright 2014 Advanced Micro Devices, Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: 27 * Kevin E. Martin <martin@valinux.com> 28 * Gareth Hughes <gareth@valinux.com> 29 * Keith Whitwell <keith@tungstengraphics.com> 30 */ 31 32 #ifndef __AMDGPU_DRM_H__ 33 #define __AMDGPU_DRM_H__ 34 35 #include "drm.h" 36 37 #if defined(__cplusplus) 38 extern "C" { 39 #endif 40 41 #define DRM_AMDGPU_GEM_CREATE 0x00 42 #define DRM_AMDGPU_GEM_MMAP 0x01 43 #define DRM_AMDGPU_CTX 0x02 44 #define DRM_AMDGPU_BO_LIST 0x03 45 #define DRM_AMDGPU_CS 0x04 46 #define DRM_AMDGPU_INFO 0x05 47 #define DRM_AMDGPU_GEM_METADATA 0x06 48 #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 49 #define DRM_AMDGPU_GEM_VA 0x08 50 #define DRM_AMDGPU_WAIT_CS 0x09 51 #define DRM_AMDGPU_GEM_OP 0x10 52 #define DRM_AMDGPU_GEM_USERPTR 0x11 53 #define DRM_AMDGPU_WAIT_FENCES 0x12 54 #define DRM_AMDGPU_VM 0x13 55 #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 56 #define DRM_AMDGPU_SCHED 0x15 57 58 #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 59 #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) 60 #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) 61 #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) 62 #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) 63 #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) 64 #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) 65 #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) 66 #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) 67 #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) 68 #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) 69 #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 70 #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) 71 #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) 72 #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) 73 #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) 74 75 /** 76 * DOC: memory domains 77 * 78 * %AMDGPU_GEM_DOMAIN_CPU System memory that is not GPU accessible. 79 * Memory in this pool could be swapped out to disk if there is pressure. 80 * 81 * %AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into the 82 * GPU's virtual address space via gart. Gart memory linearizes non-contiguous 83 * pages of system memory, allows GPU access system memory in a linearized 84 * fashion. 85 * 86 * %AMDGPU_GEM_DOMAIN_VRAM Local video memory. For APUs, it is memory 87 * carved out by the BIOS. 88 * 89 * %AMDGPU_GEM_DOMAIN_GDS Global on-chip data storage used to share data 90 * across shader threads. 91 * 92 * %AMDGPU_GEM_DOMAIN_GWS Global wave sync, used to synchronize the 93 * execution of all the waves on a device. 94 * 95 * %AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute engines 96 * for appending data. 97 */ 98 #define AMDGPU_GEM_DOMAIN_CPU 0x1 99 #define AMDGPU_GEM_DOMAIN_GTT 0x2 100 #define AMDGPU_GEM_DOMAIN_VRAM 0x4 101 #define AMDGPU_GEM_DOMAIN_GDS 0x8 102 #define AMDGPU_GEM_DOMAIN_GWS 0x10 103 #define AMDGPU_GEM_DOMAIN_OA 0x20 104 #define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \ 105 AMDGPU_GEM_DOMAIN_GTT | \ 106 AMDGPU_GEM_DOMAIN_VRAM | \ 107 AMDGPU_GEM_DOMAIN_GDS | \ 108 AMDGPU_GEM_DOMAIN_GWS | \ 109 AMDGPU_GEM_DOMAIN_OA) 110 111 /* Flag that CPU access will be required for the case of VRAM domain */ 112 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) 113 /* Flag that CPU access will not work, this VRAM domain is invisible */ 114 #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) 115 /* Flag that USWC attributes should be used for GTT */ 116 #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) 117 /* Flag that the memory should be in VRAM and cleared */ 118 #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) 119 /* Flag that allocating the BO should use linear VRAM */ 120 #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) 121 /* Flag that BO is always valid in this VM */ 122 #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6) 123 /* Flag that BO sharing will be explicitly synchronized */ 124 #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7) 125 /* Flag that indicates allocating MQD gart on GFX9, where the mtype 126 * for the second page onward should be set to NC. It should never 127 * be used by user space applications. 128 */ 129 #define AMDGPU_GEM_CREATE_CP_MQD_GFX9 (1 << 8) 130 /* Flag that BO may contain sensitive data that must be wiped before 131 * releasing the memory 132 */ 133 #define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE (1 << 9) 134 /* Flag that BO will be encrypted and that the TMZ bit should be 135 * set in the PTEs when mapping this buffer via GPUVM or 136 * accessing it with various hw blocks 137 */ 138 #define AMDGPU_GEM_CREATE_ENCRYPTED (1 << 10) 139 /* Flag that BO will be used only in preemptible context, which does 140 * not require GTT memory accounting 141 */ 142 #define AMDGPU_GEM_CREATE_PREEMPTIBLE (1 << 11) 143 /* Flag that BO can be discarded under memory pressure without keeping the 144 * content. 145 */ 146 #define AMDGPU_GEM_CREATE_DISCARDABLE (1 << 12) 147 /* Flag that BO is shared coherently between multiple devices or CPU threads. 148 * May depend on GPU instructions to flush caches explicitly 149 * 150 * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and 151 * may override the MTYPE selected in AMDGPU_VA_OP_MAP. 152 */ 153 #define AMDGPU_GEM_CREATE_COHERENT (1 << 13) 154 /* Flag that BO should not be cached by GPU. Coherent without having to flush 155 * GPU caches explicitly 156 * 157 * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and 158 * may override the MTYPE selected in AMDGPU_VA_OP_MAP. 159 */ 160 #define AMDGPU_GEM_CREATE_UNCACHED (1 << 14) 161 162 struct drm_amdgpu_gem_create_in { 163 /** the requested memory size */ 164 __u64 bo_size; 165 /** physical start_addr alignment in bytes for some HW requirements */ 166 __u64 alignment; 167 /** the requested memory domains */ 168 __u64 domains; 169 /** allocation flags */ 170 __u64 domain_flags; 171 }; 172 173 struct drm_amdgpu_gem_create_out { 174 /** returned GEM object handle */ 175 __u32 handle; 176 __u32 _pad; 177 }; 178 179 union drm_amdgpu_gem_create { 180 struct drm_amdgpu_gem_create_in in; 181 struct drm_amdgpu_gem_create_out out; 182 }; 183 184 /** Opcode to create new residency list. */ 185 #define AMDGPU_BO_LIST_OP_CREATE 0 186 /** Opcode to destroy previously created residency list */ 187 #define AMDGPU_BO_LIST_OP_DESTROY 1 188 /** Opcode to update resource information in the list */ 189 #define AMDGPU_BO_LIST_OP_UPDATE 2 190 191 struct drm_amdgpu_bo_list_in { 192 /** Type of operation */ 193 __u32 operation; 194 /** Handle of list or 0 if we want to create one */ 195 __u32 list_handle; 196 /** Number of BOs in list */ 197 __u32 bo_number; 198 /** Size of each element describing BO */ 199 __u32 bo_info_size; 200 /** Pointer to array describing BOs */ 201 __u64 bo_info_ptr; 202 }; 203 204 struct drm_amdgpu_bo_list_entry { 205 /** Handle of BO */ 206 __u32 bo_handle; 207 /** New (if specified) BO priority to be used during migration */ 208 __u32 bo_priority; 209 }; 210 211 struct drm_amdgpu_bo_list_out { 212 /** Handle of resource list */ 213 __u32 list_handle; 214 __u32 _pad; 215 }; 216 217 union drm_amdgpu_bo_list { 218 struct drm_amdgpu_bo_list_in in; 219 struct drm_amdgpu_bo_list_out out; 220 }; 221 222 /* context related */ 223 #define AMDGPU_CTX_OP_ALLOC_CTX 1 224 #define AMDGPU_CTX_OP_FREE_CTX 2 225 #define AMDGPU_CTX_OP_QUERY_STATE 3 226 #define AMDGPU_CTX_OP_QUERY_STATE2 4 227 #define AMDGPU_CTX_OP_GET_STABLE_PSTATE 5 228 #define AMDGPU_CTX_OP_SET_STABLE_PSTATE 6 229 230 /* GPU reset status */ 231 #define AMDGPU_CTX_NO_RESET 0 232 /* this the context caused it */ 233 #define AMDGPU_CTX_GUILTY_RESET 1 234 /* some other context caused it */ 235 #define AMDGPU_CTX_INNOCENT_RESET 2 236 /* unknown cause */ 237 #define AMDGPU_CTX_UNKNOWN_RESET 3 238 239 /* indicate gpu reset occured after ctx created */ 240 #define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0) 241 /* indicate vram lost occured after ctx created */ 242 #define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1) 243 /* indicate some job from this context once cause gpu hang */ 244 #define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2) 245 /* indicate some errors are detected by RAS */ 246 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1<<3) 247 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1<<4) 248 /* indicate that the reset hasn't completed yet */ 249 #define AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS (1<<5) 250 251 /* Context priority level */ 252 #define AMDGPU_CTX_PRIORITY_UNSET -2048 253 #define AMDGPU_CTX_PRIORITY_VERY_LOW -1023 254 #define AMDGPU_CTX_PRIORITY_LOW -512 255 #define AMDGPU_CTX_PRIORITY_NORMAL 0 256 /* 257 * When used in struct drm_amdgpu_ctx_in, a priority above NORMAL requires 258 * CAP_SYS_NICE or DRM_MASTER 259 */ 260 #define AMDGPU_CTX_PRIORITY_HIGH 512 261 #define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023 262 263 /* select a stable profiling pstate for perfmon tools */ 264 #define AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK 0xf 265 #define AMDGPU_CTX_STABLE_PSTATE_NONE 0 266 #define AMDGPU_CTX_STABLE_PSTATE_STANDARD 1 267 #define AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK 2 268 #define AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK 3 269 #define AMDGPU_CTX_STABLE_PSTATE_PEAK 4 270 271 struct drm_amdgpu_ctx_in { 272 /** AMDGPU_CTX_OP_* */ 273 __u32 op; 274 /** Flags */ 275 __u32 flags; 276 __u32 ctx_id; 277 /** AMDGPU_CTX_PRIORITY_* */ 278 __s32 priority; 279 }; 280 281 union drm_amdgpu_ctx_out { 282 struct { 283 __u32 ctx_id; 284 __u32 _pad; 285 } alloc; 286 287 struct { 288 /** For future use, no flags defined so far */ 289 __u64 flags; 290 /** Number of resets caused by this context so far. */ 291 __u32 hangs; 292 /** Reset status since the last call of the ioctl. */ 293 __u32 reset_status; 294 } state; 295 296 struct { 297 __u32 flags; 298 __u32 _pad; 299 } pstate; 300 }; 301 302 union drm_amdgpu_ctx { 303 struct drm_amdgpu_ctx_in in; 304 union drm_amdgpu_ctx_out out; 305 }; 306 307 /* vm ioctl */ 308 #define AMDGPU_VM_OP_RESERVE_VMID 1 309 #define AMDGPU_VM_OP_UNRESERVE_VMID 2 310 311 struct drm_amdgpu_vm_in { 312 /** AMDGPU_VM_OP_* */ 313 __u32 op; 314 __u32 flags; 315 }; 316 317 struct drm_amdgpu_vm_out { 318 /** For future use, no flags defined so far */ 319 __u64 flags; 320 }; 321 322 union drm_amdgpu_vm { 323 struct drm_amdgpu_vm_in in; 324 struct drm_amdgpu_vm_out out; 325 }; 326 327 /* sched ioctl */ 328 #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1 329 #define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2 330 331 struct drm_amdgpu_sched_in { 332 /* AMDGPU_SCHED_OP_* */ 333 __u32 op; 334 __u32 fd; 335 /** AMDGPU_CTX_PRIORITY_* */ 336 __s32 priority; 337 __u32 ctx_id; 338 }; 339 340 union drm_amdgpu_sched { 341 struct drm_amdgpu_sched_in in; 342 }; 343 344 /* 345 * This is not a reliable API and you should expect it to fail for any 346 * number of reasons and have fallback path that do not use userptr to 347 * perform any operation. 348 */ 349 #define AMDGPU_GEM_USERPTR_READONLY (1 << 0) 350 #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) 351 #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) 352 #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) 353 354 struct drm_amdgpu_gem_userptr { 355 __u64 addr; 356 __u64 size; 357 /* AMDGPU_GEM_USERPTR_* */ 358 __u32 flags; 359 /* Resulting GEM handle */ 360 __u32 handle; 361 }; 362 363 /* SI-CI-VI: */ 364 /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ 365 #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 366 #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf 367 #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 368 #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f 369 #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 370 #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 371 #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 372 #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 373 #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 374 #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 375 #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 376 #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 377 #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 378 #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 379 #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 380 #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 381 382 /* GFX9 and later: */ 383 #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 384 #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f 385 #define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5 386 #define AMDGPU_TILING_DCC_OFFSET_256B_MASK 0xFFFFFF 387 #define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT 29 388 #define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF 389 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43 390 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1 391 #define AMDGPU_TILING_DCC_INDEPENDENT_128B_SHIFT 44 392 #define AMDGPU_TILING_DCC_INDEPENDENT_128B_MASK 0x1 393 #define AMDGPU_TILING_SCANOUT_SHIFT 63 394 #define AMDGPU_TILING_SCANOUT_MASK 0x1 395 396 /* Set/Get helpers for tiling flags. */ 397 #define AMDGPU_TILING_SET(field, value) \ 398 (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) 399 #define AMDGPU_TILING_GET(value, field) \ 400 (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) 401 402 #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 403 #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 404 405 /** The same structure is shared for input/output */ 406 struct drm_amdgpu_gem_metadata { 407 /** GEM Object handle */ 408 __u32 handle; 409 /** Do we want get or set metadata */ 410 __u32 op; 411 struct { 412 /** For future use, no flags defined so far */ 413 __u64 flags; 414 /** family specific tiling info */ 415 __u64 tiling_info; 416 __u32 data_size_bytes; 417 __u32 data[64]; 418 } data; 419 }; 420 421 struct drm_amdgpu_gem_mmap_in { 422 /** the GEM object handle */ 423 __u32 handle; 424 __u32 _pad; 425 }; 426 427 struct drm_amdgpu_gem_mmap_out { 428 /** mmap offset from the vma offset manager */ 429 __u64 addr_ptr; 430 }; 431 432 union drm_amdgpu_gem_mmap { 433 struct drm_amdgpu_gem_mmap_in in; 434 struct drm_amdgpu_gem_mmap_out out; 435 }; 436 437 struct drm_amdgpu_gem_wait_idle_in { 438 /** GEM object handle */ 439 __u32 handle; 440 /** For future use, no flags defined so far */ 441 __u32 flags; 442 /** Absolute timeout to wait */ 443 __u64 timeout; 444 }; 445 446 struct drm_amdgpu_gem_wait_idle_out { 447 /** BO status: 0 - BO is idle, 1 - BO is busy */ 448 __u32 status; 449 /** Returned current memory domain */ 450 __u32 domain; 451 }; 452 453 union drm_amdgpu_gem_wait_idle { 454 struct drm_amdgpu_gem_wait_idle_in in; 455 struct drm_amdgpu_gem_wait_idle_out out; 456 }; 457 458 struct drm_amdgpu_wait_cs_in { 459 /* Command submission handle 460 * handle equals 0 means none to wait for 461 * handle equals ~0ull means wait for the latest sequence number 462 */ 463 __u64 handle; 464 /** Absolute timeout to wait */ 465 __u64 timeout; 466 __u32 ip_type; 467 __u32 ip_instance; 468 __u32 ring; 469 __u32 ctx_id; 470 }; 471 472 struct drm_amdgpu_wait_cs_out { 473 /** CS status: 0 - CS completed, 1 - CS still busy */ 474 __u64 status; 475 }; 476 477 union drm_amdgpu_wait_cs { 478 struct drm_amdgpu_wait_cs_in in; 479 struct drm_amdgpu_wait_cs_out out; 480 }; 481 482 struct drm_amdgpu_fence { 483 __u32 ctx_id; 484 __u32 ip_type; 485 __u32 ip_instance; 486 __u32 ring; 487 __u64 seq_no; 488 }; 489 490 struct drm_amdgpu_wait_fences_in { 491 /** This points to uint64_t * which points to fences */ 492 __u64 fences; 493 __u32 fence_count; 494 __u32 wait_all; 495 __u64 timeout_ns; 496 }; 497 498 struct drm_amdgpu_wait_fences_out { 499 __u32 status; 500 __u32 first_signaled; 501 }; 502 503 union drm_amdgpu_wait_fences { 504 struct drm_amdgpu_wait_fences_in in; 505 struct drm_amdgpu_wait_fences_out out; 506 }; 507 508 #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 509 #define AMDGPU_GEM_OP_SET_PLACEMENT 1 510 511 /* Sets or returns a value associated with a buffer. */ 512 struct drm_amdgpu_gem_op { 513 /** GEM object handle */ 514 __u32 handle; 515 /** AMDGPU_GEM_OP_* */ 516 __u32 op; 517 /** Input or return value */ 518 __u64 value; 519 }; 520 521 #define AMDGPU_VA_OP_MAP 1 522 #define AMDGPU_VA_OP_UNMAP 2 523 #define AMDGPU_VA_OP_CLEAR 3 524 #define AMDGPU_VA_OP_REPLACE 4 525 526 /* Delay the page table update till the next CS */ 527 #define AMDGPU_VM_DELAY_UPDATE (1 << 0) 528 529 /* Mapping flags */ 530 /* readable mapping */ 531 #define AMDGPU_VM_PAGE_READABLE (1 << 1) 532 /* writable mapping */ 533 #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) 534 /* executable mapping, new for VI */ 535 #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) 536 /* partially resident texture */ 537 #define AMDGPU_VM_PAGE_PRT (1 << 4) 538 /* MTYPE flags use bit 5 to 8 */ 539 #define AMDGPU_VM_MTYPE_MASK (0xf << 5) 540 /* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */ 541 #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) 542 /* Use Non Coherent MTYPE instead of default MTYPE */ 543 #define AMDGPU_VM_MTYPE_NC (1 << 5) 544 /* Use Write Combine MTYPE instead of default MTYPE */ 545 #define AMDGPU_VM_MTYPE_WC (2 << 5) 546 /* Use Cache Coherent MTYPE instead of default MTYPE */ 547 #define AMDGPU_VM_MTYPE_CC (3 << 5) 548 /* Use UnCached MTYPE instead of default MTYPE */ 549 #define AMDGPU_VM_MTYPE_UC (4 << 5) 550 /* Use Read Write MTYPE instead of default MTYPE */ 551 #define AMDGPU_VM_MTYPE_RW (5 << 5) 552 /* don't allocate MALL */ 553 #define AMDGPU_VM_PAGE_NOALLOC (1 << 9) 554 555 struct drm_amdgpu_gem_va { 556 /** GEM object handle */ 557 __u32 handle; 558 __u32 _pad; 559 /** AMDGPU_VA_OP_* */ 560 __u32 operation; 561 /** AMDGPU_VM_PAGE_* */ 562 __u32 flags; 563 /** va address to assign . Must be correctly aligned.*/ 564 __u64 va_address; 565 /** Specify offset inside of BO to assign. Must be correctly aligned.*/ 566 __u64 offset_in_bo; 567 /** Specify mapping size. Must be correctly aligned. */ 568 __u64 map_size; 569 }; 570 571 #define AMDGPU_HW_IP_GFX 0 572 #define AMDGPU_HW_IP_COMPUTE 1 573 #define AMDGPU_HW_IP_DMA 2 574 #define AMDGPU_HW_IP_UVD 3 575 #define AMDGPU_HW_IP_VCE 4 576 #define AMDGPU_HW_IP_UVD_ENC 5 577 #define AMDGPU_HW_IP_VCN_DEC 6 578 /* 579 * From VCN4, AMDGPU_HW_IP_VCN_ENC is re-used to support 580 * both encoding and decoding jobs. 581 */ 582 #define AMDGPU_HW_IP_VCN_ENC 7 583 #define AMDGPU_HW_IP_VCN_JPEG 8 584 #define AMDGPU_HW_IP_NUM 9 585 586 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 587 588 #define AMDGPU_CHUNK_ID_IB 0x01 589 #define AMDGPU_CHUNK_ID_FENCE 0x02 590 #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 591 #define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04 592 #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05 593 #define AMDGPU_CHUNK_ID_BO_HANDLES 0x06 594 #define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07 595 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08 596 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09 597 #define AMDGPU_CHUNK_ID_CP_GFX_SHADOW 0x0a 598 599 struct drm_amdgpu_cs_chunk { 600 __u32 chunk_id; 601 __u32 length_dw; 602 __u64 chunk_data; 603 }; 604 605 struct drm_amdgpu_cs_in { 606 /** Rendering context id */ 607 __u32 ctx_id; 608 /** Handle of resource list associated with CS */ 609 __u32 bo_list_handle; 610 __u32 num_chunks; 611 __u32 flags; 612 /** this points to __u64 * which point to cs chunks */ 613 __u64 chunks; 614 }; 615 616 struct drm_amdgpu_cs_out { 617 __u64 handle; 618 }; 619 620 union drm_amdgpu_cs { 621 struct drm_amdgpu_cs_in in; 622 struct drm_amdgpu_cs_out out; 623 }; 624 625 /* Specify flags to be used for IB */ 626 627 /* This IB should be submitted to CE */ 628 #define AMDGPU_IB_FLAG_CE (1<<0) 629 630 /* Preamble flag, which means the IB could be dropped if no context switch */ 631 #define AMDGPU_IB_FLAG_PREAMBLE (1<<1) 632 633 /* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */ 634 #define AMDGPU_IB_FLAG_PREEMPT (1<<2) 635 636 /* The IB fence should do the L2 writeback but not invalidate any shader 637 * caches (L2/vL1/sL1/I$). */ 638 #define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3) 639 640 /* Set GDS_COMPUTE_MAX_WAVE_ID = DEFAULT before PACKET3_INDIRECT_BUFFER. 641 * This will reset wave ID counters for the IB. 642 */ 643 #define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4) 644 645 /* Flag the IB as secure (TMZ) 646 */ 647 #define AMDGPU_IB_FLAGS_SECURE (1 << 5) 648 649 /* Tell KMD to flush and invalidate caches 650 */ 651 #define AMDGPU_IB_FLAG_EMIT_MEM_SYNC (1 << 6) 652 653 struct drm_amdgpu_cs_chunk_ib { 654 __u32 _pad; 655 /** AMDGPU_IB_FLAG_* */ 656 __u32 flags; 657 /** Virtual address to begin IB execution */ 658 __u64 va_start; 659 /** Size of submission */ 660 __u32 ib_bytes; 661 /** HW IP to submit to */ 662 __u32 ip_type; 663 /** HW IP index of the same type to submit to */ 664 __u32 ip_instance; 665 /** Ring index to submit to */ 666 __u32 ring; 667 }; 668 669 struct drm_amdgpu_cs_chunk_dep { 670 __u32 ip_type; 671 __u32 ip_instance; 672 __u32 ring; 673 __u32 ctx_id; 674 __u64 handle; 675 }; 676 677 struct drm_amdgpu_cs_chunk_fence { 678 __u32 handle; 679 __u32 offset; 680 }; 681 682 struct drm_amdgpu_cs_chunk_sem { 683 __u32 handle; 684 }; 685 686 struct drm_amdgpu_cs_chunk_syncobj { 687 __u32 handle; 688 __u32 flags; 689 __u64 point; 690 }; 691 692 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0 693 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1 694 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2 695 696 union drm_amdgpu_fence_to_handle { 697 struct { 698 struct drm_amdgpu_fence fence; 699 __u32 what; 700 __u32 pad; 701 } in; 702 struct { 703 __u32 handle; 704 } out; 705 }; 706 707 struct drm_amdgpu_cs_chunk_data { 708 union { 709 struct drm_amdgpu_cs_chunk_ib ib_data; 710 struct drm_amdgpu_cs_chunk_fence fence_data; 711 }; 712 }; 713 714 #define AMDGPU_CS_CHUNK_CP_GFX_SHADOW_FLAGS_INIT_SHADOW 0x1 715 716 struct drm_amdgpu_cs_chunk_cp_gfx_shadow { 717 __u64 shadow_va; 718 __u64 csa_va; 719 __u64 gds_va; 720 __u64 flags; 721 }; 722 723 /* 724 * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU 725 * 726 */ 727 #define AMDGPU_IDS_FLAGS_FUSION 0x1 728 #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 729 #define AMDGPU_IDS_FLAGS_TMZ 0x4 730 #define AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD 0x8 731 732 /* indicate if acceleration can be working */ 733 #define AMDGPU_INFO_ACCEL_WORKING 0x00 734 /* get the crtc_id from the mode object id? */ 735 #define AMDGPU_INFO_CRTC_FROM_ID 0x01 736 /* query hw IP info */ 737 #define AMDGPU_INFO_HW_IP_INFO 0x02 738 /* query hw IP instance count for the specified type */ 739 #define AMDGPU_INFO_HW_IP_COUNT 0x03 740 /* timestamp for GL_ARB_timer_query */ 741 #define AMDGPU_INFO_TIMESTAMP 0x05 742 /* Query the firmware version */ 743 #define AMDGPU_INFO_FW_VERSION 0x0e 744 /* Subquery id: Query VCE firmware version */ 745 #define AMDGPU_INFO_FW_VCE 0x1 746 /* Subquery id: Query UVD firmware version */ 747 #define AMDGPU_INFO_FW_UVD 0x2 748 /* Subquery id: Query GMC firmware version */ 749 #define AMDGPU_INFO_FW_GMC 0x03 750 /* Subquery id: Query GFX ME firmware version */ 751 #define AMDGPU_INFO_FW_GFX_ME 0x04 752 /* Subquery id: Query GFX PFP firmware version */ 753 #define AMDGPU_INFO_FW_GFX_PFP 0x05 754 /* Subquery id: Query GFX CE firmware version */ 755 #define AMDGPU_INFO_FW_GFX_CE 0x06 756 /* Subquery id: Query GFX RLC firmware version */ 757 #define AMDGPU_INFO_FW_GFX_RLC 0x07 758 /* Subquery id: Query GFX MEC firmware version */ 759 #define AMDGPU_INFO_FW_GFX_MEC 0x08 760 /* Subquery id: Query SMC firmware version */ 761 #define AMDGPU_INFO_FW_SMC 0x0a 762 /* Subquery id: Query SDMA firmware version */ 763 #define AMDGPU_INFO_FW_SDMA 0x0b 764 /* Subquery id: Query PSP SOS firmware version */ 765 #define AMDGPU_INFO_FW_SOS 0x0c 766 /* Subquery id: Query PSP ASD firmware version */ 767 #define AMDGPU_INFO_FW_ASD 0x0d 768 /* Subquery id: Query VCN firmware version */ 769 #define AMDGPU_INFO_FW_VCN 0x0e 770 /* Subquery id: Query GFX RLC SRLC firmware version */ 771 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f 772 /* Subquery id: Query GFX RLC SRLG firmware version */ 773 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10 774 /* Subquery id: Query GFX RLC SRLS firmware version */ 775 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11 776 /* Subquery id: Query DMCU firmware version */ 777 #define AMDGPU_INFO_FW_DMCU 0x12 778 #define AMDGPU_INFO_FW_TA 0x13 779 /* Subquery id: Query DMCUB firmware version */ 780 #define AMDGPU_INFO_FW_DMCUB 0x14 781 /* Subquery id: Query TOC firmware version */ 782 #define AMDGPU_INFO_FW_TOC 0x15 783 /* Subquery id: Query CAP firmware version */ 784 #define AMDGPU_INFO_FW_CAP 0x16 785 /* Subquery id: Query GFX RLCP firmware version */ 786 #define AMDGPU_INFO_FW_GFX_RLCP 0x17 787 /* Subquery id: Query GFX RLCV firmware version */ 788 #define AMDGPU_INFO_FW_GFX_RLCV 0x18 789 /* Subquery id: Query MES_KIQ firmware version */ 790 #define AMDGPU_INFO_FW_MES_KIQ 0x19 791 /* Subquery id: Query MES firmware version */ 792 #define AMDGPU_INFO_FW_MES 0x1a 793 /* Subquery id: Query IMU firmware version */ 794 #define AMDGPU_INFO_FW_IMU 0x1b 795 796 /* number of bytes moved for TTM migration */ 797 #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f 798 /* the used VRAM size */ 799 #define AMDGPU_INFO_VRAM_USAGE 0x10 800 /* the used GTT size */ 801 #define AMDGPU_INFO_GTT_USAGE 0x11 802 /* Information about GDS, etc. resource configuration */ 803 #define AMDGPU_INFO_GDS_CONFIG 0x13 804 /* Query information about VRAM and GTT domains */ 805 #define AMDGPU_INFO_VRAM_GTT 0x14 806 /* Query information about register in MMR address space*/ 807 #define AMDGPU_INFO_READ_MMR_REG 0x15 808 /* Query information about device: rev id, family, etc. */ 809 #define AMDGPU_INFO_DEV_INFO 0x16 810 /* visible vram usage */ 811 #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 812 /* number of TTM buffer evictions */ 813 #define AMDGPU_INFO_NUM_EVICTIONS 0x18 814 /* Query memory about VRAM and GTT domains */ 815 #define AMDGPU_INFO_MEMORY 0x19 816 /* Query vce clock table */ 817 #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A 818 /* Query vbios related information */ 819 #define AMDGPU_INFO_VBIOS 0x1B 820 /* Subquery id: Query vbios size */ 821 #define AMDGPU_INFO_VBIOS_SIZE 0x1 822 /* Subquery id: Query vbios image */ 823 #define AMDGPU_INFO_VBIOS_IMAGE 0x2 824 /* Subquery id: Query vbios info */ 825 #define AMDGPU_INFO_VBIOS_INFO 0x3 826 /* Query UVD handles */ 827 #define AMDGPU_INFO_NUM_HANDLES 0x1C 828 /* Query sensor related information */ 829 #define AMDGPU_INFO_SENSOR 0x1D 830 /* Subquery id: Query GPU shader clock */ 831 #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1 832 /* Subquery id: Query GPU memory clock */ 833 #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2 834 /* Subquery id: Query GPU temperature */ 835 #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3 836 /* Subquery id: Query GPU load */ 837 #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4 838 /* Subquery id: Query average GPU power */ 839 #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5 840 /* Subquery id: Query northbridge voltage */ 841 #define AMDGPU_INFO_SENSOR_VDDNB 0x6 842 /* Subquery id: Query graphics voltage */ 843 #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 844 /* Subquery id: Query GPU stable pstate shader clock */ 845 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8 846 /* Subquery id: Query GPU stable pstate memory clock */ 847 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9 848 /* Subquery id: Query GPU peak pstate shader clock */ 849 #define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK 0xa 850 /* Subquery id: Query GPU peak pstate memory clock */ 851 #define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK 0xb 852 /* Number of VRAM page faults on CPU access. */ 853 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E 854 #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F 855 /* query ras mask of enabled features*/ 856 #define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20 857 /* RAS MASK: UMC (VRAM) */ 858 #define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0) 859 /* RAS MASK: SDMA */ 860 #define AMDGPU_INFO_RAS_ENABLED_SDMA (1 << 1) 861 /* RAS MASK: GFX */ 862 #define AMDGPU_INFO_RAS_ENABLED_GFX (1 << 2) 863 /* RAS MASK: MMHUB */ 864 #define AMDGPU_INFO_RAS_ENABLED_MMHUB (1 << 3) 865 /* RAS MASK: ATHUB */ 866 #define AMDGPU_INFO_RAS_ENABLED_ATHUB (1 << 4) 867 /* RAS MASK: PCIE */ 868 #define AMDGPU_INFO_RAS_ENABLED_PCIE (1 << 5) 869 /* RAS MASK: HDP */ 870 #define AMDGPU_INFO_RAS_ENABLED_HDP (1 << 6) 871 /* RAS MASK: XGMI */ 872 #define AMDGPU_INFO_RAS_ENABLED_XGMI (1 << 7) 873 /* RAS MASK: DF */ 874 #define AMDGPU_INFO_RAS_ENABLED_DF (1 << 8) 875 /* RAS MASK: SMN */ 876 #define AMDGPU_INFO_RAS_ENABLED_SMN (1 << 9) 877 /* RAS MASK: SEM */ 878 #define AMDGPU_INFO_RAS_ENABLED_SEM (1 << 10) 879 /* RAS MASK: MP0 */ 880 #define AMDGPU_INFO_RAS_ENABLED_MP0 (1 << 11) 881 /* RAS MASK: MP1 */ 882 #define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12) 883 /* RAS MASK: FUSE */ 884 #define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13) 885 /* query video encode/decode caps */ 886 #define AMDGPU_INFO_VIDEO_CAPS 0x21 887 /* Subquery id: Decode */ 888 #define AMDGPU_INFO_VIDEO_CAPS_DECODE 0 889 /* Subquery id: Encode */ 890 #define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1 891 /* Query the max number of IBs per gang per submission */ 892 #define AMDGPU_INFO_MAX_IBS 0x22 893 894 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 895 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 896 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 897 #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff 898 899 struct drm_amdgpu_query_fw { 900 /** AMDGPU_INFO_FW_* */ 901 __u32 fw_type; 902 /** 903 * Index of the IP if there are more IPs of 904 * the same type. 905 */ 906 __u32 ip_instance; 907 /** 908 * Index of the engine. Whether this is used depends 909 * on the firmware type. (e.g. MEC, SDMA) 910 */ 911 __u32 index; 912 __u32 _pad; 913 }; 914 915 /* Input structure for the INFO ioctl */ 916 struct drm_amdgpu_info { 917 /* Where the return value will be stored */ 918 __u64 return_pointer; 919 /* The size of the return value. Just like "size" in "snprintf", 920 * it limits how many bytes the kernel can write. */ 921 __u32 return_size; 922 /* The query request id. */ 923 __u32 query; 924 925 union { 926 struct { 927 __u32 id; 928 __u32 _pad; 929 } mode_crtc; 930 931 struct { 932 /** AMDGPU_HW_IP_* */ 933 __u32 type; 934 /** 935 * Index of the IP if there are more IPs of the same 936 * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. 937 */ 938 __u32 ip_instance; 939 } query_hw_ip; 940 941 struct { 942 __u32 dword_offset; 943 /** number of registers to read */ 944 __u32 count; 945 __u32 instance; 946 /** For future use, no flags defined so far */ 947 __u32 flags; 948 } read_mmr_reg; 949 950 struct drm_amdgpu_query_fw query_fw; 951 952 struct { 953 __u32 type; 954 __u32 offset; 955 } vbios_info; 956 957 struct { 958 __u32 type; 959 } sensor_info; 960 961 struct { 962 __u32 type; 963 } video_cap; 964 }; 965 }; 966 967 struct drm_amdgpu_info_gds { 968 /** GDS GFX partition size */ 969 __u32 gds_gfx_partition_size; 970 /** GDS compute partition size */ 971 __u32 compute_partition_size; 972 /** total GDS memory size */ 973 __u32 gds_total_size; 974 /** GWS size per GFX partition */ 975 __u32 gws_per_gfx_partition; 976 /** GSW size per compute partition */ 977 __u32 gws_per_compute_partition; 978 /** OA size per GFX partition */ 979 __u32 oa_per_gfx_partition; 980 /** OA size per compute partition */ 981 __u32 oa_per_compute_partition; 982 __u32 _pad; 983 }; 984 985 struct drm_amdgpu_info_vram_gtt { 986 __u64 vram_size; 987 __u64 vram_cpu_accessible_size; 988 __u64 gtt_size; 989 }; 990 991 struct drm_amdgpu_heap_info { 992 /** max. physical memory */ 993 __u64 total_heap_size; 994 995 /** Theoretical max. available memory in the given heap */ 996 __u64 usable_heap_size; 997 998 /** 999 * Number of bytes allocated in the heap. This includes all processes 1000 * and private allocations in the kernel. It changes when new buffers 1001 * are allocated, freed, and moved. It cannot be larger than 1002 * heap_size. 1003 */ 1004 __u64 heap_usage; 1005 1006 /** 1007 * Theoretical possible max. size of buffer which 1008 * could be allocated in the given heap 1009 */ 1010 __u64 max_allocation; 1011 }; 1012 1013 struct drm_amdgpu_memory_info { 1014 struct drm_amdgpu_heap_info vram; 1015 struct drm_amdgpu_heap_info cpu_accessible_vram; 1016 struct drm_amdgpu_heap_info gtt; 1017 }; 1018 1019 struct drm_amdgpu_info_firmware { 1020 __u32 ver; 1021 __u32 feature; 1022 }; 1023 1024 struct drm_amdgpu_info_vbios { 1025 __u8 name[64]; 1026 __u8 vbios_pn[64]; 1027 __u32 version; 1028 __u32 pad; 1029 __u8 vbios_ver_str[32]; 1030 __u8 date[32]; 1031 }; 1032 1033 #define AMDGPU_VRAM_TYPE_UNKNOWN 0 1034 #define AMDGPU_VRAM_TYPE_GDDR1 1 1035 #define AMDGPU_VRAM_TYPE_DDR2 2 1036 #define AMDGPU_VRAM_TYPE_GDDR3 3 1037 #define AMDGPU_VRAM_TYPE_GDDR4 4 1038 #define AMDGPU_VRAM_TYPE_GDDR5 5 1039 #define AMDGPU_VRAM_TYPE_HBM 6 1040 #define AMDGPU_VRAM_TYPE_DDR3 7 1041 #define AMDGPU_VRAM_TYPE_DDR4 8 1042 #define AMDGPU_VRAM_TYPE_GDDR6 9 1043 #define AMDGPU_VRAM_TYPE_DDR5 10 1044 #define AMDGPU_VRAM_TYPE_LPDDR4 11 1045 #define AMDGPU_VRAM_TYPE_LPDDR5 12 1046 1047 struct drm_amdgpu_info_device { 1048 /** PCI Device ID */ 1049 __u32 device_id; 1050 /** Internal chip revision: A0, A1, etc.) */ 1051 __u32 chip_rev; 1052 __u32 external_rev; 1053 /** Revision id in PCI Config space */ 1054 __u32 pci_rev; 1055 __u32 family; 1056 __u32 num_shader_engines; 1057 __u32 num_shader_arrays_per_engine; 1058 /* in KHz */ 1059 __u32 gpu_counter_freq; 1060 __u64 max_engine_clock; 1061 __u64 max_memory_clock; 1062 /* cu information */ 1063 __u32 cu_active_number; 1064 /* NOTE: cu_ao_mask is INVALID, DON'T use it */ 1065 __u32 cu_ao_mask; 1066 __u32 cu_bitmap[4][4]; 1067 /** Render backend pipe mask. One render backend is CB+DB. */ 1068 __u32 enabled_rb_pipes_mask; 1069 __u32 num_rb_pipes; 1070 __u32 num_hw_gfx_contexts; 1071 /* PCIe version (the smaller of the GPU and the CPU/motherboard) */ 1072 __u32 pcie_gen; 1073 __u64 ids_flags; 1074 /** Starting virtual address for UMDs. */ 1075 __u64 virtual_address_offset; 1076 /** The maximum virtual address */ 1077 __u64 virtual_address_max; 1078 /** Required alignment of virtual addresses. */ 1079 __u32 virtual_address_alignment; 1080 /** Page table entry - fragment size */ 1081 __u32 pte_fragment_size; 1082 __u32 gart_page_size; 1083 /** constant engine ram size*/ 1084 __u32 ce_ram_size; 1085 /** video memory type info*/ 1086 __u32 vram_type; 1087 /** video memory bit width*/ 1088 __u32 vram_bit_width; 1089 /* vce harvesting instance */ 1090 __u32 vce_harvest_config; 1091 /* gfx double offchip LDS buffers */ 1092 __u32 gc_double_offchip_lds_buf; 1093 /* NGG Primitive Buffer */ 1094 __u64 prim_buf_gpu_addr; 1095 /* NGG Position Buffer */ 1096 __u64 pos_buf_gpu_addr; 1097 /* NGG Control Sideband */ 1098 __u64 cntl_sb_buf_gpu_addr; 1099 /* NGG Parameter Cache */ 1100 __u64 param_buf_gpu_addr; 1101 __u32 prim_buf_size; 1102 __u32 pos_buf_size; 1103 __u32 cntl_sb_buf_size; 1104 __u32 param_buf_size; 1105 /* wavefront size*/ 1106 __u32 wave_front_size; 1107 /* shader visible vgprs*/ 1108 __u32 num_shader_visible_vgprs; 1109 /* CU per shader array*/ 1110 __u32 num_cu_per_sh; 1111 /* number of tcc blocks*/ 1112 __u32 num_tcc_blocks; 1113 /* gs vgt table depth*/ 1114 __u32 gs_vgt_table_depth; 1115 /* gs primitive buffer depth*/ 1116 __u32 gs_prim_buffer_depth; 1117 /* max gs wavefront per vgt*/ 1118 __u32 max_gs_waves_per_vgt; 1119 /* PCIe number of lanes (the smaller of the GPU and the CPU/motherboard) */ 1120 __u32 pcie_num_lanes; 1121 /* always on cu bitmap */ 1122 __u32 cu_ao_bitmap[4][4]; 1123 /** Starting high virtual address for UMDs. */ 1124 __u64 high_va_offset; 1125 /** The maximum high virtual address */ 1126 __u64 high_va_max; 1127 /* gfx10 pa_sc_tile_steering_override */ 1128 __u32 pa_sc_tile_steering_override; 1129 /* disabled TCCs */ 1130 __u64 tcc_disabled_mask; 1131 __u64 min_engine_clock; 1132 __u64 min_memory_clock; 1133 /* The following fields are only set on gfx11+, older chips set 0. */ 1134 __u32 tcp_cache_size; /* AKA GL0, VMEM cache */ 1135 __u32 num_sqc_per_wgp; 1136 __u32 sqc_data_cache_size; /* AKA SMEM cache */ 1137 __u32 sqc_inst_cache_size; 1138 __u32 gl1c_cache_size; 1139 __u32 gl2c_cache_size; 1140 __u64 mall_size; /* AKA infinity cache */ 1141 /* high 32 bits of the rb pipes mask */ 1142 __u32 enabled_rb_pipes_mask_hi; 1143 /* shadow area size for gfx11 */ 1144 __u32 shadow_size; 1145 /* shadow area base virtual alignment for gfx11 */ 1146 __u32 shadow_alignment; 1147 /* context save area size for gfx11 */ 1148 __u32 csa_size; 1149 /* context save area base virtual alignment for gfx11 */ 1150 __u32 csa_alignment; 1151 }; 1152 1153 struct drm_amdgpu_info_hw_ip { 1154 /** Version of h/w IP */ 1155 __u32 hw_ip_version_major; 1156 __u32 hw_ip_version_minor; 1157 /** Capabilities */ 1158 __u64 capabilities_flags; 1159 /** command buffer address start alignment*/ 1160 __u32 ib_start_alignment; 1161 /** command buffer size alignment*/ 1162 __u32 ib_size_alignment; 1163 /** Bitmask of available rings. Bit 0 means ring 0, etc. */ 1164 __u32 available_rings; 1165 /** version info: bits 23:16 major, 15:8 minor, 7:0 revision */ 1166 __u32 ip_discovery_version; 1167 }; 1168 1169 struct drm_amdgpu_info_num_handles { 1170 /** Max handles as supported by firmware for UVD */ 1171 __u32 uvd_max_handles; 1172 /** Handles currently in use for UVD */ 1173 __u32 uvd_used_handles; 1174 }; 1175 1176 #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 1177 1178 struct drm_amdgpu_info_vce_clock_table_entry { 1179 /** System clock */ 1180 __u32 sclk; 1181 /** Memory clock */ 1182 __u32 mclk; 1183 /** VCE clock */ 1184 __u32 eclk; 1185 __u32 pad; 1186 }; 1187 1188 struct drm_amdgpu_info_vce_clock_table { 1189 struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; 1190 __u32 num_valid_entries; 1191 __u32 pad; 1192 }; 1193 1194 /* query video encode/decode caps */ 1195 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2 0 1196 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4 1 1197 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1 2 1198 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC 3 1199 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC 4 1200 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG 5 1201 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9 6 1202 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1 7 1203 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT 8 1204 1205 struct drm_amdgpu_info_video_codec_info { 1206 __u32 valid; 1207 __u32 max_width; 1208 __u32 max_height; 1209 __u32 max_pixels_per_frame; 1210 __u32 max_level; 1211 __u32 pad; 1212 }; 1213 1214 struct drm_amdgpu_info_video_caps { 1215 struct drm_amdgpu_info_video_codec_info codec_info[AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT]; 1216 }; 1217 1218 /* 1219 * Supported GPU families 1220 */ 1221 #define AMDGPU_FAMILY_UNKNOWN 0 1222 #define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */ 1223 #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ 1224 #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ 1225 #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ 1226 #define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ 1227 #define AMDGPU_FAMILY_AI 141 /* Vega10 */ 1228 #define AMDGPU_FAMILY_RV 142 /* Raven */ 1229 #define AMDGPU_FAMILY_NV 143 /* Navi10 */ 1230 #define AMDGPU_FAMILY_VGH 144 /* Van Gogh */ 1231 #define AMDGPU_FAMILY_GC_11_0_0 145 /* GC 11.0.0 */ 1232 #define AMDGPU_FAMILY_YC 146 /* Yellow Carp */ 1233 #define AMDGPU_FAMILY_GC_11_0_1 148 /* GC 11.0.1 */ 1234 #define AMDGPU_FAMILY_GC_10_3_6 149 /* GC 10.3.6 */ 1235 #define AMDGPU_FAMILY_GC_10_3_7 151 /* GC 10.3.7 */ 1236 1237 #if defined(__cplusplus) 1238 } 1239 #endif 1240 1241 #endif 1242