1 /* 2 * Driver for One Laptop Per Child ‘CAFÉ’ controller, aka Marvell 88ALP01 3 * 4 * The data sheet for this device can be found at: 5 * http://wiki.laptop.org/go/Datasheets 6 * 7 * Copyright © 2006 Red Hat, Inc. 8 * Copyright © 2006 David Woodhouse <dwmw2@infradead.org> 9 */ 10 11 #define DEBUG 12 13 #include <linux/device.h> 14 #undef DEBUG 15 #include <linux/mtd/mtd.h> 16 #include <linux/mtd/rawnand.h> 17 #include <linux/mtd/partitions.h> 18 #include <linux/rslib.h> 19 #include <linux/pci.h> 20 #include <linux/delay.h> 21 #include <linux/interrupt.h> 22 #include <linux/dma-mapping.h> 23 #include <linux/slab.h> 24 #include <linux/module.h> 25 #include <asm/io.h> 26 27 #define CAFE_NAND_CTRL1 0x00 28 #define CAFE_NAND_CTRL2 0x04 29 #define CAFE_NAND_CTRL3 0x08 30 #define CAFE_NAND_STATUS 0x0c 31 #define CAFE_NAND_IRQ 0x10 32 #define CAFE_NAND_IRQ_MASK 0x14 33 #define CAFE_NAND_DATA_LEN 0x18 34 #define CAFE_NAND_ADDR1 0x1c 35 #define CAFE_NAND_ADDR2 0x20 36 #define CAFE_NAND_TIMING1 0x24 37 #define CAFE_NAND_TIMING2 0x28 38 #define CAFE_NAND_TIMING3 0x2c 39 #define CAFE_NAND_NONMEM 0x30 40 #define CAFE_NAND_ECC_RESULT 0x3C 41 #define CAFE_NAND_DMA_CTRL 0x40 42 #define CAFE_NAND_DMA_ADDR0 0x44 43 #define CAFE_NAND_DMA_ADDR1 0x48 44 #define CAFE_NAND_ECC_SYN01 0x50 45 #define CAFE_NAND_ECC_SYN23 0x54 46 #define CAFE_NAND_ECC_SYN45 0x58 47 #define CAFE_NAND_ECC_SYN67 0x5c 48 #define CAFE_NAND_READ_DATA 0x1000 49 #define CAFE_NAND_WRITE_DATA 0x2000 50 51 #define CAFE_GLOBAL_CTRL 0x3004 52 #define CAFE_GLOBAL_IRQ 0x3008 53 #define CAFE_GLOBAL_IRQ_MASK 0x300c 54 #define CAFE_NAND_RESET 0x3034 55 56 /* Missing from the datasheet: bit 19 of CTRL1 sets CE0 vs. CE1 */ 57 #define CTRL1_CHIPSELECT (1<<19) 58 59 struct cafe_priv { 60 struct nand_chip nand; 61 struct pci_dev *pdev; 62 void __iomem *mmio; 63 struct rs_control *rs; 64 uint32_t ctl1; 65 uint32_t ctl2; 66 int datalen; 67 int nr_data; 68 int data_pos; 69 int page_addr; 70 bool usedma; 71 dma_addr_t dmaaddr; 72 unsigned char *dmabuf; 73 }; 74 75 static int usedma = 1; 76 module_param(usedma, int, 0644); 77 78 static int skipbbt = 0; 79 module_param(skipbbt, int, 0644); 80 81 static int debug = 0; 82 module_param(debug, int, 0644); 83 84 static int regdebug = 0; 85 module_param(regdebug, int, 0644); 86 87 static int checkecc = 1; 88 module_param(checkecc, int, 0644); 89 90 static unsigned int numtimings; 91 static int timing[3]; 92 module_param_array(timing, int, &numtimings, 0644); 93 94 static const char *part_probes[] = { "cmdlinepart", "RedBoot", NULL }; 95 96 /* Hrm. Why isn't this already conditional on something in the struct device? */ 97 #define cafe_dev_dbg(dev, args...) do { if (debug) dev_dbg(dev, ##args); } while(0) 98 99 /* Make it easier to switch to PIO if we need to */ 100 #define cafe_readl(cafe, addr) readl((cafe)->mmio + CAFE_##addr) 101 #define cafe_writel(cafe, datum, addr) writel(datum, (cafe)->mmio + CAFE_##addr) 102 103 static int cafe_device_ready(struct nand_chip *chip) 104 { 105 struct cafe_priv *cafe = nand_get_controller_data(chip); 106 int result = !!(cafe_readl(cafe, NAND_STATUS) & 0x40000000); 107 uint32_t irqs = cafe_readl(cafe, NAND_IRQ); 108 109 cafe_writel(cafe, irqs, NAND_IRQ); 110 111 cafe_dev_dbg(&cafe->pdev->dev, "NAND device is%s ready, IRQ %x (%x) (%x,%x)\n", 112 result?"":" not", irqs, cafe_readl(cafe, NAND_IRQ), 113 cafe_readl(cafe, GLOBAL_IRQ), cafe_readl(cafe, GLOBAL_IRQ_MASK)); 114 115 return result; 116 } 117 118 119 static void cafe_write_buf(struct nand_chip *chip, const uint8_t *buf, int len) 120 { 121 struct cafe_priv *cafe = nand_get_controller_data(chip); 122 123 if (cafe->usedma) 124 memcpy(cafe->dmabuf + cafe->datalen, buf, len); 125 else 126 memcpy_toio(cafe->mmio + CAFE_NAND_WRITE_DATA + cafe->datalen, buf, len); 127 128 cafe->datalen += len; 129 130 cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes to write buffer. datalen 0x%x\n", 131 len, cafe->datalen); 132 } 133 134 static void cafe_read_buf(struct nand_chip *chip, uint8_t *buf, int len) 135 { 136 struct cafe_priv *cafe = nand_get_controller_data(chip); 137 138 if (cafe->usedma) 139 memcpy(buf, cafe->dmabuf + cafe->datalen, len); 140 else 141 memcpy_fromio(buf, cafe->mmio + CAFE_NAND_READ_DATA + cafe->datalen, len); 142 143 cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes from position 0x%x in read buffer.\n", 144 len, cafe->datalen); 145 cafe->datalen += len; 146 } 147 148 static uint8_t cafe_read_byte(struct nand_chip *chip) 149 { 150 struct cafe_priv *cafe = nand_get_controller_data(chip); 151 uint8_t d; 152 153 cafe_read_buf(chip, &d, 1); 154 cafe_dev_dbg(&cafe->pdev->dev, "Read %02x\n", d); 155 156 return d; 157 } 158 159 static void cafe_nand_cmdfunc(struct nand_chip *chip, unsigned command, 160 int column, int page_addr) 161 { 162 struct mtd_info *mtd = nand_to_mtd(chip); 163 struct cafe_priv *cafe = nand_get_controller_data(chip); 164 int adrbytes = 0; 165 uint32_t ctl1; 166 uint32_t doneint = 0x80000000; 167 168 cafe_dev_dbg(&cafe->pdev->dev, "cmdfunc %02x, 0x%x, 0x%x\n", 169 command, column, page_addr); 170 171 if (command == NAND_CMD_ERASE2 || command == NAND_CMD_PAGEPROG) { 172 /* Second half of a command we already calculated */ 173 cafe_writel(cafe, cafe->ctl2 | 0x100 | command, NAND_CTRL2); 174 ctl1 = cafe->ctl1; 175 cafe->ctl2 &= ~(1<<30); 176 cafe_dev_dbg(&cafe->pdev->dev, "Continue command, ctl1 %08x, #data %d\n", 177 cafe->ctl1, cafe->nr_data); 178 goto do_command; 179 } 180 /* Reset ECC engine */ 181 cafe_writel(cafe, 0, NAND_CTRL2); 182 183 /* Emulate NAND_CMD_READOOB on large-page chips */ 184 if (mtd->writesize > 512 && 185 command == NAND_CMD_READOOB) { 186 column += mtd->writesize; 187 command = NAND_CMD_READ0; 188 } 189 190 /* FIXME: Do we need to send read command before sending data 191 for small-page chips, to position the buffer correctly? */ 192 193 if (column != -1) { 194 cafe_writel(cafe, column, NAND_ADDR1); 195 adrbytes = 2; 196 if (page_addr != -1) 197 goto write_adr2; 198 } else if (page_addr != -1) { 199 cafe_writel(cafe, page_addr & 0xffff, NAND_ADDR1); 200 page_addr >>= 16; 201 write_adr2: 202 cafe_writel(cafe, page_addr, NAND_ADDR2); 203 adrbytes += 2; 204 if (mtd->size > mtd->writesize << 16) 205 adrbytes++; 206 } 207 208 cafe->data_pos = cafe->datalen = 0; 209 210 /* Set command valid bit, mask in the chip select bit */ 211 ctl1 = 0x80000000 | command | (cafe->ctl1 & CTRL1_CHIPSELECT); 212 213 /* Set RD or WR bits as appropriate */ 214 if (command == NAND_CMD_READID || command == NAND_CMD_STATUS) { 215 ctl1 |= (1<<26); /* rd */ 216 /* Always 5 bytes, for now */ 217 cafe->datalen = 4; 218 /* And one address cycle -- even for STATUS, since the controller doesn't work without */ 219 adrbytes = 1; 220 } else if (command == NAND_CMD_READ0 || command == NAND_CMD_READ1 || 221 command == NAND_CMD_READOOB || command == NAND_CMD_RNDOUT) { 222 ctl1 |= 1<<26; /* rd */ 223 /* For now, assume just read to end of page */ 224 cafe->datalen = mtd->writesize + mtd->oobsize - column; 225 } else if (command == NAND_CMD_SEQIN) 226 ctl1 |= 1<<25; /* wr */ 227 228 /* Set number of address bytes */ 229 if (adrbytes) 230 ctl1 |= ((adrbytes-1)|8) << 27; 231 232 if (command == NAND_CMD_SEQIN || command == NAND_CMD_ERASE1) { 233 /* Ignore the first command of a pair; the hardware 234 deals with them both at once, later */ 235 cafe->ctl1 = ctl1; 236 cafe_dev_dbg(&cafe->pdev->dev, "Setup for delayed command, ctl1 %08x, dlen %x\n", 237 cafe->ctl1, cafe->datalen); 238 return; 239 } 240 /* RNDOUT and READ0 commands need a following byte */ 241 if (command == NAND_CMD_RNDOUT) 242 cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_RNDOUTSTART, NAND_CTRL2); 243 else if (command == NAND_CMD_READ0 && mtd->writesize > 512) 244 cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_READSTART, NAND_CTRL2); 245 246 do_command: 247 cafe_dev_dbg(&cafe->pdev->dev, "dlen %x, ctl1 %x, ctl2 %x\n", 248 cafe->datalen, ctl1, cafe_readl(cafe, NAND_CTRL2)); 249 250 /* NB: The datasheet lies -- we really should be subtracting 1 here */ 251 cafe_writel(cafe, cafe->datalen, NAND_DATA_LEN); 252 cafe_writel(cafe, 0x90000000, NAND_IRQ); 253 if (cafe->usedma && (ctl1 & (3<<25))) { 254 uint32_t dmactl = 0xc0000000 + cafe->datalen; 255 /* If WR or RD bits set, set up DMA */ 256 if (ctl1 & (1<<26)) { 257 /* It's a read */ 258 dmactl |= (1<<29); 259 /* ... so it's done when the DMA is done, not just 260 the command. */ 261 doneint = 0x10000000; 262 } 263 cafe_writel(cafe, dmactl, NAND_DMA_CTRL); 264 } 265 cafe->datalen = 0; 266 267 if (unlikely(regdebug)) { 268 int i; 269 printk("About to write command %08x to register 0\n", ctl1); 270 for (i=4; i< 0x5c; i+=4) 271 printk("Register %x: %08x\n", i, readl(cafe->mmio + i)); 272 } 273 274 cafe_writel(cafe, ctl1, NAND_CTRL1); 275 /* Apply this short delay always to ensure that we do wait tWB in 276 * any case on any machine. */ 277 ndelay(100); 278 279 if (1) { 280 int c; 281 uint32_t irqs; 282 283 for (c = 500000; c != 0; c--) { 284 irqs = cafe_readl(cafe, NAND_IRQ); 285 if (irqs & doneint) 286 break; 287 udelay(1); 288 if (!(c % 100000)) 289 cafe_dev_dbg(&cafe->pdev->dev, "Wait for ready, IRQ %x\n", irqs); 290 cpu_relax(); 291 } 292 cafe_writel(cafe, doneint, NAND_IRQ); 293 cafe_dev_dbg(&cafe->pdev->dev, "Command %x completed after %d usec, irqs %x (%x)\n", 294 command, 500000-c, irqs, cafe_readl(cafe, NAND_IRQ)); 295 } 296 297 WARN_ON(cafe->ctl2 & (1<<30)); 298 299 switch (command) { 300 301 case NAND_CMD_CACHEDPROG: 302 case NAND_CMD_PAGEPROG: 303 case NAND_CMD_ERASE1: 304 case NAND_CMD_ERASE2: 305 case NAND_CMD_SEQIN: 306 case NAND_CMD_RNDIN: 307 case NAND_CMD_STATUS: 308 case NAND_CMD_RNDOUT: 309 cafe_writel(cafe, cafe->ctl2, NAND_CTRL2); 310 return; 311 } 312 nand_wait_ready(chip); 313 cafe_writel(cafe, cafe->ctl2, NAND_CTRL2); 314 } 315 316 static void cafe_select_chip(struct nand_chip *chip, int chipnr) 317 { 318 struct cafe_priv *cafe = nand_get_controller_data(chip); 319 320 cafe_dev_dbg(&cafe->pdev->dev, "select_chip %d\n", chipnr); 321 322 /* Mask the appropriate bit into the stored value of ctl1 323 which will be used by cafe_nand_cmdfunc() */ 324 if (chipnr) 325 cafe->ctl1 |= CTRL1_CHIPSELECT; 326 else 327 cafe->ctl1 &= ~CTRL1_CHIPSELECT; 328 } 329 330 static irqreturn_t cafe_nand_interrupt(int irq, void *id) 331 { 332 struct mtd_info *mtd = id; 333 struct nand_chip *chip = mtd_to_nand(mtd); 334 struct cafe_priv *cafe = nand_get_controller_data(chip); 335 uint32_t irqs = cafe_readl(cafe, NAND_IRQ); 336 cafe_writel(cafe, irqs & ~0x90000000, NAND_IRQ); 337 if (!irqs) 338 return IRQ_NONE; 339 340 cafe_dev_dbg(&cafe->pdev->dev, "irq, bits %x (%x)\n", irqs, cafe_readl(cafe, NAND_IRQ)); 341 return IRQ_HANDLED; 342 } 343 344 static int cafe_nand_write_oob(struct nand_chip *chip, int page) 345 { 346 struct mtd_info *mtd = nand_to_mtd(chip); 347 348 return nand_prog_page_op(chip, page, mtd->writesize, chip->oob_poi, 349 mtd->oobsize); 350 } 351 352 /* Don't use -- use nand_read_oob_std for now */ 353 static int cafe_nand_read_oob(struct nand_chip *chip, int page) 354 { 355 struct mtd_info *mtd = nand_to_mtd(chip); 356 357 return nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize); 358 } 359 /** 360 * cafe_nand_read_page_syndrome - [REPLACEABLE] hardware ecc syndrome based page read 361 * @mtd: mtd info structure 362 * @chip: nand chip info structure 363 * @buf: buffer to store read data 364 * @oob_required: caller expects OOB data read to chip->oob_poi 365 * 366 * The hw generator calculates the error syndrome automatically. Therefore 367 * we need a special oob layout and handling. 368 */ 369 static int cafe_nand_read_page(struct nand_chip *chip, uint8_t *buf, 370 int oob_required, int page) 371 { 372 struct mtd_info *mtd = nand_to_mtd(chip); 373 struct cafe_priv *cafe = nand_get_controller_data(chip); 374 unsigned int max_bitflips = 0; 375 376 cafe_dev_dbg(&cafe->pdev->dev, "ECC result %08x SYN1,2 %08x\n", 377 cafe_readl(cafe, NAND_ECC_RESULT), 378 cafe_readl(cafe, NAND_ECC_SYN01)); 379 380 nand_read_page_op(chip, page, 0, buf, mtd->writesize); 381 chip->legacy.read_buf(chip, chip->oob_poi, mtd->oobsize); 382 383 if (checkecc && cafe_readl(cafe, NAND_ECC_RESULT) & (1<<18)) { 384 unsigned short syn[8], pat[4]; 385 int pos[4]; 386 u8 *oob = chip->oob_poi; 387 int i, n; 388 389 for (i=0; i<8; i+=2) { 390 uint32_t tmp = cafe_readl(cafe, NAND_ECC_SYN01 + (i*2)); 391 392 syn[i] = cafe->rs->codec->index_of[tmp & 0xfff]; 393 syn[i+1] = cafe->rs->codec->index_of[(tmp >> 16) & 0xfff]; 394 } 395 396 n = decode_rs16(cafe->rs, NULL, NULL, 1367, syn, 0, pos, 0, 397 pat); 398 399 for (i = 0; i < n; i++) { 400 int p = pos[i]; 401 402 /* The 12-bit symbols are mapped to bytes here */ 403 404 if (p > 1374) { 405 /* out of range */ 406 n = -1374; 407 } else if (p == 0) { 408 /* high four bits do not correspond to data */ 409 if (pat[i] > 0xff) 410 n = -2048; 411 else 412 buf[0] ^= pat[i]; 413 } else if (p == 1365) { 414 buf[2047] ^= pat[i] >> 4; 415 oob[0] ^= pat[i] << 4; 416 } else if (p > 1365) { 417 if ((p & 1) == 1) { 418 oob[3*p/2 - 2048] ^= pat[i] >> 4; 419 oob[3*p/2 - 2047] ^= pat[i] << 4; 420 } else { 421 oob[3*p/2 - 2049] ^= pat[i] >> 8; 422 oob[3*p/2 - 2048] ^= pat[i]; 423 } 424 } else if ((p & 1) == 1) { 425 buf[3*p/2] ^= pat[i] >> 4; 426 buf[3*p/2 + 1] ^= pat[i] << 4; 427 } else { 428 buf[3*p/2 - 1] ^= pat[i] >> 8; 429 buf[3*p/2] ^= pat[i]; 430 } 431 } 432 433 if (n < 0) { 434 dev_dbg(&cafe->pdev->dev, "Failed to correct ECC at %08x\n", 435 cafe_readl(cafe, NAND_ADDR2) * 2048); 436 for (i = 0; i < 0x5c; i += 4) 437 printk("Register %x: %08x\n", i, readl(cafe->mmio + i)); 438 mtd->ecc_stats.failed++; 439 } else { 440 dev_dbg(&cafe->pdev->dev, "Corrected %d symbol errors\n", n); 441 mtd->ecc_stats.corrected += n; 442 max_bitflips = max_t(unsigned int, max_bitflips, n); 443 } 444 } 445 446 return max_bitflips; 447 } 448 449 static int cafe_ooblayout_ecc(struct mtd_info *mtd, int section, 450 struct mtd_oob_region *oobregion) 451 { 452 struct nand_chip *chip = mtd_to_nand(mtd); 453 454 if (section) 455 return -ERANGE; 456 457 oobregion->offset = 0; 458 oobregion->length = chip->ecc.total; 459 460 return 0; 461 } 462 463 static int cafe_ooblayout_free(struct mtd_info *mtd, int section, 464 struct mtd_oob_region *oobregion) 465 { 466 struct nand_chip *chip = mtd_to_nand(mtd); 467 468 if (section) 469 return -ERANGE; 470 471 oobregion->offset = chip->ecc.total; 472 oobregion->length = mtd->oobsize - chip->ecc.total; 473 474 return 0; 475 } 476 477 static const struct mtd_ooblayout_ops cafe_ooblayout_ops = { 478 .ecc = cafe_ooblayout_ecc, 479 .free = cafe_ooblayout_free, 480 }; 481 482 /* Ick. The BBT code really ought to be able to work this bit out 483 for itself from the above, at least for the 2KiB case */ 484 static uint8_t cafe_bbt_pattern_2048[] = { 'B', 'b', 't', '0' }; 485 static uint8_t cafe_mirror_pattern_2048[] = { '1', 't', 'b', 'B' }; 486 487 static uint8_t cafe_bbt_pattern_512[] = { 0xBB }; 488 static uint8_t cafe_mirror_pattern_512[] = { 0xBC }; 489 490 491 static struct nand_bbt_descr cafe_bbt_main_descr_2048 = { 492 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE 493 | NAND_BBT_2BIT | NAND_BBT_VERSION, 494 .offs = 14, 495 .len = 4, 496 .veroffs = 18, 497 .maxblocks = 4, 498 .pattern = cafe_bbt_pattern_2048 499 }; 500 501 static struct nand_bbt_descr cafe_bbt_mirror_descr_2048 = { 502 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE 503 | NAND_BBT_2BIT | NAND_BBT_VERSION, 504 .offs = 14, 505 .len = 4, 506 .veroffs = 18, 507 .maxblocks = 4, 508 .pattern = cafe_mirror_pattern_2048 509 }; 510 511 static struct nand_bbt_descr cafe_bbt_main_descr_512 = { 512 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE 513 | NAND_BBT_2BIT | NAND_BBT_VERSION, 514 .offs = 14, 515 .len = 1, 516 .veroffs = 15, 517 .maxblocks = 4, 518 .pattern = cafe_bbt_pattern_512 519 }; 520 521 static struct nand_bbt_descr cafe_bbt_mirror_descr_512 = { 522 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE 523 | NAND_BBT_2BIT | NAND_BBT_VERSION, 524 .offs = 14, 525 .len = 1, 526 .veroffs = 15, 527 .maxblocks = 4, 528 .pattern = cafe_mirror_pattern_512 529 }; 530 531 532 static int cafe_nand_write_page_lowlevel(struct nand_chip *chip, 533 const uint8_t *buf, int oob_required, 534 int page) 535 { 536 struct mtd_info *mtd = nand_to_mtd(chip); 537 struct cafe_priv *cafe = nand_get_controller_data(chip); 538 539 nand_prog_page_begin_op(chip, page, 0, buf, mtd->writesize); 540 chip->legacy.write_buf(chip, chip->oob_poi, mtd->oobsize); 541 542 /* Set up ECC autogeneration */ 543 cafe->ctl2 |= (1<<30); 544 545 return nand_prog_page_end_op(chip); 546 } 547 548 static int cafe_nand_block_bad(struct nand_chip *chip, loff_t ofs) 549 { 550 return 0; 551 } 552 553 /* F_2[X]/(X**6+X+1) */ 554 static unsigned short gf64_mul(u8 a, u8 b) 555 { 556 u8 c; 557 unsigned int i; 558 559 c = 0; 560 for (i = 0; i < 6; i++) { 561 if (a & 1) 562 c ^= b; 563 a >>= 1; 564 b <<= 1; 565 if ((b & 0x40) != 0) 566 b ^= 0x43; 567 } 568 569 return c; 570 } 571 572 /* F_64[X]/(X**2+X+A**-1) with A the generator of F_64[X] */ 573 static u16 gf4096_mul(u16 a, u16 b) 574 { 575 u8 ah, al, bh, bl, ch, cl; 576 577 ah = a >> 6; 578 al = a & 0x3f; 579 bh = b >> 6; 580 bl = b & 0x3f; 581 582 ch = gf64_mul(ah ^ al, bh ^ bl) ^ gf64_mul(al, bl); 583 cl = gf64_mul(gf64_mul(ah, bh), 0x21) ^ gf64_mul(al, bl); 584 585 return (ch << 6) ^ cl; 586 } 587 588 static int cafe_mul(int x) 589 { 590 if (x == 0) 591 return 1; 592 return gf4096_mul(x, 0xe01); 593 } 594 595 static int cafe_nand_attach_chip(struct nand_chip *chip) 596 { 597 struct mtd_info *mtd = nand_to_mtd(chip); 598 struct cafe_priv *cafe = nand_get_controller_data(chip); 599 int err = 0; 600 601 cafe->dmabuf = dma_alloc_coherent(&cafe->pdev->dev, 2112, 602 &cafe->dmaaddr, GFP_KERNEL); 603 if (!cafe->dmabuf) 604 return -ENOMEM; 605 606 /* Set up DMA address */ 607 cafe_writel(cafe, lower_32_bits(cafe->dmaaddr), NAND_DMA_ADDR0); 608 cafe_writel(cafe, upper_32_bits(cafe->dmaaddr), NAND_DMA_ADDR1); 609 610 cafe_dev_dbg(&cafe->pdev->dev, "Set DMA address to %x (virt %p)\n", 611 cafe_readl(cafe, NAND_DMA_ADDR0), cafe->dmabuf); 612 613 /* Restore the DMA flag */ 614 cafe->usedma = usedma; 615 616 cafe->ctl2 = BIT(27); /* Reed-Solomon ECC */ 617 if (mtd->writesize == 2048) 618 cafe->ctl2 |= BIT(29); /* 2KiB page size */ 619 620 /* Set up ECC according to the type of chip we found */ 621 mtd_set_ooblayout(mtd, &cafe_ooblayout_ops); 622 if (mtd->writesize == 2048) { 623 cafe->nand.bbt_td = &cafe_bbt_main_descr_2048; 624 cafe->nand.bbt_md = &cafe_bbt_mirror_descr_2048; 625 } else if (mtd->writesize == 512) { 626 cafe->nand.bbt_td = &cafe_bbt_main_descr_512; 627 cafe->nand.bbt_md = &cafe_bbt_mirror_descr_512; 628 } else { 629 dev_warn(&cafe->pdev->dev, 630 "Unexpected NAND flash writesize %d. Aborting\n", 631 mtd->writesize); 632 err = -ENOTSUPP; 633 goto out_free_dma; 634 } 635 636 cafe->nand.ecc.mode = NAND_ECC_HW_SYNDROME; 637 cafe->nand.ecc.size = mtd->writesize; 638 cafe->nand.ecc.bytes = 14; 639 cafe->nand.ecc.strength = 4; 640 cafe->nand.ecc.write_page = cafe_nand_write_page_lowlevel; 641 cafe->nand.ecc.write_oob = cafe_nand_write_oob; 642 cafe->nand.ecc.read_page = cafe_nand_read_page; 643 cafe->nand.ecc.read_oob = cafe_nand_read_oob; 644 645 return 0; 646 647 out_free_dma: 648 dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr); 649 650 return err; 651 } 652 653 static void cafe_nand_detach_chip(struct nand_chip *chip) 654 { 655 struct cafe_priv *cafe = nand_get_controller_data(chip); 656 657 dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr); 658 } 659 660 static const struct nand_controller_ops cafe_nand_controller_ops = { 661 .attach_chip = cafe_nand_attach_chip, 662 .detach_chip = cafe_nand_detach_chip, 663 }; 664 665 static int cafe_nand_probe(struct pci_dev *pdev, 666 const struct pci_device_id *ent) 667 { 668 struct mtd_info *mtd; 669 struct cafe_priv *cafe; 670 uint32_t ctrl; 671 int err = 0; 672 673 /* Very old versions shared the same PCI ident for all three 674 functions on the chip. Verify the class too... */ 675 if ((pdev->class >> 8) != PCI_CLASS_MEMORY_FLASH) 676 return -ENODEV; 677 678 err = pci_enable_device(pdev); 679 if (err) 680 return err; 681 682 pci_set_master(pdev); 683 684 cafe = kzalloc(sizeof(*cafe), GFP_KERNEL); 685 if (!cafe) 686 return -ENOMEM; 687 688 mtd = nand_to_mtd(&cafe->nand); 689 mtd->dev.parent = &pdev->dev; 690 nand_set_controller_data(&cafe->nand, cafe); 691 692 cafe->pdev = pdev; 693 cafe->mmio = pci_iomap(pdev, 0, 0); 694 if (!cafe->mmio) { 695 dev_warn(&pdev->dev, "failed to iomap\n"); 696 err = -ENOMEM; 697 goto out_free_mtd; 698 } 699 700 cafe->rs = init_rs_non_canonical(12, &cafe_mul, 0, 1, 8); 701 if (!cafe->rs) { 702 err = -ENOMEM; 703 goto out_ior; 704 } 705 706 cafe->nand.legacy.cmdfunc = cafe_nand_cmdfunc; 707 cafe->nand.legacy.dev_ready = cafe_device_ready; 708 cafe->nand.legacy.read_byte = cafe_read_byte; 709 cafe->nand.legacy.read_buf = cafe_read_buf; 710 cafe->nand.legacy.write_buf = cafe_write_buf; 711 cafe->nand.legacy.select_chip = cafe_select_chip; 712 cafe->nand.legacy.set_features = nand_get_set_features_notsupp; 713 cafe->nand.legacy.get_features = nand_get_set_features_notsupp; 714 715 cafe->nand.legacy.chip_delay = 0; 716 717 /* Enable the following for a flash based bad block table */ 718 cafe->nand.bbt_options = NAND_BBT_USE_FLASH; 719 720 if (skipbbt) { 721 cafe->nand.options |= NAND_SKIP_BBTSCAN; 722 cafe->nand.legacy.block_bad = cafe_nand_block_bad; 723 } 724 725 if (numtimings && numtimings != 3) { 726 dev_warn(&cafe->pdev->dev, "%d timing register values ignored; precisely three are required\n", numtimings); 727 } 728 729 if (numtimings == 3) { 730 cafe_dev_dbg(&cafe->pdev->dev, "Using provided timings (%08x %08x %08x)\n", 731 timing[0], timing[1], timing[2]); 732 } else { 733 timing[0] = cafe_readl(cafe, NAND_TIMING1); 734 timing[1] = cafe_readl(cafe, NAND_TIMING2); 735 timing[2] = cafe_readl(cafe, NAND_TIMING3); 736 737 if (timing[0] | timing[1] | timing[2]) { 738 cafe_dev_dbg(&cafe->pdev->dev, "Timing registers already set (%08x %08x %08x)\n", 739 timing[0], timing[1], timing[2]); 740 } else { 741 dev_warn(&cafe->pdev->dev, "Timing registers unset; using most conservative defaults\n"); 742 timing[0] = timing[1] = timing[2] = 0xffffffff; 743 } 744 } 745 746 /* Start off by resetting the NAND controller completely */ 747 cafe_writel(cafe, 1, NAND_RESET); 748 cafe_writel(cafe, 0, NAND_RESET); 749 750 cafe_writel(cafe, timing[0], NAND_TIMING1); 751 cafe_writel(cafe, timing[1], NAND_TIMING2); 752 cafe_writel(cafe, timing[2], NAND_TIMING3); 753 754 cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK); 755 err = request_irq(pdev->irq, &cafe_nand_interrupt, IRQF_SHARED, 756 "CAFE NAND", mtd); 757 if (err) { 758 dev_warn(&pdev->dev, "Could not register IRQ %d\n", pdev->irq); 759 goto out_ior; 760 } 761 762 /* Disable master reset, enable NAND clock */ 763 ctrl = cafe_readl(cafe, GLOBAL_CTRL); 764 ctrl &= 0xffffeff0; 765 ctrl |= 0x00007000; 766 cafe_writel(cafe, ctrl | 0x05, GLOBAL_CTRL); 767 cafe_writel(cafe, ctrl | 0x0a, GLOBAL_CTRL); 768 cafe_writel(cafe, 0, NAND_DMA_CTRL); 769 770 cafe_writel(cafe, 0x7006, GLOBAL_CTRL); 771 cafe_writel(cafe, 0x700a, GLOBAL_CTRL); 772 773 /* Enable NAND IRQ in global IRQ mask register */ 774 cafe_writel(cafe, 0x80000007, GLOBAL_IRQ_MASK); 775 cafe_dev_dbg(&cafe->pdev->dev, "Control %x, IRQ mask %x\n", 776 cafe_readl(cafe, GLOBAL_CTRL), 777 cafe_readl(cafe, GLOBAL_IRQ_MASK)); 778 779 /* Do not use the DMA during the NAND identification */ 780 cafe->usedma = 0; 781 782 /* Scan to find existence of the device */ 783 cafe->nand.legacy.dummy_controller.ops = &cafe_nand_controller_ops; 784 err = nand_scan(&cafe->nand, 2); 785 if (err) 786 goto out_irq; 787 788 pci_set_drvdata(pdev, mtd); 789 790 mtd->name = "cafe_nand"; 791 err = mtd_device_parse_register(mtd, part_probes, NULL, NULL, 0); 792 if (err) 793 goto out_cleanup_nand; 794 795 goto out; 796 797 out_cleanup_nand: 798 nand_cleanup(&cafe->nand); 799 out_irq: 800 /* Disable NAND IRQ in global IRQ mask register */ 801 cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK); 802 free_irq(pdev->irq, mtd); 803 out_ior: 804 pci_iounmap(pdev, cafe->mmio); 805 out_free_mtd: 806 kfree(cafe); 807 out: 808 return err; 809 } 810 811 static void cafe_nand_remove(struct pci_dev *pdev) 812 { 813 struct mtd_info *mtd = pci_get_drvdata(pdev); 814 struct nand_chip *chip = mtd_to_nand(mtd); 815 struct cafe_priv *cafe = nand_get_controller_data(chip); 816 817 /* Disable NAND IRQ in global IRQ mask register */ 818 cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK); 819 free_irq(pdev->irq, mtd); 820 nand_release(chip); 821 free_rs(cafe->rs); 822 pci_iounmap(pdev, cafe->mmio); 823 dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr); 824 kfree(cafe); 825 } 826 827 static const struct pci_device_id cafe_nand_tbl[] = { 828 { PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_88ALP01_NAND, 829 PCI_ANY_ID, PCI_ANY_ID }, 830 { } 831 }; 832 833 MODULE_DEVICE_TABLE(pci, cafe_nand_tbl); 834 835 static int cafe_nand_resume(struct pci_dev *pdev) 836 { 837 uint32_t ctrl; 838 struct mtd_info *mtd = pci_get_drvdata(pdev); 839 struct nand_chip *chip = mtd_to_nand(mtd); 840 struct cafe_priv *cafe = nand_get_controller_data(chip); 841 842 /* Start off by resetting the NAND controller completely */ 843 cafe_writel(cafe, 1, NAND_RESET); 844 cafe_writel(cafe, 0, NAND_RESET); 845 cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK); 846 847 /* Restore timing configuration */ 848 cafe_writel(cafe, timing[0], NAND_TIMING1); 849 cafe_writel(cafe, timing[1], NAND_TIMING2); 850 cafe_writel(cafe, timing[2], NAND_TIMING3); 851 852 /* Disable master reset, enable NAND clock */ 853 ctrl = cafe_readl(cafe, GLOBAL_CTRL); 854 ctrl &= 0xffffeff0; 855 ctrl |= 0x00007000; 856 cafe_writel(cafe, ctrl | 0x05, GLOBAL_CTRL); 857 cafe_writel(cafe, ctrl | 0x0a, GLOBAL_CTRL); 858 cafe_writel(cafe, 0, NAND_DMA_CTRL); 859 cafe_writel(cafe, 0x7006, GLOBAL_CTRL); 860 cafe_writel(cafe, 0x700a, GLOBAL_CTRL); 861 862 /* Set up DMA address */ 863 cafe_writel(cafe, cafe->dmaaddr & 0xffffffff, NAND_DMA_ADDR0); 864 if (sizeof(cafe->dmaaddr) > 4) 865 /* Shift in two parts to shut the compiler up */ 866 cafe_writel(cafe, (cafe->dmaaddr >> 16) >> 16, NAND_DMA_ADDR1); 867 else 868 cafe_writel(cafe, 0, NAND_DMA_ADDR1); 869 870 /* Enable NAND IRQ in global IRQ mask register */ 871 cafe_writel(cafe, 0x80000007, GLOBAL_IRQ_MASK); 872 return 0; 873 } 874 875 static struct pci_driver cafe_nand_pci_driver = { 876 .name = "CAFÉ NAND", 877 .id_table = cafe_nand_tbl, 878 .probe = cafe_nand_probe, 879 .remove = cafe_nand_remove, 880 .resume = cafe_nand_resume, 881 }; 882 883 module_pci_driver(cafe_nand_pci_driver); 884 885 MODULE_LICENSE("GPL"); 886 MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>"); 887 MODULE_DESCRIPTION("NAND flash driver for OLPC CAFÉ chip"); 888