1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * ALSA driver for RME Hammerfall DSP MADI audio interface(s) 4 * 5 * Copyright (c) 2003 Winfried Ritsch (IEM) 6 * code based on hdsp.c Paul Davis 7 * Marcus Andersson 8 * Thomas Charbonnel 9 * Modified 2006-06-01 for AES32 support by Remy Bruno 10 * <remy.bruno@trinnov.com> 11 * 12 * Modified 2009-04-13 for proper metering by Florian Faber 13 * <faber@faberman.de> 14 * 15 * Modified 2009-04-14 for native float support by Florian Faber 16 * <faber@faberman.de> 17 * 18 * Modified 2009-04-26 fixed bug in rms metering by Florian Faber 19 * <faber@faberman.de> 20 * 21 * Modified 2009-04-30 added hw serial number support by Florian Faber 22 * 23 * Modified 2011-01-14 added S/PDIF input on RayDATs by Adrian Knoth 24 * 25 * Modified 2011-01-25 variable period sizes on RayDAT/AIO by Adrian Knoth 26 * 27 * Modified 2019-05-23 fix AIO single speed ADAT capture and playback 28 * by Philippe.Bekaert@uhasselt.be 29 */ 30 31 /* ************* Register Documentation ******************************************************* 32 * 33 * Work in progress! Documentation is based on the code in this file. 34 * 35 * --------- HDSPM_controlRegister --------- 36 * :7654.3210:7654.3210:7654.3210:7654.3210: bit number per byte 37 * :||||.||||:||||.||||:||||.||||:||||.||||: 38 * :3322.2222:2222.1111:1111.1100:0000.0000: bit number 39 * :1098.7654:3210.9876:5432.1098:7654.3210: 0..31 40 * :||||.||||:||||.||||:||||.||||:||||.||||: 41 * :8421.8421:8421.8421:8421.8421:8421.8421: hex digit 42 * : . : . : . : x . : HDSPM_AudioInterruptEnable \_ setting both bits 43 * : . : . : . : . x: HDSPM_Start / enables audio IO 44 * : . : . : . : x. : HDSPM_ClockModeMaster - 1: Master, 0: Slave 45 * : . : . : . : .210 : HDSPM_LatencyMask - 3 Bit value for latency 46 * : . : . : . : . : 0:64, 1:128, 2:256, 3:512, 47 * : . : . : . : . : 4:1024, 5:2048, 6:4096, 7:8192 48 * :x . : . : . x:xx . : HDSPM_FrequencyMask 49 * : . : . : . :10 . : HDSPM_Frequency1|HDSPM_Frequency0: 1=32K,2=44.1K,3=48K,0=?? 50 * : . : . : . x: . : <MADI> HDSPM_DoubleSpeed 51 * :x . : . : . : . : <MADI> HDSPM_QuadSpeed 52 * : . 3 : . 10: 2 . : . : HDSPM_SyncRefMask : 53 * : . : . x: . : . : HDSPM_SyncRef0 54 * : . : . x : . : . : HDSPM_SyncRef1 55 * : . : . : x . : . : <AES32> HDSPM_SyncRef2 56 * : . x : . : . : . : <AES32> HDSPM_SyncRef3 57 * : . : . 10: . : . : <MADI> sync ref: 0:WC, 1:Madi, 2:TCO, 3:SyncIn 58 * : . 3 : . 10: 2 . : . : <AES32> 0:WC, 1:AES1 ... 8:AES8, 9: TCO, 10:SyncIn? 59 * : . x : . : . : . : <MADIe> HDSPe_FLOAT_FORMAT 60 * : . : . : x . : . : <MADI> HDSPM_InputSelect0 : 0=optical,1=coax 61 * : . : . :x . : . : <MADI> HDSPM_InputSelect1 62 * : . : .x : . : . : <MADI> HDSPM_clr_tms 63 * : . : . : . x : . : <MADI> HDSPM_TX_64ch 64 * : . : . : . x : . : <AES32> HDSPM_Emphasis 65 * : . : . : .x : . : <MADI> HDSPM_AutoInp 66 * : . : . x : . : . : <MADI> HDSPM_SMUX 67 * : . : .x : . : . : <MADI> HDSPM_clr_tms 68 * : . : x. : . : . : <MADI> HDSPM_taxi_reset 69 * : . x: . : . : . : <MADI> HDSPM_LineOut 70 * : . x: . : . : . : <AES32> ?????????????????? 71 * : . : x. : . : . : <AES32> HDSPM_WCK48 72 * : . : . : .x : . : <AES32> HDSPM_Dolby 73 * : . : x . : . : . : HDSPM_Midi0InterruptEnable 74 * : . :x . : . : . : HDSPM_Midi1InterruptEnable 75 * : . : x . : . : . : HDSPM_Midi2InterruptEnable 76 * : . x : . : . : . : <MADI> HDSPM_Midi3InterruptEnable 77 * : . x : . : . : . : <AES32> HDSPM_DS_DoubleWire 78 * : .x : . : . : . : <AES32> HDSPM_QS_DoubleWire 79 * : x. : . : . : . : <AES32> HDSPM_QS_QuadWire 80 * : . : . : . x : . : <AES32> HDSPM_Professional 81 * : x . : . : . : . : HDSPM_wclk_sel 82 * : . : . : . : . : 83 * :7654.3210:7654.3210:7654.3210:7654.3210: bit number per byte 84 * :||||.||||:||||.||||:||||.||||:||||.||||: 85 * :3322.2222:2222.1111:1111.1100:0000.0000: bit number 86 * :1098.7654:3210.9876:5432.1098:7654.3210: 0..31 87 * :||||.||||:||||.||||:||||.||||:||||.||||: 88 * :8421.8421:8421.8421:8421.8421:8421.8421:hex digit 89 * 90 * 91 * 92 * AIO / RayDAT only 93 * 94 * ------------ HDSPM_WR_SETTINGS ---------- 95 * :3322.2222:2222.1111:1111.1100:0000.0000: bit number per byte 96 * :1098.7654:3210.9876:5432.1098:7654.3210: 97 * :||||.||||:||||.||||:||||.||||:||||.||||: bit number 98 * :7654.3210:7654.3210:7654.3210:7654.3210: 0..31 99 * :||||.||||:||||.||||:||||.||||:||||.||||: 100 * :8421.8421:8421.8421:8421.8421:8421.8421: hex digit 101 * : . : . : . : . x: HDSPM_c0Master 1: Master, 0: Slave 102 * : . : . : . : . x : HDSPM_c0_SyncRef0 103 * : . : . : . : . x : HDSPM_c0_SyncRef1 104 * : . : . : . : .x : HDSPM_c0_SyncRef2 105 * : . : . : . : x. : HDSPM_c0_SyncRef3 106 * : . : . : . : 3.210 : HDSPM_c0_SyncRefMask: 107 * : . : . : . : . : RayDat: 0:WC, 1:AES, 2:SPDIF, 3..6: ADAT1..4, 108 * : . : . : . : . : 9:TCO, 10:SyncIn 109 * : . : . : . : . : AIO: 0:WC, 1:AES, 2: SPDIF, 3: ATAT, 110 * : . : . : . : . : 9:TCO, 10:SyncIn 111 * : . : . : . : . : 112 * : . : . : . : . : 113 * :3322.2222:2222.1111:1111.1100:0000.0000: bit number per byte 114 * :1098.7654:3210.9876:5432.1098:7654.3210: 115 * :||||.||||:||||.||||:||||.||||:||||.||||: bit number 116 * :7654.3210:7654.3210:7654.3210:7654.3210: 0..31 117 * :||||.||||:||||.||||:||||.||||:||||.||||: 118 * :8421.8421:8421.8421:8421.8421:8421.8421: hex digit 119 * 120 */ 121 #include <linux/init.h> 122 #include <linux/delay.h> 123 #include <linux/interrupt.h> 124 #include <linux/module.h> 125 #include <linux/slab.h> 126 #include <linux/pci.h> 127 #include <linux/math64.h> 128 #include <linux/io.h> 129 #include <linux/nospec.h> 130 131 #include <sound/core.h> 132 #include <sound/control.h> 133 #include <sound/pcm.h> 134 #include <sound/pcm_params.h> 135 #include <sound/info.h> 136 #include <sound/asoundef.h> 137 #include <sound/rawmidi.h> 138 #include <sound/hwdep.h> 139 #include <sound/initval.h> 140 141 #include <sound/hdspm.h> 142 143 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 144 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 145 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */ 146 147 module_param_array(index, int, NULL, 0444); 148 MODULE_PARM_DESC(index, "Index value for RME HDSPM interface."); 149 150 module_param_array(id, charp, NULL, 0444); 151 MODULE_PARM_DESC(id, "ID string for RME HDSPM interface."); 152 153 module_param_array(enable, bool, NULL, 0444); 154 MODULE_PARM_DESC(enable, "Enable/disable specific HDSPM soundcards."); 155 156 157 MODULE_AUTHOR 158 ( 159 "Winfried Ritsch <ritsch_AT_iem.at>, " 160 "Paul Davis <paul@linuxaudiosystems.com>, " 161 "Marcus Andersson, Thomas Charbonnel <thomas@undata.org>, " 162 "Remy Bruno <remy.bruno@trinnov.com>, " 163 "Florian Faber <faberman@linuxproaudio.org>, " 164 "Adrian Knoth <adi@drcomp.erfurt.thur.de>" 165 ); 166 MODULE_DESCRIPTION("RME HDSPM"); 167 MODULE_LICENSE("GPL"); 168 MODULE_SUPPORTED_DEVICE("{{RME HDSPM-MADI}}"); 169 170 /* --- Write registers. --- 171 These are defined as byte-offsets from the iobase value. */ 172 173 #define HDSPM_WR_SETTINGS 0 174 #define HDSPM_outputBufferAddress 32 175 #define HDSPM_inputBufferAddress 36 176 #define HDSPM_controlRegister 64 177 #define HDSPM_interruptConfirmation 96 178 #define HDSPM_control2Reg 256 /* not in specs ???????? */ 179 #define HDSPM_freqReg 256 /* for setting arbitrary clock values (DDS feature) */ 180 #define HDSPM_midiDataOut0 352 /* just believe in old code */ 181 #define HDSPM_midiDataOut1 356 182 #define HDSPM_eeprom_wr 384 /* for AES32 */ 183 184 /* DMA enable for 64 channels, only Bit 0 is relevant */ 185 #define HDSPM_outputEnableBase 512 /* 512-767 input DMA */ 186 #define HDSPM_inputEnableBase 768 /* 768-1023 output DMA */ 187 188 /* 16 page addresses for each of the 64 channels DMA buffer in and out 189 (each 64k=16*4k) Buffer must be 4k aligned (which is default i386 ????) */ 190 #define HDSPM_pageAddressBufferOut 8192 191 #define HDSPM_pageAddressBufferIn (HDSPM_pageAddressBufferOut+64*16*4) 192 193 #define HDSPM_MADI_mixerBase 32768 /* 32768-65535 for 2x64x64 Fader */ 194 195 #define HDSPM_MATRIX_MIXER_SIZE 8192 /* = 2*64*64 * 4 Byte => 32kB */ 196 197 /* --- Read registers. --- 198 These are defined as byte-offsets from the iobase value */ 199 #define HDSPM_statusRegister 0 200 /*#define HDSPM_statusRegister2 96 */ 201 /* after RME Windows driver sources, status2 is 4-byte word # 48 = word at 202 * offset 192, for AES32 *and* MADI 203 * => need to check that offset 192 is working on MADI */ 204 #define HDSPM_statusRegister2 192 205 #define HDSPM_timecodeRegister 128 206 207 /* AIO, RayDAT */ 208 #define HDSPM_RD_STATUS_0 0 209 #define HDSPM_RD_STATUS_1 64 210 #define HDSPM_RD_STATUS_2 128 211 #define HDSPM_RD_STATUS_3 192 212 213 #define HDSPM_RD_TCO 256 214 #define HDSPM_RD_PLL_FREQ 512 215 #define HDSPM_WR_TCO 128 216 217 #define HDSPM_TCO1_TCO_lock 0x00000001 218 #define HDSPM_TCO1_WCK_Input_Range_LSB 0x00000002 219 #define HDSPM_TCO1_WCK_Input_Range_MSB 0x00000004 220 #define HDSPM_TCO1_LTC_Input_valid 0x00000008 221 #define HDSPM_TCO1_WCK_Input_valid 0x00000010 222 #define HDSPM_TCO1_Video_Input_Format_NTSC 0x00000020 223 #define HDSPM_TCO1_Video_Input_Format_PAL 0x00000040 224 225 #define HDSPM_TCO1_set_TC 0x00000100 226 #define HDSPM_TCO1_set_drop_frame_flag 0x00000200 227 #define HDSPM_TCO1_LTC_Format_LSB 0x00000400 228 #define HDSPM_TCO1_LTC_Format_MSB 0x00000800 229 230 #define HDSPM_TCO2_TC_run 0x00010000 231 #define HDSPM_TCO2_WCK_IO_ratio_LSB 0x00020000 232 #define HDSPM_TCO2_WCK_IO_ratio_MSB 0x00040000 233 #define HDSPM_TCO2_set_num_drop_frames_LSB 0x00080000 234 #define HDSPM_TCO2_set_num_drop_frames_MSB 0x00100000 235 #define HDSPM_TCO2_set_jam_sync 0x00200000 236 #define HDSPM_TCO2_set_flywheel 0x00400000 237 238 #define HDSPM_TCO2_set_01_4 0x01000000 239 #define HDSPM_TCO2_set_pull_down 0x02000000 240 #define HDSPM_TCO2_set_pull_up 0x04000000 241 #define HDSPM_TCO2_set_freq 0x08000000 242 #define HDSPM_TCO2_set_term_75R 0x10000000 243 #define HDSPM_TCO2_set_input_LSB 0x20000000 244 #define HDSPM_TCO2_set_input_MSB 0x40000000 245 #define HDSPM_TCO2_set_freq_from_app 0x80000000 246 247 248 #define HDSPM_midiDataOut0 352 249 #define HDSPM_midiDataOut1 356 250 #define HDSPM_midiDataOut2 368 251 252 #define HDSPM_midiDataIn0 360 253 #define HDSPM_midiDataIn1 364 254 #define HDSPM_midiDataIn2 372 255 #define HDSPM_midiDataIn3 376 256 257 /* status is data bytes in MIDI-FIFO (0-128) */ 258 #define HDSPM_midiStatusOut0 384 259 #define HDSPM_midiStatusOut1 388 260 #define HDSPM_midiStatusOut2 400 261 262 #define HDSPM_midiStatusIn0 392 263 #define HDSPM_midiStatusIn1 396 264 #define HDSPM_midiStatusIn2 404 265 #define HDSPM_midiStatusIn3 408 266 267 268 /* the meters are regular i/o-mapped registers, but offset 269 considerably from the rest. the peak registers are reset 270 when read; the least-significant 4 bits are full-scale counters; 271 the actual peak value is in the most-significant 24 bits. 272 */ 273 274 #define HDSPM_MADI_INPUT_PEAK 4096 275 #define HDSPM_MADI_PLAYBACK_PEAK 4352 276 #define HDSPM_MADI_OUTPUT_PEAK 4608 277 278 #define HDSPM_MADI_INPUT_RMS_L 6144 279 #define HDSPM_MADI_PLAYBACK_RMS_L 6400 280 #define HDSPM_MADI_OUTPUT_RMS_L 6656 281 282 #define HDSPM_MADI_INPUT_RMS_H 7168 283 #define HDSPM_MADI_PLAYBACK_RMS_H 7424 284 #define HDSPM_MADI_OUTPUT_RMS_H 7680 285 286 /* --- Control Register bits --------- */ 287 #define HDSPM_Start (1<<0) /* start engine */ 288 289 #define HDSPM_Latency0 (1<<1) /* buffer size = 2^n */ 290 #define HDSPM_Latency1 (1<<2) /* where n is defined */ 291 #define HDSPM_Latency2 (1<<3) /* by Latency{2,1,0} */ 292 293 #define HDSPM_ClockModeMaster (1<<4) /* 1=Master, 0=Autosync */ 294 #define HDSPM_c0Master 0x1 /* Master clock bit in settings 295 register [RayDAT, AIO] */ 296 297 #define HDSPM_AudioInterruptEnable (1<<5) /* what do you think ? */ 298 299 #define HDSPM_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz 1=48kHz/96kHz */ 300 #define HDSPM_Frequency1 (1<<7) /* 0=32kHz/64kHz */ 301 #define HDSPM_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */ 302 #define HDSPM_QuadSpeed (1<<31) /* quad speed bit */ 303 304 #define HDSPM_Professional (1<<9) /* Professional */ /* AES32 ONLY */ 305 #define HDSPM_TX_64ch (1<<10) /* Output 64channel MODE=1, 306 56channelMODE=0 */ /* MADI ONLY*/ 307 #define HDSPM_Emphasis (1<<10) /* Emphasis */ /* AES32 ONLY */ 308 309 #define HDSPM_AutoInp (1<<11) /* Auto Input (takeover) == Safe Mode, 310 0=off, 1=on */ /* MADI ONLY */ 311 #define HDSPM_Dolby (1<<11) /* Dolby = "NonAudio" ?? */ /* AES32 ONLY */ 312 313 #define HDSPM_InputSelect0 (1<<14) /* Input select 0= optical, 1=coax 314 * -- MADI ONLY 315 */ 316 #define HDSPM_InputSelect1 (1<<15) /* should be 0 */ 317 318 #define HDSPM_SyncRef2 (1<<13) 319 #define HDSPM_SyncRef3 (1<<25) 320 321 #define HDSPM_SMUX (1<<18) /* Frame ??? */ /* MADI ONY */ 322 #define HDSPM_clr_tms (1<<19) /* clear track marker, do not use 323 AES additional bits in 324 lower 5 Audiodatabits ??? */ 325 #define HDSPM_taxi_reset (1<<20) /* ??? */ /* MADI ONLY ? */ 326 #define HDSPM_WCK48 (1<<20) /* Frame ??? = HDSPM_SMUX */ /* AES32 ONLY */ 327 328 #define HDSPM_Midi0InterruptEnable 0x0400000 329 #define HDSPM_Midi1InterruptEnable 0x0800000 330 #define HDSPM_Midi2InterruptEnable 0x0200000 331 #define HDSPM_Midi3InterruptEnable 0x4000000 332 333 #define HDSPM_LineOut (1<<24) /* Analog Out on channel 63/64 on=1, mute=0 */ 334 #define HDSPe_FLOAT_FORMAT 0x2000000 335 336 #define HDSPM_DS_DoubleWire (1<<26) /* AES32 ONLY */ 337 #define HDSPM_QS_DoubleWire (1<<27) /* AES32 ONLY */ 338 #define HDSPM_QS_QuadWire (1<<28) /* AES32 ONLY */ 339 340 #define HDSPM_wclk_sel (1<<30) 341 342 /* additional control register bits for AIO*/ 343 #define HDSPM_c0_Wck48 0x20 /* also RayDAT */ 344 #define HDSPM_c0_Input0 0x1000 345 #define HDSPM_c0_Input1 0x2000 346 #define HDSPM_c0_Spdif_Opt 0x4000 347 #define HDSPM_c0_Pro 0x8000 348 #define HDSPM_c0_clr_tms 0x10000 349 #define HDSPM_c0_AEB1 0x20000 350 #define HDSPM_c0_AEB2 0x40000 351 #define HDSPM_c0_LineOut 0x80000 352 #define HDSPM_c0_AD_GAIN0 0x100000 353 #define HDSPM_c0_AD_GAIN1 0x200000 354 #define HDSPM_c0_DA_GAIN0 0x400000 355 #define HDSPM_c0_DA_GAIN1 0x800000 356 #define HDSPM_c0_PH_GAIN0 0x1000000 357 #define HDSPM_c0_PH_GAIN1 0x2000000 358 #define HDSPM_c0_Sym6db 0x4000000 359 360 361 /* --- bit helper defines */ 362 #define HDSPM_LatencyMask (HDSPM_Latency0|HDSPM_Latency1|HDSPM_Latency2) 363 #define HDSPM_FrequencyMask (HDSPM_Frequency0|HDSPM_Frequency1|\ 364 HDSPM_DoubleSpeed|HDSPM_QuadSpeed) 365 #define HDSPM_InputMask (HDSPM_InputSelect0|HDSPM_InputSelect1) 366 #define HDSPM_InputOptical 0 367 #define HDSPM_InputCoaxial (HDSPM_InputSelect0) 368 #define HDSPM_SyncRefMask (HDSPM_SyncRef0|HDSPM_SyncRef1|\ 369 HDSPM_SyncRef2|HDSPM_SyncRef3) 370 371 #define HDSPM_c0_SyncRef0 0x2 372 #define HDSPM_c0_SyncRef1 0x4 373 #define HDSPM_c0_SyncRef2 0x8 374 #define HDSPM_c0_SyncRef3 0x10 375 #define HDSPM_c0_SyncRefMask (HDSPM_c0_SyncRef0 | HDSPM_c0_SyncRef1 |\ 376 HDSPM_c0_SyncRef2 | HDSPM_c0_SyncRef3) 377 378 #define HDSPM_SYNC_FROM_WORD 0 /* Preferred sync reference */ 379 #define HDSPM_SYNC_FROM_MADI 1 /* choices - used by "pref_sync_ref" */ 380 #define HDSPM_SYNC_FROM_TCO 2 381 #define HDSPM_SYNC_FROM_SYNC_IN 3 382 383 #define HDSPM_Frequency32KHz HDSPM_Frequency0 384 #define HDSPM_Frequency44_1KHz HDSPM_Frequency1 385 #define HDSPM_Frequency48KHz (HDSPM_Frequency1|HDSPM_Frequency0) 386 #define HDSPM_Frequency64KHz (HDSPM_DoubleSpeed|HDSPM_Frequency0) 387 #define HDSPM_Frequency88_2KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1) 388 #define HDSPM_Frequency96KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1|\ 389 HDSPM_Frequency0) 390 #define HDSPM_Frequency128KHz (HDSPM_QuadSpeed|HDSPM_Frequency0) 391 #define HDSPM_Frequency176_4KHz (HDSPM_QuadSpeed|HDSPM_Frequency1) 392 #define HDSPM_Frequency192KHz (HDSPM_QuadSpeed|HDSPM_Frequency1|\ 393 HDSPM_Frequency0) 394 395 396 /* Synccheck Status */ 397 #define HDSPM_SYNC_CHECK_NO_LOCK 0 398 #define HDSPM_SYNC_CHECK_LOCK 1 399 #define HDSPM_SYNC_CHECK_SYNC 2 400 401 /* AutoSync References - used by "autosync_ref" control switch */ 402 #define HDSPM_AUTOSYNC_FROM_WORD 0 403 #define HDSPM_AUTOSYNC_FROM_MADI 1 404 #define HDSPM_AUTOSYNC_FROM_TCO 2 405 #define HDSPM_AUTOSYNC_FROM_SYNC_IN 3 406 #define HDSPM_AUTOSYNC_FROM_NONE 4 407 408 /* Possible sources of MADI input */ 409 #define HDSPM_OPTICAL 0 /* optical */ 410 #define HDSPM_COAXIAL 1 /* BNC */ 411 412 #define hdspm_encode_latency(x) (((x)<<1) & HDSPM_LatencyMask) 413 #define hdspm_decode_latency(x) ((((x) & HDSPM_LatencyMask)>>1)) 414 415 #define hdspm_encode_in(x) (((x)&0x3)<<14) 416 #define hdspm_decode_in(x) (((x)>>14)&0x3) 417 418 /* --- control2 register bits --- */ 419 #define HDSPM_TMS (1<<0) 420 #define HDSPM_TCK (1<<1) 421 #define HDSPM_TDI (1<<2) 422 #define HDSPM_JTAG (1<<3) 423 #define HDSPM_PWDN (1<<4) 424 #define HDSPM_PROGRAM (1<<5) 425 #define HDSPM_CONFIG_MODE_0 (1<<6) 426 #define HDSPM_CONFIG_MODE_1 (1<<7) 427 /*#define HDSPM_VERSION_BIT (1<<8) not defined any more*/ 428 #define HDSPM_BIGENDIAN_MODE (1<<9) 429 #define HDSPM_RD_MULTIPLE (1<<10) 430 431 /* --- Status Register bits --- */ /* MADI ONLY */ /* Bits defined here and 432 that do not conflict with specific bits for AES32 seem to be valid also 433 for the AES32 434 */ 435 #define HDSPM_audioIRQPending (1<<0) /* IRQ is high and pending */ 436 #define HDSPM_RX_64ch (1<<1) /* Input 64chan. MODE=1, 56chn MODE=0 */ 437 #define HDSPM_AB_int (1<<2) /* InputChannel Opt=0, Coax=1 438 * (like inp0) 439 */ 440 441 #define HDSPM_madiLock (1<<3) /* MADI Locked =1, no=0 */ 442 #define HDSPM_madiSync (1<<18) /* MADI is in sync */ 443 444 #define HDSPM_tcoLockMadi 0x00000020 /* Optional TCO locked status for HDSPe MADI*/ 445 #define HDSPM_tcoSync 0x10000000 /* Optional TCO sync status for HDSPe MADI and AES32!*/ 446 447 #define HDSPM_syncInLock 0x00010000 /* Sync In lock status for HDSPe MADI! */ 448 #define HDSPM_syncInSync 0x00020000 /* Sync In sync status for HDSPe MADI! */ 449 450 #define HDSPM_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */ 451 /* since 64byte accurate, last 6 bits are not used */ 452 453 454 455 #define HDSPM_DoubleSpeedStatus (1<<19) /* (input) card in double speed */ 456 457 #define HDSPM_madiFreq0 (1<<22) /* system freq 0=error */ 458 #define HDSPM_madiFreq1 (1<<23) /* 1=32, 2=44.1 3=48 */ 459 #define HDSPM_madiFreq2 (1<<24) /* 4=64, 5=88.2 6=96 */ 460 #define HDSPM_madiFreq3 (1<<25) /* 7=128, 8=176.4 9=192 */ 461 462 #define HDSPM_BufferID (1<<26) /* (Double)Buffer ID toggles with 463 * Interrupt 464 */ 465 #define HDSPM_tco_detect 0x08000000 466 #define HDSPM_tcoLockAes 0x20000000 /* Optional TCO locked status for HDSPe AES */ 467 468 #define HDSPM_s2_tco_detect 0x00000040 469 #define HDSPM_s2_AEBO_D 0x00000080 470 #define HDSPM_s2_AEBI_D 0x00000100 471 472 473 #define HDSPM_midi0IRQPending 0x40000000 474 #define HDSPM_midi1IRQPending 0x80000000 475 #define HDSPM_midi2IRQPending 0x20000000 476 #define HDSPM_midi2IRQPendingAES 0x00000020 477 #define HDSPM_midi3IRQPending 0x00200000 478 479 /* --- status bit helpers */ 480 #define HDSPM_madiFreqMask (HDSPM_madiFreq0|HDSPM_madiFreq1|\ 481 HDSPM_madiFreq2|HDSPM_madiFreq3) 482 #define HDSPM_madiFreq32 (HDSPM_madiFreq0) 483 #define HDSPM_madiFreq44_1 (HDSPM_madiFreq1) 484 #define HDSPM_madiFreq48 (HDSPM_madiFreq0|HDSPM_madiFreq1) 485 #define HDSPM_madiFreq64 (HDSPM_madiFreq2) 486 #define HDSPM_madiFreq88_2 (HDSPM_madiFreq0|HDSPM_madiFreq2) 487 #define HDSPM_madiFreq96 (HDSPM_madiFreq1|HDSPM_madiFreq2) 488 #define HDSPM_madiFreq128 (HDSPM_madiFreq0|HDSPM_madiFreq1|HDSPM_madiFreq2) 489 #define HDSPM_madiFreq176_4 (HDSPM_madiFreq3) 490 #define HDSPM_madiFreq192 (HDSPM_madiFreq3|HDSPM_madiFreq0) 491 492 /* Status2 Register bits */ /* MADI ONLY */ 493 494 #define HDSPM_version0 (1<<0) /* not really defined but I guess */ 495 #define HDSPM_version1 (1<<1) /* in former cards it was ??? */ 496 #define HDSPM_version2 (1<<2) 497 498 #define HDSPM_wcLock (1<<3) /* Wordclock is detected and locked */ 499 #define HDSPM_wcSync (1<<4) /* Wordclock is in sync with systemclock */ 500 501 #define HDSPM_wc_freq0 (1<<5) /* input freq detected via autosync */ 502 #define HDSPM_wc_freq1 (1<<6) /* 001=32, 010==44.1, 011=48, */ 503 #define HDSPM_wc_freq2 (1<<7) /* 100=64, 101=88.2, 110=96, 111=128 */ 504 #define HDSPM_wc_freq3 0x800 /* 1000=176.4, 1001=192 */ 505 506 #define HDSPM_SyncRef0 0x10000 /* Sync Reference */ 507 #define HDSPM_SyncRef1 0x20000 508 509 #define HDSPM_SelSyncRef0 (1<<8) /* AutoSync Source */ 510 #define HDSPM_SelSyncRef1 (1<<9) /* 000=word, 001=MADI, */ 511 #define HDSPM_SelSyncRef2 (1<<10) /* 111=no valid signal */ 512 513 #define HDSPM_wc_valid (HDSPM_wcLock|HDSPM_wcSync) 514 515 #define HDSPM_wcFreqMask (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2|\ 516 HDSPM_wc_freq3) 517 #define HDSPM_wcFreq32 (HDSPM_wc_freq0) 518 #define HDSPM_wcFreq44_1 (HDSPM_wc_freq1) 519 #define HDSPM_wcFreq48 (HDSPM_wc_freq0|HDSPM_wc_freq1) 520 #define HDSPM_wcFreq64 (HDSPM_wc_freq2) 521 #define HDSPM_wcFreq88_2 (HDSPM_wc_freq0|HDSPM_wc_freq2) 522 #define HDSPM_wcFreq96 (HDSPM_wc_freq1|HDSPM_wc_freq2) 523 #define HDSPM_wcFreq128 (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2) 524 #define HDSPM_wcFreq176_4 (HDSPM_wc_freq3) 525 #define HDSPM_wcFreq192 (HDSPM_wc_freq0|HDSPM_wc_freq3) 526 527 #define HDSPM_status1_F_0 0x0400000 528 #define HDSPM_status1_F_1 0x0800000 529 #define HDSPM_status1_F_2 0x1000000 530 #define HDSPM_status1_F_3 0x2000000 531 #define HDSPM_status1_freqMask (HDSPM_status1_F_0|HDSPM_status1_F_1|HDSPM_status1_F_2|HDSPM_status1_F_3) 532 533 534 #define HDSPM_SelSyncRefMask (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\ 535 HDSPM_SelSyncRef2) 536 #define HDSPM_SelSyncRef_WORD 0 537 #define HDSPM_SelSyncRef_MADI (HDSPM_SelSyncRef0) 538 #define HDSPM_SelSyncRef_TCO (HDSPM_SelSyncRef1) 539 #define HDSPM_SelSyncRef_SyncIn (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1) 540 #define HDSPM_SelSyncRef_NVALID (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\ 541 HDSPM_SelSyncRef2) 542 543 /* 544 For AES32, bits for status, status2 and timecode are different 545 */ 546 /* status */ 547 #define HDSPM_AES32_wcLock 0x0200000 548 #define HDSPM_AES32_wcSync 0x0100000 549 #define HDSPM_AES32_wcFreq_bit 22 550 /* (status >> HDSPM_AES32_wcFreq_bit) & 0xF gives WC frequency (cf function 551 HDSPM_bit2freq */ 552 #define HDSPM_AES32_syncref_bit 16 553 /* (status >> HDSPM_AES32_syncref_bit) & 0xF gives sync source */ 554 555 #define HDSPM_AES32_AUTOSYNC_FROM_WORD 0 556 #define HDSPM_AES32_AUTOSYNC_FROM_AES1 1 557 #define HDSPM_AES32_AUTOSYNC_FROM_AES2 2 558 #define HDSPM_AES32_AUTOSYNC_FROM_AES3 3 559 #define HDSPM_AES32_AUTOSYNC_FROM_AES4 4 560 #define HDSPM_AES32_AUTOSYNC_FROM_AES5 5 561 #define HDSPM_AES32_AUTOSYNC_FROM_AES6 6 562 #define HDSPM_AES32_AUTOSYNC_FROM_AES7 7 563 #define HDSPM_AES32_AUTOSYNC_FROM_AES8 8 564 #define HDSPM_AES32_AUTOSYNC_FROM_TCO 9 565 #define HDSPM_AES32_AUTOSYNC_FROM_SYNC_IN 10 566 #define HDSPM_AES32_AUTOSYNC_FROM_NONE 11 567 568 /* status2 */ 569 /* HDSPM_LockAES_bit is given by HDSPM_LockAES >> (AES# - 1) */ 570 #define HDSPM_LockAES 0x80 571 #define HDSPM_LockAES1 0x80 572 #define HDSPM_LockAES2 0x40 573 #define HDSPM_LockAES3 0x20 574 #define HDSPM_LockAES4 0x10 575 #define HDSPM_LockAES5 0x8 576 #define HDSPM_LockAES6 0x4 577 #define HDSPM_LockAES7 0x2 578 #define HDSPM_LockAES8 0x1 579 /* 580 Timecode 581 After windows driver sources, bits 4*i to 4*i+3 give the input frequency on 582 AES i+1 583 bits 3210 584 0001 32kHz 585 0010 44.1kHz 586 0011 48kHz 587 0100 64kHz 588 0101 88.2kHz 589 0110 96kHz 590 0111 128kHz 591 1000 176.4kHz 592 1001 192kHz 593 NB: Timecode register doesn't seem to work on AES32 card revision 230 594 */ 595 596 /* Mixer Values */ 597 #define UNITY_GAIN 32768 /* = 65536/2 */ 598 #define MINUS_INFINITY_GAIN 0 599 600 /* Number of channels for different Speed Modes */ 601 #define MADI_SS_CHANNELS 64 602 #define MADI_DS_CHANNELS 32 603 #define MADI_QS_CHANNELS 16 604 605 #define RAYDAT_SS_CHANNELS 36 606 #define RAYDAT_DS_CHANNELS 20 607 #define RAYDAT_QS_CHANNELS 12 608 609 #define AIO_IN_SS_CHANNELS 14 610 #define AIO_IN_DS_CHANNELS 10 611 #define AIO_IN_QS_CHANNELS 8 612 #define AIO_OUT_SS_CHANNELS 16 613 #define AIO_OUT_DS_CHANNELS 12 614 #define AIO_OUT_QS_CHANNELS 10 615 616 #define AES32_CHANNELS 16 617 618 /* the size of a substream (1 mono data stream) */ 619 #define HDSPM_CHANNEL_BUFFER_SAMPLES (16*1024) 620 #define HDSPM_CHANNEL_BUFFER_BYTES (4*HDSPM_CHANNEL_BUFFER_SAMPLES) 621 622 /* the size of the area we need to allocate for DMA transfers. the 623 size is the same regardless of the number of channels, and 624 also the latency to use. 625 for one direction !!! 626 */ 627 #define HDSPM_DMA_AREA_BYTES (HDSPM_MAX_CHANNELS * HDSPM_CHANNEL_BUFFER_BYTES) 628 #define HDSPM_DMA_AREA_KILOBYTES (HDSPM_DMA_AREA_BYTES/1024) 629 630 #define HDSPM_RAYDAT_REV 211 631 #define HDSPM_AIO_REV 212 632 #define HDSPM_MADIFACE_REV 213 633 634 /* speed factor modes */ 635 #define HDSPM_SPEED_SINGLE 0 636 #define HDSPM_SPEED_DOUBLE 1 637 #define HDSPM_SPEED_QUAD 2 638 639 /* names for speed modes */ 640 static char *hdspm_speed_names[] = { "single", "double", "quad" }; 641 642 static const char *const texts_autosync_aes_tco[] = { "Word Clock", 643 "AES1", "AES2", "AES3", "AES4", 644 "AES5", "AES6", "AES7", "AES8", 645 "TCO", "Sync In" 646 }; 647 static const char *const texts_autosync_aes[] = { "Word Clock", 648 "AES1", "AES2", "AES3", "AES4", 649 "AES5", "AES6", "AES7", "AES8", 650 "Sync In" 651 }; 652 static const char *const texts_autosync_madi_tco[] = { "Word Clock", 653 "MADI", "TCO", "Sync In" }; 654 static const char *const texts_autosync_madi[] = { "Word Clock", 655 "MADI", "Sync In" }; 656 657 static const char *const texts_autosync_raydat_tco[] = { 658 "Word Clock", 659 "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4", 660 "AES", "SPDIF", "TCO", "Sync In" 661 }; 662 static const char *const texts_autosync_raydat[] = { 663 "Word Clock", 664 "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4", 665 "AES", "SPDIF", "Sync In" 666 }; 667 static const char *const texts_autosync_aio_tco[] = { 668 "Word Clock", 669 "ADAT", "AES", "SPDIF", "TCO", "Sync In" 670 }; 671 static const char *const texts_autosync_aio[] = { "Word Clock", 672 "ADAT", "AES", "SPDIF", "Sync In" }; 673 674 static const char *const texts_freq[] = { 675 "No Lock", 676 "32 kHz", 677 "44.1 kHz", 678 "48 kHz", 679 "64 kHz", 680 "88.2 kHz", 681 "96 kHz", 682 "128 kHz", 683 "176.4 kHz", 684 "192 kHz" 685 }; 686 687 static char *texts_ports_madi[] = { 688 "MADI.1", "MADI.2", "MADI.3", "MADI.4", "MADI.5", "MADI.6", 689 "MADI.7", "MADI.8", "MADI.9", "MADI.10", "MADI.11", "MADI.12", 690 "MADI.13", "MADI.14", "MADI.15", "MADI.16", "MADI.17", "MADI.18", 691 "MADI.19", "MADI.20", "MADI.21", "MADI.22", "MADI.23", "MADI.24", 692 "MADI.25", "MADI.26", "MADI.27", "MADI.28", "MADI.29", "MADI.30", 693 "MADI.31", "MADI.32", "MADI.33", "MADI.34", "MADI.35", "MADI.36", 694 "MADI.37", "MADI.38", "MADI.39", "MADI.40", "MADI.41", "MADI.42", 695 "MADI.43", "MADI.44", "MADI.45", "MADI.46", "MADI.47", "MADI.48", 696 "MADI.49", "MADI.50", "MADI.51", "MADI.52", "MADI.53", "MADI.54", 697 "MADI.55", "MADI.56", "MADI.57", "MADI.58", "MADI.59", "MADI.60", 698 "MADI.61", "MADI.62", "MADI.63", "MADI.64", 699 }; 700 701 702 static char *texts_ports_raydat_ss[] = { 703 "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", "ADAT1.5", "ADAT1.6", 704 "ADAT1.7", "ADAT1.8", "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4", 705 "ADAT2.5", "ADAT2.6", "ADAT2.7", "ADAT2.8", "ADAT3.1", "ADAT3.2", 706 "ADAT3.3", "ADAT3.4", "ADAT3.5", "ADAT3.6", "ADAT3.7", "ADAT3.8", 707 "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", "ADAT4.5", "ADAT4.6", 708 "ADAT4.7", "ADAT4.8", 709 "AES.L", "AES.R", 710 "SPDIF.L", "SPDIF.R" 711 }; 712 713 static char *texts_ports_raydat_ds[] = { 714 "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", 715 "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4", 716 "ADAT3.1", "ADAT3.2", "ADAT3.3", "ADAT3.4", 717 "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", 718 "AES.L", "AES.R", 719 "SPDIF.L", "SPDIF.R" 720 }; 721 722 static char *texts_ports_raydat_qs[] = { 723 "ADAT1.1", "ADAT1.2", 724 "ADAT2.1", "ADAT2.2", 725 "ADAT3.1", "ADAT3.2", 726 "ADAT4.1", "ADAT4.2", 727 "AES.L", "AES.R", 728 "SPDIF.L", "SPDIF.R" 729 }; 730 731 732 static char *texts_ports_aio_in_ss[] = { 733 "Analogue.L", "Analogue.R", 734 "AES.L", "AES.R", 735 "SPDIF.L", "SPDIF.R", 736 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6", 737 "ADAT.7", "ADAT.8", 738 "AEB.1", "AEB.2", "AEB.3", "AEB.4" 739 }; 740 741 static char *texts_ports_aio_out_ss[] = { 742 "Analogue.L", "Analogue.R", 743 "AES.L", "AES.R", 744 "SPDIF.L", "SPDIF.R", 745 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6", 746 "ADAT.7", "ADAT.8", 747 "Phone.L", "Phone.R", 748 "AEB.1", "AEB.2", "AEB.3", "AEB.4" 749 }; 750 751 static char *texts_ports_aio_in_ds[] = { 752 "Analogue.L", "Analogue.R", 753 "AES.L", "AES.R", 754 "SPDIF.L", "SPDIF.R", 755 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", 756 "AEB.1", "AEB.2", "AEB.3", "AEB.4" 757 }; 758 759 static char *texts_ports_aio_out_ds[] = { 760 "Analogue.L", "Analogue.R", 761 "AES.L", "AES.R", 762 "SPDIF.L", "SPDIF.R", 763 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", 764 "Phone.L", "Phone.R", 765 "AEB.1", "AEB.2", "AEB.3", "AEB.4" 766 }; 767 768 static char *texts_ports_aio_in_qs[] = { 769 "Analogue.L", "Analogue.R", 770 "AES.L", "AES.R", 771 "SPDIF.L", "SPDIF.R", 772 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", 773 "AEB.1", "AEB.2", "AEB.3", "AEB.4" 774 }; 775 776 static char *texts_ports_aio_out_qs[] = { 777 "Analogue.L", "Analogue.R", 778 "AES.L", "AES.R", 779 "SPDIF.L", "SPDIF.R", 780 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", 781 "Phone.L", "Phone.R", 782 "AEB.1", "AEB.2", "AEB.3", "AEB.4" 783 }; 784 785 static char *texts_ports_aes32[] = { 786 "AES.1", "AES.2", "AES.3", "AES.4", "AES.5", "AES.6", "AES.7", 787 "AES.8", "AES.9.", "AES.10", "AES.11", "AES.12", "AES.13", "AES.14", 788 "AES.15", "AES.16" 789 }; 790 791 /* These tables map the ALSA channels 1..N to the channels that we 792 need to use in order to find the relevant channel buffer. RME 793 refers to this kind of mapping as between "the ADAT channel and 794 the DMA channel." We index it using the logical audio channel, 795 and the value is the DMA channel (i.e. channel buffer number) 796 where the data for that channel can be read/written from/to. 797 */ 798 799 static char channel_map_unity_ss[HDSPM_MAX_CHANNELS] = { 800 0, 1, 2, 3, 4, 5, 6, 7, 801 8, 9, 10, 11, 12, 13, 14, 15, 802 16, 17, 18, 19, 20, 21, 22, 23, 803 24, 25, 26, 27, 28, 29, 30, 31, 804 32, 33, 34, 35, 36, 37, 38, 39, 805 40, 41, 42, 43, 44, 45, 46, 47, 806 48, 49, 50, 51, 52, 53, 54, 55, 807 56, 57, 58, 59, 60, 61, 62, 63 808 }; 809 810 static char channel_map_raydat_ss[HDSPM_MAX_CHANNELS] = { 811 4, 5, 6, 7, 8, 9, 10, 11, /* ADAT 1 */ 812 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT 2 */ 813 20, 21, 22, 23, 24, 25, 26, 27, /* ADAT 3 */ 814 28, 29, 30, 31, 32, 33, 34, 35, /* ADAT 4 */ 815 0, 1, /* AES */ 816 2, 3, /* SPDIF */ 817 -1, -1, -1, -1, 818 -1, -1, -1, -1, -1, -1, -1, -1, 819 -1, -1, -1, -1, -1, -1, -1, -1, 820 -1, -1, -1, -1, -1, -1, -1, -1, 821 }; 822 823 static char channel_map_raydat_ds[HDSPM_MAX_CHANNELS] = { 824 4, 5, 6, 7, /* ADAT 1 */ 825 8, 9, 10, 11, /* ADAT 2 */ 826 12, 13, 14, 15, /* ADAT 3 */ 827 16, 17, 18, 19, /* ADAT 4 */ 828 0, 1, /* AES */ 829 2, 3, /* SPDIF */ 830 -1, -1, -1, -1, 831 -1, -1, -1, -1, -1, -1, -1, -1, 832 -1, -1, -1, -1, -1, -1, -1, -1, 833 -1, -1, -1, -1, -1, -1, -1, -1, 834 -1, -1, -1, -1, -1, -1, -1, -1, 835 -1, -1, -1, -1, -1, -1, -1, -1, 836 }; 837 838 static char channel_map_raydat_qs[HDSPM_MAX_CHANNELS] = { 839 4, 5, /* ADAT 1 */ 840 6, 7, /* ADAT 2 */ 841 8, 9, /* ADAT 3 */ 842 10, 11, /* ADAT 4 */ 843 0, 1, /* AES */ 844 2, 3, /* SPDIF */ 845 -1, -1, -1, -1, 846 -1, -1, -1, -1, -1, -1, -1, -1, 847 -1, -1, -1, -1, -1, -1, -1, -1, 848 -1, -1, -1, -1, -1, -1, -1, -1, 849 -1, -1, -1, -1, -1, -1, -1, -1, 850 -1, -1, -1, -1, -1, -1, -1, -1, 851 -1, -1, -1, -1, -1, -1, -1, -1, 852 }; 853 854 static char channel_map_aio_in_ss[HDSPM_MAX_CHANNELS] = { 855 0, 1, /* line in */ 856 8, 9, /* aes in, */ 857 10, 11, /* spdif in */ 858 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT in */ 859 2, 3, 4, 5, /* AEB */ 860 -1, -1, -1, -1, -1, -1, 861 -1, -1, -1, -1, -1, -1, -1, -1, 862 -1, -1, -1, -1, -1, -1, -1, -1, 863 -1, -1, -1, -1, -1, -1, -1, -1, 864 -1, -1, -1, -1, -1, -1, -1, -1, 865 -1, -1, -1, -1, -1, -1, -1, -1, 866 }; 867 868 static char channel_map_aio_out_ss[HDSPM_MAX_CHANNELS] = { 869 0, 1, /* line out */ 870 8, 9, /* aes out */ 871 10, 11, /* spdif out */ 872 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT out */ 873 6, 7, /* phone out */ 874 2, 3, 4, 5, /* AEB */ 875 -1, -1, -1, -1, 876 -1, -1, -1, -1, -1, -1, -1, -1, 877 -1, -1, -1, -1, -1, -1, -1, -1, 878 -1, -1, -1, -1, -1, -1, -1, -1, 879 -1, -1, -1, -1, -1, -1, -1, -1, 880 -1, -1, -1, -1, -1, -1, -1, -1, 881 }; 882 883 static char channel_map_aio_in_ds[HDSPM_MAX_CHANNELS] = { 884 0, 1, /* line in */ 885 8, 9, /* aes in */ 886 10, 11, /* spdif in */ 887 12, 14, 16, 18, /* adat in */ 888 2, 3, 4, 5, /* AEB */ 889 -1, -1, 890 -1, -1, -1, -1, -1, -1, -1, -1, 891 -1, -1, -1, -1, -1, -1, -1, -1, 892 -1, -1, -1, -1, -1, -1, -1, -1, 893 -1, -1, -1, -1, -1, -1, -1, -1, 894 -1, -1, -1, -1, -1, -1, -1, -1, 895 -1, -1, -1, -1, -1, -1, -1, -1 896 }; 897 898 static char channel_map_aio_out_ds[HDSPM_MAX_CHANNELS] = { 899 0, 1, /* line out */ 900 8, 9, /* aes out */ 901 10, 11, /* spdif out */ 902 12, 14, 16, 18, /* adat out */ 903 6, 7, /* phone out */ 904 2, 3, 4, 5, /* AEB */ 905 -1, -1, -1, -1, -1, -1, -1, -1, 906 -1, -1, -1, -1, -1, -1, -1, -1, 907 -1, -1, -1, -1, -1, -1, -1, -1, 908 -1, -1, -1, -1, -1, -1, -1, -1, 909 -1, -1, -1, -1, -1, -1, -1, -1, 910 -1, -1, -1, -1, -1, -1, -1, -1 911 }; 912 913 static char channel_map_aio_in_qs[HDSPM_MAX_CHANNELS] = { 914 0, 1, /* line in */ 915 8, 9, /* aes in */ 916 10, 11, /* spdif in */ 917 12, 16, /* adat in */ 918 2, 3, 4, 5, /* AEB */ 919 -1, -1, -1, -1, 920 -1, -1, -1, -1, -1, -1, -1, -1, 921 -1, -1, -1, -1, -1, -1, -1, -1, 922 -1, -1, -1, -1, -1, -1, -1, -1, 923 -1, -1, -1, -1, -1, -1, -1, -1, 924 -1, -1, -1, -1, -1, -1, -1, -1, 925 -1, -1, -1, -1, -1, -1, -1, -1 926 }; 927 928 static char channel_map_aio_out_qs[HDSPM_MAX_CHANNELS] = { 929 0, 1, /* line out */ 930 8, 9, /* aes out */ 931 10, 11, /* spdif out */ 932 12, 16, /* adat out */ 933 6, 7, /* phone out */ 934 2, 3, 4, 5, /* AEB */ 935 -1, -1, 936 -1, -1, -1, -1, -1, -1, -1, -1, 937 -1, -1, -1, -1, -1, -1, -1, -1, 938 -1, -1, -1, -1, -1, -1, -1, -1, 939 -1, -1, -1, -1, -1, -1, -1, -1, 940 -1, -1, -1, -1, -1, -1, -1, -1, 941 -1, -1, -1, -1, -1, -1, -1, -1 942 }; 943 944 static char channel_map_aes32[HDSPM_MAX_CHANNELS] = { 945 0, 1, 2, 3, 4, 5, 6, 7, 946 8, 9, 10, 11, 12, 13, 14, 15, 947 -1, -1, -1, -1, -1, -1, -1, -1, 948 -1, -1, -1, -1, -1, -1, -1, -1, 949 -1, -1, -1, -1, -1, -1, -1, -1, 950 -1, -1, -1, -1, -1, -1, -1, -1, 951 -1, -1, -1, -1, -1, -1, -1, -1, 952 -1, -1, -1, -1, -1, -1, -1, -1 953 }; 954 955 struct hdspm_midi { 956 struct hdspm *hdspm; 957 int id; 958 struct snd_rawmidi *rmidi; 959 struct snd_rawmidi_substream *input; 960 struct snd_rawmidi_substream *output; 961 char istimer; /* timer in use */ 962 struct timer_list timer; 963 spinlock_t lock; 964 int pending; 965 int dataIn; 966 int statusIn; 967 int dataOut; 968 int statusOut; 969 int ie; 970 int irq; 971 }; 972 973 struct hdspm_tco { 974 int input; /* 0: LTC, 1:Video, 2: WC*/ 975 int framerate; /* 0=24, 1=25, 2=29.97, 3=29.97d, 4=30, 5=30d */ 976 int wordclock; /* 0=1:1, 1=44.1->48, 2=48->44.1 */ 977 int samplerate; /* 0=44.1, 1=48, 2= freq from app */ 978 int pull; /* 0=0, 1=+0.1%, 2=-0.1%, 3=+4%, 4=-4%*/ 979 int term; /* 0 = off, 1 = on */ 980 }; 981 982 struct hdspm { 983 spinlock_t lock; 984 /* only one playback and/or capture stream */ 985 struct snd_pcm_substream *capture_substream; 986 struct snd_pcm_substream *playback_substream; 987 988 char *card_name; /* for procinfo */ 989 unsigned short firmware_rev; /* dont know if relevant (yes if AES32)*/ 990 991 uint8_t io_type; 992 993 int monitor_outs; /* set up monitoring outs init flag */ 994 995 u32 control_register; /* cached value */ 996 u32 control2_register; /* cached value */ 997 u32 settings_register; /* cached value for AIO / RayDat (sync reference, master/slave) */ 998 999 struct hdspm_midi midi[4]; 1000 struct tasklet_struct midi_tasklet; 1001 1002 size_t period_bytes; 1003 unsigned char ss_in_channels; 1004 unsigned char ds_in_channels; 1005 unsigned char qs_in_channels; 1006 unsigned char ss_out_channels; 1007 unsigned char ds_out_channels; 1008 unsigned char qs_out_channels; 1009 1010 unsigned char max_channels_in; 1011 unsigned char max_channels_out; 1012 1013 signed char *channel_map_in; 1014 signed char *channel_map_out; 1015 1016 signed char *channel_map_in_ss, *channel_map_in_ds, *channel_map_in_qs; 1017 signed char *channel_map_out_ss, *channel_map_out_ds, *channel_map_out_qs; 1018 1019 char **port_names_in; 1020 char **port_names_out; 1021 1022 char **port_names_in_ss, **port_names_in_ds, **port_names_in_qs; 1023 char **port_names_out_ss, **port_names_out_ds, **port_names_out_qs; 1024 1025 unsigned char *playback_buffer; /* suitably aligned address */ 1026 unsigned char *capture_buffer; /* suitably aligned address */ 1027 1028 pid_t capture_pid; /* process id which uses capture */ 1029 pid_t playback_pid; /* process id which uses capture */ 1030 int running; /* running status */ 1031 1032 int last_external_sample_rate; /* samplerate mystic ... */ 1033 int last_internal_sample_rate; 1034 int system_sample_rate; 1035 1036 int dev; /* Hardware vars... */ 1037 int irq; 1038 unsigned long port; 1039 void __iomem *iobase; 1040 1041 int irq_count; /* for debug */ 1042 int midiPorts; 1043 1044 struct snd_card *card; /* one card */ 1045 struct snd_pcm *pcm; /* has one pcm */ 1046 struct snd_hwdep *hwdep; /* and a hwdep for additional ioctl */ 1047 struct pci_dev *pci; /* and an pci info */ 1048 1049 /* Mixer vars */ 1050 /* fast alsa mixer */ 1051 struct snd_kcontrol *playback_mixer_ctls[HDSPM_MAX_CHANNELS]; 1052 /* but input to much, so not used */ 1053 struct snd_kcontrol *input_mixer_ctls[HDSPM_MAX_CHANNELS]; 1054 /* full mixer accessible over mixer ioctl or hwdep-device */ 1055 struct hdspm_mixer *mixer; 1056 1057 struct hdspm_tco *tco; /* NULL if no TCO detected */ 1058 1059 const char *const *texts_autosync; 1060 int texts_autosync_items; 1061 1062 cycles_t last_interrupt; 1063 1064 unsigned int serial; 1065 1066 struct hdspm_peak_rms peak_rms; 1067 }; 1068 1069 1070 static const struct pci_device_id snd_hdspm_ids[] = { 1071 { 1072 .vendor = PCI_VENDOR_ID_XILINX, 1073 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI, 1074 .subvendor = PCI_ANY_ID, 1075 .subdevice = PCI_ANY_ID, 1076 .class = 0, 1077 .class_mask = 0, 1078 .driver_data = 0}, 1079 {0,} 1080 }; 1081 1082 MODULE_DEVICE_TABLE(pci, snd_hdspm_ids); 1083 1084 /* prototypes */ 1085 static int snd_hdspm_create_alsa_devices(struct snd_card *card, 1086 struct hdspm *hdspm); 1087 static int snd_hdspm_create_pcm(struct snd_card *card, 1088 struct hdspm *hdspm); 1089 1090 static inline void snd_hdspm_initialize_midi_flush(struct hdspm *hdspm); 1091 static inline int hdspm_get_pll_freq(struct hdspm *hdspm); 1092 static int hdspm_update_simple_mixer_controls(struct hdspm *hdspm); 1093 static int hdspm_autosync_ref(struct hdspm *hdspm); 1094 static int hdspm_set_toggle_setting(struct hdspm *hdspm, u32 regmask, int out); 1095 static int snd_hdspm_set_defaults(struct hdspm *hdspm); 1096 static int hdspm_system_clock_mode(struct hdspm *hdspm); 1097 static void hdspm_set_channel_dma_addr(struct hdspm *hdspm, 1098 struct snd_pcm_substream *substream, 1099 unsigned int reg, int channels); 1100 1101 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx); 1102 static int hdspm_wc_sync_check(struct hdspm *hdspm); 1103 static int hdspm_tco_sync_check(struct hdspm *hdspm); 1104 static int hdspm_sync_in_sync_check(struct hdspm *hdspm); 1105 1106 static int hdspm_get_aes_sample_rate(struct hdspm *hdspm, int index); 1107 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm); 1108 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm); 1109 1110 1111 1112 static inline int HDSPM_bit2freq(int n) 1113 { 1114 static const int bit2freq_tab[] = { 1115 0, 32000, 44100, 48000, 64000, 88200, 1116 96000, 128000, 176400, 192000 }; 1117 if (n < 1 || n > 9) 1118 return 0; 1119 return bit2freq_tab[n]; 1120 } 1121 1122 static bool hdspm_is_raydat_or_aio(struct hdspm *hdspm) 1123 { 1124 return ((AIO == hdspm->io_type) || (RayDAT == hdspm->io_type)); 1125 } 1126 1127 1128 /* Write/read to/from HDSPM with Adresses in Bytes 1129 not words but only 32Bit writes are allowed */ 1130 1131 static inline void hdspm_write(struct hdspm * hdspm, unsigned int reg, 1132 unsigned int val) 1133 { 1134 writel(val, hdspm->iobase + reg); 1135 } 1136 1137 static inline unsigned int hdspm_read(struct hdspm * hdspm, unsigned int reg) 1138 { 1139 return readl(hdspm->iobase + reg); 1140 } 1141 1142 /* for each output channel (chan) I have an Input (in) and Playback (pb) Fader 1143 mixer is write only on hardware so we have to cache him for read 1144 each fader is a u32, but uses only the first 16 bit */ 1145 1146 static inline int hdspm_read_in_gain(struct hdspm * hdspm, unsigned int chan, 1147 unsigned int in) 1148 { 1149 if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS) 1150 return 0; 1151 1152 return hdspm->mixer->ch[chan].in[in]; 1153 } 1154 1155 static inline int hdspm_read_pb_gain(struct hdspm * hdspm, unsigned int chan, 1156 unsigned int pb) 1157 { 1158 if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS) 1159 return 0; 1160 return hdspm->mixer->ch[chan].pb[pb]; 1161 } 1162 1163 static int hdspm_write_in_gain(struct hdspm *hdspm, unsigned int chan, 1164 unsigned int in, unsigned short data) 1165 { 1166 if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS) 1167 return -1; 1168 1169 hdspm_write(hdspm, 1170 HDSPM_MADI_mixerBase + 1171 ((in + 128 * chan) * sizeof(u32)), 1172 (hdspm->mixer->ch[chan].in[in] = data & 0xFFFF)); 1173 return 0; 1174 } 1175 1176 static int hdspm_write_pb_gain(struct hdspm *hdspm, unsigned int chan, 1177 unsigned int pb, unsigned short data) 1178 { 1179 if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS) 1180 return -1; 1181 1182 hdspm_write(hdspm, 1183 HDSPM_MADI_mixerBase + 1184 ((64 + pb + 128 * chan) * sizeof(u32)), 1185 (hdspm->mixer->ch[chan].pb[pb] = data & 0xFFFF)); 1186 return 0; 1187 } 1188 1189 1190 /* enable DMA for specific channels, now available for DSP-MADI */ 1191 static inline void snd_hdspm_enable_in(struct hdspm * hdspm, int i, int v) 1192 { 1193 hdspm_write(hdspm, HDSPM_inputEnableBase + (4 * i), v); 1194 } 1195 1196 static inline void snd_hdspm_enable_out(struct hdspm * hdspm, int i, int v) 1197 { 1198 hdspm_write(hdspm, HDSPM_outputEnableBase + (4 * i), v); 1199 } 1200 1201 /* check if same process is writing and reading */ 1202 static int snd_hdspm_use_is_exclusive(struct hdspm *hdspm) 1203 { 1204 unsigned long flags; 1205 int ret = 1; 1206 1207 spin_lock_irqsave(&hdspm->lock, flags); 1208 if ((hdspm->playback_pid != hdspm->capture_pid) && 1209 (hdspm->playback_pid >= 0) && (hdspm->capture_pid >= 0)) { 1210 ret = 0; 1211 } 1212 spin_unlock_irqrestore(&hdspm->lock, flags); 1213 return ret; 1214 } 1215 1216 /* round arbitary sample rates to commonly known rates */ 1217 static int hdspm_round_frequency(int rate) 1218 { 1219 if (rate < 38050) 1220 return 32000; 1221 if (rate < 46008) 1222 return 44100; 1223 else 1224 return 48000; 1225 } 1226 1227 /* QS and DS rates normally can not be detected 1228 * automatically by the card. Only exception is MADI 1229 * in 96k frame mode. 1230 * 1231 * So if we read SS values (32 .. 48k), check for 1232 * user-provided DS/QS bits in the control register 1233 * and multiply the base frequency accordingly. 1234 */ 1235 static int hdspm_rate_multiplier(struct hdspm *hdspm, int rate) 1236 { 1237 if (rate <= 48000) { 1238 if (hdspm->control_register & HDSPM_QuadSpeed) 1239 return rate * 4; 1240 else if (hdspm->control_register & 1241 HDSPM_DoubleSpeed) 1242 return rate * 2; 1243 } 1244 return rate; 1245 } 1246 1247 /* check for external sample rate, returns the sample rate in Hz*/ 1248 static int hdspm_external_sample_rate(struct hdspm *hdspm) 1249 { 1250 unsigned int status, status2; 1251 int syncref, rate = 0, rate_bits; 1252 1253 switch (hdspm->io_type) { 1254 case AES32: 1255 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 1256 status = hdspm_read(hdspm, HDSPM_statusRegister); 1257 1258 syncref = hdspm_autosync_ref(hdspm); 1259 switch (syncref) { 1260 case HDSPM_AES32_AUTOSYNC_FROM_WORD: 1261 /* Check WC sync and get sample rate */ 1262 if (hdspm_wc_sync_check(hdspm)) 1263 return HDSPM_bit2freq(hdspm_get_wc_sample_rate(hdspm)); 1264 break; 1265 1266 case HDSPM_AES32_AUTOSYNC_FROM_AES1: 1267 case HDSPM_AES32_AUTOSYNC_FROM_AES2: 1268 case HDSPM_AES32_AUTOSYNC_FROM_AES3: 1269 case HDSPM_AES32_AUTOSYNC_FROM_AES4: 1270 case HDSPM_AES32_AUTOSYNC_FROM_AES5: 1271 case HDSPM_AES32_AUTOSYNC_FROM_AES6: 1272 case HDSPM_AES32_AUTOSYNC_FROM_AES7: 1273 case HDSPM_AES32_AUTOSYNC_FROM_AES8: 1274 /* Check AES sync and get sample rate */ 1275 if (hdspm_aes_sync_check(hdspm, syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1)) 1276 return HDSPM_bit2freq(hdspm_get_aes_sample_rate(hdspm, 1277 syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1)); 1278 break; 1279 1280 1281 case HDSPM_AES32_AUTOSYNC_FROM_TCO: 1282 /* Check TCO sync and get sample rate */ 1283 if (hdspm_tco_sync_check(hdspm)) 1284 return HDSPM_bit2freq(hdspm_get_tco_sample_rate(hdspm)); 1285 break; 1286 default: 1287 return 0; 1288 } /* end switch(syncref) */ 1289 break; 1290 1291 case MADIface: 1292 status = hdspm_read(hdspm, HDSPM_statusRegister); 1293 1294 if (!(status & HDSPM_madiLock)) { 1295 rate = 0; /* no lock */ 1296 } else { 1297 switch (status & (HDSPM_status1_freqMask)) { 1298 case HDSPM_status1_F_0*1: 1299 rate = 32000; break; 1300 case HDSPM_status1_F_0*2: 1301 rate = 44100; break; 1302 case HDSPM_status1_F_0*3: 1303 rate = 48000; break; 1304 case HDSPM_status1_F_0*4: 1305 rate = 64000; break; 1306 case HDSPM_status1_F_0*5: 1307 rate = 88200; break; 1308 case HDSPM_status1_F_0*6: 1309 rate = 96000; break; 1310 case HDSPM_status1_F_0*7: 1311 rate = 128000; break; 1312 case HDSPM_status1_F_0*8: 1313 rate = 176400; break; 1314 case HDSPM_status1_F_0*9: 1315 rate = 192000; break; 1316 default: 1317 rate = 0; break; 1318 } 1319 } 1320 1321 break; 1322 1323 case MADI: 1324 case AIO: 1325 case RayDAT: 1326 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 1327 status = hdspm_read(hdspm, HDSPM_statusRegister); 1328 rate = 0; 1329 1330 /* if wordclock has synced freq and wordclock is valid */ 1331 if ((status2 & HDSPM_wcLock) != 0 && 1332 (status2 & HDSPM_SelSyncRef0) == 0) { 1333 1334 rate_bits = status2 & HDSPM_wcFreqMask; 1335 1336 1337 switch (rate_bits) { 1338 case HDSPM_wcFreq32: 1339 rate = 32000; 1340 break; 1341 case HDSPM_wcFreq44_1: 1342 rate = 44100; 1343 break; 1344 case HDSPM_wcFreq48: 1345 rate = 48000; 1346 break; 1347 case HDSPM_wcFreq64: 1348 rate = 64000; 1349 break; 1350 case HDSPM_wcFreq88_2: 1351 rate = 88200; 1352 break; 1353 case HDSPM_wcFreq96: 1354 rate = 96000; 1355 break; 1356 case HDSPM_wcFreq128: 1357 rate = 128000; 1358 break; 1359 case HDSPM_wcFreq176_4: 1360 rate = 176400; 1361 break; 1362 case HDSPM_wcFreq192: 1363 rate = 192000; 1364 break; 1365 default: 1366 rate = 0; 1367 break; 1368 } 1369 } 1370 1371 /* if rate detected and Syncref is Word than have it, 1372 * word has priority to MADI 1373 */ 1374 if (rate != 0 && 1375 (status2 & HDSPM_SelSyncRefMask) == HDSPM_SelSyncRef_WORD) 1376 return hdspm_rate_multiplier(hdspm, rate); 1377 1378 /* maybe a madi input (which is taken if sel sync is madi) */ 1379 if (status & HDSPM_madiLock) { 1380 rate_bits = status & HDSPM_madiFreqMask; 1381 1382 switch (rate_bits) { 1383 case HDSPM_madiFreq32: 1384 rate = 32000; 1385 break; 1386 case HDSPM_madiFreq44_1: 1387 rate = 44100; 1388 break; 1389 case HDSPM_madiFreq48: 1390 rate = 48000; 1391 break; 1392 case HDSPM_madiFreq64: 1393 rate = 64000; 1394 break; 1395 case HDSPM_madiFreq88_2: 1396 rate = 88200; 1397 break; 1398 case HDSPM_madiFreq96: 1399 rate = 96000; 1400 break; 1401 case HDSPM_madiFreq128: 1402 rate = 128000; 1403 break; 1404 case HDSPM_madiFreq176_4: 1405 rate = 176400; 1406 break; 1407 case HDSPM_madiFreq192: 1408 rate = 192000; 1409 break; 1410 default: 1411 rate = 0; 1412 break; 1413 } 1414 1415 } /* endif HDSPM_madiLock */ 1416 1417 /* check sample rate from TCO or SYNC_IN */ 1418 { 1419 bool is_valid_input = 0; 1420 bool has_sync = 0; 1421 1422 syncref = hdspm_autosync_ref(hdspm); 1423 if (HDSPM_AUTOSYNC_FROM_TCO == syncref) { 1424 is_valid_input = 1; 1425 has_sync = (HDSPM_SYNC_CHECK_SYNC == 1426 hdspm_tco_sync_check(hdspm)); 1427 } else if (HDSPM_AUTOSYNC_FROM_SYNC_IN == syncref) { 1428 is_valid_input = 1; 1429 has_sync = (HDSPM_SYNC_CHECK_SYNC == 1430 hdspm_sync_in_sync_check(hdspm)); 1431 } 1432 1433 if (is_valid_input && has_sync) { 1434 rate = hdspm_round_frequency( 1435 hdspm_get_pll_freq(hdspm)); 1436 } 1437 } 1438 1439 rate = hdspm_rate_multiplier(hdspm, rate); 1440 1441 break; 1442 } 1443 1444 return rate; 1445 } 1446 1447 /* return latency in samples per period */ 1448 static int hdspm_get_latency(struct hdspm *hdspm) 1449 { 1450 int n; 1451 1452 n = hdspm_decode_latency(hdspm->control_register); 1453 1454 /* Special case for new RME cards with 32 samples period size. 1455 * The three latency bits in the control register 1456 * (HDSP_LatencyMask) encode latency values of 64 samples as 1457 * 0, 128 samples as 1 ... 4096 samples as 6. For old cards, 7 1458 * denotes 8192 samples, but on new cards like RayDAT or AIO, 1459 * it corresponds to 32 samples. 1460 */ 1461 if ((7 == n) && (RayDAT == hdspm->io_type || AIO == hdspm->io_type)) 1462 n = -1; 1463 1464 return 1 << (n + 6); 1465 } 1466 1467 /* Latency function */ 1468 static inline void hdspm_compute_period_size(struct hdspm *hdspm) 1469 { 1470 hdspm->period_bytes = 4 * hdspm_get_latency(hdspm); 1471 } 1472 1473 1474 static snd_pcm_uframes_t hdspm_hw_pointer(struct hdspm *hdspm) 1475 { 1476 int position; 1477 1478 position = hdspm_read(hdspm, HDSPM_statusRegister); 1479 1480 switch (hdspm->io_type) { 1481 case RayDAT: 1482 case AIO: 1483 position &= HDSPM_BufferPositionMask; 1484 position /= 4; /* Bytes per sample */ 1485 break; 1486 default: 1487 position = (position & HDSPM_BufferID) ? 1488 (hdspm->period_bytes / 4) : 0; 1489 } 1490 1491 return position; 1492 } 1493 1494 1495 static inline void hdspm_start_audio(struct hdspm * s) 1496 { 1497 s->control_register |= (HDSPM_AudioInterruptEnable | HDSPM_Start); 1498 hdspm_write(s, HDSPM_controlRegister, s->control_register); 1499 } 1500 1501 static inline void hdspm_stop_audio(struct hdspm * s) 1502 { 1503 s->control_register &= ~(HDSPM_Start | HDSPM_AudioInterruptEnable); 1504 hdspm_write(s, HDSPM_controlRegister, s->control_register); 1505 } 1506 1507 /* should I silence all or only opened ones ? doit all for first even is 4MB*/ 1508 static void hdspm_silence_playback(struct hdspm *hdspm) 1509 { 1510 int i; 1511 int n = hdspm->period_bytes; 1512 void *buf = hdspm->playback_buffer; 1513 1514 if (!buf) 1515 return; 1516 1517 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) { 1518 memset(buf, 0, n); 1519 buf += HDSPM_CHANNEL_BUFFER_BYTES; 1520 } 1521 } 1522 1523 static int hdspm_set_interrupt_interval(struct hdspm *s, unsigned int frames) 1524 { 1525 int n; 1526 1527 spin_lock_irq(&s->lock); 1528 1529 if (32 == frames) { 1530 /* Special case for new RME cards like RayDAT/AIO which 1531 * support period sizes of 32 samples. Since latency is 1532 * encoded in the three bits of HDSP_LatencyMask, we can only 1533 * have values from 0 .. 7. While 0 still means 64 samples and 1534 * 6 represents 4096 samples on all cards, 7 represents 8192 1535 * on older cards and 32 samples on new cards. 1536 * 1537 * In other words, period size in samples is calculated by 1538 * 2^(n+6) with n ranging from 0 .. 7. 1539 */ 1540 n = 7; 1541 } else { 1542 frames >>= 7; 1543 n = 0; 1544 while (frames) { 1545 n++; 1546 frames >>= 1; 1547 } 1548 } 1549 1550 s->control_register &= ~HDSPM_LatencyMask; 1551 s->control_register |= hdspm_encode_latency(n); 1552 1553 hdspm_write(s, HDSPM_controlRegister, s->control_register); 1554 1555 hdspm_compute_period_size(s); 1556 1557 spin_unlock_irq(&s->lock); 1558 1559 return 0; 1560 } 1561 1562 static u64 hdspm_calc_dds_value(struct hdspm *hdspm, u64 period) 1563 { 1564 u64 freq_const; 1565 1566 if (period == 0) 1567 return 0; 1568 1569 switch (hdspm->io_type) { 1570 case MADI: 1571 case AES32: 1572 freq_const = 110069313433624ULL; 1573 break; 1574 case RayDAT: 1575 case AIO: 1576 freq_const = 104857600000000ULL; 1577 break; 1578 case MADIface: 1579 freq_const = 131072000000000ULL; 1580 break; 1581 default: 1582 snd_BUG(); 1583 return 0; 1584 } 1585 1586 return div_u64(freq_const, period); 1587 } 1588 1589 1590 static void hdspm_set_dds_value(struct hdspm *hdspm, int rate) 1591 { 1592 u64 n; 1593 1594 if (snd_BUG_ON(rate <= 0)) 1595 return; 1596 1597 if (rate >= 112000) 1598 rate /= 4; 1599 else if (rate >= 56000) 1600 rate /= 2; 1601 1602 switch (hdspm->io_type) { 1603 case MADIface: 1604 n = 131072000000000ULL; /* 125 MHz */ 1605 break; 1606 case MADI: 1607 case AES32: 1608 n = 110069313433624ULL; /* 105 MHz */ 1609 break; 1610 case RayDAT: 1611 case AIO: 1612 n = 104857600000000ULL; /* 100 MHz */ 1613 break; 1614 default: 1615 snd_BUG(); 1616 return; 1617 } 1618 1619 n = div_u64(n, rate); 1620 /* n should be less than 2^32 for being written to FREQ register */ 1621 snd_BUG_ON(n >> 32); 1622 hdspm_write(hdspm, HDSPM_freqReg, (u32)n); 1623 } 1624 1625 /* dummy set rate lets see what happens */ 1626 static int hdspm_set_rate(struct hdspm * hdspm, int rate, int called_internally) 1627 { 1628 int current_rate; 1629 int rate_bits; 1630 int not_set = 0; 1631 int current_speed, target_speed; 1632 1633 /* ASSUMPTION: hdspm->lock is either set, or there is no need for 1634 it (e.g. during module initialization). 1635 */ 1636 1637 if (!(hdspm->control_register & HDSPM_ClockModeMaster)) { 1638 1639 /* SLAVE --- */ 1640 if (called_internally) { 1641 1642 /* request from ctl or card initialization 1643 just make a warning an remember setting 1644 for future master mode switching */ 1645 1646 dev_warn(hdspm->card->dev, 1647 "Warning: device is not running as a clock master.\n"); 1648 not_set = 1; 1649 } else { 1650 1651 /* hw_param request while in AutoSync mode */ 1652 int external_freq = 1653 hdspm_external_sample_rate(hdspm); 1654 1655 if (hdspm_autosync_ref(hdspm) == 1656 HDSPM_AUTOSYNC_FROM_NONE) { 1657 1658 dev_warn(hdspm->card->dev, 1659 "Detected no External Sync\n"); 1660 not_set = 1; 1661 1662 } else if (rate != external_freq) { 1663 1664 dev_warn(hdspm->card->dev, 1665 "Warning: No AutoSync source for requested rate\n"); 1666 not_set = 1; 1667 } 1668 } 1669 } 1670 1671 current_rate = hdspm->system_sample_rate; 1672 1673 /* Changing between Singe, Double and Quad speed is not 1674 allowed if any substreams are open. This is because such a change 1675 causes a shift in the location of the DMA buffers and a reduction 1676 in the number of available buffers. 1677 1678 Note that a similar but essentially insoluble problem exists for 1679 externally-driven rate changes. All we can do is to flag rate 1680 changes in the read/write routines. 1681 */ 1682 1683 if (current_rate <= 48000) 1684 current_speed = HDSPM_SPEED_SINGLE; 1685 else if (current_rate <= 96000) 1686 current_speed = HDSPM_SPEED_DOUBLE; 1687 else 1688 current_speed = HDSPM_SPEED_QUAD; 1689 1690 if (rate <= 48000) 1691 target_speed = HDSPM_SPEED_SINGLE; 1692 else if (rate <= 96000) 1693 target_speed = HDSPM_SPEED_DOUBLE; 1694 else 1695 target_speed = HDSPM_SPEED_QUAD; 1696 1697 switch (rate) { 1698 case 32000: 1699 rate_bits = HDSPM_Frequency32KHz; 1700 break; 1701 case 44100: 1702 rate_bits = HDSPM_Frequency44_1KHz; 1703 break; 1704 case 48000: 1705 rate_bits = HDSPM_Frequency48KHz; 1706 break; 1707 case 64000: 1708 rate_bits = HDSPM_Frequency64KHz; 1709 break; 1710 case 88200: 1711 rate_bits = HDSPM_Frequency88_2KHz; 1712 break; 1713 case 96000: 1714 rate_bits = HDSPM_Frequency96KHz; 1715 break; 1716 case 128000: 1717 rate_bits = HDSPM_Frequency128KHz; 1718 break; 1719 case 176400: 1720 rate_bits = HDSPM_Frequency176_4KHz; 1721 break; 1722 case 192000: 1723 rate_bits = HDSPM_Frequency192KHz; 1724 break; 1725 default: 1726 return -EINVAL; 1727 } 1728 1729 if (current_speed != target_speed 1730 && (hdspm->capture_pid >= 0 || hdspm->playback_pid >= 0)) { 1731 dev_err(hdspm->card->dev, 1732 "cannot change from %s speed to %s speed mode (capture PID = %d, playback PID = %d)\n", 1733 hdspm_speed_names[current_speed], 1734 hdspm_speed_names[target_speed], 1735 hdspm->capture_pid, hdspm->playback_pid); 1736 return -EBUSY; 1737 } 1738 1739 hdspm->control_register &= ~HDSPM_FrequencyMask; 1740 hdspm->control_register |= rate_bits; 1741 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 1742 1743 /* For AES32, need to set DDS value in FREQ register 1744 For MADI, also apparently */ 1745 hdspm_set_dds_value(hdspm, rate); 1746 1747 if (AES32 == hdspm->io_type && rate != current_rate) 1748 hdspm_write(hdspm, HDSPM_eeprom_wr, 0); 1749 1750 hdspm->system_sample_rate = rate; 1751 1752 if (rate <= 48000) { 1753 hdspm->channel_map_in = hdspm->channel_map_in_ss; 1754 hdspm->channel_map_out = hdspm->channel_map_out_ss; 1755 hdspm->max_channels_in = hdspm->ss_in_channels; 1756 hdspm->max_channels_out = hdspm->ss_out_channels; 1757 hdspm->port_names_in = hdspm->port_names_in_ss; 1758 hdspm->port_names_out = hdspm->port_names_out_ss; 1759 } else if (rate <= 96000) { 1760 hdspm->channel_map_in = hdspm->channel_map_in_ds; 1761 hdspm->channel_map_out = hdspm->channel_map_out_ds; 1762 hdspm->max_channels_in = hdspm->ds_in_channels; 1763 hdspm->max_channels_out = hdspm->ds_out_channels; 1764 hdspm->port_names_in = hdspm->port_names_in_ds; 1765 hdspm->port_names_out = hdspm->port_names_out_ds; 1766 } else { 1767 hdspm->channel_map_in = hdspm->channel_map_in_qs; 1768 hdspm->channel_map_out = hdspm->channel_map_out_qs; 1769 hdspm->max_channels_in = hdspm->qs_in_channels; 1770 hdspm->max_channels_out = hdspm->qs_out_channels; 1771 hdspm->port_names_in = hdspm->port_names_in_qs; 1772 hdspm->port_names_out = hdspm->port_names_out_qs; 1773 } 1774 1775 if (not_set != 0) 1776 return -1; 1777 1778 return 0; 1779 } 1780 1781 /* mainly for init to 0 on load */ 1782 static void all_in_all_mixer(struct hdspm * hdspm, int sgain) 1783 { 1784 int i, j; 1785 unsigned int gain; 1786 1787 if (sgain > UNITY_GAIN) 1788 gain = UNITY_GAIN; 1789 else if (sgain < 0) 1790 gain = 0; 1791 else 1792 gain = sgain; 1793 1794 for (i = 0; i < HDSPM_MIXER_CHANNELS; i++) 1795 for (j = 0; j < HDSPM_MIXER_CHANNELS; j++) { 1796 hdspm_write_in_gain(hdspm, i, j, gain); 1797 hdspm_write_pb_gain(hdspm, i, j, gain); 1798 } 1799 } 1800 1801 /*---------------------------------------------------------------------------- 1802 MIDI 1803 ----------------------------------------------------------------------------*/ 1804 1805 static inline unsigned char snd_hdspm_midi_read_byte (struct hdspm *hdspm, 1806 int id) 1807 { 1808 /* the hardware already does the relevant bit-mask with 0xff */ 1809 return hdspm_read(hdspm, hdspm->midi[id].dataIn); 1810 } 1811 1812 static inline void snd_hdspm_midi_write_byte (struct hdspm *hdspm, int id, 1813 int val) 1814 { 1815 /* the hardware already does the relevant bit-mask with 0xff */ 1816 return hdspm_write(hdspm, hdspm->midi[id].dataOut, val); 1817 } 1818 1819 static inline int snd_hdspm_midi_input_available (struct hdspm *hdspm, int id) 1820 { 1821 return hdspm_read(hdspm, hdspm->midi[id].statusIn) & 0xFF; 1822 } 1823 1824 static inline int snd_hdspm_midi_output_possible (struct hdspm *hdspm, int id) 1825 { 1826 int fifo_bytes_used; 1827 1828 fifo_bytes_used = hdspm_read(hdspm, hdspm->midi[id].statusOut) & 0xFF; 1829 1830 if (fifo_bytes_used < 128) 1831 return 128 - fifo_bytes_used; 1832 else 1833 return 0; 1834 } 1835 1836 static void snd_hdspm_flush_midi_input(struct hdspm *hdspm, int id) 1837 { 1838 while (snd_hdspm_midi_input_available (hdspm, id)) 1839 snd_hdspm_midi_read_byte (hdspm, id); 1840 } 1841 1842 static int snd_hdspm_midi_output_write (struct hdspm_midi *hmidi) 1843 { 1844 unsigned long flags; 1845 int n_pending; 1846 int to_write; 1847 int i; 1848 unsigned char buf[128]; 1849 1850 /* Output is not interrupt driven */ 1851 1852 spin_lock_irqsave (&hmidi->lock, flags); 1853 if (hmidi->output && 1854 !snd_rawmidi_transmit_empty (hmidi->output)) { 1855 n_pending = snd_hdspm_midi_output_possible (hmidi->hdspm, 1856 hmidi->id); 1857 if (n_pending > 0) { 1858 if (n_pending > (int)sizeof (buf)) 1859 n_pending = sizeof (buf); 1860 1861 to_write = snd_rawmidi_transmit (hmidi->output, buf, 1862 n_pending); 1863 if (to_write > 0) { 1864 for (i = 0; i < to_write; ++i) 1865 snd_hdspm_midi_write_byte (hmidi->hdspm, 1866 hmidi->id, 1867 buf[i]); 1868 } 1869 } 1870 } 1871 spin_unlock_irqrestore (&hmidi->lock, flags); 1872 return 0; 1873 } 1874 1875 static int snd_hdspm_midi_input_read (struct hdspm_midi *hmidi) 1876 { 1877 unsigned char buf[128]; /* this buffer is designed to match the MIDI 1878 * input FIFO size 1879 */ 1880 unsigned long flags; 1881 int n_pending; 1882 int i; 1883 1884 spin_lock_irqsave (&hmidi->lock, flags); 1885 n_pending = snd_hdspm_midi_input_available (hmidi->hdspm, hmidi->id); 1886 if (n_pending > 0) { 1887 if (hmidi->input) { 1888 if (n_pending > (int)sizeof (buf)) 1889 n_pending = sizeof (buf); 1890 for (i = 0; i < n_pending; ++i) 1891 buf[i] = snd_hdspm_midi_read_byte (hmidi->hdspm, 1892 hmidi->id); 1893 if (n_pending) 1894 snd_rawmidi_receive (hmidi->input, buf, 1895 n_pending); 1896 } else { 1897 /* flush the MIDI input FIFO */ 1898 while (n_pending--) 1899 snd_hdspm_midi_read_byte (hmidi->hdspm, 1900 hmidi->id); 1901 } 1902 } 1903 hmidi->pending = 0; 1904 spin_unlock_irqrestore(&hmidi->lock, flags); 1905 1906 spin_lock_irqsave(&hmidi->hdspm->lock, flags); 1907 hmidi->hdspm->control_register |= hmidi->ie; 1908 hdspm_write(hmidi->hdspm, HDSPM_controlRegister, 1909 hmidi->hdspm->control_register); 1910 spin_unlock_irqrestore(&hmidi->hdspm->lock, flags); 1911 1912 return snd_hdspm_midi_output_write (hmidi); 1913 } 1914 1915 static void 1916 snd_hdspm_midi_input_trigger(struct snd_rawmidi_substream *substream, int up) 1917 { 1918 struct hdspm *hdspm; 1919 struct hdspm_midi *hmidi; 1920 unsigned long flags; 1921 1922 hmidi = substream->rmidi->private_data; 1923 hdspm = hmidi->hdspm; 1924 1925 spin_lock_irqsave (&hdspm->lock, flags); 1926 if (up) { 1927 if (!(hdspm->control_register & hmidi->ie)) { 1928 snd_hdspm_flush_midi_input (hdspm, hmidi->id); 1929 hdspm->control_register |= hmidi->ie; 1930 } 1931 } else { 1932 hdspm->control_register &= ~hmidi->ie; 1933 } 1934 1935 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 1936 spin_unlock_irqrestore (&hdspm->lock, flags); 1937 } 1938 1939 static void snd_hdspm_midi_output_timer(struct timer_list *t) 1940 { 1941 struct hdspm_midi *hmidi = from_timer(hmidi, t, timer); 1942 unsigned long flags; 1943 1944 snd_hdspm_midi_output_write(hmidi); 1945 spin_lock_irqsave (&hmidi->lock, flags); 1946 1947 /* this does not bump hmidi->istimer, because the 1948 kernel automatically removed the timer when it 1949 expired, and we are now adding it back, thus 1950 leaving istimer wherever it was set before. 1951 */ 1952 1953 if (hmidi->istimer) 1954 mod_timer(&hmidi->timer, 1 + jiffies); 1955 1956 spin_unlock_irqrestore (&hmidi->lock, flags); 1957 } 1958 1959 static void 1960 snd_hdspm_midi_output_trigger(struct snd_rawmidi_substream *substream, int up) 1961 { 1962 struct hdspm_midi *hmidi; 1963 unsigned long flags; 1964 1965 hmidi = substream->rmidi->private_data; 1966 spin_lock_irqsave (&hmidi->lock, flags); 1967 if (up) { 1968 if (!hmidi->istimer) { 1969 timer_setup(&hmidi->timer, 1970 snd_hdspm_midi_output_timer, 0); 1971 mod_timer(&hmidi->timer, 1 + jiffies); 1972 hmidi->istimer++; 1973 } 1974 } else { 1975 if (hmidi->istimer && --hmidi->istimer <= 0) 1976 del_timer (&hmidi->timer); 1977 } 1978 spin_unlock_irqrestore (&hmidi->lock, flags); 1979 if (up) 1980 snd_hdspm_midi_output_write(hmidi); 1981 } 1982 1983 static int snd_hdspm_midi_input_open(struct snd_rawmidi_substream *substream) 1984 { 1985 struct hdspm_midi *hmidi; 1986 1987 hmidi = substream->rmidi->private_data; 1988 spin_lock_irq (&hmidi->lock); 1989 snd_hdspm_flush_midi_input (hmidi->hdspm, hmidi->id); 1990 hmidi->input = substream; 1991 spin_unlock_irq (&hmidi->lock); 1992 1993 return 0; 1994 } 1995 1996 static int snd_hdspm_midi_output_open(struct snd_rawmidi_substream *substream) 1997 { 1998 struct hdspm_midi *hmidi; 1999 2000 hmidi = substream->rmidi->private_data; 2001 spin_lock_irq (&hmidi->lock); 2002 hmidi->output = substream; 2003 spin_unlock_irq (&hmidi->lock); 2004 2005 return 0; 2006 } 2007 2008 static int snd_hdspm_midi_input_close(struct snd_rawmidi_substream *substream) 2009 { 2010 struct hdspm_midi *hmidi; 2011 2012 snd_hdspm_midi_input_trigger (substream, 0); 2013 2014 hmidi = substream->rmidi->private_data; 2015 spin_lock_irq (&hmidi->lock); 2016 hmidi->input = NULL; 2017 spin_unlock_irq (&hmidi->lock); 2018 2019 return 0; 2020 } 2021 2022 static int snd_hdspm_midi_output_close(struct snd_rawmidi_substream *substream) 2023 { 2024 struct hdspm_midi *hmidi; 2025 2026 snd_hdspm_midi_output_trigger (substream, 0); 2027 2028 hmidi = substream->rmidi->private_data; 2029 spin_lock_irq (&hmidi->lock); 2030 hmidi->output = NULL; 2031 spin_unlock_irq (&hmidi->lock); 2032 2033 return 0; 2034 } 2035 2036 static const struct snd_rawmidi_ops snd_hdspm_midi_output = 2037 { 2038 .open = snd_hdspm_midi_output_open, 2039 .close = snd_hdspm_midi_output_close, 2040 .trigger = snd_hdspm_midi_output_trigger, 2041 }; 2042 2043 static const struct snd_rawmidi_ops snd_hdspm_midi_input = 2044 { 2045 .open = snd_hdspm_midi_input_open, 2046 .close = snd_hdspm_midi_input_close, 2047 .trigger = snd_hdspm_midi_input_trigger, 2048 }; 2049 2050 static int snd_hdspm_create_midi(struct snd_card *card, 2051 struct hdspm *hdspm, int id) 2052 { 2053 int err; 2054 char buf[64]; 2055 2056 hdspm->midi[id].id = id; 2057 hdspm->midi[id].hdspm = hdspm; 2058 spin_lock_init (&hdspm->midi[id].lock); 2059 2060 if (0 == id) { 2061 if (MADIface == hdspm->io_type) { 2062 /* MIDI-over-MADI on HDSPe MADIface */ 2063 hdspm->midi[0].dataIn = HDSPM_midiDataIn2; 2064 hdspm->midi[0].statusIn = HDSPM_midiStatusIn2; 2065 hdspm->midi[0].dataOut = HDSPM_midiDataOut2; 2066 hdspm->midi[0].statusOut = HDSPM_midiStatusOut2; 2067 hdspm->midi[0].ie = HDSPM_Midi2InterruptEnable; 2068 hdspm->midi[0].irq = HDSPM_midi2IRQPending; 2069 } else { 2070 hdspm->midi[0].dataIn = HDSPM_midiDataIn0; 2071 hdspm->midi[0].statusIn = HDSPM_midiStatusIn0; 2072 hdspm->midi[0].dataOut = HDSPM_midiDataOut0; 2073 hdspm->midi[0].statusOut = HDSPM_midiStatusOut0; 2074 hdspm->midi[0].ie = HDSPM_Midi0InterruptEnable; 2075 hdspm->midi[0].irq = HDSPM_midi0IRQPending; 2076 } 2077 } else if (1 == id) { 2078 hdspm->midi[1].dataIn = HDSPM_midiDataIn1; 2079 hdspm->midi[1].statusIn = HDSPM_midiStatusIn1; 2080 hdspm->midi[1].dataOut = HDSPM_midiDataOut1; 2081 hdspm->midi[1].statusOut = HDSPM_midiStatusOut1; 2082 hdspm->midi[1].ie = HDSPM_Midi1InterruptEnable; 2083 hdspm->midi[1].irq = HDSPM_midi1IRQPending; 2084 } else if ((2 == id) && (MADI == hdspm->io_type)) { 2085 /* MIDI-over-MADI on HDSPe MADI */ 2086 hdspm->midi[2].dataIn = HDSPM_midiDataIn2; 2087 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2; 2088 hdspm->midi[2].dataOut = HDSPM_midiDataOut2; 2089 hdspm->midi[2].statusOut = HDSPM_midiStatusOut2; 2090 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable; 2091 hdspm->midi[2].irq = HDSPM_midi2IRQPending; 2092 } else if (2 == id) { 2093 /* TCO MTC, read only */ 2094 hdspm->midi[2].dataIn = HDSPM_midiDataIn2; 2095 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2; 2096 hdspm->midi[2].dataOut = -1; 2097 hdspm->midi[2].statusOut = -1; 2098 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable; 2099 hdspm->midi[2].irq = HDSPM_midi2IRQPendingAES; 2100 } else if (3 == id) { 2101 /* TCO MTC on HDSPe MADI */ 2102 hdspm->midi[3].dataIn = HDSPM_midiDataIn3; 2103 hdspm->midi[3].statusIn = HDSPM_midiStatusIn3; 2104 hdspm->midi[3].dataOut = -1; 2105 hdspm->midi[3].statusOut = -1; 2106 hdspm->midi[3].ie = HDSPM_Midi3InterruptEnable; 2107 hdspm->midi[3].irq = HDSPM_midi3IRQPending; 2108 } 2109 2110 if ((id < 2) || ((2 == id) && ((MADI == hdspm->io_type) || 2111 (MADIface == hdspm->io_type)))) { 2112 if ((id == 0) && (MADIface == hdspm->io_type)) { 2113 snprintf(buf, sizeof(buf), "%s MIDIoverMADI", 2114 card->shortname); 2115 } else if ((id == 2) && (MADI == hdspm->io_type)) { 2116 snprintf(buf, sizeof(buf), "%s MIDIoverMADI", 2117 card->shortname); 2118 } else { 2119 snprintf(buf, sizeof(buf), "%s MIDI %d", 2120 card->shortname, id+1); 2121 } 2122 err = snd_rawmidi_new(card, buf, id, 1, 1, 2123 &hdspm->midi[id].rmidi); 2124 if (err < 0) 2125 return err; 2126 2127 snprintf(hdspm->midi[id].rmidi->name, 2128 sizeof(hdspm->midi[id].rmidi->name), 2129 "%s MIDI %d", card->id, id+1); 2130 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id]; 2131 2132 snd_rawmidi_set_ops(hdspm->midi[id].rmidi, 2133 SNDRV_RAWMIDI_STREAM_OUTPUT, 2134 &snd_hdspm_midi_output); 2135 snd_rawmidi_set_ops(hdspm->midi[id].rmidi, 2136 SNDRV_RAWMIDI_STREAM_INPUT, 2137 &snd_hdspm_midi_input); 2138 2139 hdspm->midi[id].rmidi->info_flags |= 2140 SNDRV_RAWMIDI_INFO_OUTPUT | 2141 SNDRV_RAWMIDI_INFO_INPUT | 2142 SNDRV_RAWMIDI_INFO_DUPLEX; 2143 } else { 2144 /* TCO MTC, read only */ 2145 snprintf(buf, sizeof(buf), "%s MTC %d", 2146 card->shortname, id+1); 2147 err = snd_rawmidi_new(card, buf, id, 1, 1, 2148 &hdspm->midi[id].rmidi); 2149 if (err < 0) 2150 return err; 2151 2152 snprintf(hdspm->midi[id].rmidi->name, 2153 sizeof(hdspm->midi[id].rmidi->name), 2154 "%s MTC %d", card->id, id+1); 2155 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id]; 2156 2157 snd_rawmidi_set_ops(hdspm->midi[id].rmidi, 2158 SNDRV_RAWMIDI_STREAM_INPUT, 2159 &snd_hdspm_midi_input); 2160 2161 hdspm->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_INPUT; 2162 } 2163 2164 return 0; 2165 } 2166 2167 2168 static void hdspm_midi_tasklet(unsigned long arg) 2169 { 2170 struct hdspm *hdspm = (struct hdspm *)arg; 2171 int i = 0; 2172 2173 while (i < hdspm->midiPorts) { 2174 if (hdspm->midi[i].pending) 2175 snd_hdspm_midi_input_read(&hdspm->midi[i]); 2176 2177 i++; 2178 } 2179 } 2180 2181 2182 /*----------------------------------------------------------------------------- 2183 Status Interface 2184 ----------------------------------------------------------------------------*/ 2185 2186 /* get the system sample rate which is set */ 2187 2188 2189 static inline int hdspm_get_pll_freq(struct hdspm *hdspm) 2190 { 2191 unsigned int period, rate; 2192 2193 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ); 2194 rate = hdspm_calc_dds_value(hdspm, period); 2195 2196 return rate; 2197 } 2198 2199 /* 2200 * Calculate the real sample rate from the 2201 * current DDS value. 2202 */ 2203 static int hdspm_get_system_sample_rate(struct hdspm *hdspm) 2204 { 2205 unsigned int rate; 2206 2207 rate = hdspm_get_pll_freq(hdspm); 2208 2209 if (rate > 207000) { 2210 /* Unreasonable high sample rate as seen on PCI MADI cards. */ 2211 if (0 == hdspm_system_clock_mode(hdspm)) { 2212 /* master mode, return internal sample rate */ 2213 rate = hdspm->system_sample_rate; 2214 } else { 2215 /* slave mode, return external sample rate */ 2216 rate = hdspm_external_sample_rate(hdspm); 2217 if (!rate) 2218 rate = hdspm->system_sample_rate; 2219 } 2220 } 2221 2222 return rate; 2223 } 2224 2225 2226 #define HDSPM_SYSTEM_SAMPLE_RATE(xname, xindex) \ 2227 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2228 .name = xname, \ 2229 .index = xindex, \ 2230 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 2231 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2232 .info = snd_hdspm_info_system_sample_rate, \ 2233 .put = snd_hdspm_put_system_sample_rate, \ 2234 .get = snd_hdspm_get_system_sample_rate \ 2235 } 2236 2237 static int snd_hdspm_info_system_sample_rate(struct snd_kcontrol *kcontrol, 2238 struct snd_ctl_elem_info *uinfo) 2239 { 2240 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 2241 uinfo->count = 1; 2242 uinfo->value.integer.min = 27000; 2243 uinfo->value.integer.max = 207000; 2244 uinfo->value.integer.step = 1; 2245 return 0; 2246 } 2247 2248 2249 static int snd_hdspm_get_system_sample_rate(struct snd_kcontrol *kcontrol, 2250 struct snd_ctl_elem_value * 2251 ucontrol) 2252 { 2253 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2254 2255 ucontrol->value.integer.value[0] = hdspm_get_system_sample_rate(hdspm); 2256 return 0; 2257 } 2258 2259 static int snd_hdspm_put_system_sample_rate(struct snd_kcontrol *kcontrol, 2260 struct snd_ctl_elem_value * 2261 ucontrol) 2262 { 2263 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2264 int rate = ucontrol->value.integer.value[0]; 2265 2266 if (rate < 27000 || rate > 207000) 2267 return -EINVAL; 2268 hdspm_set_dds_value(hdspm, ucontrol->value.integer.value[0]); 2269 return 0; 2270 } 2271 2272 2273 /* 2274 * Returns the WordClock sample rate class for the given card. 2275 */ 2276 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm) 2277 { 2278 int status; 2279 2280 switch (hdspm->io_type) { 2281 case RayDAT: 2282 case AIO: 2283 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); 2284 return (status >> 16) & 0xF; 2285 break; 2286 case AES32: 2287 status = hdspm_read(hdspm, HDSPM_statusRegister); 2288 return (status >> HDSPM_AES32_wcFreq_bit) & 0xF; 2289 default: 2290 break; 2291 } 2292 2293 2294 return 0; 2295 } 2296 2297 2298 /* 2299 * Returns the TCO sample rate class for the given card. 2300 */ 2301 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm) 2302 { 2303 int status; 2304 2305 if (hdspm->tco) { 2306 switch (hdspm->io_type) { 2307 case RayDAT: 2308 case AIO: 2309 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); 2310 return (status >> 20) & 0xF; 2311 break; 2312 case AES32: 2313 status = hdspm_read(hdspm, HDSPM_statusRegister); 2314 return (status >> 1) & 0xF; 2315 default: 2316 break; 2317 } 2318 } 2319 2320 return 0; 2321 } 2322 2323 2324 /* 2325 * Returns the SYNC_IN sample rate class for the given card. 2326 */ 2327 static int hdspm_get_sync_in_sample_rate(struct hdspm *hdspm) 2328 { 2329 int status; 2330 2331 if (hdspm->tco) { 2332 switch (hdspm->io_type) { 2333 case RayDAT: 2334 case AIO: 2335 status = hdspm_read(hdspm, HDSPM_RD_STATUS_2); 2336 return (status >> 12) & 0xF; 2337 break; 2338 default: 2339 break; 2340 } 2341 } 2342 2343 return 0; 2344 } 2345 2346 /* 2347 * Returns the AES sample rate class for the given card. 2348 */ 2349 static int hdspm_get_aes_sample_rate(struct hdspm *hdspm, int index) 2350 { 2351 int timecode; 2352 2353 switch (hdspm->io_type) { 2354 case AES32: 2355 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister); 2356 return (timecode >> (4*index)) & 0xF; 2357 break; 2358 default: 2359 break; 2360 } 2361 return 0; 2362 } 2363 2364 /* 2365 * Returns the sample rate class for input source <idx> for 2366 * 'new style' cards like the AIO and RayDAT. 2367 */ 2368 static int hdspm_get_s1_sample_rate(struct hdspm *hdspm, unsigned int idx) 2369 { 2370 int status = hdspm_read(hdspm, HDSPM_RD_STATUS_2); 2371 2372 return (status >> (idx*4)) & 0xF; 2373 } 2374 2375 #define ENUMERATED_CTL_INFO(info, texts) \ 2376 snd_ctl_enum_info(info, 1, ARRAY_SIZE(texts), texts) 2377 2378 2379 /* Helper function to query the external sample rate and return the 2380 * corresponding enum to be returned to userspace. 2381 */ 2382 static int hdspm_external_rate_to_enum(struct hdspm *hdspm) 2383 { 2384 int rate = hdspm_external_sample_rate(hdspm); 2385 int i, selected_rate = 0; 2386 for (i = 1; i < 10; i++) 2387 if (HDSPM_bit2freq(i) == rate) { 2388 selected_rate = i; 2389 break; 2390 } 2391 return selected_rate; 2392 } 2393 2394 2395 #define HDSPM_AUTOSYNC_SAMPLE_RATE(xname, xindex) \ 2396 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2397 .name = xname, \ 2398 .private_value = xindex, \ 2399 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 2400 .info = snd_hdspm_info_autosync_sample_rate, \ 2401 .get = snd_hdspm_get_autosync_sample_rate \ 2402 } 2403 2404 2405 static int snd_hdspm_info_autosync_sample_rate(struct snd_kcontrol *kcontrol, 2406 struct snd_ctl_elem_info *uinfo) 2407 { 2408 ENUMERATED_CTL_INFO(uinfo, texts_freq); 2409 return 0; 2410 } 2411 2412 2413 static int snd_hdspm_get_autosync_sample_rate(struct snd_kcontrol *kcontrol, 2414 struct snd_ctl_elem_value * 2415 ucontrol) 2416 { 2417 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2418 2419 switch (hdspm->io_type) { 2420 case RayDAT: 2421 switch (kcontrol->private_value) { 2422 case 0: 2423 ucontrol->value.enumerated.item[0] = 2424 hdspm_get_wc_sample_rate(hdspm); 2425 break; 2426 case 7: 2427 ucontrol->value.enumerated.item[0] = 2428 hdspm_get_tco_sample_rate(hdspm); 2429 break; 2430 case 8: 2431 ucontrol->value.enumerated.item[0] = 2432 hdspm_get_sync_in_sample_rate(hdspm); 2433 break; 2434 default: 2435 ucontrol->value.enumerated.item[0] = 2436 hdspm_get_s1_sample_rate(hdspm, 2437 kcontrol->private_value-1); 2438 } 2439 break; 2440 2441 case AIO: 2442 switch (kcontrol->private_value) { 2443 case 0: /* WC */ 2444 ucontrol->value.enumerated.item[0] = 2445 hdspm_get_wc_sample_rate(hdspm); 2446 break; 2447 case 4: /* TCO */ 2448 ucontrol->value.enumerated.item[0] = 2449 hdspm_get_tco_sample_rate(hdspm); 2450 break; 2451 case 5: /* SYNC_IN */ 2452 ucontrol->value.enumerated.item[0] = 2453 hdspm_get_sync_in_sample_rate(hdspm); 2454 break; 2455 default: 2456 ucontrol->value.enumerated.item[0] = 2457 hdspm_get_s1_sample_rate(hdspm, 2458 kcontrol->private_value-1); 2459 } 2460 break; 2461 2462 case AES32: 2463 2464 switch (kcontrol->private_value) { 2465 case 0: /* WC */ 2466 ucontrol->value.enumerated.item[0] = 2467 hdspm_get_wc_sample_rate(hdspm); 2468 break; 2469 case 9: /* TCO */ 2470 ucontrol->value.enumerated.item[0] = 2471 hdspm_get_tco_sample_rate(hdspm); 2472 break; 2473 case 10: /* SYNC_IN */ 2474 ucontrol->value.enumerated.item[0] = 2475 hdspm_get_sync_in_sample_rate(hdspm); 2476 break; 2477 case 11: /* External Rate */ 2478 ucontrol->value.enumerated.item[0] = 2479 hdspm_external_rate_to_enum(hdspm); 2480 break; 2481 default: /* AES1 to AES8 */ 2482 ucontrol->value.enumerated.item[0] = 2483 hdspm_get_aes_sample_rate(hdspm, 2484 kcontrol->private_value - 2485 HDSPM_AES32_AUTOSYNC_FROM_AES1); 2486 break; 2487 } 2488 break; 2489 2490 case MADI: 2491 case MADIface: 2492 ucontrol->value.enumerated.item[0] = 2493 hdspm_external_rate_to_enum(hdspm); 2494 break; 2495 default: 2496 break; 2497 } 2498 2499 return 0; 2500 } 2501 2502 2503 #define HDSPM_SYSTEM_CLOCK_MODE(xname, xindex) \ 2504 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2505 .name = xname, \ 2506 .index = xindex, \ 2507 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 2508 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2509 .info = snd_hdspm_info_system_clock_mode, \ 2510 .get = snd_hdspm_get_system_clock_mode, \ 2511 .put = snd_hdspm_put_system_clock_mode, \ 2512 } 2513 2514 2515 /* 2516 * Returns the system clock mode for the given card. 2517 * @returns 0 - master, 1 - slave 2518 */ 2519 static int hdspm_system_clock_mode(struct hdspm *hdspm) 2520 { 2521 switch (hdspm->io_type) { 2522 case AIO: 2523 case RayDAT: 2524 if (hdspm->settings_register & HDSPM_c0Master) 2525 return 0; 2526 break; 2527 2528 default: 2529 if (hdspm->control_register & HDSPM_ClockModeMaster) 2530 return 0; 2531 } 2532 2533 return 1; 2534 } 2535 2536 2537 /* 2538 * Sets the system clock mode. 2539 * @param mode 0 - master, 1 - slave 2540 */ 2541 static void hdspm_set_system_clock_mode(struct hdspm *hdspm, int mode) 2542 { 2543 hdspm_set_toggle_setting(hdspm, 2544 (hdspm_is_raydat_or_aio(hdspm)) ? 2545 HDSPM_c0Master : HDSPM_ClockModeMaster, 2546 (0 == mode)); 2547 } 2548 2549 2550 static int snd_hdspm_info_system_clock_mode(struct snd_kcontrol *kcontrol, 2551 struct snd_ctl_elem_info *uinfo) 2552 { 2553 static const char *const texts[] = { "Master", "AutoSync" }; 2554 ENUMERATED_CTL_INFO(uinfo, texts); 2555 return 0; 2556 } 2557 2558 static int snd_hdspm_get_system_clock_mode(struct snd_kcontrol *kcontrol, 2559 struct snd_ctl_elem_value *ucontrol) 2560 { 2561 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2562 2563 ucontrol->value.enumerated.item[0] = hdspm_system_clock_mode(hdspm); 2564 return 0; 2565 } 2566 2567 static int snd_hdspm_put_system_clock_mode(struct snd_kcontrol *kcontrol, 2568 struct snd_ctl_elem_value *ucontrol) 2569 { 2570 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2571 int val; 2572 2573 if (!snd_hdspm_use_is_exclusive(hdspm)) 2574 return -EBUSY; 2575 2576 val = ucontrol->value.enumerated.item[0]; 2577 if (val < 0) 2578 val = 0; 2579 else if (val > 1) 2580 val = 1; 2581 2582 hdspm_set_system_clock_mode(hdspm, val); 2583 2584 return 0; 2585 } 2586 2587 2588 #define HDSPM_INTERNAL_CLOCK(xname, xindex) \ 2589 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2590 .name = xname, \ 2591 .index = xindex, \ 2592 .info = snd_hdspm_info_clock_source, \ 2593 .get = snd_hdspm_get_clock_source, \ 2594 .put = snd_hdspm_put_clock_source \ 2595 } 2596 2597 2598 static int hdspm_clock_source(struct hdspm * hdspm) 2599 { 2600 switch (hdspm->system_sample_rate) { 2601 case 32000: return 0; 2602 case 44100: return 1; 2603 case 48000: return 2; 2604 case 64000: return 3; 2605 case 88200: return 4; 2606 case 96000: return 5; 2607 case 128000: return 6; 2608 case 176400: return 7; 2609 case 192000: return 8; 2610 } 2611 2612 return -1; 2613 } 2614 2615 static int hdspm_set_clock_source(struct hdspm * hdspm, int mode) 2616 { 2617 int rate; 2618 switch (mode) { 2619 case 0: 2620 rate = 32000; break; 2621 case 1: 2622 rate = 44100; break; 2623 case 2: 2624 rate = 48000; break; 2625 case 3: 2626 rate = 64000; break; 2627 case 4: 2628 rate = 88200; break; 2629 case 5: 2630 rate = 96000; break; 2631 case 6: 2632 rate = 128000; break; 2633 case 7: 2634 rate = 176400; break; 2635 case 8: 2636 rate = 192000; break; 2637 default: 2638 rate = 48000; 2639 } 2640 hdspm_set_rate(hdspm, rate, 1); 2641 return 0; 2642 } 2643 2644 static int snd_hdspm_info_clock_source(struct snd_kcontrol *kcontrol, 2645 struct snd_ctl_elem_info *uinfo) 2646 { 2647 return snd_ctl_enum_info(uinfo, 1, 9, texts_freq + 1); 2648 } 2649 2650 static int snd_hdspm_get_clock_source(struct snd_kcontrol *kcontrol, 2651 struct snd_ctl_elem_value *ucontrol) 2652 { 2653 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2654 2655 ucontrol->value.enumerated.item[0] = hdspm_clock_source(hdspm); 2656 return 0; 2657 } 2658 2659 static int snd_hdspm_put_clock_source(struct snd_kcontrol *kcontrol, 2660 struct snd_ctl_elem_value *ucontrol) 2661 { 2662 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2663 int change; 2664 int val; 2665 2666 if (!snd_hdspm_use_is_exclusive(hdspm)) 2667 return -EBUSY; 2668 val = ucontrol->value.enumerated.item[0]; 2669 if (val < 0) 2670 val = 0; 2671 if (val > 9) 2672 val = 9; 2673 spin_lock_irq(&hdspm->lock); 2674 if (val != hdspm_clock_source(hdspm)) 2675 change = (hdspm_set_clock_source(hdspm, val) == 0) ? 1 : 0; 2676 else 2677 change = 0; 2678 spin_unlock_irq(&hdspm->lock); 2679 return change; 2680 } 2681 2682 2683 #define HDSPM_PREF_SYNC_REF(xname, xindex) \ 2684 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2685 .name = xname, \ 2686 .index = xindex, \ 2687 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 2688 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2689 .info = snd_hdspm_info_pref_sync_ref, \ 2690 .get = snd_hdspm_get_pref_sync_ref, \ 2691 .put = snd_hdspm_put_pref_sync_ref \ 2692 } 2693 2694 2695 /* 2696 * Returns the current preferred sync reference setting. 2697 * The semantics of the return value are depending on the 2698 * card, please see the comments for clarification. 2699 */ 2700 static int hdspm_pref_sync_ref(struct hdspm * hdspm) 2701 { 2702 switch (hdspm->io_type) { 2703 case AES32: 2704 switch (hdspm->control_register & HDSPM_SyncRefMask) { 2705 case 0: return 0; /* WC */ 2706 case HDSPM_SyncRef0: return 1; /* AES 1 */ 2707 case HDSPM_SyncRef1: return 2; /* AES 2 */ 2708 case HDSPM_SyncRef1+HDSPM_SyncRef0: return 3; /* AES 3 */ 2709 case HDSPM_SyncRef2: return 4; /* AES 4 */ 2710 case HDSPM_SyncRef2+HDSPM_SyncRef0: return 5; /* AES 5 */ 2711 case HDSPM_SyncRef2+HDSPM_SyncRef1: return 6; /* AES 6 */ 2712 case HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0: 2713 return 7; /* AES 7 */ 2714 case HDSPM_SyncRef3: return 8; /* AES 8 */ 2715 case HDSPM_SyncRef3+HDSPM_SyncRef0: return 9; /* TCO */ 2716 } 2717 break; 2718 2719 case MADI: 2720 case MADIface: 2721 if (hdspm->tco) { 2722 switch (hdspm->control_register & HDSPM_SyncRefMask) { 2723 case 0: return 0; /* WC */ 2724 case HDSPM_SyncRef0: return 1; /* MADI */ 2725 case HDSPM_SyncRef1: return 2; /* TCO */ 2726 case HDSPM_SyncRef1+HDSPM_SyncRef0: 2727 return 3; /* SYNC_IN */ 2728 } 2729 } else { 2730 switch (hdspm->control_register & HDSPM_SyncRefMask) { 2731 case 0: return 0; /* WC */ 2732 case HDSPM_SyncRef0: return 1; /* MADI */ 2733 case HDSPM_SyncRef1+HDSPM_SyncRef0: 2734 return 2; /* SYNC_IN */ 2735 } 2736 } 2737 break; 2738 2739 case RayDAT: 2740 if (hdspm->tco) { 2741 switch ((hdspm->settings_register & 2742 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { 2743 case 0: return 0; /* WC */ 2744 case 3: return 1; /* ADAT 1 */ 2745 case 4: return 2; /* ADAT 2 */ 2746 case 5: return 3; /* ADAT 3 */ 2747 case 6: return 4; /* ADAT 4 */ 2748 case 1: return 5; /* AES */ 2749 case 2: return 6; /* SPDIF */ 2750 case 9: return 7; /* TCO */ 2751 case 10: return 8; /* SYNC_IN */ 2752 } 2753 } else { 2754 switch ((hdspm->settings_register & 2755 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { 2756 case 0: return 0; /* WC */ 2757 case 3: return 1; /* ADAT 1 */ 2758 case 4: return 2; /* ADAT 2 */ 2759 case 5: return 3; /* ADAT 3 */ 2760 case 6: return 4; /* ADAT 4 */ 2761 case 1: return 5; /* AES */ 2762 case 2: return 6; /* SPDIF */ 2763 case 10: return 7; /* SYNC_IN */ 2764 } 2765 } 2766 2767 break; 2768 2769 case AIO: 2770 if (hdspm->tco) { 2771 switch ((hdspm->settings_register & 2772 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { 2773 case 0: return 0; /* WC */ 2774 case 3: return 1; /* ADAT */ 2775 case 1: return 2; /* AES */ 2776 case 2: return 3; /* SPDIF */ 2777 case 9: return 4; /* TCO */ 2778 case 10: return 5; /* SYNC_IN */ 2779 } 2780 } else { 2781 switch ((hdspm->settings_register & 2782 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { 2783 case 0: return 0; /* WC */ 2784 case 3: return 1; /* ADAT */ 2785 case 1: return 2; /* AES */ 2786 case 2: return 3; /* SPDIF */ 2787 case 10: return 4; /* SYNC_IN */ 2788 } 2789 } 2790 2791 break; 2792 } 2793 2794 return -1; 2795 } 2796 2797 2798 /* 2799 * Set the preferred sync reference to <pref>. The semantics 2800 * of <pref> are depending on the card type, see the comments 2801 * for clarification. 2802 */ 2803 static int hdspm_set_pref_sync_ref(struct hdspm * hdspm, int pref) 2804 { 2805 int p = 0; 2806 2807 switch (hdspm->io_type) { 2808 case AES32: 2809 hdspm->control_register &= ~HDSPM_SyncRefMask; 2810 switch (pref) { 2811 case 0: /* WC */ 2812 break; 2813 case 1: /* AES 1 */ 2814 hdspm->control_register |= HDSPM_SyncRef0; 2815 break; 2816 case 2: /* AES 2 */ 2817 hdspm->control_register |= HDSPM_SyncRef1; 2818 break; 2819 case 3: /* AES 3 */ 2820 hdspm->control_register |= 2821 HDSPM_SyncRef1+HDSPM_SyncRef0; 2822 break; 2823 case 4: /* AES 4 */ 2824 hdspm->control_register |= HDSPM_SyncRef2; 2825 break; 2826 case 5: /* AES 5 */ 2827 hdspm->control_register |= 2828 HDSPM_SyncRef2+HDSPM_SyncRef0; 2829 break; 2830 case 6: /* AES 6 */ 2831 hdspm->control_register |= 2832 HDSPM_SyncRef2+HDSPM_SyncRef1; 2833 break; 2834 case 7: /* AES 7 */ 2835 hdspm->control_register |= 2836 HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0; 2837 break; 2838 case 8: /* AES 8 */ 2839 hdspm->control_register |= HDSPM_SyncRef3; 2840 break; 2841 case 9: /* TCO */ 2842 hdspm->control_register |= 2843 HDSPM_SyncRef3+HDSPM_SyncRef0; 2844 break; 2845 default: 2846 return -1; 2847 } 2848 2849 break; 2850 2851 case MADI: 2852 case MADIface: 2853 hdspm->control_register &= ~HDSPM_SyncRefMask; 2854 if (hdspm->tco) { 2855 switch (pref) { 2856 case 0: /* WC */ 2857 break; 2858 case 1: /* MADI */ 2859 hdspm->control_register |= HDSPM_SyncRef0; 2860 break; 2861 case 2: /* TCO */ 2862 hdspm->control_register |= HDSPM_SyncRef1; 2863 break; 2864 case 3: /* SYNC_IN */ 2865 hdspm->control_register |= 2866 HDSPM_SyncRef0+HDSPM_SyncRef1; 2867 break; 2868 default: 2869 return -1; 2870 } 2871 } else { 2872 switch (pref) { 2873 case 0: /* WC */ 2874 break; 2875 case 1: /* MADI */ 2876 hdspm->control_register |= HDSPM_SyncRef0; 2877 break; 2878 case 2: /* SYNC_IN */ 2879 hdspm->control_register |= 2880 HDSPM_SyncRef0+HDSPM_SyncRef1; 2881 break; 2882 default: 2883 return -1; 2884 } 2885 } 2886 2887 break; 2888 2889 case RayDAT: 2890 if (hdspm->tco) { 2891 switch (pref) { 2892 case 0: p = 0; break; /* WC */ 2893 case 1: p = 3; break; /* ADAT 1 */ 2894 case 2: p = 4; break; /* ADAT 2 */ 2895 case 3: p = 5; break; /* ADAT 3 */ 2896 case 4: p = 6; break; /* ADAT 4 */ 2897 case 5: p = 1; break; /* AES */ 2898 case 6: p = 2; break; /* SPDIF */ 2899 case 7: p = 9; break; /* TCO */ 2900 case 8: p = 10; break; /* SYNC_IN */ 2901 default: return -1; 2902 } 2903 } else { 2904 switch (pref) { 2905 case 0: p = 0; break; /* WC */ 2906 case 1: p = 3; break; /* ADAT 1 */ 2907 case 2: p = 4; break; /* ADAT 2 */ 2908 case 3: p = 5; break; /* ADAT 3 */ 2909 case 4: p = 6; break; /* ADAT 4 */ 2910 case 5: p = 1; break; /* AES */ 2911 case 6: p = 2; break; /* SPDIF */ 2912 case 7: p = 10; break; /* SYNC_IN */ 2913 default: return -1; 2914 } 2915 } 2916 break; 2917 2918 case AIO: 2919 if (hdspm->tco) { 2920 switch (pref) { 2921 case 0: p = 0; break; /* WC */ 2922 case 1: p = 3; break; /* ADAT */ 2923 case 2: p = 1; break; /* AES */ 2924 case 3: p = 2; break; /* SPDIF */ 2925 case 4: p = 9; break; /* TCO */ 2926 case 5: p = 10; break; /* SYNC_IN */ 2927 default: return -1; 2928 } 2929 } else { 2930 switch (pref) { 2931 case 0: p = 0; break; /* WC */ 2932 case 1: p = 3; break; /* ADAT */ 2933 case 2: p = 1; break; /* AES */ 2934 case 3: p = 2; break; /* SPDIF */ 2935 case 4: p = 10; break; /* SYNC_IN */ 2936 default: return -1; 2937 } 2938 } 2939 break; 2940 } 2941 2942 switch (hdspm->io_type) { 2943 case RayDAT: 2944 case AIO: 2945 hdspm->settings_register &= ~HDSPM_c0_SyncRefMask; 2946 hdspm->settings_register |= HDSPM_c0_SyncRef0 * p; 2947 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register); 2948 break; 2949 2950 case MADI: 2951 case MADIface: 2952 case AES32: 2953 hdspm_write(hdspm, HDSPM_controlRegister, 2954 hdspm->control_register); 2955 } 2956 2957 return 0; 2958 } 2959 2960 2961 static int snd_hdspm_info_pref_sync_ref(struct snd_kcontrol *kcontrol, 2962 struct snd_ctl_elem_info *uinfo) 2963 { 2964 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2965 2966 snd_ctl_enum_info(uinfo, 1, hdspm->texts_autosync_items, hdspm->texts_autosync); 2967 2968 return 0; 2969 } 2970 2971 static int snd_hdspm_get_pref_sync_ref(struct snd_kcontrol *kcontrol, 2972 struct snd_ctl_elem_value *ucontrol) 2973 { 2974 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2975 int psf = hdspm_pref_sync_ref(hdspm); 2976 2977 if (psf >= 0) { 2978 ucontrol->value.enumerated.item[0] = psf; 2979 return 0; 2980 } 2981 2982 return -1; 2983 } 2984 2985 static int snd_hdspm_put_pref_sync_ref(struct snd_kcontrol *kcontrol, 2986 struct snd_ctl_elem_value *ucontrol) 2987 { 2988 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2989 int val, change = 0; 2990 2991 if (!snd_hdspm_use_is_exclusive(hdspm)) 2992 return -EBUSY; 2993 2994 val = ucontrol->value.enumerated.item[0]; 2995 2996 if (val < 0) 2997 val = 0; 2998 else if (val >= hdspm->texts_autosync_items) 2999 val = hdspm->texts_autosync_items-1; 3000 3001 spin_lock_irq(&hdspm->lock); 3002 if (val != hdspm_pref_sync_ref(hdspm)) 3003 change = (0 == hdspm_set_pref_sync_ref(hdspm, val)) ? 1 : 0; 3004 3005 spin_unlock_irq(&hdspm->lock); 3006 return change; 3007 } 3008 3009 3010 #define HDSPM_AUTOSYNC_REF(xname, xindex) \ 3011 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3012 .name = xname, \ 3013 .index = xindex, \ 3014 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 3015 .info = snd_hdspm_info_autosync_ref, \ 3016 .get = snd_hdspm_get_autosync_ref, \ 3017 } 3018 3019 static int hdspm_autosync_ref(struct hdspm *hdspm) 3020 { 3021 /* This looks at the autosync selected sync reference */ 3022 if (AES32 == hdspm->io_type) { 3023 3024 unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister); 3025 unsigned int syncref = (status >> HDSPM_AES32_syncref_bit) & 0xF; 3026 if ((syncref >= HDSPM_AES32_AUTOSYNC_FROM_WORD) && 3027 (syncref <= HDSPM_AES32_AUTOSYNC_FROM_SYNC_IN)) { 3028 return syncref; 3029 } 3030 return HDSPM_AES32_AUTOSYNC_FROM_NONE; 3031 3032 } else if (MADI == hdspm->io_type) { 3033 3034 unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 3035 switch (status2 & HDSPM_SelSyncRefMask) { 3036 case HDSPM_SelSyncRef_WORD: 3037 return HDSPM_AUTOSYNC_FROM_WORD; 3038 case HDSPM_SelSyncRef_MADI: 3039 return HDSPM_AUTOSYNC_FROM_MADI; 3040 case HDSPM_SelSyncRef_TCO: 3041 return HDSPM_AUTOSYNC_FROM_TCO; 3042 case HDSPM_SelSyncRef_SyncIn: 3043 return HDSPM_AUTOSYNC_FROM_SYNC_IN; 3044 case HDSPM_SelSyncRef_NVALID: 3045 return HDSPM_AUTOSYNC_FROM_NONE; 3046 default: 3047 return HDSPM_AUTOSYNC_FROM_NONE; 3048 } 3049 3050 } 3051 return 0; 3052 } 3053 3054 3055 static int snd_hdspm_info_autosync_ref(struct snd_kcontrol *kcontrol, 3056 struct snd_ctl_elem_info *uinfo) 3057 { 3058 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3059 3060 if (AES32 == hdspm->io_type) { 3061 static const char *const texts[] = { "WordClock", "AES1", "AES2", "AES3", 3062 "AES4", "AES5", "AES6", "AES7", "AES8", "TCO", "Sync In", "None"}; 3063 3064 ENUMERATED_CTL_INFO(uinfo, texts); 3065 } else if (MADI == hdspm->io_type) { 3066 static const char *const texts[] = {"Word Clock", "MADI", "TCO", 3067 "Sync In", "None" }; 3068 3069 ENUMERATED_CTL_INFO(uinfo, texts); 3070 } 3071 return 0; 3072 } 3073 3074 static int snd_hdspm_get_autosync_ref(struct snd_kcontrol *kcontrol, 3075 struct snd_ctl_elem_value *ucontrol) 3076 { 3077 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3078 3079 ucontrol->value.enumerated.item[0] = hdspm_autosync_ref(hdspm); 3080 return 0; 3081 } 3082 3083 3084 3085 #define HDSPM_TCO_VIDEO_INPUT_FORMAT(xname, xindex) \ 3086 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3087 .name = xname, \ 3088 .access = SNDRV_CTL_ELEM_ACCESS_READ |\ 3089 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3090 .info = snd_hdspm_info_tco_video_input_format, \ 3091 .get = snd_hdspm_get_tco_video_input_format, \ 3092 } 3093 3094 static int snd_hdspm_info_tco_video_input_format(struct snd_kcontrol *kcontrol, 3095 struct snd_ctl_elem_info *uinfo) 3096 { 3097 static const char *const texts[] = {"No video", "NTSC", "PAL"}; 3098 ENUMERATED_CTL_INFO(uinfo, texts); 3099 return 0; 3100 } 3101 3102 static int snd_hdspm_get_tco_video_input_format(struct snd_kcontrol *kcontrol, 3103 struct snd_ctl_elem_value *ucontrol) 3104 { 3105 u32 status; 3106 int ret = 0; 3107 3108 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3109 status = hdspm_read(hdspm, HDSPM_RD_TCO + 4); 3110 switch (status & (HDSPM_TCO1_Video_Input_Format_NTSC | 3111 HDSPM_TCO1_Video_Input_Format_PAL)) { 3112 case HDSPM_TCO1_Video_Input_Format_NTSC: 3113 /* ntsc */ 3114 ret = 1; 3115 break; 3116 case HDSPM_TCO1_Video_Input_Format_PAL: 3117 /* pal */ 3118 ret = 2; 3119 break; 3120 default: 3121 /* no video */ 3122 ret = 0; 3123 break; 3124 } 3125 ucontrol->value.enumerated.item[0] = ret; 3126 return 0; 3127 } 3128 3129 3130 3131 #define HDSPM_TCO_LTC_FRAMES(xname, xindex) \ 3132 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3133 .name = xname, \ 3134 .access = SNDRV_CTL_ELEM_ACCESS_READ |\ 3135 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3136 .info = snd_hdspm_info_tco_ltc_frames, \ 3137 .get = snd_hdspm_get_tco_ltc_frames, \ 3138 } 3139 3140 static int snd_hdspm_info_tco_ltc_frames(struct snd_kcontrol *kcontrol, 3141 struct snd_ctl_elem_info *uinfo) 3142 { 3143 static const char *const texts[] = {"No lock", "24 fps", "25 fps", "29.97 fps", 3144 "30 fps"}; 3145 ENUMERATED_CTL_INFO(uinfo, texts); 3146 return 0; 3147 } 3148 3149 static int hdspm_tco_ltc_frames(struct hdspm *hdspm) 3150 { 3151 u32 status; 3152 int ret = 0; 3153 3154 status = hdspm_read(hdspm, HDSPM_RD_TCO + 4); 3155 if (status & HDSPM_TCO1_LTC_Input_valid) { 3156 switch (status & (HDSPM_TCO1_LTC_Format_LSB | 3157 HDSPM_TCO1_LTC_Format_MSB)) { 3158 case 0: 3159 /* 24 fps */ 3160 ret = fps_24; 3161 break; 3162 case HDSPM_TCO1_LTC_Format_LSB: 3163 /* 25 fps */ 3164 ret = fps_25; 3165 break; 3166 case HDSPM_TCO1_LTC_Format_MSB: 3167 /* 29.97 fps */ 3168 ret = fps_2997; 3169 break; 3170 default: 3171 /* 30 fps */ 3172 ret = fps_30; 3173 break; 3174 } 3175 } 3176 3177 return ret; 3178 } 3179 3180 static int snd_hdspm_get_tco_ltc_frames(struct snd_kcontrol *kcontrol, 3181 struct snd_ctl_elem_value *ucontrol) 3182 { 3183 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3184 3185 ucontrol->value.enumerated.item[0] = hdspm_tco_ltc_frames(hdspm); 3186 return 0; 3187 } 3188 3189 #define HDSPM_TOGGLE_SETTING(xname, xindex) \ 3190 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3191 .name = xname, \ 3192 .private_value = xindex, \ 3193 .info = snd_hdspm_info_toggle_setting, \ 3194 .get = snd_hdspm_get_toggle_setting, \ 3195 .put = snd_hdspm_put_toggle_setting \ 3196 } 3197 3198 static int hdspm_toggle_setting(struct hdspm *hdspm, u32 regmask) 3199 { 3200 u32 reg; 3201 3202 if (hdspm_is_raydat_or_aio(hdspm)) 3203 reg = hdspm->settings_register; 3204 else 3205 reg = hdspm->control_register; 3206 3207 return (reg & regmask) ? 1 : 0; 3208 } 3209 3210 static int hdspm_set_toggle_setting(struct hdspm *hdspm, u32 regmask, int out) 3211 { 3212 u32 *reg; 3213 u32 target_reg; 3214 3215 if (hdspm_is_raydat_or_aio(hdspm)) { 3216 reg = &(hdspm->settings_register); 3217 target_reg = HDSPM_WR_SETTINGS; 3218 } else { 3219 reg = &(hdspm->control_register); 3220 target_reg = HDSPM_controlRegister; 3221 } 3222 3223 if (out) 3224 *reg |= regmask; 3225 else 3226 *reg &= ~regmask; 3227 3228 hdspm_write(hdspm, target_reg, *reg); 3229 3230 return 0; 3231 } 3232 3233 #define snd_hdspm_info_toggle_setting snd_ctl_boolean_mono_info 3234 3235 static int snd_hdspm_get_toggle_setting(struct snd_kcontrol *kcontrol, 3236 struct snd_ctl_elem_value *ucontrol) 3237 { 3238 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3239 u32 regmask = kcontrol->private_value; 3240 3241 spin_lock_irq(&hdspm->lock); 3242 ucontrol->value.integer.value[0] = hdspm_toggle_setting(hdspm, regmask); 3243 spin_unlock_irq(&hdspm->lock); 3244 return 0; 3245 } 3246 3247 static int snd_hdspm_put_toggle_setting(struct snd_kcontrol *kcontrol, 3248 struct snd_ctl_elem_value *ucontrol) 3249 { 3250 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3251 u32 regmask = kcontrol->private_value; 3252 int change; 3253 unsigned int val; 3254 3255 if (!snd_hdspm_use_is_exclusive(hdspm)) 3256 return -EBUSY; 3257 val = ucontrol->value.integer.value[0] & 1; 3258 spin_lock_irq(&hdspm->lock); 3259 change = (int) val != hdspm_toggle_setting(hdspm, regmask); 3260 hdspm_set_toggle_setting(hdspm, regmask, val); 3261 spin_unlock_irq(&hdspm->lock); 3262 return change; 3263 } 3264 3265 #define HDSPM_INPUT_SELECT(xname, xindex) \ 3266 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3267 .name = xname, \ 3268 .index = xindex, \ 3269 .info = snd_hdspm_info_input_select, \ 3270 .get = snd_hdspm_get_input_select, \ 3271 .put = snd_hdspm_put_input_select \ 3272 } 3273 3274 static int hdspm_input_select(struct hdspm * hdspm) 3275 { 3276 return (hdspm->control_register & HDSPM_InputSelect0) ? 1 : 0; 3277 } 3278 3279 static int hdspm_set_input_select(struct hdspm * hdspm, int out) 3280 { 3281 if (out) 3282 hdspm->control_register |= HDSPM_InputSelect0; 3283 else 3284 hdspm->control_register &= ~HDSPM_InputSelect0; 3285 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3286 3287 return 0; 3288 } 3289 3290 static int snd_hdspm_info_input_select(struct snd_kcontrol *kcontrol, 3291 struct snd_ctl_elem_info *uinfo) 3292 { 3293 static const char *const texts[] = { "optical", "coaxial" }; 3294 ENUMERATED_CTL_INFO(uinfo, texts); 3295 return 0; 3296 } 3297 3298 static int snd_hdspm_get_input_select(struct snd_kcontrol *kcontrol, 3299 struct snd_ctl_elem_value *ucontrol) 3300 { 3301 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3302 3303 spin_lock_irq(&hdspm->lock); 3304 ucontrol->value.enumerated.item[0] = hdspm_input_select(hdspm); 3305 spin_unlock_irq(&hdspm->lock); 3306 return 0; 3307 } 3308 3309 static int snd_hdspm_put_input_select(struct snd_kcontrol *kcontrol, 3310 struct snd_ctl_elem_value *ucontrol) 3311 { 3312 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3313 int change; 3314 unsigned int val; 3315 3316 if (!snd_hdspm_use_is_exclusive(hdspm)) 3317 return -EBUSY; 3318 val = ucontrol->value.integer.value[0] & 1; 3319 spin_lock_irq(&hdspm->lock); 3320 change = (int) val != hdspm_input_select(hdspm); 3321 hdspm_set_input_select(hdspm, val); 3322 spin_unlock_irq(&hdspm->lock); 3323 return change; 3324 } 3325 3326 3327 #define HDSPM_DS_WIRE(xname, xindex) \ 3328 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3329 .name = xname, \ 3330 .index = xindex, \ 3331 .info = snd_hdspm_info_ds_wire, \ 3332 .get = snd_hdspm_get_ds_wire, \ 3333 .put = snd_hdspm_put_ds_wire \ 3334 } 3335 3336 static int hdspm_ds_wire(struct hdspm * hdspm) 3337 { 3338 return (hdspm->control_register & HDSPM_DS_DoubleWire) ? 1 : 0; 3339 } 3340 3341 static int hdspm_set_ds_wire(struct hdspm * hdspm, int ds) 3342 { 3343 if (ds) 3344 hdspm->control_register |= HDSPM_DS_DoubleWire; 3345 else 3346 hdspm->control_register &= ~HDSPM_DS_DoubleWire; 3347 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3348 3349 return 0; 3350 } 3351 3352 static int snd_hdspm_info_ds_wire(struct snd_kcontrol *kcontrol, 3353 struct snd_ctl_elem_info *uinfo) 3354 { 3355 static const char *const texts[] = { "Single", "Double" }; 3356 ENUMERATED_CTL_INFO(uinfo, texts); 3357 return 0; 3358 } 3359 3360 static int snd_hdspm_get_ds_wire(struct snd_kcontrol *kcontrol, 3361 struct snd_ctl_elem_value *ucontrol) 3362 { 3363 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3364 3365 spin_lock_irq(&hdspm->lock); 3366 ucontrol->value.enumerated.item[0] = hdspm_ds_wire(hdspm); 3367 spin_unlock_irq(&hdspm->lock); 3368 return 0; 3369 } 3370 3371 static int snd_hdspm_put_ds_wire(struct snd_kcontrol *kcontrol, 3372 struct snd_ctl_elem_value *ucontrol) 3373 { 3374 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3375 int change; 3376 unsigned int val; 3377 3378 if (!snd_hdspm_use_is_exclusive(hdspm)) 3379 return -EBUSY; 3380 val = ucontrol->value.integer.value[0] & 1; 3381 spin_lock_irq(&hdspm->lock); 3382 change = (int) val != hdspm_ds_wire(hdspm); 3383 hdspm_set_ds_wire(hdspm, val); 3384 spin_unlock_irq(&hdspm->lock); 3385 return change; 3386 } 3387 3388 3389 #define HDSPM_QS_WIRE(xname, xindex) \ 3390 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3391 .name = xname, \ 3392 .index = xindex, \ 3393 .info = snd_hdspm_info_qs_wire, \ 3394 .get = snd_hdspm_get_qs_wire, \ 3395 .put = snd_hdspm_put_qs_wire \ 3396 } 3397 3398 static int hdspm_qs_wire(struct hdspm * hdspm) 3399 { 3400 if (hdspm->control_register & HDSPM_QS_DoubleWire) 3401 return 1; 3402 if (hdspm->control_register & HDSPM_QS_QuadWire) 3403 return 2; 3404 return 0; 3405 } 3406 3407 static int hdspm_set_qs_wire(struct hdspm * hdspm, int mode) 3408 { 3409 hdspm->control_register &= ~(HDSPM_QS_DoubleWire | HDSPM_QS_QuadWire); 3410 switch (mode) { 3411 case 0: 3412 break; 3413 case 1: 3414 hdspm->control_register |= HDSPM_QS_DoubleWire; 3415 break; 3416 case 2: 3417 hdspm->control_register |= HDSPM_QS_QuadWire; 3418 break; 3419 } 3420 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3421 3422 return 0; 3423 } 3424 3425 static int snd_hdspm_info_qs_wire(struct snd_kcontrol *kcontrol, 3426 struct snd_ctl_elem_info *uinfo) 3427 { 3428 static const char *const texts[] = { "Single", "Double", "Quad" }; 3429 ENUMERATED_CTL_INFO(uinfo, texts); 3430 return 0; 3431 } 3432 3433 static int snd_hdspm_get_qs_wire(struct snd_kcontrol *kcontrol, 3434 struct snd_ctl_elem_value *ucontrol) 3435 { 3436 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3437 3438 spin_lock_irq(&hdspm->lock); 3439 ucontrol->value.enumerated.item[0] = hdspm_qs_wire(hdspm); 3440 spin_unlock_irq(&hdspm->lock); 3441 return 0; 3442 } 3443 3444 static int snd_hdspm_put_qs_wire(struct snd_kcontrol *kcontrol, 3445 struct snd_ctl_elem_value *ucontrol) 3446 { 3447 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3448 int change; 3449 int val; 3450 3451 if (!snd_hdspm_use_is_exclusive(hdspm)) 3452 return -EBUSY; 3453 val = ucontrol->value.integer.value[0]; 3454 if (val < 0) 3455 val = 0; 3456 if (val > 2) 3457 val = 2; 3458 spin_lock_irq(&hdspm->lock); 3459 change = val != hdspm_qs_wire(hdspm); 3460 hdspm_set_qs_wire(hdspm, val); 3461 spin_unlock_irq(&hdspm->lock); 3462 return change; 3463 } 3464 3465 #define HDSPM_CONTROL_TRISTATE(xname, xindex) \ 3466 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3467 .name = xname, \ 3468 .private_value = xindex, \ 3469 .info = snd_hdspm_info_tristate, \ 3470 .get = snd_hdspm_get_tristate, \ 3471 .put = snd_hdspm_put_tristate \ 3472 } 3473 3474 static int hdspm_tristate(struct hdspm *hdspm, u32 regmask) 3475 { 3476 u32 reg = hdspm->settings_register & (regmask * 3); 3477 return reg / regmask; 3478 } 3479 3480 static int hdspm_set_tristate(struct hdspm *hdspm, int mode, u32 regmask) 3481 { 3482 hdspm->settings_register &= ~(regmask * 3); 3483 hdspm->settings_register |= (regmask * mode); 3484 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register); 3485 3486 return 0; 3487 } 3488 3489 static int snd_hdspm_info_tristate(struct snd_kcontrol *kcontrol, 3490 struct snd_ctl_elem_info *uinfo) 3491 { 3492 u32 regmask = kcontrol->private_value; 3493 3494 static const char *const texts_spdif[] = { "Optical", "Coaxial", "Internal" }; 3495 static const char *const texts_levels[] = { "Hi Gain", "+4 dBu", "-10 dBV" }; 3496 3497 switch (regmask) { 3498 case HDSPM_c0_Input0: 3499 ENUMERATED_CTL_INFO(uinfo, texts_spdif); 3500 break; 3501 default: 3502 ENUMERATED_CTL_INFO(uinfo, texts_levels); 3503 break; 3504 } 3505 return 0; 3506 } 3507 3508 static int snd_hdspm_get_tristate(struct snd_kcontrol *kcontrol, 3509 struct snd_ctl_elem_value *ucontrol) 3510 { 3511 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3512 u32 regmask = kcontrol->private_value; 3513 3514 spin_lock_irq(&hdspm->lock); 3515 ucontrol->value.enumerated.item[0] = hdspm_tristate(hdspm, regmask); 3516 spin_unlock_irq(&hdspm->lock); 3517 return 0; 3518 } 3519 3520 static int snd_hdspm_put_tristate(struct snd_kcontrol *kcontrol, 3521 struct snd_ctl_elem_value *ucontrol) 3522 { 3523 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3524 u32 regmask = kcontrol->private_value; 3525 int change; 3526 int val; 3527 3528 if (!snd_hdspm_use_is_exclusive(hdspm)) 3529 return -EBUSY; 3530 val = ucontrol->value.integer.value[0]; 3531 if (val < 0) 3532 val = 0; 3533 if (val > 2) 3534 val = 2; 3535 3536 spin_lock_irq(&hdspm->lock); 3537 change = val != hdspm_tristate(hdspm, regmask); 3538 hdspm_set_tristate(hdspm, val, regmask); 3539 spin_unlock_irq(&hdspm->lock); 3540 return change; 3541 } 3542 3543 #define HDSPM_MADI_SPEEDMODE(xname, xindex) \ 3544 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3545 .name = xname, \ 3546 .index = xindex, \ 3547 .info = snd_hdspm_info_madi_speedmode, \ 3548 .get = snd_hdspm_get_madi_speedmode, \ 3549 .put = snd_hdspm_put_madi_speedmode \ 3550 } 3551 3552 static int hdspm_madi_speedmode(struct hdspm *hdspm) 3553 { 3554 if (hdspm->control_register & HDSPM_QuadSpeed) 3555 return 2; 3556 if (hdspm->control_register & HDSPM_DoubleSpeed) 3557 return 1; 3558 return 0; 3559 } 3560 3561 static int hdspm_set_madi_speedmode(struct hdspm *hdspm, int mode) 3562 { 3563 hdspm->control_register &= ~(HDSPM_DoubleSpeed | HDSPM_QuadSpeed); 3564 switch (mode) { 3565 case 0: 3566 break; 3567 case 1: 3568 hdspm->control_register |= HDSPM_DoubleSpeed; 3569 break; 3570 case 2: 3571 hdspm->control_register |= HDSPM_QuadSpeed; 3572 break; 3573 } 3574 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3575 3576 return 0; 3577 } 3578 3579 static int snd_hdspm_info_madi_speedmode(struct snd_kcontrol *kcontrol, 3580 struct snd_ctl_elem_info *uinfo) 3581 { 3582 static const char *const texts[] = { "Single", "Double", "Quad" }; 3583 ENUMERATED_CTL_INFO(uinfo, texts); 3584 return 0; 3585 } 3586 3587 static int snd_hdspm_get_madi_speedmode(struct snd_kcontrol *kcontrol, 3588 struct snd_ctl_elem_value *ucontrol) 3589 { 3590 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3591 3592 spin_lock_irq(&hdspm->lock); 3593 ucontrol->value.enumerated.item[0] = hdspm_madi_speedmode(hdspm); 3594 spin_unlock_irq(&hdspm->lock); 3595 return 0; 3596 } 3597 3598 static int snd_hdspm_put_madi_speedmode(struct snd_kcontrol *kcontrol, 3599 struct snd_ctl_elem_value *ucontrol) 3600 { 3601 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3602 int change; 3603 int val; 3604 3605 if (!snd_hdspm_use_is_exclusive(hdspm)) 3606 return -EBUSY; 3607 val = ucontrol->value.integer.value[0]; 3608 if (val < 0) 3609 val = 0; 3610 if (val > 2) 3611 val = 2; 3612 spin_lock_irq(&hdspm->lock); 3613 change = val != hdspm_madi_speedmode(hdspm); 3614 hdspm_set_madi_speedmode(hdspm, val); 3615 spin_unlock_irq(&hdspm->lock); 3616 return change; 3617 } 3618 3619 #define HDSPM_MIXER(xname, xindex) \ 3620 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ 3621 .name = xname, \ 3622 .index = xindex, \ 3623 .device = 0, \ 3624 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ 3625 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3626 .info = snd_hdspm_info_mixer, \ 3627 .get = snd_hdspm_get_mixer, \ 3628 .put = snd_hdspm_put_mixer \ 3629 } 3630 3631 static int snd_hdspm_info_mixer(struct snd_kcontrol *kcontrol, 3632 struct snd_ctl_elem_info *uinfo) 3633 { 3634 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 3635 uinfo->count = 3; 3636 uinfo->value.integer.min = 0; 3637 uinfo->value.integer.max = 65535; 3638 uinfo->value.integer.step = 1; 3639 return 0; 3640 } 3641 3642 static int snd_hdspm_get_mixer(struct snd_kcontrol *kcontrol, 3643 struct snd_ctl_elem_value *ucontrol) 3644 { 3645 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3646 int source; 3647 int destination; 3648 3649 source = ucontrol->value.integer.value[0]; 3650 if (source < 0) 3651 source = 0; 3652 else if (source >= 2 * HDSPM_MAX_CHANNELS) 3653 source = 2 * HDSPM_MAX_CHANNELS - 1; 3654 3655 destination = ucontrol->value.integer.value[1]; 3656 if (destination < 0) 3657 destination = 0; 3658 else if (destination >= HDSPM_MAX_CHANNELS) 3659 destination = HDSPM_MAX_CHANNELS - 1; 3660 3661 spin_lock_irq(&hdspm->lock); 3662 if (source >= HDSPM_MAX_CHANNELS) 3663 ucontrol->value.integer.value[2] = 3664 hdspm_read_pb_gain(hdspm, destination, 3665 source - HDSPM_MAX_CHANNELS); 3666 else 3667 ucontrol->value.integer.value[2] = 3668 hdspm_read_in_gain(hdspm, destination, source); 3669 3670 spin_unlock_irq(&hdspm->lock); 3671 3672 return 0; 3673 } 3674 3675 static int snd_hdspm_put_mixer(struct snd_kcontrol *kcontrol, 3676 struct snd_ctl_elem_value *ucontrol) 3677 { 3678 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3679 int change; 3680 int source; 3681 int destination; 3682 int gain; 3683 3684 if (!snd_hdspm_use_is_exclusive(hdspm)) 3685 return -EBUSY; 3686 3687 source = ucontrol->value.integer.value[0]; 3688 destination = ucontrol->value.integer.value[1]; 3689 3690 if (source < 0 || source >= 2 * HDSPM_MAX_CHANNELS) 3691 return -1; 3692 if (destination < 0 || destination >= HDSPM_MAX_CHANNELS) 3693 return -1; 3694 3695 gain = ucontrol->value.integer.value[2]; 3696 3697 spin_lock_irq(&hdspm->lock); 3698 3699 if (source >= HDSPM_MAX_CHANNELS) 3700 change = gain != hdspm_read_pb_gain(hdspm, destination, 3701 source - 3702 HDSPM_MAX_CHANNELS); 3703 else 3704 change = gain != hdspm_read_in_gain(hdspm, destination, 3705 source); 3706 3707 if (change) { 3708 if (source >= HDSPM_MAX_CHANNELS) 3709 hdspm_write_pb_gain(hdspm, destination, 3710 source - HDSPM_MAX_CHANNELS, 3711 gain); 3712 else 3713 hdspm_write_in_gain(hdspm, destination, source, 3714 gain); 3715 } 3716 spin_unlock_irq(&hdspm->lock); 3717 3718 return change; 3719 } 3720 3721 /* The simple mixer control(s) provide gain control for the 3722 basic 1:1 mappings of playback streams to output 3723 streams. 3724 */ 3725 3726 #define HDSPM_PLAYBACK_MIXER \ 3727 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3728 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE | \ 3729 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3730 .info = snd_hdspm_info_playback_mixer, \ 3731 .get = snd_hdspm_get_playback_mixer, \ 3732 .put = snd_hdspm_put_playback_mixer \ 3733 } 3734 3735 static int snd_hdspm_info_playback_mixer(struct snd_kcontrol *kcontrol, 3736 struct snd_ctl_elem_info *uinfo) 3737 { 3738 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 3739 uinfo->count = 1; 3740 uinfo->value.integer.min = 0; 3741 uinfo->value.integer.max = 64; 3742 uinfo->value.integer.step = 1; 3743 return 0; 3744 } 3745 3746 static int snd_hdspm_get_playback_mixer(struct snd_kcontrol *kcontrol, 3747 struct snd_ctl_elem_value *ucontrol) 3748 { 3749 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3750 int channel; 3751 3752 channel = ucontrol->id.index - 1; 3753 3754 if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS)) 3755 return -EINVAL; 3756 3757 spin_lock_irq(&hdspm->lock); 3758 ucontrol->value.integer.value[0] = 3759 (hdspm_read_pb_gain(hdspm, channel, channel)*64)/UNITY_GAIN; 3760 spin_unlock_irq(&hdspm->lock); 3761 3762 return 0; 3763 } 3764 3765 static int snd_hdspm_put_playback_mixer(struct snd_kcontrol *kcontrol, 3766 struct snd_ctl_elem_value *ucontrol) 3767 { 3768 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3769 int change; 3770 int channel; 3771 int gain; 3772 3773 if (!snd_hdspm_use_is_exclusive(hdspm)) 3774 return -EBUSY; 3775 3776 channel = ucontrol->id.index - 1; 3777 3778 if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS)) 3779 return -EINVAL; 3780 3781 gain = ucontrol->value.integer.value[0]*UNITY_GAIN/64; 3782 3783 spin_lock_irq(&hdspm->lock); 3784 change = 3785 gain != hdspm_read_pb_gain(hdspm, channel, 3786 channel); 3787 if (change) 3788 hdspm_write_pb_gain(hdspm, channel, channel, 3789 gain); 3790 spin_unlock_irq(&hdspm->lock); 3791 return change; 3792 } 3793 3794 #define HDSPM_SYNC_CHECK(xname, xindex) \ 3795 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3796 .name = xname, \ 3797 .private_value = xindex, \ 3798 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3799 .info = snd_hdspm_info_sync_check, \ 3800 .get = snd_hdspm_get_sync_check \ 3801 } 3802 3803 #define HDSPM_TCO_LOCK_CHECK(xname, xindex) \ 3804 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3805 .name = xname, \ 3806 .private_value = xindex, \ 3807 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3808 .info = snd_hdspm_tco_info_lock_check, \ 3809 .get = snd_hdspm_get_sync_check \ 3810 } 3811 3812 3813 3814 static int snd_hdspm_info_sync_check(struct snd_kcontrol *kcontrol, 3815 struct snd_ctl_elem_info *uinfo) 3816 { 3817 static const char *const texts[] = { "No Lock", "Lock", "Sync", "N/A" }; 3818 ENUMERATED_CTL_INFO(uinfo, texts); 3819 return 0; 3820 } 3821 3822 static int snd_hdspm_tco_info_lock_check(struct snd_kcontrol *kcontrol, 3823 struct snd_ctl_elem_info *uinfo) 3824 { 3825 static const char *const texts[] = { "No Lock", "Lock" }; 3826 ENUMERATED_CTL_INFO(uinfo, texts); 3827 return 0; 3828 } 3829 3830 static int hdspm_wc_sync_check(struct hdspm *hdspm) 3831 { 3832 int status, status2; 3833 3834 switch (hdspm->io_type) { 3835 case AES32: 3836 status = hdspm_read(hdspm, HDSPM_statusRegister); 3837 if (status & HDSPM_AES32_wcLock) { 3838 if (status & HDSPM_AES32_wcSync) 3839 return 2; 3840 else 3841 return 1; 3842 } 3843 return 0; 3844 break; 3845 3846 case MADI: 3847 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 3848 if (status2 & HDSPM_wcLock) { 3849 if (status2 & HDSPM_wcSync) 3850 return 2; 3851 else 3852 return 1; 3853 } 3854 return 0; 3855 break; 3856 3857 case RayDAT: 3858 case AIO: 3859 status = hdspm_read(hdspm, HDSPM_statusRegister); 3860 3861 if (status & 0x2000000) 3862 return 2; 3863 else if (status & 0x1000000) 3864 return 1; 3865 return 0; 3866 3867 break; 3868 3869 case MADIface: 3870 break; 3871 } 3872 3873 3874 return 3; 3875 } 3876 3877 3878 static int hdspm_madi_sync_check(struct hdspm *hdspm) 3879 { 3880 int status = hdspm_read(hdspm, HDSPM_statusRegister); 3881 if (status & HDSPM_madiLock) { 3882 if (status & HDSPM_madiSync) 3883 return 2; 3884 else 3885 return 1; 3886 } 3887 return 0; 3888 } 3889 3890 3891 static int hdspm_s1_sync_check(struct hdspm *hdspm, int idx) 3892 { 3893 int status, lock, sync; 3894 3895 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); 3896 3897 lock = (status & (0x1<<idx)) ? 1 : 0; 3898 sync = (status & (0x100<<idx)) ? 1 : 0; 3899 3900 if (lock && sync) 3901 return 2; 3902 else if (lock) 3903 return 1; 3904 return 0; 3905 } 3906 3907 3908 static int hdspm_sync_in_sync_check(struct hdspm *hdspm) 3909 { 3910 int status, lock = 0, sync = 0; 3911 3912 switch (hdspm->io_type) { 3913 case RayDAT: 3914 case AIO: 3915 status = hdspm_read(hdspm, HDSPM_RD_STATUS_3); 3916 lock = (status & 0x400) ? 1 : 0; 3917 sync = (status & 0x800) ? 1 : 0; 3918 break; 3919 3920 case MADI: 3921 status = hdspm_read(hdspm, HDSPM_statusRegister); 3922 lock = (status & HDSPM_syncInLock) ? 1 : 0; 3923 sync = (status & HDSPM_syncInSync) ? 1 : 0; 3924 break; 3925 3926 case AES32: 3927 status = hdspm_read(hdspm, HDSPM_statusRegister2); 3928 lock = (status & 0x100000) ? 1 : 0; 3929 sync = (status & 0x200000) ? 1 : 0; 3930 break; 3931 3932 case MADIface: 3933 break; 3934 } 3935 3936 if (lock && sync) 3937 return 2; 3938 else if (lock) 3939 return 1; 3940 3941 return 0; 3942 } 3943 3944 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx) 3945 { 3946 int status2, lock, sync; 3947 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 3948 3949 lock = (status2 & (0x0080 >> idx)) ? 1 : 0; 3950 sync = (status2 & (0x8000 >> idx)) ? 1 : 0; 3951 3952 if (sync) 3953 return 2; 3954 else if (lock) 3955 return 1; 3956 return 0; 3957 } 3958 3959 static int hdspm_tco_input_check(struct hdspm *hdspm, u32 mask) 3960 { 3961 u32 status; 3962 status = hdspm_read(hdspm, HDSPM_RD_TCO + 4); 3963 3964 return (status & mask) ? 1 : 0; 3965 } 3966 3967 3968 static int hdspm_tco_sync_check(struct hdspm *hdspm) 3969 { 3970 int status; 3971 3972 if (hdspm->tco) { 3973 switch (hdspm->io_type) { 3974 case MADI: 3975 status = hdspm_read(hdspm, HDSPM_statusRegister); 3976 if (status & HDSPM_tcoLockMadi) { 3977 if (status & HDSPM_tcoSync) 3978 return 2; 3979 else 3980 return 1; 3981 } 3982 return 0; 3983 case AES32: 3984 status = hdspm_read(hdspm, HDSPM_statusRegister); 3985 if (status & HDSPM_tcoLockAes) { 3986 if (status & HDSPM_tcoSync) 3987 return 2; 3988 else 3989 return 1; 3990 } 3991 return 0; 3992 case RayDAT: 3993 case AIO: 3994 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); 3995 3996 if (status & 0x8000000) 3997 return 2; /* Sync */ 3998 if (status & 0x4000000) 3999 return 1; /* Lock */ 4000 return 0; /* No signal */ 4001 4002 default: 4003 break; 4004 } 4005 } 4006 4007 return 3; /* N/A */ 4008 } 4009 4010 4011 static int snd_hdspm_get_sync_check(struct snd_kcontrol *kcontrol, 4012 struct snd_ctl_elem_value *ucontrol) 4013 { 4014 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4015 int val = -1; 4016 4017 switch (hdspm->io_type) { 4018 case RayDAT: 4019 switch (kcontrol->private_value) { 4020 case 0: /* WC */ 4021 val = hdspm_wc_sync_check(hdspm); break; 4022 case 7: /* TCO */ 4023 val = hdspm_tco_sync_check(hdspm); break; 4024 case 8: /* SYNC IN */ 4025 val = hdspm_sync_in_sync_check(hdspm); break; 4026 default: 4027 val = hdspm_s1_sync_check(hdspm, 4028 kcontrol->private_value-1); 4029 } 4030 break; 4031 4032 case AIO: 4033 switch (kcontrol->private_value) { 4034 case 0: /* WC */ 4035 val = hdspm_wc_sync_check(hdspm); break; 4036 case 4: /* TCO */ 4037 val = hdspm_tco_sync_check(hdspm); break; 4038 case 5: /* SYNC IN */ 4039 val = hdspm_sync_in_sync_check(hdspm); break; 4040 default: 4041 val = hdspm_s1_sync_check(hdspm, 4042 kcontrol->private_value-1); 4043 } 4044 break; 4045 4046 case MADI: 4047 switch (kcontrol->private_value) { 4048 case 0: /* WC */ 4049 val = hdspm_wc_sync_check(hdspm); break; 4050 case 1: /* MADI */ 4051 val = hdspm_madi_sync_check(hdspm); break; 4052 case 2: /* TCO */ 4053 val = hdspm_tco_sync_check(hdspm); break; 4054 case 3: /* SYNC_IN */ 4055 val = hdspm_sync_in_sync_check(hdspm); break; 4056 } 4057 break; 4058 4059 case MADIface: 4060 val = hdspm_madi_sync_check(hdspm); /* MADI */ 4061 break; 4062 4063 case AES32: 4064 switch (kcontrol->private_value) { 4065 case 0: /* WC */ 4066 val = hdspm_wc_sync_check(hdspm); break; 4067 case 9: /* TCO */ 4068 val = hdspm_tco_sync_check(hdspm); break; 4069 case 10 /* SYNC IN */: 4070 val = hdspm_sync_in_sync_check(hdspm); break; 4071 default: /* AES1 to AES8 */ 4072 val = hdspm_aes_sync_check(hdspm, 4073 kcontrol->private_value-1); 4074 } 4075 break; 4076 4077 } 4078 4079 if (hdspm->tco) { 4080 switch (kcontrol->private_value) { 4081 case 11: 4082 /* Check TCO for lock state of its current input */ 4083 val = hdspm_tco_input_check(hdspm, HDSPM_TCO1_TCO_lock); 4084 break; 4085 case 12: 4086 /* Check TCO for valid time code on LTC input. */ 4087 val = hdspm_tco_input_check(hdspm, 4088 HDSPM_TCO1_LTC_Input_valid); 4089 break; 4090 default: 4091 break; 4092 } 4093 } 4094 4095 if (-1 == val) 4096 val = 3; 4097 4098 ucontrol->value.enumerated.item[0] = val; 4099 return 0; 4100 } 4101 4102 4103 4104 /* 4105 * TCO controls 4106 */ 4107 static void hdspm_tco_write(struct hdspm *hdspm) 4108 { 4109 unsigned int tc[4] = { 0, 0, 0, 0}; 4110 4111 switch (hdspm->tco->input) { 4112 case 0: 4113 tc[2] |= HDSPM_TCO2_set_input_MSB; 4114 break; 4115 case 1: 4116 tc[2] |= HDSPM_TCO2_set_input_LSB; 4117 break; 4118 default: 4119 break; 4120 } 4121 4122 switch (hdspm->tco->framerate) { 4123 case 1: 4124 tc[1] |= HDSPM_TCO1_LTC_Format_LSB; 4125 break; 4126 case 2: 4127 tc[1] |= HDSPM_TCO1_LTC_Format_MSB; 4128 break; 4129 case 3: 4130 tc[1] |= HDSPM_TCO1_LTC_Format_MSB + 4131 HDSPM_TCO1_set_drop_frame_flag; 4132 break; 4133 case 4: 4134 tc[1] |= HDSPM_TCO1_LTC_Format_LSB + 4135 HDSPM_TCO1_LTC_Format_MSB; 4136 break; 4137 case 5: 4138 tc[1] |= HDSPM_TCO1_LTC_Format_LSB + 4139 HDSPM_TCO1_LTC_Format_MSB + 4140 HDSPM_TCO1_set_drop_frame_flag; 4141 break; 4142 default: 4143 break; 4144 } 4145 4146 switch (hdspm->tco->wordclock) { 4147 case 1: 4148 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_LSB; 4149 break; 4150 case 2: 4151 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_MSB; 4152 break; 4153 default: 4154 break; 4155 } 4156 4157 switch (hdspm->tco->samplerate) { 4158 case 1: 4159 tc[2] |= HDSPM_TCO2_set_freq; 4160 break; 4161 case 2: 4162 tc[2] |= HDSPM_TCO2_set_freq_from_app; 4163 break; 4164 default: 4165 break; 4166 } 4167 4168 switch (hdspm->tco->pull) { 4169 case 1: 4170 tc[2] |= HDSPM_TCO2_set_pull_up; 4171 break; 4172 case 2: 4173 tc[2] |= HDSPM_TCO2_set_pull_down; 4174 break; 4175 case 3: 4176 tc[2] |= HDSPM_TCO2_set_pull_up + HDSPM_TCO2_set_01_4; 4177 break; 4178 case 4: 4179 tc[2] |= HDSPM_TCO2_set_pull_down + HDSPM_TCO2_set_01_4; 4180 break; 4181 default: 4182 break; 4183 } 4184 4185 if (1 == hdspm->tco->term) { 4186 tc[2] |= HDSPM_TCO2_set_term_75R; 4187 } 4188 4189 hdspm_write(hdspm, HDSPM_WR_TCO, tc[0]); 4190 hdspm_write(hdspm, HDSPM_WR_TCO+4, tc[1]); 4191 hdspm_write(hdspm, HDSPM_WR_TCO+8, tc[2]); 4192 hdspm_write(hdspm, HDSPM_WR_TCO+12, tc[3]); 4193 } 4194 4195 4196 #define HDSPM_TCO_SAMPLE_RATE(xname, xindex) \ 4197 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4198 .name = xname, \ 4199 .index = xindex, \ 4200 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4201 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4202 .info = snd_hdspm_info_tco_sample_rate, \ 4203 .get = snd_hdspm_get_tco_sample_rate, \ 4204 .put = snd_hdspm_put_tco_sample_rate \ 4205 } 4206 4207 static int snd_hdspm_info_tco_sample_rate(struct snd_kcontrol *kcontrol, 4208 struct snd_ctl_elem_info *uinfo) 4209 { 4210 /* TODO freq from app could be supported here, see tco->samplerate */ 4211 static const char *const texts[] = { "44.1 kHz", "48 kHz" }; 4212 ENUMERATED_CTL_INFO(uinfo, texts); 4213 return 0; 4214 } 4215 4216 static int snd_hdspm_get_tco_sample_rate(struct snd_kcontrol *kcontrol, 4217 struct snd_ctl_elem_value *ucontrol) 4218 { 4219 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4220 4221 ucontrol->value.enumerated.item[0] = hdspm->tco->samplerate; 4222 4223 return 0; 4224 } 4225 4226 static int snd_hdspm_put_tco_sample_rate(struct snd_kcontrol *kcontrol, 4227 struct snd_ctl_elem_value *ucontrol) 4228 { 4229 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4230 4231 if (hdspm->tco->samplerate != ucontrol->value.enumerated.item[0]) { 4232 hdspm->tco->samplerate = ucontrol->value.enumerated.item[0]; 4233 4234 hdspm_tco_write(hdspm); 4235 4236 return 1; 4237 } 4238 4239 return 0; 4240 } 4241 4242 4243 #define HDSPM_TCO_PULL(xname, xindex) \ 4244 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4245 .name = xname, \ 4246 .index = xindex, \ 4247 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4248 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4249 .info = snd_hdspm_info_tco_pull, \ 4250 .get = snd_hdspm_get_tco_pull, \ 4251 .put = snd_hdspm_put_tco_pull \ 4252 } 4253 4254 static int snd_hdspm_info_tco_pull(struct snd_kcontrol *kcontrol, 4255 struct snd_ctl_elem_info *uinfo) 4256 { 4257 static const char *const texts[] = { "0", "+ 0.1 %", "- 0.1 %", 4258 "+ 4 %", "- 4 %" }; 4259 ENUMERATED_CTL_INFO(uinfo, texts); 4260 return 0; 4261 } 4262 4263 static int snd_hdspm_get_tco_pull(struct snd_kcontrol *kcontrol, 4264 struct snd_ctl_elem_value *ucontrol) 4265 { 4266 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4267 4268 ucontrol->value.enumerated.item[0] = hdspm->tco->pull; 4269 4270 return 0; 4271 } 4272 4273 static int snd_hdspm_put_tco_pull(struct snd_kcontrol *kcontrol, 4274 struct snd_ctl_elem_value *ucontrol) 4275 { 4276 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4277 4278 if (hdspm->tco->pull != ucontrol->value.enumerated.item[0]) { 4279 hdspm->tco->pull = ucontrol->value.enumerated.item[0]; 4280 4281 hdspm_tco_write(hdspm); 4282 4283 return 1; 4284 } 4285 4286 return 0; 4287 } 4288 4289 #define HDSPM_TCO_WCK_CONVERSION(xname, xindex) \ 4290 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4291 .name = xname, \ 4292 .index = xindex, \ 4293 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4294 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4295 .info = snd_hdspm_info_tco_wck_conversion, \ 4296 .get = snd_hdspm_get_tco_wck_conversion, \ 4297 .put = snd_hdspm_put_tco_wck_conversion \ 4298 } 4299 4300 static int snd_hdspm_info_tco_wck_conversion(struct snd_kcontrol *kcontrol, 4301 struct snd_ctl_elem_info *uinfo) 4302 { 4303 static const char *const texts[] = { "1:1", "44.1 -> 48", "48 -> 44.1" }; 4304 ENUMERATED_CTL_INFO(uinfo, texts); 4305 return 0; 4306 } 4307 4308 static int snd_hdspm_get_tco_wck_conversion(struct snd_kcontrol *kcontrol, 4309 struct snd_ctl_elem_value *ucontrol) 4310 { 4311 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4312 4313 ucontrol->value.enumerated.item[0] = hdspm->tco->wordclock; 4314 4315 return 0; 4316 } 4317 4318 static int snd_hdspm_put_tco_wck_conversion(struct snd_kcontrol *kcontrol, 4319 struct snd_ctl_elem_value *ucontrol) 4320 { 4321 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4322 4323 if (hdspm->tco->wordclock != ucontrol->value.enumerated.item[0]) { 4324 hdspm->tco->wordclock = ucontrol->value.enumerated.item[0]; 4325 4326 hdspm_tco_write(hdspm); 4327 4328 return 1; 4329 } 4330 4331 return 0; 4332 } 4333 4334 4335 #define HDSPM_TCO_FRAME_RATE(xname, xindex) \ 4336 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4337 .name = xname, \ 4338 .index = xindex, \ 4339 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4340 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4341 .info = snd_hdspm_info_tco_frame_rate, \ 4342 .get = snd_hdspm_get_tco_frame_rate, \ 4343 .put = snd_hdspm_put_tco_frame_rate \ 4344 } 4345 4346 static int snd_hdspm_info_tco_frame_rate(struct snd_kcontrol *kcontrol, 4347 struct snd_ctl_elem_info *uinfo) 4348 { 4349 static const char *const texts[] = { "24 fps", "25 fps", "29.97fps", 4350 "29.97 dfps", "30 fps", "30 dfps" }; 4351 ENUMERATED_CTL_INFO(uinfo, texts); 4352 return 0; 4353 } 4354 4355 static int snd_hdspm_get_tco_frame_rate(struct snd_kcontrol *kcontrol, 4356 struct snd_ctl_elem_value *ucontrol) 4357 { 4358 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4359 4360 ucontrol->value.enumerated.item[0] = hdspm->tco->framerate; 4361 4362 return 0; 4363 } 4364 4365 static int snd_hdspm_put_tco_frame_rate(struct snd_kcontrol *kcontrol, 4366 struct snd_ctl_elem_value *ucontrol) 4367 { 4368 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4369 4370 if (hdspm->tco->framerate != ucontrol->value.enumerated.item[0]) { 4371 hdspm->tco->framerate = ucontrol->value.enumerated.item[0]; 4372 4373 hdspm_tco_write(hdspm); 4374 4375 return 1; 4376 } 4377 4378 return 0; 4379 } 4380 4381 4382 #define HDSPM_TCO_SYNC_SOURCE(xname, xindex) \ 4383 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4384 .name = xname, \ 4385 .index = xindex, \ 4386 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4387 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4388 .info = snd_hdspm_info_tco_sync_source, \ 4389 .get = snd_hdspm_get_tco_sync_source, \ 4390 .put = snd_hdspm_put_tco_sync_source \ 4391 } 4392 4393 static int snd_hdspm_info_tco_sync_source(struct snd_kcontrol *kcontrol, 4394 struct snd_ctl_elem_info *uinfo) 4395 { 4396 static const char *const texts[] = { "LTC", "Video", "WCK" }; 4397 ENUMERATED_CTL_INFO(uinfo, texts); 4398 return 0; 4399 } 4400 4401 static int snd_hdspm_get_tco_sync_source(struct snd_kcontrol *kcontrol, 4402 struct snd_ctl_elem_value *ucontrol) 4403 { 4404 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4405 4406 ucontrol->value.enumerated.item[0] = hdspm->tco->input; 4407 4408 return 0; 4409 } 4410 4411 static int snd_hdspm_put_tco_sync_source(struct snd_kcontrol *kcontrol, 4412 struct snd_ctl_elem_value *ucontrol) 4413 { 4414 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4415 4416 if (hdspm->tco->input != ucontrol->value.enumerated.item[0]) { 4417 hdspm->tco->input = ucontrol->value.enumerated.item[0]; 4418 4419 hdspm_tco_write(hdspm); 4420 4421 return 1; 4422 } 4423 4424 return 0; 4425 } 4426 4427 4428 #define HDSPM_TCO_WORD_TERM(xname, xindex) \ 4429 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4430 .name = xname, \ 4431 .index = xindex, \ 4432 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4433 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4434 .info = snd_hdspm_info_tco_word_term, \ 4435 .get = snd_hdspm_get_tco_word_term, \ 4436 .put = snd_hdspm_put_tco_word_term \ 4437 } 4438 4439 static int snd_hdspm_info_tco_word_term(struct snd_kcontrol *kcontrol, 4440 struct snd_ctl_elem_info *uinfo) 4441 { 4442 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 4443 uinfo->count = 1; 4444 uinfo->value.integer.min = 0; 4445 uinfo->value.integer.max = 1; 4446 4447 return 0; 4448 } 4449 4450 4451 static int snd_hdspm_get_tco_word_term(struct snd_kcontrol *kcontrol, 4452 struct snd_ctl_elem_value *ucontrol) 4453 { 4454 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4455 4456 ucontrol->value.integer.value[0] = hdspm->tco->term; 4457 4458 return 0; 4459 } 4460 4461 4462 static int snd_hdspm_put_tco_word_term(struct snd_kcontrol *kcontrol, 4463 struct snd_ctl_elem_value *ucontrol) 4464 { 4465 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4466 4467 if (hdspm->tco->term != ucontrol->value.integer.value[0]) { 4468 hdspm->tco->term = ucontrol->value.integer.value[0]; 4469 4470 hdspm_tco_write(hdspm); 4471 4472 return 1; 4473 } 4474 4475 return 0; 4476 } 4477 4478 4479 4480 4481 static struct snd_kcontrol_new snd_hdspm_controls_madi[] = { 4482 HDSPM_MIXER("Mixer", 0), 4483 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4484 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 4485 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0), 4486 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0), 4487 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4488 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0), 4489 HDSPM_SYNC_CHECK("WC SyncCheck", 0), 4490 HDSPM_SYNC_CHECK("MADI SyncCheck", 1), 4491 HDSPM_SYNC_CHECK("TCO SyncCheck", 2), 4492 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 3), 4493 HDSPM_TOGGLE_SETTING("Line Out", HDSPM_LineOut), 4494 HDSPM_TOGGLE_SETTING("TX 64 channels mode", HDSPM_TX_64ch), 4495 HDSPM_TOGGLE_SETTING("Disable 96K frames", HDSPM_SMUX), 4496 HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms), 4497 HDSPM_TOGGLE_SETTING("Safe Mode", HDSPM_AutoInp), 4498 HDSPM_INPUT_SELECT("Input Select", 0), 4499 HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0) 4500 }; 4501 4502 4503 static struct snd_kcontrol_new snd_hdspm_controls_madiface[] = { 4504 HDSPM_MIXER("Mixer", 0), 4505 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4506 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 4507 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4508 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0), 4509 HDSPM_SYNC_CHECK("MADI SyncCheck", 0), 4510 HDSPM_TOGGLE_SETTING("TX 64 channels mode", HDSPM_TX_64ch), 4511 HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms), 4512 HDSPM_TOGGLE_SETTING("Safe Mode", HDSPM_AutoInp), 4513 HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0) 4514 }; 4515 4516 static struct snd_kcontrol_new snd_hdspm_controls_aio[] = { 4517 HDSPM_MIXER("Mixer", 0), 4518 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4519 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 4520 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0), 4521 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4522 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0), 4523 HDSPM_SYNC_CHECK("WC SyncCheck", 0), 4524 HDSPM_SYNC_CHECK("AES SyncCheck", 1), 4525 HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2), 4526 HDSPM_SYNC_CHECK("ADAT SyncCheck", 3), 4527 HDSPM_SYNC_CHECK("TCO SyncCheck", 4), 4528 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 5), 4529 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0), 4530 HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1), 4531 HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2), 4532 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT Frequency", 3), 4533 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 4), 4534 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 5), 4535 HDSPM_CONTROL_TRISTATE("S/PDIF Input", HDSPM_c0_Input0), 4536 HDSPM_TOGGLE_SETTING("S/PDIF Out Optical", HDSPM_c0_Spdif_Opt), 4537 HDSPM_TOGGLE_SETTING("S/PDIF Out Professional", HDSPM_c0_Pro), 4538 HDSPM_TOGGLE_SETTING("ADAT internal (AEB/TEB)", HDSPM_c0_AEB1), 4539 HDSPM_TOGGLE_SETTING("XLR Breakout Cable", HDSPM_c0_Sym6db), 4540 HDSPM_TOGGLE_SETTING("Single Speed WordClock Out", HDSPM_c0_Wck48), 4541 HDSPM_CONTROL_TRISTATE("Input Level", HDSPM_c0_AD_GAIN0), 4542 HDSPM_CONTROL_TRISTATE("Output Level", HDSPM_c0_DA_GAIN0), 4543 HDSPM_CONTROL_TRISTATE("Phones Level", HDSPM_c0_PH_GAIN0) 4544 4545 /* 4546 HDSPM_INPUT_SELECT("Input Select", 0), 4547 HDSPM_SPDIF_OPTICAL("SPDIF Out Optical", 0), 4548 HDSPM_PROFESSIONAL("SPDIF Out Professional", 0); 4549 HDSPM_SPDIF_IN("SPDIF In", 0); 4550 HDSPM_BREAKOUT_CABLE("Breakout Cable", 0); 4551 HDSPM_INPUT_LEVEL("Input Level", 0); 4552 HDSPM_OUTPUT_LEVEL("Output Level", 0); 4553 HDSPM_PHONES("Phones", 0); 4554 */ 4555 }; 4556 4557 static struct snd_kcontrol_new snd_hdspm_controls_raydat[] = { 4558 HDSPM_MIXER("Mixer", 0), 4559 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4560 HDSPM_SYSTEM_CLOCK_MODE("Clock Mode", 0), 4561 HDSPM_PREF_SYNC_REF("Pref Sync Ref", 0), 4562 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4563 HDSPM_SYNC_CHECK("WC SyncCheck", 0), 4564 HDSPM_SYNC_CHECK("AES SyncCheck", 1), 4565 HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2), 4566 HDSPM_SYNC_CHECK("ADAT1 SyncCheck", 3), 4567 HDSPM_SYNC_CHECK("ADAT2 SyncCheck", 4), 4568 HDSPM_SYNC_CHECK("ADAT3 SyncCheck", 5), 4569 HDSPM_SYNC_CHECK("ADAT4 SyncCheck", 6), 4570 HDSPM_SYNC_CHECK("TCO SyncCheck", 7), 4571 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 8), 4572 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0), 4573 HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1), 4574 HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2), 4575 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT1 Frequency", 3), 4576 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT2 Frequency", 4), 4577 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT3 Frequency", 5), 4578 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT4 Frequency", 6), 4579 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 7), 4580 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 8), 4581 HDSPM_TOGGLE_SETTING("S/PDIF Out Professional", HDSPM_c0_Pro), 4582 HDSPM_TOGGLE_SETTING("Single Speed WordClock Out", HDSPM_c0_Wck48) 4583 }; 4584 4585 static struct snd_kcontrol_new snd_hdspm_controls_aes32[] = { 4586 HDSPM_MIXER("Mixer", 0), 4587 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4588 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 4589 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0), 4590 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0), 4591 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4592 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 11), 4593 HDSPM_SYNC_CHECK("WC Sync Check", 0), 4594 HDSPM_SYNC_CHECK("AES1 Sync Check", 1), 4595 HDSPM_SYNC_CHECK("AES2 Sync Check", 2), 4596 HDSPM_SYNC_CHECK("AES3 Sync Check", 3), 4597 HDSPM_SYNC_CHECK("AES4 Sync Check", 4), 4598 HDSPM_SYNC_CHECK("AES5 Sync Check", 5), 4599 HDSPM_SYNC_CHECK("AES6 Sync Check", 6), 4600 HDSPM_SYNC_CHECK("AES7 Sync Check", 7), 4601 HDSPM_SYNC_CHECK("AES8 Sync Check", 8), 4602 HDSPM_SYNC_CHECK("TCO Sync Check", 9), 4603 HDSPM_SYNC_CHECK("SYNC IN Sync Check", 10), 4604 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0), 4605 HDSPM_AUTOSYNC_SAMPLE_RATE("AES1 Frequency", 1), 4606 HDSPM_AUTOSYNC_SAMPLE_RATE("AES2 Frequency", 2), 4607 HDSPM_AUTOSYNC_SAMPLE_RATE("AES3 Frequency", 3), 4608 HDSPM_AUTOSYNC_SAMPLE_RATE("AES4 Frequency", 4), 4609 HDSPM_AUTOSYNC_SAMPLE_RATE("AES5 Frequency", 5), 4610 HDSPM_AUTOSYNC_SAMPLE_RATE("AES6 Frequency", 6), 4611 HDSPM_AUTOSYNC_SAMPLE_RATE("AES7 Frequency", 7), 4612 HDSPM_AUTOSYNC_SAMPLE_RATE("AES8 Frequency", 8), 4613 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 9), 4614 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 10), 4615 HDSPM_TOGGLE_SETTING("Line Out", HDSPM_LineOut), 4616 HDSPM_TOGGLE_SETTING("Emphasis", HDSPM_Emphasis), 4617 HDSPM_TOGGLE_SETTING("Non Audio", HDSPM_Dolby), 4618 HDSPM_TOGGLE_SETTING("Professional", HDSPM_Professional), 4619 HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms), 4620 HDSPM_DS_WIRE("Double Speed Wire Mode", 0), 4621 HDSPM_QS_WIRE("Quad Speed Wire Mode", 0), 4622 }; 4623 4624 4625 4626 /* Control elements for the optional TCO module */ 4627 static struct snd_kcontrol_new snd_hdspm_controls_tco[] = { 4628 HDSPM_TCO_SAMPLE_RATE("TCO Sample Rate", 0), 4629 HDSPM_TCO_PULL("TCO Pull", 0), 4630 HDSPM_TCO_WCK_CONVERSION("TCO WCK Conversion", 0), 4631 HDSPM_TCO_FRAME_RATE("TCO Frame Rate", 0), 4632 HDSPM_TCO_SYNC_SOURCE("TCO Sync Source", 0), 4633 HDSPM_TCO_WORD_TERM("TCO Word Term", 0), 4634 HDSPM_TCO_LOCK_CHECK("TCO Input Check", 11), 4635 HDSPM_TCO_LOCK_CHECK("TCO LTC Valid", 12), 4636 HDSPM_TCO_LTC_FRAMES("TCO Detected Frame Rate", 0), 4637 HDSPM_TCO_VIDEO_INPUT_FORMAT("Video Input Format", 0) 4638 }; 4639 4640 4641 static struct snd_kcontrol_new snd_hdspm_playback_mixer = HDSPM_PLAYBACK_MIXER; 4642 4643 4644 static int hdspm_update_simple_mixer_controls(struct hdspm * hdspm) 4645 { 4646 int i; 4647 4648 for (i = hdspm->ds_out_channels; i < hdspm->ss_out_channels; ++i) { 4649 if (hdspm->system_sample_rate > 48000) { 4650 hdspm->playback_mixer_ctls[i]->vd[0].access = 4651 SNDRV_CTL_ELEM_ACCESS_INACTIVE | 4652 SNDRV_CTL_ELEM_ACCESS_READ | 4653 SNDRV_CTL_ELEM_ACCESS_VOLATILE; 4654 } else { 4655 hdspm->playback_mixer_ctls[i]->vd[0].access = 4656 SNDRV_CTL_ELEM_ACCESS_READWRITE | 4657 SNDRV_CTL_ELEM_ACCESS_VOLATILE; 4658 } 4659 snd_ctl_notify(hdspm->card, SNDRV_CTL_EVENT_MASK_VALUE | 4660 SNDRV_CTL_EVENT_MASK_INFO, 4661 &hdspm->playback_mixer_ctls[i]->id); 4662 } 4663 4664 return 0; 4665 } 4666 4667 4668 static int snd_hdspm_create_controls(struct snd_card *card, 4669 struct hdspm *hdspm) 4670 { 4671 unsigned int idx, limit; 4672 int err; 4673 struct snd_kcontrol *kctl; 4674 struct snd_kcontrol_new *list = NULL; 4675 4676 switch (hdspm->io_type) { 4677 case MADI: 4678 list = snd_hdspm_controls_madi; 4679 limit = ARRAY_SIZE(snd_hdspm_controls_madi); 4680 break; 4681 case MADIface: 4682 list = snd_hdspm_controls_madiface; 4683 limit = ARRAY_SIZE(snd_hdspm_controls_madiface); 4684 break; 4685 case AIO: 4686 list = snd_hdspm_controls_aio; 4687 limit = ARRAY_SIZE(snd_hdspm_controls_aio); 4688 break; 4689 case RayDAT: 4690 list = snd_hdspm_controls_raydat; 4691 limit = ARRAY_SIZE(snd_hdspm_controls_raydat); 4692 break; 4693 case AES32: 4694 list = snd_hdspm_controls_aes32; 4695 limit = ARRAY_SIZE(snd_hdspm_controls_aes32); 4696 break; 4697 } 4698 4699 if (list) { 4700 for (idx = 0; idx < limit; idx++) { 4701 err = snd_ctl_add(card, 4702 snd_ctl_new1(&list[idx], hdspm)); 4703 if (err < 0) 4704 return err; 4705 } 4706 } 4707 4708 4709 /* create simple 1:1 playback mixer controls */ 4710 snd_hdspm_playback_mixer.name = "Chn"; 4711 if (hdspm->system_sample_rate >= 128000) { 4712 limit = hdspm->qs_out_channels; 4713 } else if (hdspm->system_sample_rate >= 64000) { 4714 limit = hdspm->ds_out_channels; 4715 } else { 4716 limit = hdspm->ss_out_channels; 4717 } 4718 for (idx = 0; idx < limit; ++idx) { 4719 snd_hdspm_playback_mixer.index = idx + 1; 4720 kctl = snd_ctl_new1(&snd_hdspm_playback_mixer, hdspm); 4721 err = snd_ctl_add(card, kctl); 4722 if (err < 0) 4723 return err; 4724 hdspm->playback_mixer_ctls[idx] = kctl; 4725 } 4726 4727 4728 if (hdspm->tco) { 4729 /* add tco control elements */ 4730 list = snd_hdspm_controls_tco; 4731 limit = ARRAY_SIZE(snd_hdspm_controls_tco); 4732 for (idx = 0; idx < limit; idx++) { 4733 err = snd_ctl_add(card, 4734 snd_ctl_new1(&list[idx], hdspm)); 4735 if (err < 0) 4736 return err; 4737 } 4738 } 4739 4740 return 0; 4741 } 4742 4743 /*------------------------------------------------------------ 4744 /proc interface 4745 ------------------------------------------------------------*/ 4746 4747 static void 4748 snd_hdspm_proc_read_tco(struct snd_info_entry *entry, 4749 struct snd_info_buffer *buffer) 4750 { 4751 struct hdspm *hdspm = entry->private_data; 4752 unsigned int status, control; 4753 int a, ltc, frames, seconds, minutes, hours; 4754 unsigned int period; 4755 u64 freq_const = 0; 4756 u32 rate; 4757 4758 snd_iprintf(buffer, "--- TCO ---\n"); 4759 4760 status = hdspm_read(hdspm, HDSPM_statusRegister); 4761 control = hdspm->control_register; 4762 4763 4764 if (status & HDSPM_tco_detect) { 4765 snd_iprintf(buffer, "TCO module detected.\n"); 4766 a = hdspm_read(hdspm, HDSPM_RD_TCO+4); 4767 if (a & HDSPM_TCO1_LTC_Input_valid) { 4768 snd_iprintf(buffer, " LTC valid, "); 4769 switch (a & (HDSPM_TCO1_LTC_Format_LSB | 4770 HDSPM_TCO1_LTC_Format_MSB)) { 4771 case 0: 4772 snd_iprintf(buffer, "24 fps, "); 4773 break; 4774 case HDSPM_TCO1_LTC_Format_LSB: 4775 snd_iprintf(buffer, "25 fps, "); 4776 break; 4777 case HDSPM_TCO1_LTC_Format_MSB: 4778 snd_iprintf(buffer, "29.97 fps, "); 4779 break; 4780 default: 4781 snd_iprintf(buffer, "30 fps, "); 4782 break; 4783 } 4784 if (a & HDSPM_TCO1_set_drop_frame_flag) { 4785 snd_iprintf(buffer, "drop frame\n"); 4786 } else { 4787 snd_iprintf(buffer, "full frame\n"); 4788 } 4789 } else { 4790 snd_iprintf(buffer, " no LTC\n"); 4791 } 4792 if (a & HDSPM_TCO1_Video_Input_Format_NTSC) { 4793 snd_iprintf(buffer, " Video: NTSC\n"); 4794 } else if (a & HDSPM_TCO1_Video_Input_Format_PAL) { 4795 snd_iprintf(buffer, " Video: PAL\n"); 4796 } else { 4797 snd_iprintf(buffer, " No video\n"); 4798 } 4799 if (a & HDSPM_TCO1_TCO_lock) { 4800 snd_iprintf(buffer, " Sync: lock\n"); 4801 } else { 4802 snd_iprintf(buffer, " Sync: no lock\n"); 4803 } 4804 4805 switch (hdspm->io_type) { 4806 case MADI: 4807 case AES32: 4808 freq_const = 110069313433624ULL; 4809 break; 4810 case RayDAT: 4811 case AIO: 4812 freq_const = 104857600000000ULL; 4813 break; 4814 case MADIface: 4815 break; /* no TCO possible */ 4816 } 4817 4818 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ); 4819 snd_iprintf(buffer, " period: %u\n", period); 4820 4821 4822 /* rate = freq_const/period; */ 4823 rate = div_u64(freq_const, period); 4824 4825 if (control & HDSPM_QuadSpeed) { 4826 rate *= 4; 4827 } else if (control & HDSPM_DoubleSpeed) { 4828 rate *= 2; 4829 } 4830 4831 snd_iprintf(buffer, " Frequency: %u Hz\n", 4832 (unsigned int) rate); 4833 4834 ltc = hdspm_read(hdspm, HDSPM_RD_TCO); 4835 frames = ltc & 0xF; 4836 ltc >>= 4; 4837 frames += (ltc & 0x3) * 10; 4838 ltc >>= 4; 4839 seconds = ltc & 0xF; 4840 ltc >>= 4; 4841 seconds += (ltc & 0x7) * 10; 4842 ltc >>= 4; 4843 minutes = ltc & 0xF; 4844 ltc >>= 4; 4845 minutes += (ltc & 0x7) * 10; 4846 ltc >>= 4; 4847 hours = ltc & 0xF; 4848 ltc >>= 4; 4849 hours += (ltc & 0x3) * 10; 4850 snd_iprintf(buffer, 4851 " LTC In: %02d:%02d:%02d:%02d\n", 4852 hours, minutes, seconds, frames); 4853 4854 } else { 4855 snd_iprintf(buffer, "No TCO module detected.\n"); 4856 } 4857 } 4858 4859 static void 4860 snd_hdspm_proc_read_madi(struct snd_info_entry *entry, 4861 struct snd_info_buffer *buffer) 4862 { 4863 struct hdspm *hdspm = entry->private_data; 4864 unsigned int status, status2; 4865 4866 char *pref_sync_ref; 4867 char *autosync_ref; 4868 char *system_clock_mode; 4869 int x, x2; 4870 4871 status = hdspm_read(hdspm, HDSPM_statusRegister); 4872 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 4873 4874 snd_iprintf(buffer, "%s (Card #%d) Rev.%x Status2first3bits: %x\n", 4875 hdspm->card_name, hdspm->card->number + 1, 4876 hdspm->firmware_rev, 4877 (status2 & HDSPM_version0) | 4878 (status2 & HDSPM_version1) | (status2 & 4879 HDSPM_version2)); 4880 4881 snd_iprintf(buffer, "HW Serial: 0x%06x%06x\n", 4882 (hdspm_read(hdspm, HDSPM_midiStatusIn1)>>8) & 0xFFFFFF, 4883 hdspm->serial); 4884 4885 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n", 4886 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase); 4887 4888 snd_iprintf(buffer, "--- System ---\n"); 4889 4890 snd_iprintf(buffer, 4891 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n", 4892 status & HDSPM_audioIRQPending, 4893 (status & HDSPM_midi0IRQPending) ? 1 : 0, 4894 (status & HDSPM_midi1IRQPending) ? 1 : 0, 4895 hdspm->irq_count); 4896 snd_iprintf(buffer, 4897 "HW pointer: id = %d, rawptr = %d (%d->%d) " 4898 "estimated= %ld (bytes)\n", 4899 ((status & HDSPM_BufferID) ? 1 : 0), 4900 (status & HDSPM_BufferPositionMask), 4901 (status & HDSPM_BufferPositionMask) % 4902 (2 * (int)hdspm->period_bytes), 4903 ((status & HDSPM_BufferPositionMask) - 64) % 4904 (2 * (int)hdspm->period_bytes), 4905 (long) hdspm_hw_pointer(hdspm) * 4); 4906 4907 snd_iprintf(buffer, 4908 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n", 4909 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF, 4910 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF, 4911 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF, 4912 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF); 4913 snd_iprintf(buffer, 4914 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n", 4915 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF, 4916 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF); 4917 snd_iprintf(buffer, 4918 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, " 4919 "status2=0x%x\n", 4920 hdspm->control_register, hdspm->control2_register, 4921 status, status2); 4922 4923 4924 snd_iprintf(buffer, "--- Settings ---\n"); 4925 4926 x = hdspm_get_latency(hdspm); 4927 4928 snd_iprintf(buffer, 4929 "Size (Latency): %d samples (2 periods of %lu bytes)\n", 4930 x, (unsigned long) hdspm->period_bytes); 4931 4932 snd_iprintf(buffer, "Line out: %s\n", 4933 (hdspm->control_register & HDSPM_LineOut) ? "on " : "off"); 4934 4935 snd_iprintf(buffer, 4936 "ClearTrackMarker = %s, Transmit in %s Channel Mode, " 4937 "Auto Input %s\n", 4938 (hdspm->control_register & HDSPM_clr_tms) ? "on" : "off", 4939 (hdspm->control_register & HDSPM_TX_64ch) ? "64" : "56", 4940 (hdspm->control_register & HDSPM_AutoInp) ? "on" : "off"); 4941 4942 4943 if (!(hdspm->control_register & HDSPM_ClockModeMaster)) 4944 system_clock_mode = "AutoSync"; 4945 else 4946 system_clock_mode = "Master"; 4947 snd_iprintf(buffer, "AutoSync Reference: %s\n", system_clock_mode); 4948 4949 switch (hdspm_pref_sync_ref(hdspm)) { 4950 case HDSPM_SYNC_FROM_WORD: 4951 pref_sync_ref = "Word Clock"; 4952 break; 4953 case HDSPM_SYNC_FROM_MADI: 4954 pref_sync_ref = "MADI Sync"; 4955 break; 4956 case HDSPM_SYNC_FROM_TCO: 4957 pref_sync_ref = "TCO"; 4958 break; 4959 case HDSPM_SYNC_FROM_SYNC_IN: 4960 pref_sync_ref = "Sync In"; 4961 break; 4962 default: 4963 pref_sync_ref = "XXXX Clock"; 4964 break; 4965 } 4966 snd_iprintf(buffer, "Preferred Sync Reference: %s\n", 4967 pref_sync_ref); 4968 4969 snd_iprintf(buffer, "System Clock Frequency: %d\n", 4970 hdspm->system_sample_rate); 4971 4972 4973 snd_iprintf(buffer, "--- Status:\n"); 4974 4975 x = status & HDSPM_madiSync; 4976 x2 = status2 & HDSPM_wcSync; 4977 4978 snd_iprintf(buffer, "Inputs MADI=%s, WordClock=%s\n", 4979 (status & HDSPM_madiLock) ? (x ? "Sync" : "Lock") : 4980 "NoLock", 4981 (status2 & HDSPM_wcLock) ? (x2 ? "Sync" : "Lock") : 4982 "NoLock"); 4983 4984 switch (hdspm_autosync_ref(hdspm)) { 4985 case HDSPM_AUTOSYNC_FROM_SYNC_IN: 4986 autosync_ref = "Sync In"; 4987 break; 4988 case HDSPM_AUTOSYNC_FROM_TCO: 4989 autosync_ref = "TCO"; 4990 break; 4991 case HDSPM_AUTOSYNC_FROM_WORD: 4992 autosync_ref = "Word Clock"; 4993 break; 4994 case HDSPM_AUTOSYNC_FROM_MADI: 4995 autosync_ref = "MADI Sync"; 4996 break; 4997 case HDSPM_AUTOSYNC_FROM_NONE: 4998 autosync_ref = "Input not valid"; 4999 break; 5000 default: 5001 autosync_ref = "---"; 5002 break; 5003 } 5004 snd_iprintf(buffer, 5005 "AutoSync: Reference= %s, Freq=%d (MADI = %d, Word = %d)\n", 5006 autosync_ref, hdspm_external_sample_rate(hdspm), 5007 (status & HDSPM_madiFreqMask) >> 22, 5008 (status2 & HDSPM_wcFreqMask) >> 5); 5009 5010 snd_iprintf(buffer, "Input: %s, Mode=%s\n", 5011 (status & HDSPM_AB_int) ? "Coax" : "Optical", 5012 (status & HDSPM_RX_64ch) ? "64 channels" : 5013 "56 channels"); 5014 5015 /* call readout function for TCO specific status */ 5016 snd_hdspm_proc_read_tco(entry, buffer); 5017 5018 snd_iprintf(buffer, "\n"); 5019 } 5020 5021 static void 5022 snd_hdspm_proc_read_aes32(struct snd_info_entry * entry, 5023 struct snd_info_buffer *buffer) 5024 { 5025 struct hdspm *hdspm = entry->private_data; 5026 unsigned int status; 5027 unsigned int status2; 5028 unsigned int timecode; 5029 unsigned int wcLock, wcSync; 5030 int pref_syncref; 5031 char *autosync_ref; 5032 int x; 5033 5034 status = hdspm_read(hdspm, HDSPM_statusRegister); 5035 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 5036 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister); 5037 5038 snd_iprintf(buffer, "%s (Card #%d) Rev.%x\n", 5039 hdspm->card_name, hdspm->card->number + 1, 5040 hdspm->firmware_rev); 5041 5042 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n", 5043 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase); 5044 5045 snd_iprintf(buffer, "--- System ---\n"); 5046 5047 snd_iprintf(buffer, 5048 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n", 5049 status & HDSPM_audioIRQPending, 5050 (status & HDSPM_midi0IRQPending) ? 1 : 0, 5051 (status & HDSPM_midi1IRQPending) ? 1 : 0, 5052 hdspm->irq_count); 5053 snd_iprintf(buffer, 5054 "HW pointer: id = %d, rawptr = %d (%d->%d) " 5055 "estimated= %ld (bytes)\n", 5056 ((status & HDSPM_BufferID) ? 1 : 0), 5057 (status & HDSPM_BufferPositionMask), 5058 (status & HDSPM_BufferPositionMask) % 5059 (2 * (int)hdspm->period_bytes), 5060 ((status & HDSPM_BufferPositionMask) - 64) % 5061 (2 * (int)hdspm->period_bytes), 5062 (long) hdspm_hw_pointer(hdspm) * 4); 5063 5064 snd_iprintf(buffer, 5065 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n", 5066 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF, 5067 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF, 5068 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF, 5069 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF); 5070 snd_iprintf(buffer, 5071 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n", 5072 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF, 5073 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF); 5074 snd_iprintf(buffer, 5075 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, " 5076 "status2=0x%x\n", 5077 hdspm->control_register, hdspm->control2_register, 5078 status, status2); 5079 5080 snd_iprintf(buffer, "--- Settings ---\n"); 5081 5082 x = hdspm_get_latency(hdspm); 5083 5084 snd_iprintf(buffer, 5085 "Size (Latency): %d samples (2 periods of %lu bytes)\n", 5086 x, (unsigned long) hdspm->period_bytes); 5087 5088 snd_iprintf(buffer, "Line out: %s\n", 5089 (hdspm-> 5090 control_register & HDSPM_LineOut) ? "on " : "off"); 5091 5092 snd_iprintf(buffer, 5093 "ClearTrackMarker %s, Emphasis %s, Dolby %s\n", 5094 (hdspm-> 5095 control_register & HDSPM_clr_tms) ? "on" : "off", 5096 (hdspm-> 5097 control_register & HDSPM_Emphasis) ? "on" : "off", 5098 (hdspm-> 5099 control_register & HDSPM_Dolby) ? "on" : "off"); 5100 5101 5102 pref_syncref = hdspm_pref_sync_ref(hdspm); 5103 if (pref_syncref == 0) 5104 snd_iprintf(buffer, "Preferred Sync Reference: Word Clock\n"); 5105 else 5106 snd_iprintf(buffer, "Preferred Sync Reference: AES%d\n", 5107 pref_syncref); 5108 5109 snd_iprintf(buffer, "System Clock Frequency: %d\n", 5110 hdspm->system_sample_rate); 5111 5112 snd_iprintf(buffer, "Double speed: %s\n", 5113 hdspm->control_register & HDSPM_DS_DoubleWire? 5114 "Double wire" : "Single wire"); 5115 snd_iprintf(buffer, "Quad speed: %s\n", 5116 hdspm->control_register & HDSPM_QS_DoubleWire? 5117 "Double wire" : 5118 hdspm->control_register & HDSPM_QS_QuadWire? 5119 "Quad wire" : "Single wire"); 5120 5121 snd_iprintf(buffer, "--- Status:\n"); 5122 5123 wcLock = status & HDSPM_AES32_wcLock; 5124 wcSync = wcLock && (status & HDSPM_AES32_wcSync); 5125 5126 snd_iprintf(buffer, "Word: %s Frequency: %d\n", 5127 (wcLock) ? (wcSync ? "Sync " : "Lock ") : "No Lock", 5128 HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF)); 5129 5130 for (x = 0; x < 8; x++) { 5131 snd_iprintf(buffer, "AES%d: %s Frequency: %d\n", 5132 x+1, 5133 (status2 & (HDSPM_LockAES >> x)) ? 5134 "Sync " : "No Lock", 5135 HDSPM_bit2freq((timecode >> (4*x)) & 0xF)); 5136 } 5137 5138 switch (hdspm_autosync_ref(hdspm)) { 5139 case HDSPM_AES32_AUTOSYNC_FROM_NONE: 5140 autosync_ref = "None"; break; 5141 case HDSPM_AES32_AUTOSYNC_FROM_WORD: 5142 autosync_ref = "Word Clock"; break; 5143 case HDSPM_AES32_AUTOSYNC_FROM_AES1: 5144 autosync_ref = "AES1"; break; 5145 case HDSPM_AES32_AUTOSYNC_FROM_AES2: 5146 autosync_ref = "AES2"; break; 5147 case HDSPM_AES32_AUTOSYNC_FROM_AES3: 5148 autosync_ref = "AES3"; break; 5149 case HDSPM_AES32_AUTOSYNC_FROM_AES4: 5150 autosync_ref = "AES4"; break; 5151 case HDSPM_AES32_AUTOSYNC_FROM_AES5: 5152 autosync_ref = "AES5"; break; 5153 case HDSPM_AES32_AUTOSYNC_FROM_AES6: 5154 autosync_ref = "AES6"; break; 5155 case HDSPM_AES32_AUTOSYNC_FROM_AES7: 5156 autosync_ref = "AES7"; break; 5157 case HDSPM_AES32_AUTOSYNC_FROM_AES8: 5158 autosync_ref = "AES8"; break; 5159 case HDSPM_AES32_AUTOSYNC_FROM_TCO: 5160 autosync_ref = "TCO"; break; 5161 case HDSPM_AES32_AUTOSYNC_FROM_SYNC_IN: 5162 autosync_ref = "Sync In"; break; 5163 default: 5164 autosync_ref = "---"; break; 5165 } 5166 snd_iprintf(buffer, "AutoSync ref = %s\n", autosync_ref); 5167 5168 /* call readout function for TCO specific status */ 5169 snd_hdspm_proc_read_tco(entry, buffer); 5170 5171 snd_iprintf(buffer, "\n"); 5172 } 5173 5174 static void 5175 snd_hdspm_proc_read_raydat(struct snd_info_entry *entry, 5176 struct snd_info_buffer *buffer) 5177 { 5178 struct hdspm *hdspm = entry->private_data; 5179 unsigned int status1, status2, status3, i; 5180 unsigned int lock, sync; 5181 5182 status1 = hdspm_read(hdspm, HDSPM_RD_STATUS_1); /* s1 */ 5183 status2 = hdspm_read(hdspm, HDSPM_RD_STATUS_2); /* freq */ 5184 status3 = hdspm_read(hdspm, HDSPM_RD_STATUS_3); /* s2 */ 5185 5186 snd_iprintf(buffer, "STATUS1: 0x%08x\n", status1); 5187 snd_iprintf(buffer, "STATUS2: 0x%08x\n", status2); 5188 snd_iprintf(buffer, "STATUS3: 0x%08x\n", status3); 5189 5190 5191 snd_iprintf(buffer, "\n*** CLOCK MODE\n\n"); 5192 5193 snd_iprintf(buffer, "Clock mode : %s\n", 5194 (hdspm_system_clock_mode(hdspm) == 0) ? "master" : "slave"); 5195 snd_iprintf(buffer, "System frequency: %d Hz\n", 5196 hdspm_get_system_sample_rate(hdspm)); 5197 5198 snd_iprintf(buffer, "\n*** INPUT STATUS\n\n"); 5199 5200 lock = 0x1; 5201 sync = 0x100; 5202 5203 for (i = 0; i < 8; i++) { 5204 snd_iprintf(buffer, "s1_input %d: Lock %d, Sync %d, Freq %s\n", 5205 i, 5206 (status1 & lock) ? 1 : 0, 5207 (status1 & sync) ? 1 : 0, 5208 texts_freq[(status2 >> (i * 4)) & 0xF]); 5209 5210 lock = lock<<1; 5211 sync = sync<<1; 5212 } 5213 5214 snd_iprintf(buffer, "WC input: Lock %d, Sync %d, Freq %s\n", 5215 (status1 & 0x1000000) ? 1 : 0, 5216 (status1 & 0x2000000) ? 1 : 0, 5217 texts_freq[(status1 >> 16) & 0xF]); 5218 5219 snd_iprintf(buffer, "TCO input: Lock %d, Sync %d, Freq %s\n", 5220 (status1 & 0x4000000) ? 1 : 0, 5221 (status1 & 0x8000000) ? 1 : 0, 5222 texts_freq[(status1 >> 20) & 0xF]); 5223 5224 snd_iprintf(buffer, "SYNC IN: Lock %d, Sync %d, Freq %s\n", 5225 (status3 & 0x400) ? 1 : 0, 5226 (status3 & 0x800) ? 1 : 0, 5227 texts_freq[(status2 >> 12) & 0xF]); 5228 5229 } 5230 5231 #ifdef CONFIG_SND_DEBUG 5232 static void 5233 snd_hdspm_proc_read_debug(struct snd_info_entry *entry, 5234 struct snd_info_buffer *buffer) 5235 { 5236 struct hdspm *hdspm = entry->private_data; 5237 5238 int j,i; 5239 5240 for (i = 0; i < 256 /* 1024*64 */; i += j) { 5241 snd_iprintf(buffer, "0x%08X: ", i); 5242 for (j = 0; j < 16; j += 4) 5243 snd_iprintf(buffer, "%08X ", hdspm_read(hdspm, i + j)); 5244 snd_iprintf(buffer, "\n"); 5245 } 5246 } 5247 #endif 5248 5249 5250 static void snd_hdspm_proc_ports_in(struct snd_info_entry *entry, 5251 struct snd_info_buffer *buffer) 5252 { 5253 struct hdspm *hdspm = entry->private_data; 5254 int i; 5255 5256 snd_iprintf(buffer, "# generated by hdspm\n"); 5257 5258 for (i = 0; i < hdspm->max_channels_in; i++) { 5259 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_in[i]); 5260 } 5261 } 5262 5263 static void snd_hdspm_proc_ports_out(struct snd_info_entry *entry, 5264 struct snd_info_buffer *buffer) 5265 { 5266 struct hdspm *hdspm = entry->private_data; 5267 int i; 5268 5269 snd_iprintf(buffer, "# generated by hdspm\n"); 5270 5271 for (i = 0; i < hdspm->max_channels_out; i++) { 5272 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_out[i]); 5273 } 5274 } 5275 5276 5277 static void snd_hdspm_proc_init(struct hdspm *hdspm) 5278 { 5279 void (*read)(struct snd_info_entry *, struct snd_info_buffer *) = NULL; 5280 5281 switch (hdspm->io_type) { 5282 case AES32: 5283 read = snd_hdspm_proc_read_aes32; 5284 break; 5285 case MADI: 5286 read = snd_hdspm_proc_read_madi; 5287 break; 5288 case MADIface: 5289 /* read = snd_hdspm_proc_read_madiface; */ 5290 break; 5291 case RayDAT: 5292 read = snd_hdspm_proc_read_raydat; 5293 break; 5294 case AIO: 5295 break; 5296 } 5297 5298 snd_card_ro_proc_new(hdspm->card, "hdspm", hdspm, read); 5299 snd_card_ro_proc_new(hdspm->card, "ports.in", hdspm, 5300 snd_hdspm_proc_ports_in); 5301 snd_card_ro_proc_new(hdspm->card, "ports.out", hdspm, 5302 snd_hdspm_proc_ports_out); 5303 5304 #ifdef CONFIG_SND_DEBUG 5305 /* debug file to read all hdspm registers */ 5306 snd_card_ro_proc_new(hdspm->card, "debug", hdspm, 5307 snd_hdspm_proc_read_debug); 5308 #endif 5309 } 5310 5311 /*------------------------------------------------------------ 5312 hdspm intitialize 5313 ------------------------------------------------------------*/ 5314 5315 static int snd_hdspm_set_defaults(struct hdspm * hdspm) 5316 { 5317 /* ASSUMPTION: hdspm->lock is either held, or there is no need to 5318 hold it (e.g. during module initialization). 5319 */ 5320 5321 /* set defaults: */ 5322 5323 hdspm->settings_register = 0; 5324 5325 switch (hdspm->io_type) { 5326 case MADI: 5327 case MADIface: 5328 hdspm->control_register = 5329 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000; 5330 break; 5331 5332 case RayDAT: 5333 case AIO: 5334 hdspm->settings_register = 0x1 + 0x1000; 5335 /* Magic values are: LAT_0, LAT_2, Master, freq1, tx64ch, inp_0, 5336 * line_out */ 5337 hdspm->control_register = 5338 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000; 5339 break; 5340 5341 case AES32: 5342 hdspm->control_register = 5343 HDSPM_ClockModeMaster | /* Master Clock Mode on */ 5344 hdspm_encode_latency(7) | /* latency max=8192samples */ 5345 HDSPM_SyncRef0 | /* AES1 is syncclock */ 5346 HDSPM_LineOut | /* Analog output in */ 5347 HDSPM_Professional; /* Professional mode */ 5348 break; 5349 } 5350 5351 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 5352 5353 if (AES32 == hdspm->io_type) { 5354 /* No control2 register for AES32 */ 5355 #ifdef SNDRV_BIG_ENDIAN 5356 hdspm->control2_register = HDSPM_BIGENDIAN_MODE; 5357 #else 5358 hdspm->control2_register = 0; 5359 #endif 5360 5361 hdspm_write(hdspm, HDSPM_control2Reg, hdspm->control2_register); 5362 } 5363 hdspm_compute_period_size(hdspm); 5364 5365 /* silence everything */ 5366 5367 all_in_all_mixer(hdspm, 0 * UNITY_GAIN); 5368 5369 if (hdspm_is_raydat_or_aio(hdspm)) 5370 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register); 5371 5372 /* set a default rate so that the channel map is set up. */ 5373 hdspm_set_rate(hdspm, 48000, 1); 5374 5375 return 0; 5376 } 5377 5378 5379 /*------------------------------------------------------------ 5380 interrupt 5381 ------------------------------------------------------------*/ 5382 5383 static irqreturn_t snd_hdspm_interrupt(int irq, void *dev_id) 5384 { 5385 struct hdspm *hdspm = (struct hdspm *) dev_id; 5386 unsigned int status; 5387 int i, audio, midi, schedule = 0; 5388 /* cycles_t now; */ 5389 5390 status = hdspm_read(hdspm, HDSPM_statusRegister); 5391 5392 audio = status & HDSPM_audioIRQPending; 5393 midi = status & (HDSPM_midi0IRQPending | HDSPM_midi1IRQPending | 5394 HDSPM_midi2IRQPending | HDSPM_midi3IRQPending); 5395 5396 /* now = get_cycles(); */ 5397 /* 5398 * LAT_2..LAT_0 period counter (win) counter (mac) 5399 * 6 4096 ~256053425 ~514672358 5400 * 5 2048 ~128024983 ~257373821 5401 * 4 1024 ~64023706 ~128718089 5402 * 3 512 ~32005945 ~64385999 5403 * 2 256 ~16003039 ~32260176 5404 * 1 128 ~7998738 ~16194507 5405 * 0 64 ~3998231 ~8191558 5406 */ 5407 /* 5408 dev_info(hdspm->card->dev, "snd_hdspm_interrupt %llu @ %llx\n", 5409 now-hdspm->last_interrupt, status & 0xFFC0); 5410 hdspm->last_interrupt = now; 5411 */ 5412 5413 if (!audio && !midi) 5414 return IRQ_NONE; 5415 5416 hdspm_write(hdspm, HDSPM_interruptConfirmation, 0); 5417 hdspm->irq_count++; 5418 5419 5420 if (audio) { 5421 if (hdspm->capture_substream) 5422 snd_pcm_period_elapsed(hdspm->capture_substream); 5423 5424 if (hdspm->playback_substream) 5425 snd_pcm_period_elapsed(hdspm->playback_substream); 5426 } 5427 5428 if (midi) { 5429 i = 0; 5430 while (i < hdspm->midiPorts) { 5431 if ((hdspm_read(hdspm, 5432 hdspm->midi[i].statusIn) & 0xff) && 5433 (status & hdspm->midi[i].irq)) { 5434 /* we disable interrupts for this input until 5435 * processing is done 5436 */ 5437 hdspm->control_register &= ~hdspm->midi[i].ie; 5438 hdspm_write(hdspm, HDSPM_controlRegister, 5439 hdspm->control_register); 5440 hdspm->midi[i].pending = 1; 5441 schedule = 1; 5442 } 5443 5444 i++; 5445 } 5446 5447 if (schedule) 5448 tasklet_hi_schedule(&hdspm->midi_tasklet); 5449 } 5450 5451 return IRQ_HANDLED; 5452 } 5453 5454 /*------------------------------------------------------------ 5455 pcm interface 5456 ------------------------------------------------------------*/ 5457 5458 5459 static snd_pcm_uframes_t snd_hdspm_hw_pointer(struct snd_pcm_substream 5460 *substream) 5461 { 5462 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5463 return hdspm_hw_pointer(hdspm); 5464 } 5465 5466 5467 static int snd_hdspm_reset(struct snd_pcm_substream *substream) 5468 { 5469 struct snd_pcm_runtime *runtime = substream->runtime; 5470 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5471 struct snd_pcm_substream *other; 5472 5473 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 5474 other = hdspm->capture_substream; 5475 else 5476 other = hdspm->playback_substream; 5477 5478 if (hdspm->running) 5479 runtime->status->hw_ptr = hdspm_hw_pointer(hdspm); 5480 else 5481 runtime->status->hw_ptr = 0; 5482 if (other) { 5483 struct snd_pcm_substream *s; 5484 struct snd_pcm_runtime *oruntime = other->runtime; 5485 snd_pcm_group_for_each_entry(s, substream) { 5486 if (s == other) { 5487 oruntime->status->hw_ptr = 5488 runtime->status->hw_ptr; 5489 break; 5490 } 5491 } 5492 } 5493 return 0; 5494 } 5495 5496 static int snd_hdspm_hw_params(struct snd_pcm_substream *substream, 5497 struct snd_pcm_hw_params *params) 5498 { 5499 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5500 int err; 5501 int i; 5502 pid_t this_pid; 5503 pid_t other_pid; 5504 5505 spin_lock_irq(&hdspm->lock); 5506 5507 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5508 this_pid = hdspm->playback_pid; 5509 other_pid = hdspm->capture_pid; 5510 } else { 5511 this_pid = hdspm->capture_pid; 5512 other_pid = hdspm->playback_pid; 5513 } 5514 5515 if (other_pid > 0 && this_pid != other_pid) { 5516 5517 /* The other stream is open, and not by the same 5518 task as this one. Make sure that the parameters 5519 that matter are the same. 5520 */ 5521 5522 if (params_rate(params) != hdspm->system_sample_rate) { 5523 spin_unlock_irq(&hdspm->lock); 5524 _snd_pcm_hw_param_setempty(params, 5525 SNDRV_PCM_HW_PARAM_RATE); 5526 return -EBUSY; 5527 } 5528 5529 if (params_period_size(params) != hdspm->period_bytes / 4) { 5530 spin_unlock_irq(&hdspm->lock); 5531 _snd_pcm_hw_param_setempty(params, 5532 SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 5533 return -EBUSY; 5534 } 5535 5536 } 5537 /* We're fine. */ 5538 spin_unlock_irq(&hdspm->lock); 5539 5540 /* how to make sure that the rate matches an externally-set one ? */ 5541 5542 spin_lock_irq(&hdspm->lock); 5543 err = hdspm_set_rate(hdspm, params_rate(params), 0); 5544 if (err < 0) { 5545 dev_info(hdspm->card->dev, "err on hdspm_set_rate: %d\n", err); 5546 spin_unlock_irq(&hdspm->lock); 5547 _snd_pcm_hw_param_setempty(params, 5548 SNDRV_PCM_HW_PARAM_RATE); 5549 return err; 5550 } 5551 spin_unlock_irq(&hdspm->lock); 5552 5553 err = hdspm_set_interrupt_interval(hdspm, 5554 params_period_size(params)); 5555 if (err < 0) { 5556 dev_info(hdspm->card->dev, 5557 "err on hdspm_set_interrupt_interval: %d\n", err); 5558 _snd_pcm_hw_param_setempty(params, 5559 SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 5560 return err; 5561 } 5562 5563 /* Memory allocation, takashi's method, dont know if we should 5564 * spinlock 5565 */ 5566 /* malloc all buffer even if not enabled to get sure */ 5567 /* Update for MADI rev 204: we need to allocate for all channels, 5568 * otherwise it doesn't work at 96kHz */ 5569 5570 err = 5571 snd_pcm_lib_malloc_pages(substream, HDSPM_DMA_AREA_BYTES); 5572 if (err < 0) { 5573 dev_info(hdspm->card->dev, 5574 "err on snd_pcm_lib_malloc_pages: %d\n", err); 5575 return err; 5576 } 5577 5578 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5579 5580 for (i = 0; i < params_channels(params); ++i) { 5581 int c = hdspm->channel_map_out[i]; 5582 5583 if (c < 0) 5584 continue; /* just make sure */ 5585 hdspm_set_channel_dma_addr(hdspm, substream, 5586 HDSPM_pageAddressBufferOut, 5587 c); 5588 snd_hdspm_enable_out(hdspm, c, 1); 5589 } 5590 5591 hdspm->playback_buffer = 5592 (unsigned char *) substream->runtime->dma_area; 5593 dev_dbg(hdspm->card->dev, 5594 "Allocated sample buffer for playback at %p\n", 5595 hdspm->playback_buffer); 5596 } else { 5597 for (i = 0; i < params_channels(params); ++i) { 5598 int c = hdspm->channel_map_in[i]; 5599 5600 if (c < 0) 5601 continue; 5602 hdspm_set_channel_dma_addr(hdspm, substream, 5603 HDSPM_pageAddressBufferIn, 5604 c); 5605 snd_hdspm_enable_in(hdspm, c, 1); 5606 } 5607 5608 hdspm->capture_buffer = 5609 (unsigned char *) substream->runtime->dma_area; 5610 dev_dbg(hdspm->card->dev, 5611 "Allocated sample buffer for capture at %p\n", 5612 hdspm->capture_buffer); 5613 } 5614 5615 /* 5616 dev_dbg(hdspm->card->dev, 5617 "Allocated sample buffer for %s at 0x%08X\n", 5618 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 5619 "playback" : "capture", 5620 snd_pcm_sgbuf_get_addr(substream, 0)); 5621 */ 5622 /* 5623 dev_dbg(hdspm->card->dev, 5624 "set_hwparams: %s %d Hz, %d channels, bs = %d\n", 5625 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 5626 "playback" : "capture", 5627 params_rate(params), params_channels(params), 5628 params_buffer_size(params)); 5629 */ 5630 5631 5632 /* For AES cards, the float format bit is the same as the 5633 * preferred sync reference. Since we don't want to break 5634 * sync settings, we have to skip the remaining part of this 5635 * function. 5636 */ 5637 if (hdspm->io_type == AES32) { 5638 return 0; 5639 } 5640 5641 5642 /* Switch to native float format if requested */ 5643 if (SNDRV_PCM_FORMAT_FLOAT_LE == params_format(params)) { 5644 if (!(hdspm->control_register & HDSPe_FLOAT_FORMAT)) 5645 dev_info(hdspm->card->dev, 5646 "Switching to native 32bit LE float format.\n"); 5647 5648 hdspm->control_register |= HDSPe_FLOAT_FORMAT; 5649 } else if (SNDRV_PCM_FORMAT_S32_LE == params_format(params)) { 5650 if (hdspm->control_register & HDSPe_FLOAT_FORMAT) 5651 dev_info(hdspm->card->dev, 5652 "Switching to native 32bit LE integer format.\n"); 5653 5654 hdspm->control_register &= ~HDSPe_FLOAT_FORMAT; 5655 } 5656 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 5657 5658 return 0; 5659 } 5660 5661 static int snd_hdspm_hw_free(struct snd_pcm_substream *substream) 5662 { 5663 int i; 5664 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5665 5666 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5667 /* Just disable all channels. The saving when disabling a */ 5668 /* smaller set is not worth the trouble. */ 5669 for (i = 0; i < HDSPM_MAX_CHANNELS; ++i) 5670 snd_hdspm_enable_out(hdspm, i, 0); 5671 5672 hdspm->playback_buffer = NULL; 5673 } else { 5674 for (i = 0; i < HDSPM_MAX_CHANNELS; ++i) 5675 snd_hdspm_enable_in(hdspm, i, 0); 5676 5677 hdspm->capture_buffer = NULL; 5678 } 5679 5680 snd_pcm_lib_free_pages(substream); 5681 5682 return 0; 5683 } 5684 5685 5686 static int snd_hdspm_channel_info(struct snd_pcm_substream *substream, 5687 struct snd_pcm_channel_info *info) 5688 { 5689 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5690 unsigned int channel = info->channel; 5691 5692 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5693 if (snd_BUG_ON(channel >= hdspm->max_channels_out)) { 5694 dev_info(hdspm->card->dev, 5695 "snd_hdspm_channel_info: output channel out of range (%d)\n", 5696 channel); 5697 return -EINVAL; 5698 } 5699 5700 channel = array_index_nospec(channel, hdspm->max_channels_out); 5701 if (hdspm->channel_map_out[channel] < 0) { 5702 dev_info(hdspm->card->dev, 5703 "snd_hdspm_channel_info: output channel %d mapped out\n", 5704 channel); 5705 return -EINVAL; 5706 } 5707 5708 info->offset = hdspm->channel_map_out[channel] * 5709 HDSPM_CHANNEL_BUFFER_BYTES; 5710 } else { 5711 if (snd_BUG_ON(channel >= hdspm->max_channels_in)) { 5712 dev_info(hdspm->card->dev, 5713 "snd_hdspm_channel_info: input channel out of range (%d)\n", 5714 channel); 5715 return -EINVAL; 5716 } 5717 5718 channel = array_index_nospec(channel, hdspm->max_channels_in); 5719 if (hdspm->channel_map_in[channel] < 0) { 5720 dev_info(hdspm->card->dev, 5721 "snd_hdspm_channel_info: input channel %d mapped out\n", 5722 channel); 5723 return -EINVAL; 5724 } 5725 5726 info->offset = hdspm->channel_map_in[channel] * 5727 HDSPM_CHANNEL_BUFFER_BYTES; 5728 } 5729 5730 info->first = 0; 5731 info->step = 32; 5732 return 0; 5733 } 5734 5735 5736 static int snd_hdspm_ioctl(struct snd_pcm_substream *substream, 5737 unsigned int cmd, void *arg) 5738 { 5739 switch (cmd) { 5740 case SNDRV_PCM_IOCTL1_RESET: 5741 return snd_hdspm_reset(substream); 5742 5743 case SNDRV_PCM_IOCTL1_CHANNEL_INFO: 5744 { 5745 struct snd_pcm_channel_info *info = arg; 5746 return snd_hdspm_channel_info(substream, info); 5747 } 5748 default: 5749 break; 5750 } 5751 5752 return snd_pcm_lib_ioctl(substream, cmd, arg); 5753 } 5754 5755 static int snd_hdspm_trigger(struct snd_pcm_substream *substream, int cmd) 5756 { 5757 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5758 struct snd_pcm_substream *other; 5759 int running; 5760 5761 spin_lock(&hdspm->lock); 5762 running = hdspm->running; 5763 switch (cmd) { 5764 case SNDRV_PCM_TRIGGER_START: 5765 running |= 1 << substream->stream; 5766 break; 5767 case SNDRV_PCM_TRIGGER_STOP: 5768 running &= ~(1 << substream->stream); 5769 break; 5770 default: 5771 snd_BUG(); 5772 spin_unlock(&hdspm->lock); 5773 return -EINVAL; 5774 } 5775 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 5776 other = hdspm->capture_substream; 5777 else 5778 other = hdspm->playback_substream; 5779 5780 if (other) { 5781 struct snd_pcm_substream *s; 5782 snd_pcm_group_for_each_entry(s, substream) { 5783 if (s == other) { 5784 snd_pcm_trigger_done(s, substream); 5785 if (cmd == SNDRV_PCM_TRIGGER_START) 5786 running |= 1 << s->stream; 5787 else 5788 running &= ~(1 << s->stream); 5789 goto _ok; 5790 } 5791 } 5792 if (cmd == SNDRV_PCM_TRIGGER_START) { 5793 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) 5794 && substream->stream == 5795 SNDRV_PCM_STREAM_CAPTURE) 5796 hdspm_silence_playback(hdspm); 5797 } else { 5798 if (running && 5799 substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 5800 hdspm_silence_playback(hdspm); 5801 } 5802 } else { 5803 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 5804 hdspm_silence_playback(hdspm); 5805 } 5806 _ok: 5807 snd_pcm_trigger_done(substream, substream); 5808 if (!hdspm->running && running) 5809 hdspm_start_audio(hdspm); 5810 else if (hdspm->running && !running) 5811 hdspm_stop_audio(hdspm); 5812 hdspm->running = running; 5813 spin_unlock(&hdspm->lock); 5814 5815 return 0; 5816 } 5817 5818 static int snd_hdspm_prepare(struct snd_pcm_substream *substream) 5819 { 5820 return 0; 5821 } 5822 5823 static struct snd_pcm_hardware snd_hdspm_playback_subinfo = { 5824 .info = (SNDRV_PCM_INFO_MMAP | 5825 SNDRV_PCM_INFO_MMAP_VALID | 5826 SNDRV_PCM_INFO_NONINTERLEAVED | 5827 SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_DOUBLE), 5828 .formats = SNDRV_PCM_FMTBIT_S32_LE, 5829 .rates = (SNDRV_PCM_RATE_32000 | 5830 SNDRV_PCM_RATE_44100 | 5831 SNDRV_PCM_RATE_48000 | 5832 SNDRV_PCM_RATE_64000 | 5833 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | 5834 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000 ), 5835 .rate_min = 32000, 5836 .rate_max = 192000, 5837 .channels_min = 1, 5838 .channels_max = HDSPM_MAX_CHANNELS, 5839 .buffer_bytes_max = 5840 HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS, 5841 .period_bytes_min = (32 * 4), 5842 .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS, 5843 .periods_min = 2, 5844 .periods_max = 512, 5845 .fifo_size = 0 5846 }; 5847 5848 static struct snd_pcm_hardware snd_hdspm_capture_subinfo = { 5849 .info = (SNDRV_PCM_INFO_MMAP | 5850 SNDRV_PCM_INFO_MMAP_VALID | 5851 SNDRV_PCM_INFO_NONINTERLEAVED | 5852 SNDRV_PCM_INFO_SYNC_START), 5853 .formats = SNDRV_PCM_FMTBIT_S32_LE, 5854 .rates = (SNDRV_PCM_RATE_32000 | 5855 SNDRV_PCM_RATE_44100 | 5856 SNDRV_PCM_RATE_48000 | 5857 SNDRV_PCM_RATE_64000 | 5858 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | 5859 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000), 5860 .rate_min = 32000, 5861 .rate_max = 192000, 5862 .channels_min = 1, 5863 .channels_max = HDSPM_MAX_CHANNELS, 5864 .buffer_bytes_max = 5865 HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS, 5866 .period_bytes_min = (32 * 4), 5867 .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS, 5868 .periods_min = 2, 5869 .periods_max = 512, 5870 .fifo_size = 0 5871 }; 5872 5873 static int snd_hdspm_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params, 5874 struct snd_pcm_hw_rule *rule) 5875 { 5876 struct hdspm *hdspm = rule->private; 5877 struct snd_interval *c = 5878 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 5879 struct snd_interval *r = 5880 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 5881 5882 if (r->min > 96000 && r->max <= 192000) { 5883 struct snd_interval t = { 5884 .min = hdspm->qs_in_channels, 5885 .max = hdspm->qs_in_channels, 5886 .integer = 1, 5887 }; 5888 return snd_interval_refine(c, &t); 5889 } else if (r->min > 48000 && r->max <= 96000) { 5890 struct snd_interval t = { 5891 .min = hdspm->ds_in_channels, 5892 .max = hdspm->ds_in_channels, 5893 .integer = 1, 5894 }; 5895 return snd_interval_refine(c, &t); 5896 } else if (r->max < 64000) { 5897 struct snd_interval t = { 5898 .min = hdspm->ss_in_channels, 5899 .max = hdspm->ss_in_channels, 5900 .integer = 1, 5901 }; 5902 return snd_interval_refine(c, &t); 5903 } 5904 5905 return 0; 5906 } 5907 5908 static int snd_hdspm_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params, 5909 struct snd_pcm_hw_rule * rule) 5910 { 5911 struct hdspm *hdspm = rule->private; 5912 struct snd_interval *c = 5913 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 5914 struct snd_interval *r = 5915 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 5916 5917 if (r->min > 96000 && r->max <= 192000) { 5918 struct snd_interval t = { 5919 .min = hdspm->qs_out_channels, 5920 .max = hdspm->qs_out_channels, 5921 .integer = 1, 5922 }; 5923 return snd_interval_refine(c, &t); 5924 } else if (r->min > 48000 && r->max <= 96000) { 5925 struct snd_interval t = { 5926 .min = hdspm->ds_out_channels, 5927 .max = hdspm->ds_out_channels, 5928 .integer = 1, 5929 }; 5930 return snd_interval_refine(c, &t); 5931 } else if (r->max < 64000) { 5932 struct snd_interval t = { 5933 .min = hdspm->ss_out_channels, 5934 .max = hdspm->ss_out_channels, 5935 .integer = 1, 5936 }; 5937 return snd_interval_refine(c, &t); 5938 } else { 5939 } 5940 return 0; 5941 } 5942 5943 static int snd_hdspm_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params, 5944 struct snd_pcm_hw_rule * rule) 5945 { 5946 struct hdspm *hdspm = rule->private; 5947 struct snd_interval *c = 5948 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 5949 struct snd_interval *r = 5950 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 5951 5952 if (c->min >= hdspm->ss_in_channels) { 5953 struct snd_interval t = { 5954 .min = 32000, 5955 .max = 48000, 5956 .integer = 1, 5957 }; 5958 return snd_interval_refine(r, &t); 5959 } else if (c->max <= hdspm->qs_in_channels) { 5960 struct snd_interval t = { 5961 .min = 128000, 5962 .max = 192000, 5963 .integer = 1, 5964 }; 5965 return snd_interval_refine(r, &t); 5966 } else if (c->max <= hdspm->ds_in_channels) { 5967 struct snd_interval t = { 5968 .min = 64000, 5969 .max = 96000, 5970 .integer = 1, 5971 }; 5972 return snd_interval_refine(r, &t); 5973 } 5974 5975 return 0; 5976 } 5977 static int snd_hdspm_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params, 5978 struct snd_pcm_hw_rule *rule) 5979 { 5980 struct hdspm *hdspm = rule->private; 5981 struct snd_interval *c = 5982 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 5983 struct snd_interval *r = 5984 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 5985 5986 if (c->min >= hdspm->ss_out_channels) { 5987 struct snd_interval t = { 5988 .min = 32000, 5989 .max = 48000, 5990 .integer = 1, 5991 }; 5992 return snd_interval_refine(r, &t); 5993 } else if (c->max <= hdspm->qs_out_channels) { 5994 struct snd_interval t = { 5995 .min = 128000, 5996 .max = 192000, 5997 .integer = 1, 5998 }; 5999 return snd_interval_refine(r, &t); 6000 } else if (c->max <= hdspm->ds_out_channels) { 6001 struct snd_interval t = { 6002 .min = 64000, 6003 .max = 96000, 6004 .integer = 1, 6005 }; 6006 return snd_interval_refine(r, &t); 6007 } 6008 6009 return 0; 6010 } 6011 6012 static int snd_hdspm_hw_rule_in_channels(struct snd_pcm_hw_params *params, 6013 struct snd_pcm_hw_rule *rule) 6014 { 6015 unsigned int list[3]; 6016 struct hdspm *hdspm = rule->private; 6017 struct snd_interval *c = hw_param_interval(params, 6018 SNDRV_PCM_HW_PARAM_CHANNELS); 6019 6020 list[0] = hdspm->qs_in_channels; 6021 list[1] = hdspm->ds_in_channels; 6022 list[2] = hdspm->ss_in_channels; 6023 return snd_interval_list(c, 3, list, 0); 6024 } 6025 6026 static int snd_hdspm_hw_rule_out_channels(struct snd_pcm_hw_params *params, 6027 struct snd_pcm_hw_rule *rule) 6028 { 6029 unsigned int list[3]; 6030 struct hdspm *hdspm = rule->private; 6031 struct snd_interval *c = hw_param_interval(params, 6032 SNDRV_PCM_HW_PARAM_CHANNELS); 6033 6034 list[0] = hdspm->qs_out_channels; 6035 list[1] = hdspm->ds_out_channels; 6036 list[2] = hdspm->ss_out_channels; 6037 return snd_interval_list(c, 3, list, 0); 6038 } 6039 6040 6041 static const unsigned int hdspm_aes32_sample_rates[] = { 6042 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 6043 }; 6044 6045 static const struct snd_pcm_hw_constraint_list 6046 hdspm_hw_constraints_aes32_sample_rates = { 6047 .count = ARRAY_SIZE(hdspm_aes32_sample_rates), 6048 .list = hdspm_aes32_sample_rates, 6049 .mask = 0 6050 }; 6051 6052 static int snd_hdspm_open(struct snd_pcm_substream *substream) 6053 { 6054 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 6055 struct snd_pcm_runtime *runtime = substream->runtime; 6056 bool playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); 6057 6058 spin_lock_irq(&hdspm->lock); 6059 snd_pcm_set_sync(substream); 6060 runtime->hw = (playback) ? snd_hdspm_playback_subinfo : 6061 snd_hdspm_capture_subinfo; 6062 6063 if (playback) { 6064 if (!hdspm->capture_substream) 6065 hdspm_stop_audio(hdspm); 6066 6067 hdspm->playback_pid = current->pid; 6068 hdspm->playback_substream = substream; 6069 } else { 6070 if (!hdspm->playback_substream) 6071 hdspm_stop_audio(hdspm); 6072 6073 hdspm->capture_pid = current->pid; 6074 hdspm->capture_substream = substream; 6075 } 6076 6077 spin_unlock_irq(&hdspm->lock); 6078 6079 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); 6080 snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 6081 6082 switch (hdspm->io_type) { 6083 case AIO: 6084 case RayDAT: 6085 snd_pcm_hw_constraint_minmax(runtime, 6086 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 6087 32, 4096); 6088 /* RayDAT & AIO have a fixed buffer of 16384 samples per channel */ 6089 snd_pcm_hw_constraint_single(runtime, 6090 SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 6091 16384); 6092 break; 6093 6094 default: 6095 snd_pcm_hw_constraint_minmax(runtime, 6096 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 6097 64, 8192); 6098 snd_pcm_hw_constraint_single(runtime, 6099 SNDRV_PCM_HW_PARAM_PERIODS, 2); 6100 break; 6101 } 6102 6103 if (AES32 == hdspm->io_type) { 6104 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT; 6105 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 6106 &hdspm_hw_constraints_aes32_sample_rates); 6107 } else { 6108 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 6109 (playback ? 6110 snd_hdspm_hw_rule_rate_out_channels : 6111 snd_hdspm_hw_rule_rate_in_channels), hdspm, 6112 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 6113 } 6114 6115 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 6116 (playback ? snd_hdspm_hw_rule_out_channels : 6117 snd_hdspm_hw_rule_in_channels), hdspm, 6118 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 6119 6120 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 6121 (playback ? snd_hdspm_hw_rule_out_channels_rate : 6122 snd_hdspm_hw_rule_in_channels_rate), hdspm, 6123 SNDRV_PCM_HW_PARAM_RATE, -1); 6124 6125 return 0; 6126 } 6127 6128 static int snd_hdspm_release(struct snd_pcm_substream *substream) 6129 { 6130 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 6131 bool playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); 6132 6133 spin_lock_irq(&hdspm->lock); 6134 6135 if (playback) { 6136 hdspm->playback_pid = -1; 6137 hdspm->playback_substream = NULL; 6138 } else { 6139 hdspm->capture_pid = -1; 6140 hdspm->capture_substream = NULL; 6141 } 6142 6143 spin_unlock_irq(&hdspm->lock); 6144 6145 return 0; 6146 } 6147 6148 static int snd_hdspm_hwdep_dummy_op(struct snd_hwdep *hw, struct file *file) 6149 { 6150 /* we have nothing to initialize but the call is required */ 6151 return 0; 6152 } 6153 6154 static inline int copy_u32_le(void __user *dest, void __iomem *src) 6155 { 6156 u32 val = readl(src); 6157 return copy_to_user(dest, &val, 4); 6158 } 6159 6160 static int snd_hdspm_hwdep_ioctl(struct snd_hwdep *hw, struct file *file, 6161 unsigned int cmd, unsigned long arg) 6162 { 6163 void __user *argp = (void __user *)arg; 6164 struct hdspm *hdspm = hw->private_data; 6165 struct hdspm_mixer_ioctl mixer; 6166 struct hdspm_config info; 6167 struct hdspm_status status; 6168 struct hdspm_version hdspm_version; 6169 struct hdspm_peak_rms *levels; 6170 struct hdspm_ltc ltc; 6171 unsigned int statusregister; 6172 long unsigned int s; 6173 int i = 0; 6174 6175 switch (cmd) { 6176 6177 case SNDRV_HDSPM_IOCTL_GET_PEAK_RMS: 6178 levels = &hdspm->peak_rms; 6179 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) { 6180 levels->input_peaks[i] = 6181 readl(hdspm->iobase + 6182 HDSPM_MADI_INPUT_PEAK + i*4); 6183 levels->playback_peaks[i] = 6184 readl(hdspm->iobase + 6185 HDSPM_MADI_PLAYBACK_PEAK + i*4); 6186 levels->output_peaks[i] = 6187 readl(hdspm->iobase + 6188 HDSPM_MADI_OUTPUT_PEAK + i*4); 6189 6190 levels->input_rms[i] = 6191 ((uint64_t) readl(hdspm->iobase + 6192 HDSPM_MADI_INPUT_RMS_H + i*4) << 32) | 6193 (uint64_t) readl(hdspm->iobase + 6194 HDSPM_MADI_INPUT_RMS_L + i*4); 6195 levels->playback_rms[i] = 6196 ((uint64_t)readl(hdspm->iobase + 6197 HDSPM_MADI_PLAYBACK_RMS_H+i*4) << 32) | 6198 (uint64_t)readl(hdspm->iobase + 6199 HDSPM_MADI_PLAYBACK_RMS_L + i*4); 6200 levels->output_rms[i] = 6201 ((uint64_t)readl(hdspm->iobase + 6202 HDSPM_MADI_OUTPUT_RMS_H + i*4) << 32) | 6203 (uint64_t)readl(hdspm->iobase + 6204 HDSPM_MADI_OUTPUT_RMS_L + i*4); 6205 } 6206 6207 if (hdspm->system_sample_rate > 96000) { 6208 levels->speed = qs; 6209 } else if (hdspm->system_sample_rate > 48000) { 6210 levels->speed = ds; 6211 } else { 6212 levels->speed = ss; 6213 } 6214 levels->status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 6215 6216 s = copy_to_user(argp, levels, sizeof(*levels)); 6217 if (0 != s) { 6218 /* dev_err(hdspm->card->dev, "copy_to_user(.., .., %lu): %lu 6219 [Levels]\n", sizeof(struct hdspm_peak_rms), s); 6220 */ 6221 return -EFAULT; 6222 } 6223 break; 6224 6225 case SNDRV_HDSPM_IOCTL_GET_LTC: 6226 ltc.ltc = hdspm_read(hdspm, HDSPM_RD_TCO); 6227 i = hdspm_read(hdspm, HDSPM_RD_TCO + 4); 6228 if (i & HDSPM_TCO1_LTC_Input_valid) { 6229 switch (i & (HDSPM_TCO1_LTC_Format_LSB | 6230 HDSPM_TCO1_LTC_Format_MSB)) { 6231 case 0: 6232 ltc.format = fps_24; 6233 break; 6234 case HDSPM_TCO1_LTC_Format_LSB: 6235 ltc.format = fps_25; 6236 break; 6237 case HDSPM_TCO1_LTC_Format_MSB: 6238 ltc.format = fps_2997; 6239 break; 6240 default: 6241 ltc.format = fps_30; 6242 break; 6243 } 6244 if (i & HDSPM_TCO1_set_drop_frame_flag) { 6245 ltc.frame = drop_frame; 6246 } else { 6247 ltc.frame = full_frame; 6248 } 6249 } else { 6250 ltc.format = format_invalid; 6251 ltc.frame = frame_invalid; 6252 } 6253 if (i & HDSPM_TCO1_Video_Input_Format_NTSC) { 6254 ltc.input_format = ntsc; 6255 } else if (i & HDSPM_TCO1_Video_Input_Format_PAL) { 6256 ltc.input_format = pal; 6257 } else { 6258 ltc.input_format = no_video; 6259 } 6260 6261 s = copy_to_user(argp, <c, sizeof(ltc)); 6262 if (0 != s) { 6263 /* 6264 dev_err(hdspm->card->dev, "copy_to_user(.., .., %lu): %lu [LTC]\n", sizeof(struct hdspm_ltc), s); */ 6265 return -EFAULT; 6266 } 6267 6268 break; 6269 6270 case SNDRV_HDSPM_IOCTL_GET_CONFIG: 6271 6272 memset(&info, 0, sizeof(info)); 6273 spin_lock_irq(&hdspm->lock); 6274 info.pref_sync_ref = hdspm_pref_sync_ref(hdspm); 6275 info.wordclock_sync_check = hdspm_wc_sync_check(hdspm); 6276 6277 info.system_sample_rate = hdspm->system_sample_rate; 6278 info.autosync_sample_rate = 6279 hdspm_external_sample_rate(hdspm); 6280 info.system_clock_mode = hdspm_system_clock_mode(hdspm); 6281 info.clock_source = hdspm_clock_source(hdspm); 6282 info.autosync_ref = hdspm_autosync_ref(hdspm); 6283 info.line_out = hdspm_toggle_setting(hdspm, HDSPM_LineOut); 6284 info.passthru = 0; 6285 spin_unlock_irq(&hdspm->lock); 6286 if (copy_to_user(argp, &info, sizeof(info))) 6287 return -EFAULT; 6288 break; 6289 6290 case SNDRV_HDSPM_IOCTL_GET_STATUS: 6291 memset(&status, 0, sizeof(status)); 6292 6293 status.card_type = hdspm->io_type; 6294 6295 status.autosync_source = hdspm_autosync_ref(hdspm); 6296 6297 status.card_clock = 110069313433624ULL; 6298 status.master_period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ); 6299 6300 switch (hdspm->io_type) { 6301 case MADI: 6302 case MADIface: 6303 status.card_specific.madi.sync_wc = 6304 hdspm_wc_sync_check(hdspm); 6305 status.card_specific.madi.sync_madi = 6306 hdspm_madi_sync_check(hdspm); 6307 status.card_specific.madi.sync_tco = 6308 hdspm_tco_sync_check(hdspm); 6309 status.card_specific.madi.sync_in = 6310 hdspm_sync_in_sync_check(hdspm); 6311 6312 statusregister = 6313 hdspm_read(hdspm, HDSPM_statusRegister); 6314 status.card_specific.madi.madi_input = 6315 (statusregister & HDSPM_AB_int) ? 1 : 0; 6316 status.card_specific.madi.channel_format = 6317 (statusregister & HDSPM_RX_64ch) ? 1 : 0; 6318 /* TODO: Mac driver sets it when f_s>48kHz */ 6319 status.card_specific.madi.frame_format = 0; 6320 6321 default: 6322 break; 6323 } 6324 6325 if (copy_to_user(argp, &status, sizeof(status))) 6326 return -EFAULT; 6327 6328 6329 break; 6330 6331 case SNDRV_HDSPM_IOCTL_GET_VERSION: 6332 memset(&hdspm_version, 0, sizeof(hdspm_version)); 6333 6334 hdspm_version.card_type = hdspm->io_type; 6335 strlcpy(hdspm_version.cardname, hdspm->card_name, 6336 sizeof(hdspm_version.cardname)); 6337 hdspm_version.serial = hdspm->serial; 6338 hdspm_version.firmware_rev = hdspm->firmware_rev; 6339 hdspm_version.addons = 0; 6340 if (hdspm->tco) 6341 hdspm_version.addons |= HDSPM_ADDON_TCO; 6342 6343 if (copy_to_user(argp, &hdspm_version, 6344 sizeof(hdspm_version))) 6345 return -EFAULT; 6346 break; 6347 6348 case SNDRV_HDSPM_IOCTL_GET_MIXER: 6349 if (copy_from_user(&mixer, argp, sizeof(mixer))) 6350 return -EFAULT; 6351 if (copy_to_user((void __user *)mixer.mixer, hdspm->mixer, 6352 sizeof(*mixer.mixer))) 6353 return -EFAULT; 6354 break; 6355 6356 default: 6357 return -EINVAL; 6358 } 6359 return 0; 6360 } 6361 6362 static const struct snd_pcm_ops snd_hdspm_ops = { 6363 .open = snd_hdspm_open, 6364 .close = snd_hdspm_release, 6365 .ioctl = snd_hdspm_ioctl, 6366 .hw_params = snd_hdspm_hw_params, 6367 .hw_free = snd_hdspm_hw_free, 6368 .prepare = snd_hdspm_prepare, 6369 .trigger = snd_hdspm_trigger, 6370 .pointer = snd_hdspm_hw_pointer, 6371 }; 6372 6373 static int snd_hdspm_create_hwdep(struct snd_card *card, 6374 struct hdspm *hdspm) 6375 { 6376 struct snd_hwdep *hw; 6377 int err; 6378 6379 err = snd_hwdep_new(card, "HDSPM hwdep", 0, &hw); 6380 if (err < 0) 6381 return err; 6382 6383 hdspm->hwdep = hw; 6384 hw->private_data = hdspm; 6385 strcpy(hw->name, "HDSPM hwdep interface"); 6386 6387 hw->ops.open = snd_hdspm_hwdep_dummy_op; 6388 hw->ops.ioctl = snd_hdspm_hwdep_ioctl; 6389 hw->ops.ioctl_compat = snd_hdspm_hwdep_ioctl; 6390 hw->ops.release = snd_hdspm_hwdep_dummy_op; 6391 6392 return 0; 6393 } 6394 6395 6396 /*------------------------------------------------------------ 6397 memory interface 6398 ------------------------------------------------------------*/ 6399 static int snd_hdspm_preallocate_memory(struct hdspm *hdspm) 6400 { 6401 struct snd_pcm *pcm; 6402 size_t wanted; 6403 6404 pcm = hdspm->pcm; 6405 6406 wanted = HDSPM_DMA_AREA_BYTES; 6407 6408 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG, 6409 &hdspm->pci->dev, 6410 wanted, wanted); 6411 dev_dbg(hdspm->card->dev, " Preallocated %zd Bytes\n", wanted); 6412 return 0; 6413 } 6414 6415 /* Inform the card what DMA addresses to use for the indicated channel. */ 6416 /* Each channel got 16 4K pages allocated for DMA transfers. */ 6417 static void hdspm_set_channel_dma_addr(struct hdspm *hdspm, 6418 struct snd_pcm_substream *substream, 6419 unsigned int reg, int channel) 6420 { 6421 int i; 6422 6423 for (i = channel * 16; i < channel * 16 + 16; i++) 6424 hdspm_write(hdspm, reg + 4 * i, 6425 snd_pcm_sgbuf_get_addr(substream, 4096 * i)); 6426 } 6427 6428 6429 /* ------------- ALSA Devices ---------------------------- */ 6430 static int snd_hdspm_create_pcm(struct snd_card *card, 6431 struct hdspm *hdspm) 6432 { 6433 struct snd_pcm *pcm; 6434 int err; 6435 6436 err = snd_pcm_new(card, hdspm->card_name, 0, 1, 1, &pcm); 6437 if (err < 0) 6438 return err; 6439 6440 hdspm->pcm = pcm; 6441 pcm->private_data = hdspm; 6442 strcpy(pcm->name, hdspm->card_name); 6443 6444 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, 6445 &snd_hdspm_ops); 6446 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, 6447 &snd_hdspm_ops); 6448 6449 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX; 6450 6451 err = snd_hdspm_preallocate_memory(hdspm); 6452 if (err < 0) 6453 return err; 6454 6455 return 0; 6456 } 6457 6458 static inline void snd_hdspm_initialize_midi_flush(struct hdspm * hdspm) 6459 { 6460 int i; 6461 6462 for (i = 0; i < hdspm->midiPorts; i++) 6463 snd_hdspm_flush_midi_input(hdspm, i); 6464 } 6465 6466 static int snd_hdspm_create_alsa_devices(struct snd_card *card, 6467 struct hdspm *hdspm) 6468 { 6469 int err, i; 6470 6471 dev_dbg(card->dev, "Create card...\n"); 6472 err = snd_hdspm_create_pcm(card, hdspm); 6473 if (err < 0) 6474 return err; 6475 6476 i = 0; 6477 while (i < hdspm->midiPorts) { 6478 err = snd_hdspm_create_midi(card, hdspm, i); 6479 if (err < 0) { 6480 return err; 6481 } 6482 i++; 6483 } 6484 6485 err = snd_hdspm_create_controls(card, hdspm); 6486 if (err < 0) 6487 return err; 6488 6489 err = snd_hdspm_create_hwdep(card, hdspm); 6490 if (err < 0) 6491 return err; 6492 6493 dev_dbg(card->dev, "proc init...\n"); 6494 snd_hdspm_proc_init(hdspm); 6495 6496 hdspm->system_sample_rate = -1; 6497 hdspm->last_external_sample_rate = -1; 6498 hdspm->last_internal_sample_rate = -1; 6499 hdspm->playback_pid = -1; 6500 hdspm->capture_pid = -1; 6501 hdspm->capture_substream = NULL; 6502 hdspm->playback_substream = NULL; 6503 6504 dev_dbg(card->dev, "Set defaults...\n"); 6505 err = snd_hdspm_set_defaults(hdspm); 6506 if (err < 0) 6507 return err; 6508 6509 dev_dbg(card->dev, "Update mixer controls...\n"); 6510 hdspm_update_simple_mixer_controls(hdspm); 6511 6512 dev_dbg(card->dev, "Initializing complete?\n"); 6513 6514 err = snd_card_register(card); 6515 if (err < 0) { 6516 dev_err(card->dev, "error registering card\n"); 6517 return err; 6518 } 6519 6520 dev_dbg(card->dev, "... yes now\n"); 6521 6522 return 0; 6523 } 6524 6525 static int snd_hdspm_create(struct snd_card *card, 6526 struct hdspm *hdspm) 6527 { 6528 6529 struct pci_dev *pci = hdspm->pci; 6530 int err; 6531 unsigned long io_extent; 6532 6533 hdspm->irq = -1; 6534 hdspm->card = card; 6535 6536 spin_lock_init(&hdspm->lock); 6537 6538 pci_read_config_word(hdspm->pci, 6539 PCI_CLASS_REVISION, &hdspm->firmware_rev); 6540 6541 strcpy(card->mixername, "Xilinx FPGA"); 6542 strcpy(card->driver, "HDSPM"); 6543 6544 switch (hdspm->firmware_rev) { 6545 case HDSPM_RAYDAT_REV: 6546 hdspm->io_type = RayDAT; 6547 hdspm->card_name = "RME RayDAT"; 6548 hdspm->midiPorts = 2; 6549 break; 6550 case HDSPM_AIO_REV: 6551 hdspm->io_type = AIO; 6552 hdspm->card_name = "RME AIO"; 6553 hdspm->midiPorts = 1; 6554 break; 6555 case HDSPM_MADIFACE_REV: 6556 hdspm->io_type = MADIface; 6557 hdspm->card_name = "RME MADIface"; 6558 hdspm->midiPorts = 1; 6559 break; 6560 default: 6561 if ((hdspm->firmware_rev == 0xf0) || 6562 ((hdspm->firmware_rev >= 0xe6) && 6563 (hdspm->firmware_rev <= 0xea))) { 6564 hdspm->io_type = AES32; 6565 hdspm->card_name = "RME AES32"; 6566 hdspm->midiPorts = 2; 6567 } else if ((hdspm->firmware_rev == 0xd2) || 6568 ((hdspm->firmware_rev >= 0xc8) && 6569 (hdspm->firmware_rev <= 0xcf))) { 6570 hdspm->io_type = MADI; 6571 hdspm->card_name = "RME MADI"; 6572 hdspm->midiPorts = 3; 6573 } else { 6574 dev_err(card->dev, 6575 "unknown firmware revision %x\n", 6576 hdspm->firmware_rev); 6577 return -ENODEV; 6578 } 6579 } 6580 6581 err = pci_enable_device(pci); 6582 if (err < 0) 6583 return err; 6584 6585 pci_set_master(hdspm->pci); 6586 6587 err = pci_request_regions(pci, "hdspm"); 6588 if (err < 0) 6589 return err; 6590 6591 hdspm->port = pci_resource_start(pci, 0); 6592 io_extent = pci_resource_len(pci, 0); 6593 6594 dev_dbg(card->dev, "grabbed memory region 0x%lx-0x%lx\n", 6595 hdspm->port, hdspm->port + io_extent - 1); 6596 6597 hdspm->iobase = ioremap(hdspm->port, io_extent); 6598 if (!hdspm->iobase) { 6599 dev_err(card->dev, "unable to remap region 0x%lx-0x%lx\n", 6600 hdspm->port, hdspm->port + io_extent - 1); 6601 return -EBUSY; 6602 } 6603 dev_dbg(card->dev, "remapped region (0x%lx) 0x%lx-0x%lx\n", 6604 (unsigned long)hdspm->iobase, hdspm->port, 6605 hdspm->port + io_extent - 1); 6606 6607 if (request_irq(pci->irq, snd_hdspm_interrupt, 6608 IRQF_SHARED, KBUILD_MODNAME, hdspm)) { 6609 dev_err(card->dev, "unable to use IRQ %d\n", pci->irq); 6610 return -EBUSY; 6611 } 6612 6613 dev_dbg(card->dev, "use IRQ %d\n", pci->irq); 6614 6615 hdspm->irq = pci->irq; 6616 6617 dev_dbg(card->dev, "kmalloc Mixer memory of %zd Bytes\n", 6618 sizeof(*hdspm->mixer)); 6619 hdspm->mixer = kzalloc(sizeof(*hdspm->mixer), GFP_KERNEL); 6620 if (!hdspm->mixer) 6621 return -ENOMEM; 6622 6623 hdspm->port_names_in = NULL; 6624 hdspm->port_names_out = NULL; 6625 6626 switch (hdspm->io_type) { 6627 case AES32: 6628 hdspm->ss_in_channels = hdspm->ss_out_channels = AES32_CHANNELS; 6629 hdspm->ds_in_channels = hdspm->ds_out_channels = AES32_CHANNELS; 6630 hdspm->qs_in_channels = hdspm->qs_out_channels = AES32_CHANNELS; 6631 6632 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss = 6633 channel_map_aes32; 6634 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds = 6635 channel_map_aes32; 6636 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs = 6637 channel_map_aes32; 6638 hdspm->port_names_in_ss = hdspm->port_names_out_ss = 6639 texts_ports_aes32; 6640 hdspm->port_names_in_ds = hdspm->port_names_out_ds = 6641 texts_ports_aes32; 6642 hdspm->port_names_in_qs = hdspm->port_names_out_qs = 6643 texts_ports_aes32; 6644 6645 hdspm->max_channels_out = hdspm->max_channels_in = 6646 AES32_CHANNELS; 6647 hdspm->port_names_in = hdspm->port_names_out = 6648 texts_ports_aes32; 6649 hdspm->channel_map_in = hdspm->channel_map_out = 6650 channel_map_aes32; 6651 6652 break; 6653 6654 case MADI: 6655 case MADIface: 6656 hdspm->ss_in_channels = hdspm->ss_out_channels = 6657 MADI_SS_CHANNELS; 6658 hdspm->ds_in_channels = hdspm->ds_out_channels = 6659 MADI_DS_CHANNELS; 6660 hdspm->qs_in_channels = hdspm->qs_out_channels = 6661 MADI_QS_CHANNELS; 6662 6663 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss = 6664 channel_map_unity_ss; 6665 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds = 6666 channel_map_unity_ss; 6667 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs = 6668 channel_map_unity_ss; 6669 6670 hdspm->port_names_in_ss = hdspm->port_names_out_ss = 6671 texts_ports_madi; 6672 hdspm->port_names_in_ds = hdspm->port_names_out_ds = 6673 texts_ports_madi; 6674 hdspm->port_names_in_qs = hdspm->port_names_out_qs = 6675 texts_ports_madi; 6676 break; 6677 6678 case AIO: 6679 hdspm->ss_in_channels = AIO_IN_SS_CHANNELS; 6680 hdspm->ds_in_channels = AIO_IN_DS_CHANNELS; 6681 hdspm->qs_in_channels = AIO_IN_QS_CHANNELS; 6682 hdspm->ss_out_channels = AIO_OUT_SS_CHANNELS; 6683 hdspm->ds_out_channels = AIO_OUT_DS_CHANNELS; 6684 hdspm->qs_out_channels = AIO_OUT_QS_CHANNELS; 6685 6686 if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBI_D)) { 6687 dev_info(card->dev, "AEB input board found\n"); 6688 hdspm->ss_in_channels += 4; 6689 hdspm->ds_in_channels += 4; 6690 hdspm->qs_in_channels += 4; 6691 } 6692 6693 if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBO_D)) { 6694 dev_info(card->dev, "AEB output board found\n"); 6695 hdspm->ss_out_channels += 4; 6696 hdspm->ds_out_channels += 4; 6697 hdspm->qs_out_channels += 4; 6698 } 6699 6700 hdspm->channel_map_out_ss = channel_map_aio_out_ss; 6701 hdspm->channel_map_out_ds = channel_map_aio_out_ds; 6702 hdspm->channel_map_out_qs = channel_map_aio_out_qs; 6703 6704 hdspm->channel_map_in_ss = channel_map_aio_in_ss; 6705 hdspm->channel_map_in_ds = channel_map_aio_in_ds; 6706 hdspm->channel_map_in_qs = channel_map_aio_in_qs; 6707 6708 hdspm->port_names_in_ss = texts_ports_aio_in_ss; 6709 hdspm->port_names_out_ss = texts_ports_aio_out_ss; 6710 hdspm->port_names_in_ds = texts_ports_aio_in_ds; 6711 hdspm->port_names_out_ds = texts_ports_aio_out_ds; 6712 hdspm->port_names_in_qs = texts_ports_aio_in_qs; 6713 hdspm->port_names_out_qs = texts_ports_aio_out_qs; 6714 6715 break; 6716 6717 case RayDAT: 6718 hdspm->ss_in_channels = hdspm->ss_out_channels = 6719 RAYDAT_SS_CHANNELS; 6720 hdspm->ds_in_channels = hdspm->ds_out_channels = 6721 RAYDAT_DS_CHANNELS; 6722 hdspm->qs_in_channels = hdspm->qs_out_channels = 6723 RAYDAT_QS_CHANNELS; 6724 6725 hdspm->max_channels_in = RAYDAT_SS_CHANNELS; 6726 hdspm->max_channels_out = RAYDAT_SS_CHANNELS; 6727 6728 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss = 6729 channel_map_raydat_ss; 6730 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds = 6731 channel_map_raydat_ds; 6732 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs = 6733 channel_map_raydat_qs; 6734 hdspm->channel_map_in = hdspm->channel_map_out = 6735 channel_map_raydat_ss; 6736 6737 hdspm->port_names_in_ss = hdspm->port_names_out_ss = 6738 texts_ports_raydat_ss; 6739 hdspm->port_names_in_ds = hdspm->port_names_out_ds = 6740 texts_ports_raydat_ds; 6741 hdspm->port_names_in_qs = hdspm->port_names_out_qs = 6742 texts_ports_raydat_qs; 6743 6744 6745 break; 6746 6747 } 6748 6749 /* TCO detection */ 6750 switch (hdspm->io_type) { 6751 case AIO: 6752 case RayDAT: 6753 if (hdspm_read(hdspm, HDSPM_statusRegister2) & 6754 HDSPM_s2_tco_detect) { 6755 hdspm->midiPorts++; 6756 hdspm->tco = kzalloc(sizeof(*hdspm->tco), GFP_KERNEL); 6757 if (hdspm->tco) 6758 hdspm_tco_write(hdspm); 6759 6760 dev_info(card->dev, "AIO/RayDAT TCO module found\n"); 6761 } else { 6762 hdspm->tco = NULL; 6763 } 6764 break; 6765 6766 case MADI: 6767 case AES32: 6768 if (hdspm_read(hdspm, HDSPM_statusRegister) & HDSPM_tco_detect) { 6769 hdspm->midiPorts++; 6770 hdspm->tco = kzalloc(sizeof(*hdspm->tco), GFP_KERNEL); 6771 if (hdspm->tco) 6772 hdspm_tco_write(hdspm); 6773 6774 dev_info(card->dev, "MADI/AES TCO module found\n"); 6775 } else { 6776 hdspm->tco = NULL; 6777 } 6778 break; 6779 6780 default: 6781 hdspm->tco = NULL; 6782 } 6783 6784 /* texts */ 6785 switch (hdspm->io_type) { 6786 case AES32: 6787 if (hdspm->tco) { 6788 hdspm->texts_autosync = texts_autosync_aes_tco; 6789 hdspm->texts_autosync_items = 6790 ARRAY_SIZE(texts_autosync_aes_tco); 6791 } else { 6792 hdspm->texts_autosync = texts_autosync_aes; 6793 hdspm->texts_autosync_items = 6794 ARRAY_SIZE(texts_autosync_aes); 6795 } 6796 break; 6797 6798 case MADI: 6799 if (hdspm->tco) { 6800 hdspm->texts_autosync = texts_autosync_madi_tco; 6801 hdspm->texts_autosync_items = 4; 6802 } else { 6803 hdspm->texts_autosync = texts_autosync_madi; 6804 hdspm->texts_autosync_items = 3; 6805 } 6806 break; 6807 6808 case MADIface: 6809 6810 break; 6811 6812 case RayDAT: 6813 if (hdspm->tco) { 6814 hdspm->texts_autosync = texts_autosync_raydat_tco; 6815 hdspm->texts_autosync_items = 9; 6816 } else { 6817 hdspm->texts_autosync = texts_autosync_raydat; 6818 hdspm->texts_autosync_items = 8; 6819 } 6820 break; 6821 6822 case AIO: 6823 if (hdspm->tco) { 6824 hdspm->texts_autosync = texts_autosync_aio_tco; 6825 hdspm->texts_autosync_items = 6; 6826 } else { 6827 hdspm->texts_autosync = texts_autosync_aio; 6828 hdspm->texts_autosync_items = 5; 6829 } 6830 break; 6831 6832 } 6833 6834 tasklet_init(&hdspm->midi_tasklet, 6835 hdspm_midi_tasklet, (unsigned long) hdspm); 6836 6837 6838 if (hdspm->io_type != MADIface) { 6839 hdspm->serial = (hdspm_read(hdspm, 6840 HDSPM_midiStatusIn0)>>8) & 0xFFFFFF; 6841 /* id contains either a user-provided value or the default 6842 * NULL. If it's the default, we're safe to 6843 * fill card->id with the serial number. 6844 * 6845 * If the serial number is 0xFFFFFF, then we're dealing with 6846 * an old PCI revision that comes without a sane number. In 6847 * this case, we don't set card->id to avoid collisions 6848 * when running with multiple cards. 6849 */ 6850 if (!id[hdspm->dev] && hdspm->serial != 0xFFFFFF) { 6851 snprintf(card->id, sizeof(card->id), 6852 "HDSPMx%06x", hdspm->serial); 6853 snd_card_set_id(card, card->id); 6854 } 6855 } 6856 6857 dev_dbg(card->dev, "create alsa devices.\n"); 6858 err = snd_hdspm_create_alsa_devices(card, hdspm); 6859 if (err < 0) 6860 return err; 6861 6862 snd_hdspm_initialize_midi_flush(hdspm); 6863 6864 return 0; 6865 } 6866 6867 6868 static int snd_hdspm_free(struct hdspm * hdspm) 6869 { 6870 6871 if (hdspm->port) { 6872 6873 /* stop th audio, and cancel all interrupts */ 6874 hdspm->control_register &= 6875 ~(HDSPM_Start | HDSPM_AudioInterruptEnable | 6876 HDSPM_Midi0InterruptEnable | HDSPM_Midi1InterruptEnable | 6877 HDSPM_Midi2InterruptEnable | HDSPM_Midi3InterruptEnable); 6878 hdspm_write(hdspm, HDSPM_controlRegister, 6879 hdspm->control_register); 6880 } 6881 6882 if (hdspm->irq >= 0) 6883 free_irq(hdspm->irq, (void *) hdspm); 6884 6885 kfree(hdspm->mixer); 6886 iounmap(hdspm->iobase); 6887 6888 if (hdspm->port) 6889 pci_release_regions(hdspm->pci); 6890 6891 pci_disable_device(hdspm->pci); 6892 return 0; 6893 } 6894 6895 6896 static void snd_hdspm_card_free(struct snd_card *card) 6897 { 6898 struct hdspm *hdspm = card->private_data; 6899 6900 if (hdspm) 6901 snd_hdspm_free(hdspm); 6902 } 6903 6904 6905 static int snd_hdspm_probe(struct pci_dev *pci, 6906 const struct pci_device_id *pci_id) 6907 { 6908 static int dev; 6909 struct hdspm *hdspm; 6910 struct snd_card *card; 6911 int err; 6912 6913 if (dev >= SNDRV_CARDS) 6914 return -ENODEV; 6915 if (!enable[dev]) { 6916 dev++; 6917 return -ENOENT; 6918 } 6919 6920 err = snd_card_new(&pci->dev, index[dev], id[dev], 6921 THIS_MODULE, sizeof(*hdspm), &card); 6922 if (err < 0) 6923 return err; 6924 6925 hdspm = card->private_data; 6926 card->private_free = snd_hdspm_card_free; 6927 hdspm->dev = dev; 6928 hdspm->pci = pci; 6929 6930 err = snd_hdspm_create(card, hdspm); 6931 if (err < 0) 6932 goto free_card; 6933 6934 if (hdspm->io_type != MADIface) { 6935 snprintf(card->shortname, sizeof(card->shortname), "%s_%x", 6936 hdspm->card_name, hdspm->serial); 6937 snprintf(card->longname, sizeof(card->longname), 6938 "%s S/N 0x%x at 0x%lx, irq %d", 6939 hdspm->card_name, hdspm->serial, 6940 hdspm->port, hdspm->irq); 6941 } else { 6942 snprintf(card->shortname, sizeof(card->shortname), "%s", 6943 hdspm->card_name); 6944 snprintf(card->longname, sizeof(card->longname), 6945 "%s at 0x%lx, irq %d", 6946 hdspm->card_name, hdspm->port, hdspm->irq); 6947 } 6948 6949 err = snd_card_register(card); 6950 if (err < 0) 6951 goto free_card; 6952 6953 pci_set_drvdata(pci, card); 6954 6955 dev++; 6956 return 0; 6957 6958 free_card: 6959 snd_card_free(card); 6960 return err; 6961 } 6962 6963 static void snd_hdspm_remove(struct pci_dev *pci) 6964 { 6965 snd_card_free(pci_get_drvdata(pci)); 6966 } 6967 6968 static struct pci_driver hdspm_driver = { 6969 .name = KBUILD_MODNAME, 6970 .id_table = snd_hdspm_ids, 6971 .probe = snd_hdspm_probe, 6972 .remove = snd_hdspm_remove, 6973 }; 6974 6975 module_pci_driver(hdspm_driver); 6976