1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- 2 */ 3 /* 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation the rights to use, copy, modify, merge, publish, 11 * distribute, sub license, and/or sell copies of the Software, and to 12 * permit persons to whom the Software is furnished to do so, subject to 13 * the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the 16 * next paragraph) shall be included in all copies or substantial portions 17 * of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 26 * 27 */ 28 29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 30 31 #include <linux/slab.h> 32 #include <linux/sysrq.h> 33 34 #include <drm/drm_drv.h> 35 36 #include "display/intel_display_irq.h" 37 #include "display/intel_display_types.h" 38 #include "display/intel_hotplug.h" 39 #include "display/intel_hotplug_irq.h" 40 #include "display/intel_lpe_audio.h" 41 #include "display/intel_psr_regs.h" 42 43 #include "gt/intel_breadcrumbs.h" 44 #include "gt/intel_gt.h" 45 #include "gt/intel_gt_irq.h" 46 #include "gt/intel_gt_pm_irq.h" 47 #include "gt/intel_gt_regs.h" 48 #include "gt/intel_rps.h" 49 50 #include "i915_driver.h" 51 #include "i915_drv.h" 52 #include "i915_irq.h" 53 #include "i915_reg.h" 54 55 /** 56 * DOC: interrupt handling 57 * 58 * These functions provide the basic support for enabling and disabling the 59 * interrupt handling support. There's a lot more functionality in i915_irq.c 60 * and related files, but that will be described in separate chapters. 61 */ 62 63 /* 64 * Interrupt statistic for PMU. Increments the counter only if the 65 * interrupt originated from the GPU so interrupts from a device which 66 * shares the interrupt line are not accounted. 67 */ 68 static inline void pmu_irq_stats(struct drm_i915_private *i915, 69 irqreturn_t res) 70 { 71 if (unlikely(res != IRQ_HANDLED)) 72 return; 73 74 /* 75 * A clever compiler translates that into INC. A not so clever one 76 * should at least prevent store tearing. 77 */ 78 WRITE_ONCE(i915->pmu.irq_count, i915->pmu.irq_count + 1); 79 } 80 81 void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr, 82 i915_reg_t iir, i915_reg_t ier) 83 { 84 intel_uncore_write(uncore, imr, 0xffffffff); 85 intel_uncore_posting_read(uncore, imr); 86 87 intel_uncore_write(uncore, ier, 0); 88 89 /* IIR can theoretically queue up two events. Be paranoid. */ 90 intel_uncore_write(uncore, iir, 0xffffffff); 91 intel_uncore_posting_read(uncore, iir); 92 intel_uncore_write(uncore, iir, 0xffffffff); 93 intel_uncore_posting_read(uncore, iir); 94 } 95 96 static void gen2_irq_reset(struct intel_uncore *uncore) 97 { 98 intel_uncore_write16(uncore, GEN2_IMR, 0xffff); 99 intel_uncore_posting_read16(uncore, GEN2_IMR); 100 101 intel_uncore_write16(uncore, GEN2_IER, 0); 102 103 /* IIR can theoretically queue up two events. Be paranoid. */ 104 intel_uncore_write16(uncore, GEN2_IIR, 0xffff); 105 intel_uncore_posting_read16(uncore, GEN2_IIR); 106 intel_uncore_write16(uncore, GEN2_IIR, 0xffff); 107 intel_uncore_posting_read16(uncore, GEN2_IIR); 108 } 109 110 /* 111 * We should clear IMR at preinstall/uninstall, and just check at postinstall. 112 */ 113 void gen3_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg) 114 { 115 u32 val = intel_uncore_read(uncore, reg); 116 117 if (val == 0) 118 return; 119 120 drm_WARN(&uncore->i915->drm, 1, 121 "Interrupt register 0x%x is not zero: 0x%08x\n", 122 i915_mmio_reg_offset(reg), val); 123 intel_uncore_write(uncore, reg, 0xffffffff); 124 intel_uncore_posting_read(uncore, reg); 125 intel_uncore_write(uncore, reg, 0xffffffff); 126 intel_uncore_posting_read(uncore, reg); 127 } 128 129 static void gen2_assert_iir_is_zero(struct intel_uncore *uncore) 130 { 131 u16 val = intel_uncore_read16(uncore, GEN2_IIR); 132 133 if (val == 0) 134 return; 135 136 drm_WARN(&uncore->i915->drm, 1, 137 "Interrupt register 0x%x is not zero: 0x%08x\n", 138 i915_mmio_reg_offset(GEN2_IIR), val); 139 intel_uncore_write16(uncore, GEN2_IIR, 0xffff); 140 intel_uncore_posting_read16(uncore, GEN2_IIR); 141 intel_uncore_write16(uncore, GEN2_IIR, 0xffff); 142 intel_uncore_posting_read16(uncore, GEN2_IIR); 143 } 144 145 void gen3_irq_init(struct intel_uncore *uncore, 146 i915_reg_t imr, u32 imr_val, 147 i915_reg_t ier, u32 ier_val, 148 i915_reg_t iir) 149 { 150 gen3_assert_iir_is_zero(uncore, iir); 151 152 intel_uncore_write(uncore, ier, ier_val); 153 intel_uncore_write(uncore, imr, imr_val); 154 intel_uncore_posting_read(uncore, imr); 155 } 156 157 static void gen2_irq_init(struct intel_uncore *uncore, 158 u32 imr_val, u32 ier_val) 159 { 160 gen2_assert_iir_is_zero(uncore); 161 162 intel_uncore_write16(uncore, GEN2_IER, ier_val); 163 intel_uncore_write16(uncore, GEN2_IMR, imr_val); 164 intel_uncore_posting_read16(uncore, GEN2_IMR); 165 } 166 167 /** 168 * ivb_parity_work - Workqueue called when a parity error interrupt 169 * occurred. 170 * @work: workqueue struct 171 * 172 * Doesn't actually do anything except notify userspace. As a consequence of 173 * this event, userspace should try to remap the bad rows since statistically 174 * it is likely the same row is more likely to go bad again. 175 */ 176 static void ivb_parity_work(struct work_struct *work) 177 { 178 struct drm_i915_private *dev_priv = 179 container_of(work, typeof(*dev_priv), l3_parity.error_work); 180 struct intel_gt *gt = to_gt(dev_priv); 181 u32 error_status, row, bank, subbank; 182 char *parity_event[6]; 183 u32 misccpctl; 184 u8 slice = 0; 185 186 /* We must turn off DOP level clock gating to access the L3 registers. 187 * In order to prevent a get/put style interface, acquire struct mutex 188 * any time we access those registers. 189 */ 190 mutex_lock(&dev_priv->drm.struct_mutex); 191 192 /* If we've screwed up tracking, just let the interrupt fire again */ 193 if (drm_WARN_ON(&dev_priv->drm, !dev_priv->l3_parity.which_slice)) 194 goto out; 195 196 misccpctl = intel_uncore_rmw(&dev_priv->uncore, GEN7_MISCCPCTL, 197 GEN7_DOP_CLOCK_GATE_ENABLE, 0); 198 intel_uncore_posting_read(&dev_priv->uncore, GEN7_MISCCPCTL); 199 200 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) { 201 i915_reg_t reg; 202 203 slice--; 204 if (drm_WARN_ON_ONCE(&dev_priv->drm, 205 slice >= NUM_L3_SLICES(dev_priv))) 206 break; 207 208 dev_priv->l3_parity.which_slice &= ~(1<<slice); 209 210 reg = GEN7_L3CDERRST1(slice); 211 212 error_status = intel_uncore_read(&dev_priv->uncore, reg); 213 row = GEN7_PARITY_ERROR_ROW(error_status); 214 bank = GEN7_PARITY_ERROR_BANK(error_status); 215 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status); 216 217 intel_uncore_write(&dev_priv->uncore, reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE); 218 intel_uncore_posting_read(&dev_priv->uncore, reg); 219 220 parity_event[0] = I915_L3_PARITY_UEVENT "=1"; 221 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row); 222 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank); 223 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank); 224 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice); 225 parity_event[5] = NULL; 226 227 kobject_uevent_env(&dev_priv->drm.primary->kdev->kobj, 228 KOBJ_CHANGE, parity_event); 229 230 drm_dbg(&dev_priv->drm, 231 "Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n", 232 slice, row, bank, subbank); 233 234 kfree(parity_event[4]); 235 kfree(parity_event[3]); 236 kfree(parity_event[2]); 237 kfree(parity_event[1]); 238 } 239 240 intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl); 241 242 out: 243 drm_WARN_ON(&dev_priv->drm, dev_priv->l3_parity.which_slice); 244 spin_lock_irq(gt->irq_lock); 245 gen5_gt_enable_irq(gt, GT_PARITY_ERROR(dev_priv)); 246 spin_unlock_irq(gt->irq_lock); 247 248 mutex_unlock(&dev_priv->drm.struct_mutex); 249 } 250 251 static irqreturn_t valleyview_irq_handler(int irq, void *arg) 252 { 253 struct drm_i915_private *dev_priv = arg; 254 irqreturn_t ret = IRQ_NONE; 255 256 if (!intel_irqs_enabled(dev_priv)) 257 return IRQ_NONE; 258 259 /* IRQs are synced during runtime_suspend, we don't require a wakeref */ 260 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 261 262 do { 263 u32 iir, gt_iir, pm_iir; 264 u32 pipe_stats[I915_MAX_PIPES] = {}; 265 u32 hotplug_status = 0; 266 u32 ier = 0; 267 268 gt_iir = intel_uncore_read(&dev_priv->uncore, GTIIR); 269 pm_iir = intel_uncore_read(&dev_priv->uncore, GEN6_PMIIR); 270 iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR); 271 272 if (gt_iir == 0 && pm_iir == 0 && iir == 0) 273 break; 274 275 ret = IRQ_HANDLED; 276 277 /* 278 * Theory on interrupt generation, based on empirical evidence: 279 * 280 * x = ((VLV_IIR & VLV_IER) || 281 * (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) && 282 * (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE))); 283 * 284 * A CPU interrupt will only be raised when 'x' has a 0->1 edge. 285 * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to 286 * guarantee the CPU interrupt will be raised again even if we 287 * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR 288 * bits this time around. 289 */ 290 intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, 0); 291 ier = intel_uncore_rmw(&dev_priv->uncore, VLV_IER, ~0, 0); 292 293 if (gt_iir) 294 intel_uncore_write(&dev_priv->uncore, GTIIR, gt_iir); 295 if (pm_iir) 296 intel_uncore_write(&dev_priv->uncore, GEN6_PMIIR, pm_iir); 297 298 if (iir & I915_DISPLAY_PORT_INTERRUPT) 299 hotplug_status = i9xx_hpd_irq_ack(dev_priv); 300 301 /* Call regardless, as some status bits might not be 302 * signalled in iir */ 303 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); 304 305 if (iir & (I915_LPE_PIPE_A_INTERRUPT | 306 I915_LPE_PIPE_B_INTERRUPT)) 307 intel_lpe_audio_irq_handler(dev_priv); 308 309 /* 310 * VLV_IIR is single buffered, and reflects the level 311 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last. 312 */ 313 if (iir) 314 intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir); 315 316 intel_uncore_write(&dev_priv->uncore, VLV_IER, ier); 317 intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); 318 319 if (gt_iir) 320 gen6_gt_irq_handler(to_gt(dev_priv), gt_iir); 321 if (pm_iir) 322 gen6_rps_irq_handler(&to_gt(dev_priv)->rps, pm_iir); 323 324 if (hotplug_status) 325 i9xx_hpd_irq_handler(dev_priv, hotplug_status); 326 327 valleyview_pipestat_irq_handler(dev_priv, pipe_stats); 328 } while (0); 329 330 pmu_irq_stats(dev_priv, ret); 331 332 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 333 334 return ret; 335 } 336 337 static irqreturn_t cherryview_irq_handler(int irq, void *arg) 338 { 339 struct drm_i915_private *dev_priv = arg; 340 irqreturn_t ret = IRQ_NONE; 341 342 if (!intel_irqs_enabled(dev_priv)) 343 return IRQ_NONE; 344 345 /* IRQs are synced during runtime_suspend, we don't require a wakeref */ 346 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 347 348 do { 349 u32 master_ctl, iir; 350 u32 pipe_stats[I915_MAX_PIPES] = {}; 351 u32 hotplug_status = 0; 352 u32 ier = 0; 353 354 master_ctl = intel_uncore_read(&dev_priv->uncore, GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL; 355 iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR); 356 357 if (master_ctl == 0 && iir == 0) 358 break; 359 360 ret = IRQ_HANDLED; 361 362 /* 363 * Theory on interrupt generation, based on empirical evidence: 364 * 365 * x = ((VLV_IIR & VLV_IER) || 366 * ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) && 367 * (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL))); 368 * 369 * A CPU interrupt will only be raised when 'x' has a 0->1 edge. 370 * Hence we clear GEN8_MASTER_IRQ_CONTROL and VLV_IER to 371 * guarantee the CPU interrupt will be raised again even if we 372 * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL 373 * bits this time around. 374 */ 375 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, 0); 376 ier = intel_uncore_rmw(&dev_priv->uncore, VLV_IER, ~0, 0); 377 378 gen8_gt_irq_handler(to_gt(dev_priv), master_ctl); 379 380 if (iir & I915_DISPLAY_PORT_INTERRUPT) 381 hotplug_status = i9xx_hpd_irq_ack(dev_priv); 382 383 /* Call regardless, as some status bits might not be 384 * signalled in iir */ 385 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); 386 387 if (iir & (I915_LPE_PIPE_A_INTERRUPT | 388 I915_LPE_PIPE_B_INTERRUPT | 389 I915_LPE_PIPE_C_INTERRUPT)) 390 intel_lpe_audio_irq_handler(dev_priv); 391 392 /* 393 * VLV_IIR is single buffered, and reflects the level 394 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last. 395 */ 396 if (iir) 397 intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir); 398 399 intel_uncore_write(&dev_priv->uncore, VLV_IER, ier); 400 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); 401 402 if (hotplug_status) 403 i9xx_hpd_irq_handler(dev_priv, hotplug_status); 404 405 valleyview_pipestat_irq_handler(dev_priv, pipe_stats); 406 } while (0); 407 408 pmu_irq_stats(dev_priv, ret); 409 410 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 411 412 return ret; 413 } 414 415 /* 416 * To handle irqs with the minimum potential races with fresh interrupts, we: 417 * 1 - Disable Master Interrupt Control. 418 * 2 - Find the source(s) of the interrupt. 419 * 3 - Clear the Interrupt Identity bits (IIR). 420 * 4 - Process the interrupt(s) that had bits set in the IIRs. 421 * 5 - Re-enable Master Interrupt Control. 422 */ 423 static irqreturn_t ilk_irq_handler(int irq, void *arg) 424 { 425 struct drm_i915_private *i915 = arg; 426 void __iomem * const regs = i915->uncore.regs; 427 u32 de_iir, gt_iir, de_ier, sde_ier = 0; 428 irqreturn_t ret = IRQ_NONE; 429 430 if (unlikely(!intel_irqs_enabled(i915))) 431 return IRQ_NONE; 432 433 /* IRQs are synced during runtime_suspend, we don't require a wakeref */ 434 disable_rpm_wakeref_asserts(&i915->runtime_pm); 435 436 /* disable master interrupt before clearing iir */ 437 de_ier = raw_reg_read(regs, DEIER); 438 raw_reg_write(regs, DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); 439 440 /* Disable south interrupts. We'll only write to SDEIIR once, so further 441 * interrupts will will be stored on its back queue, and then we'll be 442 * able to process them after we restore SDEIER (as soon as we restore 443 * it, we'll get an interrupt if SDEIIR still has something to process 444 * due to its back queue). */ 445 if (!HAS_PCH_NOP(i915)) { 446 sde_ier = raw_reg_read(regs, SDEIER); 447 raw_reg_write(regs, SDEIER, 0); 448 } 449 450 /* Find, clear, then process each source of interrupt */ 451 452 gt_iir = raw_reg_read(regs, GTIIR); 453 if (gt_iir) { 454 raw_reg_write(regs, GTIIR, gt_iir); 455 if (GRAPHICS_VER(i915) >= 6) 456 gen6_gt_irq_handler(to_gt(i915), gt_iir); 457 else 458 gen5_gt_irq_handler(to_gt(i915), gt_iir); 459 ret = IRQ_HANDLED; 460 } 461 462 de_iir = raw_reg_read(regs, DEIIR); 463 if (de_iir) { 464 raw_reg_write(regs, DEIIR, de_iir); 465 if (DISPLAY_VER(i915) >= 7) 466 ivb_display_irq_handler(i915, de_iir); 467 else 468 ilk_display_irq_handler(i915, de_iir); 469 ret = IRQ_HANDLED; 470 } 471 472 if (GRAPHICS_VER(i915) >= 6) { 473 u32 pm_iir = raw_reg_read(regs, GEN6_PMIIR); 474 if (pm_iir) { 475 raw_reg_write(regs, GEN6_PMIIR, pm_iir); 476 gen6_rps_irq_handler(&to_gt(i915)->rps, pm_iir); 477 ret = IRQ_HANDLED; 478 } 479 } 480 481 raw_reg_write(regs, DEIER, de_ier); 482 if (sde_ier) 483 raw_reg_write(regs, SDEIER, sde_ier); 484 485 pmu_irq_stats(i915, ret); 486 487 /* IRQs are synced during runtime_suspend, we don't require a wakeref */ 488 enable_rpm_wakeref_asserts(&i915->runtime_pm); 489 490 return ret; 491 } 492 493 static inline u32 gen8_master_intr_disable(void __iomem * const regs) 494 { 495 raw_reg_write(regs, GEN8_MASTER_IRQ, 0); 496 497 /* 498 * Now with master disabled, get a sample of level indications 499 * for this interrupt. Indications will be cleared on related acks. 500 * New indications can and will light up during processing, 501 * and will generate new interrupt after enabling master. 502 */ 503 return raw_reg_read(regs, GEN8_MASTER_IRQ); 504 } 505 506 static inline void gen8_master_intr_enable(void __iomem * const regs) 507 { 508 raw_reg_write(regs, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); 509 } 510 511 static irqreturn_t gen8_irq_handler(int irq, void *arg) 512 { 513 struct drm_i915_private *dev_priv = arg; 514 void __iomem * const regs = dev_priv->uncore.regs; 515 u32 master_ctl; 516 517 if (!intel_irqs_enabled(dev_priv)) 518 return IRQ_NONE; 519 520 master_ctl = gen8_master_intr_disable(regs); 521 if (!master_ctl) { 522 gen8_master_intr_enable(regs); 523 return IRQ_NONE; 524 } 525 526 /* Find, queue (onto bottom-halves), then clear each source */ 527 gen8_gt_irq_handler(to_gt(dev_priv), master_ctl); 528 529 /* IRQs are synced during runtime_suspend, we don't require a wakeref */ 530 if (master_ctl & ~GEN8_GT_IRQS) { 531 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 532 gen8_de_irq_handler(dev_priv, master_ctl); 533 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 534 } 535 536 gen8_master_intr_enable(regs); 537 538 pmu_irq_stats(dev_priv, IRQ_HANDLED); 539 540 return IRQ_HANDLED; 541 } 542 543 static inline u32 gen11_master_intr_disable(void __iomem * const regs) 544 { 545 raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, 0); 546 547 /* 548 * Now with master disabled, get a sample of level indications 549 * for this interrupt. Indications will be cleared on related acks. 550 * New indications can and will light up during processing, 551 * and will generate new interrupt after enabling master. 552 */ 553 return raw_reg_read(regs, GEN11_GFX_MSTR_IRQ); 554 } 555 556 static inline void gen11_master_intr_enable(void __iomem * const regs) 557 { 558 raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ); 559 } 560 561 static irqreturn_t gen11_irq_handler(int irq, void *arg) 562 { 563 struct drm_i915_private *i915 = arg; 564 void __iomem * const regs = i915->uncore.regs; 565 struct intel_gt *gt = to_gt(i915); 566 u32 master_ctl; 567 u32 gu_misc_iir; 568 569 if (!intel_irqs_enabled(i915)) 570 return IRQ_NONE; 571 572 master_ctl = gen11_master_intr_disable(regs); 573 if (!master_ctl) { 574 gen11_master_intr_enable(regs); 575 return IRQ_NONE; 576 } 577 578 /* Find, queue (onto bottom-halves), then clear each source */ 579 gen11_gt_irq_handler(gt, master_ctl); 580 581 /* IRQs are synced during runtime_suspend, we don't require a wakeref */ 582 if (master_ctl & GEN11_DISPLAY_IRQ) 583 gen11_display_irq_handler(i915); 584 585 gu_misc_iir = gen11_gu_misc_irq_ack(i915, master_ctl); 586 587 gen11_master_intr_enable(regs); 588 589 gen11_gu_misc_irq_handler(i915, gu_misc_iir); 590 591 pmu_irq_stats(i915, IRQ_HANDLED); 592 593 return IRQ_HANDLED; 594 } 595 596 static inline u32 dg1_master_intr_disable(void __iomem * const regs) 597 { 598 u32 val; 599 600 /* First disable interrupts */ 601 raw_reg_write(regs, DG1_MSTR_TILE_INTR, 0); 602 603 /* Get the indication levels and ack the master unit */ 604 val = raw_reg_read(regs, DG1_MSTR_TILE_INTR); 605 if (unlikely(!val)) 606 return 0; 607 608 raw_reg_write(regs, DG1_MSTR_TILE_INTR, val); 609 610 return val; 611 } 612 613 static inline void dg1_master_intr_enable(void __iomem * const regs) 614 { 615 raw_reg_write(regs, DG1_MSTR_TILE_INTR, DG1_MSTR_IRQ); 616 } 617 618 static irqreturn_t dg1_irq_handler(int irq, void *arg) 619 { 620 struct drm_i915_private * const i915 = arg; 621 struct intel_gt *gt = to_gt(i915); 622 void __iomem * const regs = gt->uncore->regs; 623 u32 master_tile_ctl, master_ctl; 624 u32 gu_misc_iir; 625 626 if (!intel_irqs_enabled(i915)) 627 return IRQ_NONE; 628 629 master_tile_ctl = dg1_master_intr_disable(regs); 630 if (!master_tile_ctl) { 631 dg1_master_intr_enable(regs); 632 return IRQ_NONE; 633 } 634 635 /* FIXME: we only support tile 0 for now. */ 636 if (master_tile_ctl & DG1_MSTR_TILE(0)) { 637 master_ctl = raw_reg_read(regs, GEN11_GFX_MSTR_IRQ); 638 raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, master_ctl); 639 } else { 640 drm_err(&i915->drm, "Tile not supported: 0x%08x\n", 641 master_tile_ctl); 642 dg1_master_intr_enable(regs); 643 return IRQ_NONE; 644 } 645 646 gen11_gt_irq_handler(gt, master_ctl); 647 648 if (master_ctl & GEN11_DISPLAY_IRQ) 649 gen11_display_irq_handler(i915); 650 651 gu_misc_iir = gen11_gu_misc_irq_ack(i915, master_ctl); 652 653 dg1_master_intr_enable(regs); 654 655 gen11_gu_misc_irq_handler(i915, gu_misc_iir); 656 657 pmu_irq_stats(i915, IRQ_HANDLED); 658 659 return IRQ_HANDLED; 660 } 661 662 static void ibx_irq_reset(struct drm_i915_private *dev_priv) 663 { 664 struct intel_uncore *uncore = &dev_priv->uncore; 665 666 if (HAS_PCH_NOP(dev_priv)) 667 return; 668 669 GEN3_IRQ_RESET(uncore, SDE); 670 671 if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv)) 672 intel_uncore_write(&dev_priv->uncore, SERR_INT, 0xffffffff); 673 } 674 675 /* drm_dma.h hooks 676 */ 677 static void ilk_irq_reset(struct drm_i915_private *dev_priv) 678 { 679 struct intel_uncore *uncore = &dev_priv->uncore; 680 681 GEN3_IRQ_RESET(uncore, DE); 682 dev_priv->irq_mask = ~0u; 683 684 if (GRAPHICS_VER(dev_priv) == 7) 685 intel_uncore_write(uncore, GEN7_ERR_INT, 0xffffffff); 686 687 if (IS_HASWELL(dev_priv)) { 688 intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff); 689 intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff); 690 } 691 692 gen5_gt_irq_reset(to_gt(dev_priv)); 693 694 ibx_irq_reset(dev_priv); 695 } 696 697 static void valleyview_irq_reset(struct drm_i915_private *dev_priv) 698 { 699 intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, 0); 700 intel_uncore_posting_read(&dev_priv->uncore, VLV_MASTER_IER); 701 702 gen5_gt_irq_reset(to_gt(dev_priv)); 703 704 spin_lock_irq(&dev_priv->irq_lock); 705 if (dev_priv->display_irqs_enabled) 706 vlv_display_irq_reset(dev_priv); 707 spin_unlock_irq(&dev_priv->irq_lock); 708 } 709 710 static void gen8_irq_reset(struct drm_i915_private *dev_priv) 711 { 712 struct intel_uncore *uncore = &dev_priv->uncore; 713 714 gen8_master_intr_disable(uncore->regs); 715 716 gen8_gt_irq_reset(to_gt(dev_priv)); 717 gen8_display_irq_reset(dev_priv); 718 GEN3_IRQ_RESET(uncore, GEN8_PCU_); 719 720 if (HAS_PCH_SPLIT(dev_priv)) 721 ibx_irq_reset(dev_priv); 722 723 } 724 725 static void gen11_irq_reset(struct drm_i915_private *dev_priv) 726 { 727 struct intel_gt *gt = to_gt(dev_priv); 728 struct intel_uncore *uncore = gt->uncore; 729 730 gen11_master_intr_disable(dev_priv->uncore.regs); 731 732 gen11_gt_irq_reset(gt); 733 gen11_display_irq_reset(dev_priv); 734 735 GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_); 736 GEN3_IRQ_RESET(uncore, GEN8_PCU_); 737 } 738 739 static void dg1_irq_reset(struct drm_i915_private *dev_priv) 740 { 741 struct intel_uncore *uncore = &dev_priv->uncore; 742 struct intel_gt *gt; 743 unsigned int i; 744 745 dg1_master_intr_disable(dev_priv->uncore.regs); 746 747 for_each_gt(gt, dev_priv, i) 748 gen11_gt_irq_reset(gt); 749 750 gen11_display_irq_reset(dev_priv); 751 752 GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_); 753 GEN3_IRQ_RESET(uncore, GEN8_PCU_); 754 } 755 756 static void cherryview_irq_reset(struct drm_i915_private *dev_priv) 757 { 758 struct intel_uncore *uncore = &dev_priv->uncore; 759 760 intel_uncore_write(uncore, GEN8_MASTER_IRQ, 0); 761 intel_uncore_posting_read(&dev_priv->uncore, GEN8_MASTER_IRQ); 762 763 gen8_gt_irq_reset(to_gt(dev_priv)); 764 765 GEN3_IRQ_RESET(uncore, GEN8_PCU_); 766 767 spin_lock_irq(&dev_priv->irq_lock); 768 if (dev_priv->display_irqs_enabled) 769 vlv_display_irq_reset(dev_priv); 770 spin_unlock_irq(&dev_priv->irq_lock); 771 } 772 773 static void ilk_irq_postinstall(struct drm_i915_private *dev_priv) 774 { 775 struct intel_uncore *uncore = &dev_priv->uncore; 776 u32 display_mask, extra_mask; 777 778 if (GRAPHICS_VER(dev_priv) >= 7) { 779 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | 780 DE_PCH_EVENT_IVB | DE_AUX_CHANNEL_A_IVB); 781 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB | 782 DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB | 783 DE_PLANE_FLIP_DONE_IVB(PLANE_C) | 784 DE_PLANE_FLIP_DONE_IVB(PLANE_B) | 785 DE_PLANE_FLIP_DONE_IVB(PLANE_A) | 786 DE_DP_A_HOTPLUG_IVB); 787 } else { 788 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | 789 DE_AUX_CHANNEL_A | DE_PIPEB_CRC_DONE | 790 DE_PIPEA_CRC_DONE | DE_POISON); 791 extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | 792 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN | 793 DE_PLANE_FLIP_DONE(PLANE_A) | 794 DE_PLANE_FLIP_DONE(PLANE_B) | 795 DE_DP_A_HOTPLUG); 796 } 797 798 if (IS_HASWELL(dev_priv)) { 799 gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR); 800 display_mask |= DE_EDP_PSR_INT_HSW; 801 } 802 803 if (IS_IRONLAKE_M(dev_priv)) 804 extra_mask |= DE_PCU_EVENT; 805 806 dev_priv->irq_mask = ~display_mask; 807 808 ibx_irq_postinstall(dev_priv); 809 810 gen5_gt_irq_postinstall(to_gt(dev_priv)); 811 812 GEN3_IRQ_INIT(uncore, DE, dev_priv->irq_mask, 813 display_mask | extra_mask); 814 } 815 816 static void valleyview_irq_postinstall(struct drm_i915_private *dev_priv) 817 { 818 gen5_gt_irq_postinstall(to_gt(dev_priv)); 819 820 spin_lock_irq(&dev_priv->irq_lock); 821 if (dev_priv->display_irqs_enabled) 822 vlv_display_irq_postinstall(dev_priv); 823 spin_unlock_irq(&dev_priv->irq_lock); 824 825 intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); 826 intel_uncore_posting_read(&dev_priv->uncore, VLV_MASTER_IER); 827 } 828 829 static void gen8_irq_postinstall(struct drm_i915_private *dev_priv) 830 { 831 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 832 icp_irq_postinstall(dev_priv); 833 else if (HAS_PCH_SPLIT(dev_priv)) 834 ibx_irq_postinstall(dev_priv); 835 836 gen8_gt_irq_postinstall(to_gt(dev_priv)); 837 gen8_de_irq_postinstall(dev_priv); 838 839 gen8_master_intr_enable(dev_priv->uncore.regs); 840 } 841 842 static void gen11_irq_postinstall(struct drm_i915_private *dev_priv) 843 { 844 struct intel_gt *gt = to_gt(dev_priv); 845 struct intel_uncore *uncore = gt->uncore; 846 u32 gu_misc_masked = GEN11_GU_MISC_GSE; 847 848 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 849 icp_irq_postinstall(dev_priv); 850 851 gen11_gt_irq_postinstall(gt); 852 gen11_de_irq_postinstall(dev_priv); 853 854 GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked); 855 856 gen11_master_intr_enable(uncore->regs); 857 intel_uncore_posting_read(&dev_priv->uncore, GEN11_GFX_MSTR_IRQ); 858 } 859 860 static void dg1_irq_postinstall(struct drm_i915_private *dev_priv) 861 { 862 struct intel_uncore *uncore = &dev_priv->uncore; 863 u32 gu_misc_masked = GEN11_GU_MISC_GSE; 864 struct intel_gt *gt; 865 unsigned int i; 866 867 for_each_gt(gt, dev_priv, i) 868 gen11_gt_irq_postinstall(gt); 869 870 GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked); 871 872 if (HAS_DISPLAY(dev_priv)) { 873 if (DISPLAY_VER(dev_priv) >= 14) 874 mtp_irq_postinstall(dev_priv); 875 else 876 icp_irq_postinstall(dev_priv); 877 878 gen8_de_irq_postinstall(dev_priv); 879 intel_uncore_write(&dev_priv->uncore, GEN11_DISPLAY_INT_CTL, 880 GEN11_DISPLAY_IRQ_ENABLE); 881 } 882 883 dg1_master_intr_enable(uncore->regs); 884 intel_uncore_posting_read(uncore, DG1_MSTR_TILE_INTR); 885 } 886 887 static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv) 888 { 889 gen8_gt_irq_postinstall(to_gt(dev_priv)); 890 891 spin_lock_irq(&dev_priv->irq_lock); 892 if (dev_priv->display_irqs_enabled) 893 vlv_display_irq_postinstall(dev_priv); 894 spin_unlock_irq(&dev_priv->irq_lock); 895 896 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); 897 intel_uncore_posting_read(&dev_priv->uncore, GEN8_MASTER_IRQ); 898 } 899 900 static void i8xx_irq_reset(struct drm_i915_private *dev_priv) 901 { 902 struct intel_uncore *uncore = &dev_priv->uncore; 903 904 i9xx_pipestat_irq_reset(dev_priv); 905 906 gen2_irq_reset(uncore); 907 dev_priv->irq_mask = ~0u; 908 } 909 910 static u32 i9xx_error_mask(struct drm_i915_private *i915) 911 { 912 /* 913 * On gen2/3 FBC generates (seemingly spurious) 914 * display INVALID_GTT/INVALID_GTT_PTE table errors. 915 * 916 * Also gen3 bspec has this to say: 917 * "DISPA_INVALID_GTT_PTE 918 " [DevNapa] : Reserved. This bit does not reflect the page 919 " table error for the display plane A." 920 * 921 * Unfortunately we can't mask off individual PGTBL_ER bits, 922 * so we just have to mask off all page table errors via EMR. 923 */ 924 if (HAS_FBC(i915)) 925 return ~I915_ERROR_MEMORY_REFRESH; 926 else 927 return ~(I915_ERROR_PAGE_TABLE | 928 I915_ERROR_MEMORY_REFRESH); 929 } 930 931 static void i8xx_irq_postinstall(struct drm_i915_private *dev_priv) 932 { 933 struct intel_uncore *uncore = &dev_priv->uncore; 934 u16 enable_mask; 935 936 intel_uncore_write16(uncore, EMR, i9xx_error_mask(dev_priv)); 937 938 /* Unmask the interrupts that we always want on. */ 939 dev_priv->irq_mask = 940 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 941 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 942 I915_MASTER_ERROR_INTERRUPT); 943 944 enable_mask = 945 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 946 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 947 I915_MASTER_ERROR_INTERRUPT | 948 I915_USER_INTERRUPT; 949 950 gen2_irq_init(uncore, dev_priv->irq_mask, enable_mask); 951 952 /* Interrupt setup is already guaranteed to be single-threaded, this is 953 * just to make the assert_spin_locked check happy. */ 954 spin_lock_irq(&dev_priv->irq_lock); 955 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); 956 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); 957 spin_unlock_irq(&dev_priv->irq_lock); 958 } 959 960 static void i8xx_error_irq_ack(struct drm_i915_private *i915, 961 u16 *eir, u16 *eir_stuck) 962 { 963 struct intel_uncore *uncore = &i915->uncore; 964 u16 emr; 965 966 *eir = intel_uncore_read16(uncore, EIR); 967 intel_uncore_write16(uncore, EIR, *eir); 968 969 *eir_stuck = intel_uncore_read16(uncore, EIR); 970 if (*eir_stuck == 0) 971 return; 972 973 /* 974 * Toggle all EMR bits to make sure we get an edge 975 * in the ISR master error bit if we don't clear 976 * all the EIR bits. Otherwise the edge triggered 977 * IIR on i965/g4x wouldn't notice that an interrupt 978 * is still pending. Also some EIR bits can't be 979 * cleared except by handling the underlying error 980 * (or by a GPU reset) so we mask any bit that 981 * remains set. 982 */ 983 emr = intel_uncore_read16(uncore, EMR); 984 intel_uncore_write16(uncore, EMR, 0xffff); 985 intel_uncore_write16(uncore, EMR, emr | *eir_stuck); 986 } 987 988 static void i8xx_error_irq_handler(struct drm_i915_private *dev_priv, 989 u16 eir, u16 eir_stuck) 990 { 991 drm_dbg(&dev_priv->drm, "Master Error: EIR 0x%04x\n", eir); 992 993 if (eir_stuck) 994 drm_dbg(&dev_priv->drm, "EIR stuck: 0x%04x, masked\n", 995 eir_stuck); 996 997 drm_dbg(&dev_priv->drm, "PGTBL_ER: 0x%08x\n", 998 intel_uncore_read(&dev_priv->uncore, PGTBL_ER)); 999 } 1000 1001 static void i9xx_error_irq_ack(struct drm_i915_private *dev_priv, 1002 u32 *eir, u32 *eir_stuck) 1003 { 1004 u32 emr; 1005 1006 *eir = intel_uncore_read(&dev_priv->uncore, EIR); 1007 intel_uncore_write(&dev_priv->uncore, EIR, *eir); 1008 1009 *eir_stuck = intel_uncore_read(&dev_priv->uncore, EIR); 1010 if (*eir_stuck == 0) 1011 return; 1012 1013 /* 1014 * Toggle all EMR bits to make sure we get an edge 1015 * in the ISR master error bit if we don't clear 1016 * all the EIR bits. Otherwise the edge triggered 1017 * IIR on i965/g4x wouldn't notice that an interrupt 1018 * is still pending. Also some EIR bits can't be 1019 * cleared except by handling the underlying error 1020 * (or by a GPU reset) so we mask any bit that 1021 * remains set. 1022 */ 1023 emr = intel_uncore_read(&dev_priv->uncore, EMR); 1024 intel_uncore_write(&dev_priv->uncore, EMR, 0xffffffff); 1025 intel_uncore_write(&dev_priv->uncore, EMR, emr | *eir_stuck); 1026 } 1027 1028 static void i9xx_error_irq_handler(struct drm_i915_private *dev_priv, 1029 u32 eir, u32 eir_stuck) 1030 { 1031 drm_dbg(&dev_priv->drm, "Master Error, EIR 0x%08x\n", eir); 1032 1033 if (eir_stuck) 1034 drm_dbg(&dev_priv->drm, "EIR stuck: 0x%08x, masked\n", 1035 eir_stuck); 1036 1037 drm_dbg(&dev_priv->drm, "PGTBL_ER: 0x%08x\n", 1038 intel_uncore_read(&dev_priv->uncore, PGTBL_ER)); 1039 } 1040 1041 static irqreturn_t i8xx_irq_handler(int irq, void *arg) 1042 { 1043 struct drm_i915_private *dev_priv = arg; 1044 irqreturn_t ret = IRQ_NONE; 1045 1046 if (!intel_irqs_enabled(dev_priv)) 1047 return IRQ_NONE; 1048 1049 /* IRQs are synced during runtime_suspend, we don't require a wakeref */ 1050 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1051 1052 do { 1053 u32 pipe_stats[I915_MAX_PIPES] = {}; 1054 u16 eir = 0, eir_stuck = 0; 1055 u16 iir; 1056 1057 iir = intel_uncore_read16(&dev_priv->uncore, GEN2_IIR); 1058 if (iir == 0) 1059 break; 1060 1061 ret = IRQ_HANDLED; 1062 1063 /* Call regardless, as some status bits might not be 1064 * signalled in iir */ 1065 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); 1066 1067 if (iir & I915_MASTER_ERROR_INTERRUPT) 1068 i8xx_error_irq_ack(dev_priv, &eir, &eir_stuck); 1069 1070 intel_uncore_write16(&dev_priv->uncore, GEN2_IIR, iir); 1071 1072 if (iir & I915_USER_INTERRUPT) 1073 intel_engine_cs_irq(to_gt(dev_priv)->engine[RCS0], iir); 1074 1075 if (iir & I915_MASTER_ERROR_INTERRUPT) 1076 i8xx_error_irq_handler(dev_priv, eir, eir_stuck); 1077 1078 i8xx_pipestat_irq_handler(dev_priv, iir, pipe_stats); 1079 } while (0); 1080 1081 pmu_irq_stats(dev_priv, ret); 1082 1083 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1084 1085 return ret; 1086 } 1087 1088 static void i915_irq_reset(struct drm_i915_private *dev_priv) 1089 { 1090 struct intel_uncore *uncore = &dev_priv->uncore; 1091 1092 if (I915_HAS_HOTPLUG(dev_priv)) { 1093 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); 1094 intel_uncore_rmw(&dev_priv->uncore, PORT_HOTPLUG_STAT, 0, 0); 1095 } 1096 1097 i9xx_pipestat_irq_reset(dev_priv); 1098 1099 GEN3_IRQ_RESET(uncore, GEN2_); 1100 dev_priv->irq_mask = ~0u; 1101 } 1102 1103 static void i915_irq_postinstall(struct drm_i915_private *dev_priv) 1104 { 1105 struct intel_uncore *uncore = &dev_priv->uncore; 1106 u32 enable_mask; 1107 1108 intel_uncore_write(uncore, EMR, i9xx_error_mask(dev_priv)); 1109 1110 /* Unmask the interrupts that we always want on. */ 1111 dev_priv->irq_mask = 1112 ~(I915_ASLE_INTERRUPT | 1113 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 1114 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 1115 I915_MASTER_ERROR_INTERRUPT); 1116 1117 enable_mask = 1118 I915_ASLE_INTERRUPT | 1119 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 1120 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 1121 I915_MASTER_ERROR_INTERRUPT | 1122 I915_USER_INTERRUPT; 1123 1124 if (I915_HAS_HOTPLUG(dev_priv)) { 1125 /* Enable in IER... */ 1126 enable_mask |= I915_DISPLAY_PORT_INTERRUPT; 1127 /* and unmask in IMR */ 1128 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; 1129 } 1130 1131 GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask); 1132 1133 /* Interrupt setup is already guaranteed to be single-threaded, this is 1134 * just to make the assert_spin_locked check happy. */ 1135 spin_lock_irq(&dev_priv->irq_lock); 1136 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); 1137 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); 1138 spin_unlock_irq(&dev_priv->irq_lock); 1139 1140 i915_enable_asle_pipestat(dev_priv); 1141 } 1142 1143 static irqreturn_t i915_irq_handler(int irq, void *arg) 1144 { 1145 struct drm_i915_private *dev_priv = arg; 1146 irqreturn_t ret = IRQ_NONE; 1147 1148 if (!intel_irqs_enabled(dev_priv)) 1149 return IRQ_NONE; 1150 1151 /* IRQs are synced during runtime_suspend, we don't require a wakeref */ 1152 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1153 1154 do { 1155 u32 pipe_stats[I915_MAX_PIPES] = {}; 1156 u32 eir = 0, eir_stuck = 0; 1157 u32 hotplug_status = 0; 1158 u32 iir; 1159 1160 iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR); 1161 if (iir == 0) 1162 break; 1163 1164 ret = IRQ_HANDLED; 1165 1166 if (I915_HAS_HOTPLUG(dev_priv) && 1167 iir & I915_DISPLAY_PORT_INTERRUPT) 1168 hotplug_status = i9xx_hpd_irq_ack(dev_priv); 1169 1170 /* Call regardless, as some status bits might not be 1171 * signalled in iir */ 1172 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); 1173 1174 if (iir & I915_MASTER_ERROR_INTERRUPT) 1175 i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck); 1176 1177 intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir); 1178 1179 if (iir & I915_USER_INTERRUPT) 1180 intel_engine_cs_irq(to_gt(dev_priv)->engine[RCS0], iir); 1181 1182 if (iir & I915_MASTER_ERROR_INTERRUPT) 1183 i9xx_error_irq_handler(dev_priv, eir, eir_stuck); 1184 1185 if (hotplug_status) 1186 i9xx_hpd_irq_handler(dev_priv, hotplug_status); 1187 1188 i915_pipestat_irq_handler(dev_priv, iir, pipe_stats); 1189 } while (0); 1190 1191 pmu_irq_stats(dev_priv, ret); 1192 1193 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1194 1195 return ret; 1196 } 1197 1198 static void i965_irq_reset(struct drm_i915_private *dev_priv) 1199 { 1200 struct intel_uncore *uncore = &dev_priv->uncore; 1201 1202 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); 1203 intel_uncore_rmw(uncore, PORT_HOTPLUG_STAT, 0, 0); 1204 1205 i9xx_pipestat_irq_reset(dev_priv); 1206 1207 GEN3_IRQ_RESET(uncore, GEN2_); 1208 dev_priv->irq_mask = ~0u; 1209 } 1210 1211 static u32 i965_error_mask(struct drm_i915_private *i915) 1212 { 1213 /* 1214 * Enable some error detection, note the instruction error mask 1215 * bit is reserved, so we leave it masked. 1216 * 1217 * i965 FBC no longer generates spurious GTT errors, 1218 * so we can always enable the page table errors. 1219 */ 1220 if (IS_G4X(i915)) 1221 return ~(GM45_ERROR_PAGE_TABLE | 1222 GM45_ERROR_MEM_PRIV | 1223 GM45_ERROR_CP_PRIV | 1224 I915_ERROR_MEMORY_REFRESH); 1225 else 1226 return ~(I915_ERROR_PAGE_TABLE | 1227 I915_ERROR_MEMORY_REFRESH); 1228 } 1229 1230 static void i965_irq_postinstall(struct drm_i915_private *dev_priv) 1231 { 1232 struct intel_uncore *uncore = &dev_priv->uncore; 1233 u32 enable_mask; 1234 1235 intel_uncore_write(uncore, EMR, i965_error_mask(dev_priv)); 1236 1237 /* Unmask the interrupts that we always want on. */ 1238 dev_priv->irq_mask = 1239 ~(I915_ASLE_INTERRUPT | 1240 I915_DISPLAY_PORT_INTERRUPT | 1241 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 1242 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 1243 I915_MASTER_ERROR_INTERRUPT); 1244 1245 enable_mask = 1246 I915_ASLE_INTERRUPT | 1247 I915_DISPLAY_PORT_INTERRUPT | 1248 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 1249 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 1250 I915_MASTER_ERROR_INTERRUPT | 1251 I915_USER_INTERRUPT; 1252 1253 if (IS_G4X(dev_priv)) 1254 enable_mask |= I915_BSD_USER_INTERRUPT; 1255 1256 GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask); 1257 1258 /* Interrupt setup is already guaranteed to be single-threaded, this is 1259 * just to make the assert_spin_locked check happy. */ 1260 spin_lock_irq(&dev_priv->irq_lock); 1261 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); 1262 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); 1263 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); 1264 spin_unlock_irq(&dev_priv->irq_lock); 1265 1266 i915_enable_asle_pipestat(dev_priv); 1267 } 1268 1269 static irqreturn_t i965_irq_handler(int irq, void *arg) 1270 { 1271 struct drm_i915_private *dev_priv = arg; 1272 irqreturn_t ret = IRQ_NONE; 1273 1274 if (!intel_irqs_enabled(dev_priv)) 1275 return IRQ_NONE; 1276 1277 /* IRQs are synced during runtime_suspend, we don't require a wakeref */ 1278 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1279 1280 do { 1281 u32 pipe_stats[I915_MAX_PIPES] = {}; 1282 u32 eir = 0, eir_stuck = 0; 1283 u32 hotplug_status = 0; 1284 u32 iir; 1285 1286 iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR); 1287 if (iir == 0) 1288 break; 1289 1290 ret = IRQ_HANDLED; 1291 1292 if (iir & I915_DISPLAY_PORT_INTERRUPT) 1293 hotplug_status = i9xx_hpd_irq_ack(dev_priv); 1294 1295 /* Call regardless, as some status bits might not be 1296 * signalled in iir */ 1297 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); 1298 1299 if (iir & I915_MASTER_ERROR_INTERRUPT) 1300 i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck); 1301 1302 intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir); 1303 1304 if (iir & I915_USER_INTERRUPT) 1305 intel_engine_cs_irq(to_gt(dev_priv)->engine[RCS0], 1306 iir); 1307 1308 if (iir & I915_BSD_USER_INTERRUPT) 1309 intel_engine_cs_irq(to_gt(dev_priv)->engine[VCS0], 1310 iir >> 25); 1311 1312 if (iir & I915_MASTER_ERROR_INTERRUPT) 1313 i9xx_error_irq_handler(dev_priv, eir, eir_stuck); 1314 1315 if (hotplug_status) 1316 i9xx_hpd_irq_handler(dev_priv, hotplug_status); 1317 1318 i965_pipestat_irq_handler(dev_priv, iir, pipe_stats); 1319 } while (0); 1320 1321 pmu_irq_stats(dev_priv, IRQ_HANDLED); 1322 1323 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1324 1325 return ret; 1326 } 1327 1328 /** 1329 * intel_irq_init - initializes irq support 1330 * @dev_priv: i915 device instance 1331 * 1332 * This function initializes all the irq support including work items, timers 1333 * and all the vtables. It does not setup the interrupt itself though. 1334 */ 1335 void intel_irq_init(struct drm_i915_private *dev_priv) 1336 { 1337 int i; 1338 1339 INIT_WORK(&dev_priv->l3_parity.error_work, ivb_parity_work); 1340 for (i = 0; i < MAX_L3_SLICES; ++i) 1341 dev_priv->l3_parity.remap_info[i] = NULL; 1342 1343 /* pre-gen11 the guc irqs bits are in the upper 16 bits of the pm reg */ 1344 if (HAS_GT_UC(dev_priv) && GRAPHICS_VER(dev_priv) < 11) 1345 to_gt(dev_priv)->pm_guc_events = GUC_INTR_GUC2HOST << 16; 1346 1347 if (!HAS_DISPLAY(dev_priv)) 1348 return; 1349 1350 dev_priv->drm.vblank_disable_immediate = true; 1351 1352 /* Most platforms treat the display irq block as an always-on 1353 * power domain. vlv/chv can disable it at runtime and need 1354 * special care to avoid writing any of the display block registers 1355 * outside of the power domain. We defer setting up the display irqs 1356 * in this case to the runtime pm. 1357 */ 1358 dev_priv->display_irqs_enabled = true; 1359 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 1360 dev_priv->display_irqs_enabled = false; 1361 1362 intel_hotplug_irq_init(dev_priv); 1363 } 1364 1365 /** 1366 * intel_irq_fini - deinitializes IRQ support 1367 * @i915: i915 device instance 1368 * 1369 * This function deinitializes all the IRQ support. 1370 */ 1371 void intel_irq_fini(struct drm_i915_private *i915) 1372 { 1373 int i; 1374 1375 for (i = 0; i < MAX_L3_SLICES; ++i) 1376 kfree(i915->l3_parity.remap_info[i]); 1377 } 1378 1379 static irq_handler_t intel_irq_handler(struct drm_i915_private *dev_priv) 1380 { 1381 if (HAS_GMCH(dev_priv)) { 1382 if (IS_CHERRYVIEW(dev_priv)) 1383 return cherryview_irq_handler; 1384 else if (IS_VALLEYVIEW(dev_priv)) 1385 return valleyview_irq_handler; 1386 else if (GRAPHICS_VER(dev_priv) == 4) 1387 return i965_irq_handler; 1388 else if (GRAPHICS_VER(dev_priv) == 3) 1389 return i915_irq_handler; 1390 else 1391 return i8xx_irq_handler; 1392 } else { 1393 if (GRAPHICS_VER_FULL(dev_priv) >= IP_VER(12, 10)) 1394 return dg1_irq_handler; 1395 else if (GRAPHICS_VER(dev_priv) >= 11) 1396 return gen11_irq_handler; 1397 else if (GRAPHICS_VER(dev_priv) >= 8) 1398 return gen8_irq_handler; 1399 else 1400 return ilk_irq_handler; 1401 } 1402 } 1403 1404 static void intel_irq_reset(struct drm_i915_private *dev_priv) 1405 { 1406 if (HAS_GMCH(dev_priv)) { 1407 if (IS_CHERRYVIEW(dev_priv)) 1408 cherryview_irq_reset(dev_priv); 1409 else if (IS_VALLEYVIEW(dev_priv)) 1410 valleyview_irq_reset(dev_priv); 1411 else if (GRAPHICS_VER(dev_priv) == 4) 1412 i965_irq_reset(dev_priv); 1413 else if (GRAPHICS_VER(dev_priv) == 3) 1414 i915_irq_reset(dev_priv); 1415 else 1416 i8xx_irq_reset(dev_priv); 1417 } else { 1418 if (GRAPHICS_VER_FULL(dev_priv) >= IP_VER(12, 10)) 1419 dg1_irq_reset(dev_priv); 1420 else if (GRAPHICS_VER(dev_priv) >= 11) 1421 gen11_irq_reset(dev_priv); 1422 else if (GRAPHICS_VER(dev_priv) >= 8) 1423 gen8_irq_reset(dev_priv); 1424 else 1425 ilk_irq_reset(dev_priv); 1426 } 1427 } 1428 1429 static void intel_irq_postinstall(struct drm_i915_private *dev_priv) 1430 { 1431 if (HAS_GMCH(dev_priv)) { 1432 if (IS_CHERRYVIEW(dev_priv)) 1433 cherryview_irq_postinstall(dev_priv); 1434 else if (IS_VALLEYVIEW(dev_priv)) 1435 valleyview_irq_postinstall(dev_priv); 1436 else if (GRAPHICS_VER(dev_priv) == 4) 1437 i965_irq_postinstall(dev_priv); 1438 else if (GRAPHICS_VER(dev_priv) == 3) 1439 i915_irq_postinstall(dev_priv); 1440 else 1441 i8xx_irq_postinstall(dev_priv); 1442 } else { 1443 if (GRAPHICS_VER_FULL(dev_priv) >= IP_VER(12, 10)) 1444 dg1_irq_postinstall(dev_priv); 1445 else if (GRAPHICS_VER(dev_priv) >= 11) 1446 gen11_irq_postinstall(dev_priv); 1447 else if (GRAPHICS_VER(dev_priv) >= 8) 1448 gen8_irq_postinstall(dev_priv); 1449 else 1450 ilk_irq_postinstall(dev_priv); 1451 } 1452 } 1453 1454 /** 1455 * intel_irq_install - enables the hardware interrupt 1456 * @dev_priv: i915 device instance 1457 * 1458 * This function enables the hardware interrupt handling, but leaves the hotplug 1459 * handling still disabled. It is called after intel_irq_init(). 1460 * 1461 * In the driver load and resume code we need working interrupts in a few places 1462 * but don't want to deal with the hassle of concurrent probe and hotplug 1463 * workers. Hence the split into this two-stage approach. 1464 */ 1465 int intel_irq_install(struct drm_i915_private *dev_priv) 1466 { 1467 int irq = to_pci_dev(dev_priv->drm.dev)->irq; 1468 int ret; 1469 1470 /* 1471 * We enable some interrupt sources in our postinstall hooks, so mark 1472 * interrupts as enabled _before_ actually enabling them to avoid 1473 * special cases in our ordering checks. 1474 */ 1475 dev_priv->runtime_pm.irqs_enabled = true; 1476 1477 dev_priv->irq_enabled = true; 1478 1479 intel_irq_reset(dev_priv); 1480 1481 ret = request_irq(irq, intel_irq_handler(dev_priv), 1482 IRQF_SHARED, DRIVER_NAME, dev_priv); 1483 if (ret < 0) { 1484 dev_priv->irq_enabled = false; 1485 return ret; 1486 } 1487 1488 intel_irq_postinstall(dev_priv); 1489 1490 return ret; 1491 } 1492 1493 /** 1494 * intel_irq_uninstall - finilizes all irq handling 1495 * @dev_priv: i915 device instance 1496 * 1497 * This stops interrupt and hotplug handling and unregisters and frees all 1498 * resources acquired in the init functions. 1499 */ 1500 void intel_irq_uninstall(struct drm_i915_private *dev_priv) 1501 { 1502 int irq = to_pci_dev(dev_priv->drm.dev)->irq; 1503 1504 /* 1505 * FIXME we can get called twice during driver probe 1506 * error handling as well as during driver remove due to 1507 * intel_display_driver_remove() calling us out of sequence. 1508 * Would be nice if it didn't do that... 1509 */ 1510 if (!dev_priv->irq_enabled) 1511 return; 1512 1513 dev_priv->irq_enabled = false; 1514 1515 intel_irq_reset(dev_priv); 1516 1517 free_irq(irq, dev_priv); 1518 1519 intel_hpd_cancel_work(dev_priv); 1520 dev_priv->runtime_pm.irqs_enabled = false; 1521 } 1522 1523 /** 1524 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling 1525 * @dev_priv: i915 device instance 1526 * 1527 * This function is used to disable interrupts at runtime, both in the runtime 1528 * pm and the system suspend/resume code. 1529 */ 1530 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv) 1531 { 1532 intel_irq_reset(dev_priv); 1533 dev_priv->runtime_pm.irqs_enabled = false; 1534 intel_synchronize_irq(dev_priv); 1535 } 1536 1537 /** 1538 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling 1539 * @dev_priv: i915 device instance 1540 * 1541 * This function is used to enable interrupts at runtime, both in the runtime 1542 * pm and the system suspend/resume code. 1543 */ 1544 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv) 1545 { 1546 dev_priv->runtime_pm.irqs_enabled = true; 1547 intel_irq_reset(dev_priv); 1548 intel_irq_postinstall(dev_priv); 1549 } 1550 1551 bool intel_irqs_enabled(struct drm_i915_private *dev_priv) 1552 { 1553 return dev_priv->runtime_pm.irqs_enabled; 1554 } 1555 1556 void intel_synchronize_irq(struct drm_i915_private *i915) 1557 { 1558 synchronize_irq(to_pci_dev(i915->drm.dev)->irq); 1559 } 1560 1561 void intel_synchronize_hardirq(struct drm_i915_private *i915) 1562 { 1563 synchronize_hardirq(to_pci_dev(i915->drm.dev)->irq); 1564 } 1565