1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/soc/qcom/qcom,aoss-qmp.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Always-On Subsystem side channel
8
9maintainers:
10  - Bjorn Andersson <bjorn.andersson@linaro.org>
11
12description:
13  This binding describes the hardware component responsible for side channel
14  requests to the always-on subsystem (AOSS), used for certain power management
15  requests that is not handled by the standard RPMh interface. Each client in the
16  SoC has its own block of message RAM and IRQ for communication with the AOSS.
17  The protocol used to communicate in the message RAM is known as Qualcomm
18  Messaging Protocol (QMP)
19
20  The AOSS side channel exposes control over a set of resources, used to control
21  a set of debug related clocks and to affect the low power state of resources
22  related to the secondary subsystems.
23
24properties:
25  compatible:
26    items:
27      - enum:
28          - qcom,qdu1000-aoss-qmp
29          - qcom,sa8775p-aoss-qmp
30          - qcom,sc7180-aoss-qmp
31          - qcom,sc7280-aoss-qmp
32          - qcom,sc8180x-aoss-qmp
33          - qcom,sc8280xp-aoss-qmp
34          - qcom,sdm845-aoss-qmp
35          - qcom,sm6350-aoss-qmp
36          - qcom,sm8150-aoss-qmp
37          - qcom,sm8250-aoss-qmp
38          - qcom,sm8350-aoss-qmp
39          - qcom,sm8450-aoss-qmp
40          - qcom,sm8550-aoss-qmp
41      - const: qcom,aoss-qmp
42
43  reg:
44    maxItems: 1
45    description:
46      The base address and size of the message RAM for this client's
47      communication with the AOSS
48
49  interrupts:
50    maxItems: 1
51    description:
52      Should specify the AOSS message IRQ for this client
53
54  mboxes:
55    maxItems: 1
56    description:
57      Reference to the mailbox representing the outgoing doorbell in APCS for
58      this client, as described in mailbox/mailbox.txt
59
60  "#clock-cells":
61    const: 0
62    description:
63      The single clock represents the QDSS clock.
64
65required:
66  - compatible
67  - reg
68  - interrupts
69  - mboxes
70  - "#clock-cells"
71
72additionalProperties: false
73
74patternProperties:
75  "^(cx|mx|ebi)$":
76    type: object
77    description:
78      The AOSS side channel also provides the controls for three cooling devices,
79      these are expressed as subnodes of the QMP node. The name of the node is
80      used to identify the resource and must therefor be "cx", "mx" or "ebi".
81
82    properties:
83      "#cooling-cells":
84        const: 2
85
86    required:
87      - "#cooling-cells"
88
89    additionalProperties: false
90
91examples:
92  - |
93    #include <dt-bindings/interrupt-controller/arm-gic.h>
94
95    aoss_qmp: qmp@c300000 {
96      compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp";
97      reg = <0x0c300000 0x100000>;
98      interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
99      mboxes = <&apss_shared 0>;
100
101      #clock-cells = <0>;
102
103      cx_cdev: cx {
104        #cooling-cells = <2>;
105      };
106
107      mx_cdev: mx {
108        #cooling-cells = <2>;
109      };
110    };
111...
112