1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2021-2022 Linaro Ltd 5 * Author: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>, based on 6 * previous work of Thara Gopinath and msm-4.9 downstream sources. 7 */ 8 9 #include <linux/err.h> 10 #include <linux/interconnect.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/of_device.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm_opp.h> 18 #include <linux/regmap.h> 19 #include <linux/sizes.h> 20 21 /* 22 * The BWMON samples data throughput within 'sample_ms' time. With three 23 * configurable thresholds (Low, Medium and High) gives four windows (called 24 * zones) of current bandwidth: 25 * 26 * Zone 0: byte count < THRES_LO 27 * Zone 1: THRES_LO < byte count < THRES_MED 28 * Zone 2: THRES_MED < byte count < THRES_HIGH 29 * Zone 3: THRES_HIGH < byte count 30 * 31 * Zones 0 and 2 are not used by this driver. 32 */ 33 34 /* Internal sampling clock frequency */ 35 #define HW_TIMER_HZ 19200000 36 37 #define BWMON_V4_GLOBAL_IRQ_CLEAR 0x108 38 #define BWMON_V4_GLOBAL_IRQ_ENABLE 0x10c 39 /* 40 * All values here and further are matching regmap fields, so without absolute 41 * register offsets. 42 */ 43 #define BWMON_V4_GLOBAL_IRQ_ENABLE_ENABLE BIT(0) 44 45 /* 46 * Starting with SDM845, the BWMON4 register space has changed a bit: 47 * the global registers were jammed into the beginning of the monitor region. 48 * To keep the proper offsets, one would have to map <GLOBAL_BASE 0x200> and 49 * <GLOBAL_BASE+0x100 0x300>, which is straight up wrong. 50 * To facilitate for that, while allowing the older, arguably more proper 51 * implementations to work, offset the global registers by -0x100 to avoid 52 * having to map half of the global registers twice. 53 */ 54 #define BWMON_V4_845_OFFSET 0x100 55 #define BWMON_V4_GLOBAL_IRQ_CLEAR_845 (BWMON_V4_GLOBAL_IRQ_CLEAR - BWMON_V4_845_OFFSET) 56 #define BWMON_V4_GLOBAL_IRQ_ENABLE_845 (BWMON_V4_GLOBAL_IRQ_ENABLE - BWMON_V4_845_OFFSET) 57 58 #define BWMON_V4_IRQ_STATUS 0x100 59 #define BWMON_V4_IRQ_CLEAR 0x108 60 61 #define BWMON_V4_IRQ_ENABLE 0x10c 62 #define BWMON_IRQ_ENABLE_MASK (BIT(1) | BIT(3)) 63 #define BWMON_V5_IRQ_STATUS 0x000 64 #define BWMON_V5_IRQ_CLEAR 0x008 65 #define BWMON_V5_IRQ_ENABLE 0x00c 66 67 #define BWMON_V4_ENABLE 0x2a0 68 #define BWMON_V5_ENABLE 0x010 69 #define BWMON_ENABLE_ENABLE BIT(0) 70 71 #define BWMON_V4_CLEAR 0x2a4 72 #define BWMON_V5_CLEAR 0x014 73 #define BWMON_CLEAR_CLEAR BIT(0) 74 #define BWMON_CLEAR_CLEAR_ALL BIT(1) 75 76 #define BWMON_V4_SAMPLE_WINDOW 0x2a8 77 #define BWMON_V5_SAMPLE_WINDOW 0x020 78 79 #define BWMON_V4_THRESHOLD_HIGH 0x2ac 80 #define BWMON_V4_THRESHOLD_MED 0x2b0 81 #define BWMON_V4_THRESHOLD_LOW 0x2b4 82 #define BWMON_V5_THRESHOLD_HIGH 0x024 83 #define BWMON_V5_THRESHOLD_MED 0x028 84 #define BWMON_V5_THRESHOLD_LOW 0x02c 85 86 #define BWMON_V4_ZONE_ACTIONS 0x2b8 87 #define BWMON_V5_ZONE_ACTIONS 0x030 88 /* 89 * Actions to perform on some zone 'z' when current zone hits the threshold: 90 * Increment counter of zone 'z' 91 */ 92 #define BWMON_ZONE_ACTIONS_INCREMENT(z) (0x2 << ((z) * 2)) 93 /* Clear counter of zone 'z' */ 94 #define BWMON_ZONE_ACTIONS_CLEAR(z) (0x1 << ((z) * 2)) 95 96 /* Zone 0 threshold hit: Clear zone count */ 97 #define BWMON_ZONE_ACTIONS_ZONE0 (BWMON_ZONE_ACTIONS_CLEAR(0)) 98 99 /* Zone 1 threshold hit: Increment zone count & clear lower zones */ 100 #define BWMON_ZONE_ACTIONS_ZONE1 (BWMON_ZONE_ACTIONS_INCREMENT(1) | \ 101 BWMON_ZONE_ACTIONS_CLEAR(0)) 102 103 /* Zone 2 threshold hit: Increment zone count & clear lower zones */ 104 #define BWMON_ZONE_ACTIONS_ZONE2 (BWMON_ZONE_ACTIONS_INCREMENT(2) | \ 105 BWMON_ZONE_ACTIONS_CLEAR(1) | \ 106 BWMON_ZONE_ACTIONS_CLEAR(0)) 107 108 /* Zone 3 threshold hit: Increment zone count & clear lower zones */ 109 #define BWMON_ZONE_ACTIONS_ZONE3 (BWMON_ZONE_ACTIONS_INCREMENT(3) | \ 110 BWMON_ZONE_ACTIONS_CLEAR(2) | \ 111 BWMON_ZONE_ACTIONS_CLEAR(1) | \ 112 BWMON_ZONE_ACTIONS_CLEAR(0)) 113 114 /* 115 * There is no clear documentation/explanation of BWMON_V4_THRESHOLD_COUNT 116 * register. Based on observations, this is number of times one threshold has to 117 * be reached, to trigger interrupt in given zone. 118 * 119 * 0xff are maximum values meant to ignore the zones 0 and 2. 120 */ 121 #define BWMON_V4_THRESHOLD_COUNT 0x2bc 122 #define BWMON_V5_THRESHOLD_COUNT 0x034 123 #define BWMON_THRESHOLD_COUNT_ZONE0_DEFAULT 0xff 124 #define BWMON_THRESHOLD_COUNT_ZONE2_DEFAULT 0xff 125 126 #define BWMON_V4_ZONE_MAX(zone) (0x2e0 + 4 * (zone)) 127 #define BWMON_V5_ZONE_MAX(zone) (0x044 + 4 * (zone)) 128 129 /* Quirks for specific BWMON types */ 130 #define BWMON_HAS_GLOBAL_IRQ BIT(0) 131 #define BWMON_NEEDS_FORCE_CLEAR BIT(1) 132 133 enum bwmon_fields { 134 /* Global region fields, keep them at the top */ 135 F_GLOBAL_IRQ_CLEAR, 136 F_GLOBAL_IRQ_ENABLE, 137 F_NUM_GLOBAL_FIELDS, 138 139 /* Monitor region fields */ 140 F_IRQ_STATUS = F_NUM_GLOBAL_FIELDS, 141 F_IRQ_CLEAR, 142 F_IRQ_ENABLE, 143 F_ENABLE, 144 F_CLEAR, 145 F_SAMPLE_WINDOW, 146 F_THRESHOLD_HIGH, 147 F_THRESHOLD_MED, 148 F_THRESHOLD_LOW, 149 F_ZONE_ACTIONS_ZONE0, 150 F_ZONE_ACTIONS_ZONE1, 151 F_ZONE_ACTIONS_ZONE2, 152 F_ZONE_ACTIONS_ZONE3, 153 F_THRESHOLD_COUNT_ZONE0, 154 F_THRESHOLD_COUNT_ZONE1, 155 F_THRESHOLD_COUNT_ZONE2, 156 F_THRESHOLD_COUNT_ZONE3, 157 F_ZONE0_MAX, 158 F_ZONE1_MAX, 159 F_ZONE2_MAX, 160 F_ZONE3_MAX, 161 162 F_NUM_FIELDS 163 }; 164 165 struct icc_bwmon_data { 166 unsigned int sample_ms; 167 unsigned int count_unit_kb; /* kbytes */ 168 unsigned int default_highbw_kbps; 169 unsigned int default_medbw_kbps; 170 unsigned int default_lowbw_kbps; 171 u8 zone1_thres_count; 172 u8 zone3_thres_count; 173 unsigned int quirks; 174 175 const struct regmap_config *regmap_cfg; 176 const struct reg_field *regmap_fields; 177 178 const struct regmap_config *global_regmap_cfg; 179 const struct reg_field *global_regmap_fields; 180 }; 181 182 struct icc_bwmon { 183 struct device *dev; 184 const struct icc_bwmon_data *data; 185 int irq; 186 187 struct regmap_field *regs[F_NUM_FIELDS]; 188 struct regmap_field *global_regs[F_NUM_GLOBAL_FIELDS]; 189 190 unsigned int max_bw_kbps; 191 unsigned int min_bw_kbps; 192 unsigned int target_kbps; 193 unsigned int current_kbps; 194 }; 195 196 /* BWMON v4 */ 197 static const struct reg_field msm8998_bwmon_reg_fields[] = { 198 [F_GLOBAL_IRQ_CLEAR] = {}, 199 [F_GLOBAL_IRQ_ENABLE] = {}, 200 [F_IRQ_STATUS] = REG_FIELD(BWMON_V4_IRQ_STATUS, 4, 7), 201 [F_IRQ_CLEAR] = REG_FIELD(BWMON_V4_IRQ_CLEAR, 4, 7), 202 [F_IRQ_ENABLE] = REG_FIELD(BWMON_V4_IRQ_ENABLE, 4, 7), 203 /* F_ENABLE covers entire register to disable other features */ 204 [F_ENABLE] = REG_FIELD(BWMON_V4_ENABLE, 0, 31), 205 [F_CLEAR] = REG_FIELD(BWMON_V4_CLEAR, 0, 1), 206 [F_SAMPLE_WINDOW] = REG_FIELD(BWMON_V4_SAMPLE_WINDOW, 0, 23), 207 [F_THRESHOLD_HIGH] = REG_FIELD(BWMON_V4_THRESHOLD_HIGH, 0, 11), 208 [F_THRESHOLD_MED] = REG_FIELD(BWMON_V4_THRESHOLD_MED, 0, 11), 209 [F_THRESHOLD_LOW] = REG_FIELD(BWMON_V4_THRESHOLD_LOW, 0, 11), 210 [F_ZONE_ACTIONS_ZONE0] = REG_FIELD(BWMON_V4_ZONE_ACTIONS, 0, 7), 211 [F_ZONE_ACTIONS_ZONE1] = REG_FIELD(BWMON_V4_ZONE_ACTIONS, 8, 15), 212 [F_ZONE_ACTIONS_ZONE2] = REG_FIELD(BWMON_V4_ZONE_ACTIONS, 16, 23), 213 [F_ZONE_ACTIONS_ZONE3] = REG_FIELD(BWMON_V4_ZONE_ACTIONS, 24, 31), 214 [F_THRESHOLD_COUNT_ZONE0] = REG_FIELD(BWMON_V4_THRESHOLD_COUNT, 0, 7), 215 [F_THRESHOLD_COUNT_ZONE1] = REG_FIELD(BWMON_V4_THRESHOLD_COUNT, 8, 15), 216 [F_THRESHOLD_COUNT_ZONE2] = REG_FIELD(BWMON_V4_THRESHOLD_COUNT, 16, 23), 217 [F_THRESHOLD_COUNT_ZONE3] = REG_FIELD(BWMON_V4_THRESHOLD_COUNT, 24, 31), 218 [F_ZONE0_MAX] = REG_FIELD(BWMON_V4_ZONE_MAX(0), 0, 11), 219 [F_ZONE1_MAX] = REG_FIELD(BWMON_V4_ZONE_MAX(1), 0, 11), 220 [F_ZONE2_MAX] = REG_FIELD(BWMON_V4_ZONE_MAX(2), 0, 11), 221 [F_ZONE3_MAX] = REG_FIELD(BWMON_V4_ZONE_MAX(3), 0, 11), 222 }; 223 224 static const struct regmap_range msm8998_bwmon_reg_noread_ranges[] = { 225 regmap_reg_range(BWMON_V4_IRQ_CLEAR, BWMON_V4_IRQ_CLEAR), 226 regmap_reg_range(BWMON_V4_CLEAR, BWMON_V4_CLEAR), 227 }; 228 229 static const struct regmap_access_table msm8998_bwmon_reg_read_table = { 230 .no_ranges = msm8998_bwmon_reg_noread_ranges, 231 .n_no_ranges = ARRAY_SIZE(msm8998_bwmon_reg_noread_ranges), 232 }; 233 234 static const struct regmap_range msm8998_bwmon_reg_volatile_ranges[] = { 235 regmap_reg_range(BWMON_V4_IRQ_STATUS, BWMON_V4_IRQ_STATUS), 236 regmap_reg_range(BWMON_V4_ZONE_MAX(0), BWMON_V4_ZONE_MAX(3)), 237 }; 238 239 static const struct regmap_access_table msm8998_bwmon_reg_volatile_table = { 240 .yes_ranges = msm8998_bwmon_reg_volatile_ranges, 241 .n_yes_ranges = ARRAY_SIZE(msm8998_bwmon_reg_volatile_ranges), 242 }; 243 244 static const struct reg_field msm8998_bwmon_global_reg_fields[] = { 245 [F_GLOBAL_IRQ_CLEAR] = REG_FIELD(BWMON_V4_GLOBAL_IRQ_CLEAR, 0, 0), 246 [F_GLOBAL_IRQ_ENABLE] = REG_FIELD(BWMON_V4_GLOBAL_IRQ_ENABLE, 0, 0), 247 }; 248 249 static const struct regmap_range msm8998_bwmon_global_reg_noread_ranges[] = { 250 regmap_reg_range(BWMON_V4_GLOBAL_IRQ_CLEAR, BWMON_V4_GLOBAL_IRQ_CLEAR), 251 }; 252 253 static const struct regmap_access_table msm8998_bwmon_global_reg_read_table = { 254 .no_ranges = msm8998_bwmon_global_reg_noread_ranges, 255 .n_no_ranges = ARRAY_SIZE(msm8998_bwmon_global_reg_noread_ranges), 256 }; 257 258 /* 259 * Fill the cache for non-readable registers only as rest does not really 260 * matter and can be read from the device. 261 */ 262 static const struct reg_default msm8998_bwmon_reg_defaults[] = { 263 { BWMON_V4_IRQ_CLEAR, 0x0 }, 264 { BWMON_V4_CLEAR, 0x0 }, 265 }; 266 267 static const struct reg_default msm8998_bwmon_global_reg_defaults[] = { 268 { BWMON_V4_GLOBAL_IRQ_CLEAR, 0x0 }, 269 }; 270 271 static const struct regmap_config msm8998_bwmon_regmap_cfg = { 272 .reg_bits = 32, 273 .reg_stride = 4, 274 .val_bits = 32, 275 /* 276 * No concurrent access expected - driver has one interrupt handler, 277 * regmap is not shared, no driver or user-space API. 278 */ 279 .disable_locking = true, 280 .rd_table = &msm8998_bwmon_reg_read_table, 281 .volatile_table = &msm8998_bwmon_reg_volatile_table, 282 .reg_defaults = msm8998_bwmon_reg_defaults, 283 .num_reg_defaults = ARRAY_SIZE(msm8998_bwmon_reg_defaults), 284 /* 285 * Cache is necessary for using regmap fields with non-readable 286 * registers. 287 */ 288 .cache_type = REGCACHE_RBTREE, 289 }; 290 291 static const struct regmap_config msm8998_bwmon_global_regmap_cfg = { 292 .reg_bits = 32, 293 .reg_stride = 4, 294 .val_bits = 32, 295 /* 296 * No concurrent access expected - driver has one interrupt handler, 297 * regmap is not shared, no driver or user-space API. 298 */ 299 .disable_locking = true, 300 .rd_table = &msm8998_bwmon_global_reg_read_table, 301 .reg_defaults = msm8998_bwmon_global_reg_defaults, 302 .num_reg_defaults = ARRAY_SIZE(msm8998_bwmon_global_reg_defaults), 303 /* 304 * Cache is necessary for using regmap fields with non-readable 305 * registers. 306 */ 307 .cache_type = REGCACHE_RBTREE, 308 }; 309 310 static const struct reg_field sdm845_cpu_bwmon_reg_fields[] = { 311 [F_GLOBAL_IRQ_CLEAR] = REG_FIELD(BWMON_V4_GLOBAL_IRQ_CLEAR_845, 0, 0), 312 [F_GLOBAL_IRQ_ENABLE] = REG_FIELD(BWMON_V4_GLOBAL_IRQ_ENABLE_845, 0, 0), 313 [F_IRQ_STATUS] = REG_FIELD(BWMON_V4_IRQ_STATUS, 4, 7), 314 [F_IRQ_CLEAR] = REG_FIELD(BWMON_V4_IRQ_CLEAR, 4, 7), 315 [F_IRQ_ENABLE] = REG_FIELD(BWMON_V4_IRQ_ENABLE, 4, 7), 316 /* F_ENABLE covers entire register to disable other features */ 317 [F_ENABLE] = REG_FIELD(BWMON_V4_ENABLE, 0, 31), 318 [F_CLEAR] = REG_FIELD(BWMON_V4_CLEAR, 0, 1), 319 [F_SAMPLE_WINDOW] = REG_FIELD(BWMON_V4_SAMPLE_WINDOW, 0, 23), 320 [F_THRESHOLD_HIGH] = REG_FIELD(BWMON_V4_THRESHOLD_HIGH, 0, 11), 321 [F_THRESHOLD_MED] = REG_FIELD(BWMON_V4_THRESHOLD_MED, 0, 11), 322 [F_THRESHOLD_LOW] = REG_FIELD(BWMON_V4_THRESHOLD_LOW, 0, 11), 323 [F_ZONE_ACTIONS_ZONE0] = REG_FIELD(BWMON_V4_ZONE_ACTIONS, 0, 7), 324 [F_ZONE_ACTIONS_ZONE1] = REG_FIELD(BWMON_V4_ZONE_ACTIONS, 8, 15), 325 [F_ZONE_ACTIONS_ZONE2] = REG_FIELD(BWMON_V4_ZONE_ACTIONS, 16, 23), 326 [F_ZONE_ACTIONS_ZONE3] = REG_FIELD(BWMON_V4_ZONE_ACTIONS, 24, 31), 327 [F_THRESHOLD_COUNT_ZONE0] = REG_FIELD(BWMON_V4_THRESHOLD_COUNT, 0, 7), 328 [F_THRESHOLD_COUNT_ZONE1] = REG_FIELD(BWMON_V4_THRESHOLD_COUNT, 8, 15), 329 [F_THRESHOLD_COUNT_ZONE2] = REG_FIELD(BWMON_V4_THRESHOLD_COUNT, 16, 23), 330 [F_THRESHOLD_COUNT_ZONE3] = REG_FIELD(BWMON_V4_THRESHOLD_COUNT, 24, 31), 331 [F_ZONE0_MAX] = REG_FIELD(BWMON_V4_ZONE_MAX(0), 0, 11), 332 [F_ZONE1_MAX] = REG_FIELD(BWMON_V4_ZONE_MAX(1), 0, 11), 333 [F_ZONE2_MAX] = REG_FIELD(BWMON_V4_ZONE_MAX(2), 0, 11), 334 [F_ZONE3_MAX] = REG_FIELD(BWMON_V4_ZONE_MAX(3), 0, 11), 335 }; 336 337 static const struct regmap_range sdm845_cpu_bwmon_reg_noread_ranges[] = { 338 regmap_reg_range(BWMON_V4_GLOBAL_IRQ_CLEAR_845, BWMON_V4_GLOBAL_IRQ_CLEAR_845), 339 regmap_reg_range(BWMON_V4_IRQ_CLEAR, BWMON_V4_IRQ_CLEAR), 340 regmap_reg_range(BWMON_V4_CLEAR, BWMON_V4_CLEAR), 341 }; 342 343 static const struct regmap_access_table sdm845_cpu_bwmon_reg_read_table = { 344 .no_ranges = sdm845_cpu_bwmon_reg_noread_ranges, 345 .n_no_ranges = ARRAY_SIZE(sdm845_cpu_bwmon_reg_noread_ranges), 346 }; 347 348 /* 349 * Fill the cache for non-readable registers only as rest does not really 350 * matter and can be read from the device. 351 */ 352 static const struct reg_default sdm845_cpu_bwmon_reg_defaults[] = { 353 { BWMON_V4_GLOBAL_IRQ_CLEAR_845, 0x0 }, 354 { BWMON_V4_IRQ_CLEAR, 0x0 }, 355 { BWMON_V4_CLEAR, 0x0 }, 356 }; 357 358 static const struct regmap_config sdm845_cpu_bwmon_regmap_cfg = { 359 .reg_bits = 32, 360 .reg_stride = 4, 361 .val_bits = 32, 362 /* 363 * No concurrent access expected - driver has one interrupt handler, 364 * regmap is not shared, no driver or user-space API. 365 */ 366 .disable_locking = true, 367 .rd_table = &sdm845_cpu_bwmon_reg_read_table, 368 .volatile_table = &msm8998_bwmon_reg_volatile_table, 369 .reg_defaults = sdm845_cpu_bwmon_reg_defaults, 370 .num_reg_defaults = ARRAY_SIZE(sdm845_cpu_bwmon_reg_defaults), 371 /* 372 * Cache is necessary for using regmap fields with non-readable 373 * registers. 374 */ 375 .cache_type = REGCACHE_RBTREE, 376 }; 377 378 /* BWMON v5 */ 379 static const struct reg_field sdm845_llcc_bwmon_reg_fields[] = { 380 [F_GLOBAL_IRQ_CLEAR] = {}, 381 [F_GLOBAL_IRQ_ENABLE] = {}, 382 [F_IRQ_STATUS] = REG_FIELD(BWMON_V5_IRQ_STATUS, 0, 3), 383 [F_IRQ_CLEAR] = REG_FIELD(BWMON_V5_IRQ_CLEAR, 0, 3), 384 [F_IRQ_ENABLE] = REG_FIELD(BWMON_V5_IRQ_ENABLE, 0, 3), 385 /* F_ENABLE covers entire register to disable other features */ 386 [F_ENABLE] = REG_FIELD(BWMON_V5_ENABLE, 0, 31), 387 [F_CLEAR] = REG_FIELD(BWMON_V5_CLEAR, 0, 1), 388 [F_SAMPLE_WINDOW] = REG_FIELD(BWMON_V5_SAMPLE_WINDOW, 0, 19), 389 [F_THRESHOLD_HIGH] = REG_FIELD(BWMON_V5_THRESHOLD_HIGH, 0, 11), 390 [F_THRESHOLD_MED] = REG_FIELD(BWMON_V5_THRESHOLD_MED, 0, 11), 391 [F_THRESHOLD_LOW] = REG_FIELD(BWMON_V5_THRESHOLD_LOW, 0, 11), 392 [F_ZONE_ACTIONS_ZONE0] = REG_FIELD(BWMON_V5_ZONE_ACTIONS, 0, 7), 393 [F_ZONE_ACTIONS_ZONE1] = REG_FIELD(BWMON_V5_ZONE_ACTIONS, 8, 15), 394 [F_ZONE_ACTIONS_ZONE2] = REG_FIELD(BWMON_V5_ZONE_ACTIONS, 16, 23), 395 [F_ZONE_ACTIONS_ZONE3] = REG_FIELD(BWMON_V5_ZONE_ACTIONS, 24, 31), 396 [F_THRESHOLD_COUNT_ZONE0] = REG_FIELD(BWMON_V5_THRESHOLD_COUNT, 0, 7), 397 [F_THRESHOLD_COUNT_ZONE1] = REG_FIELD(BWMON_V5_THRESHOLD_COUNT, 8, 15), 398 [F_THRESHOLD_COUNT_ZONE2] = REG_FIELD(BWMON_V5_THRESHOLD_COUNT, 16, 23), 399 [F_THRESHOLD_COUNT_ZONE3] = REG_FIELD(BWMON_V5_THRESHOLD_COUNT, 24, 31), 400 [F_ZONE0_MAX] = REG_FIELD(BWMON_V5_ZONE_MAX(0), 0, 11), 401 [F_ZONE1_MAX] = REG_FIELD(BWMON_V5_ZONE_MAX(1), 0, 11), 402 [F_ZONE2_MAX] = REG_FIELD(BWMON_V5_ZONE_MAX(2), 0, 11), 403 [F_ZONE3_MAX] = REG_FIELD(BWMON_V5_ZONE_MAX(3), 0, 11), 404 }; 405 406 static const struct regmap_range sdm845_llcc_bwmon_reg_noread_ranges[] = { 407 regmap_reg_range(BWMON_V5_IRQ_CLEAR, BWMON_V5_IRQ_CLEAR), 408 regmap_reg_range(BWMON_V5_CLEAR, BWMON_V5_CLEAR), 409 }; 410 411 static const struct regmap_access_table sdm845_llcc_bwmon_reg_read_table = { 412 .no_ranges = sdm845_llcc_bwmon_reg_noread_ranges, 413 .n_no_ranges = ARRAY_SIZE(sdm845_llcc_bwmon_reg_noread_ranges), 414 }; 415 416 static const struct regmap_range sdm845_llcc_bwmon_reg_volatile_ranges[] = { 417 regmap_reg_range(BWMON_V5_IRQ_STATUS, BWMON_V5_IRQ_STATUS), 418 regmap_reg_range(BWMON_V5_ZONE_MAX(0), BWMON_V5_ZONE_MAX(3)), 419 }; 420 421 static const struct regmap_access_table sdm845_llcc_bwmon_reg_volatile_table = { 422 .yes_ranges = sdm845_llcc_bwmon_reg_volatile_ranges, 423 .n_yes_ranges = ARRAY_SIZE(sdm845_llcc_bwmon_reg_volatile_ranges), 424 }; 425 426 /* 427 * Fill the cache for non-readable registers only as rest does not really 428 * matter and can be read from the device. 429 */ 430 static const struct reg_default sdm845_llcc_bwmon_reg_defaults[] = { 431 { BWMON_V5_IRQ_CLEAR, 0x0 }, 432 { BWMON_V5_CLEAR, 0x0 }, 433 }; 434 435 static const struct regmap_config sdm845_llcc_bwmon_regmap_cfg = { 436 .reg_bits = 32, 437 .reg_stride = 4, 438 .val_bits = 32, 439 /* 440 * No concurrent access expected - driver has one interrupt handler, 441 * regmap is not shared, no driver or user-space API. 442 */ 443 .disable_locking = true, 444 .rd_table = &sdm845_llcc_bwmon_reg_read_table, 445 .volatile_table = &sdm845_llcc_bwmon_reg_volatile_table, 446 .reg_defaults = sdm845_llcc_bwmon_reg_defaults, 447 .num_reg_defaults = ARRAY_SIZE(sdm845_llcc_bwmon_reg_defaults), 448 /* 449 * Cache is necessary for using regmap fields with non-readable 450 * registers. 451 */ 452 .cache_type = REGCACHE_RBTREE, 453 }; 454 455 static void bwmon_clear_counters(struct icc_bwmon *bwmon, bool clear_all) 456 { 457 unsigned int val = BWMON_CLEAR_CLEAR; 458 459 if (clear_all) 460 val |= BWMON_CLEAR_CLEAR_ALL; 461 /* 462 * Clear counters. The order and barriers are 463 * important. Quoting downstream Qualcomm msm-4.9 tree: 464 * 465 * The counter clear and IRQ clear bits are not in the same 4KB 466 * region. So, we need to make sure the counter clear is completed 467 * before we try to clear the IRQ or do any other counter operations. 468 */ 469 regmap_field_force_write(bwmon->regs[F_CLEAR], val); 470 if (bwmon->data->quirks & BWMON_NEEDS_FORCE_CLEAR) 471 regmap_field_force_write(bwmon->regs[F_CLEAR], 0); 472 } 473 474 static void bwmon_clear_irq(struct icc_bwmon *bwmon) 475 { 476 struct regmap_field *global_irq_clr; 477 478 if (bwmon->data->global_regmap_fields) 479 global_irq_clr = bwmon->global_regs[F_GLOBAL_IRQ_CLEAR]; 480 else 481 global_irq_clr = bwmon->regs[F_GLOBAL_IRQ_CLEAR]; 482 483 /* 484 * Clear zone and global interrupts. The order and barriers are 485 * important. Quoting downstream Qualcomm msm-4.9 tree: 486 * 487 * Synchronize the local interrupt clear in mon_irq_clear() 488 * with the global interrupt clear here. Otherwise, the CPU 489 * may reorder the two writes and clear the global interrupt 490 * before the local interrupt, causing the global interrupt 491 * to be retriggered by the local interrupt still being high. 492 * 493 * Similarly, because the global registers are in a different 494 * region than the local registers, we need to ensure any register 495 * writes to enable the monitor after this call are ordered with the 496 * clearing here so that local writes don't happen before the 497 * interrupt is cleared. 498 */ 499 regmap_field_force_write(bwmon->regs[F_IRQ_CLEAR], BWMON_IRQ_ENABLE_MASK); 500 if (bwmon->data->quirks & BWMON_NEEDS_FORCE_CLEAR) 501 regmap_field_force_write(bwmon->regs[F_IRQ_CLEAR], 0); 502 if (bwmon->data->quirks & BWMON_HAS_GLOBAL_IRQ) 503 regmap_field_force_write(global_irq_clr, 504 BWMON_V4_GLOBAL_IRQ_ENABLE_ENABLE); 505 } 506 507 static void bwmon_disable(struct icc_bwmon *bwmon) 508 { 509 struct regmap_field *global_irq_en; 510 511 if (bwmon->data->global_regmap_fields) 512 global_irq_en = bwmon->global_regs[F_GLOBAL_IRQ_ENABLE]; 513 else 514 global_irq_en = bwmon->regs[F_GLOBAL_IRQ_ENABLE]; 515 516 /* Disable interrupts. Strict ordering, see bwmon_clear_irq(). */ 517 if (bwmon->data->quirks & BWMON_HAS_GLOBAL_IRQ) 518 regmap_field_write(global_irq_en, 0x0); 519 regmap_field_write(bwmon->regs[F_IRQ_ENABLE], 0x0); 520 521 /* 522 * Disable bwmon. Must happen before bwmon_clear_irq() to avoid spurious 523 * IRQ. 524 */ 525 regmap_field_write(bwmon->regs[F_ENABLE], 0x0); 526 } 527 528 static void bwmon_enable(struct icc_bwmon *bwmon, unsigned int irq_enable) 529 { 530 struct regmap_field *global_irq_en; 531 532 if (bwmon->data->global_regmap_fields) 533 global_irq_en = bwmon->global_regs[F_GLOBAL_IRQ_ENABLE]; 534 else 535 global_irq_en = bwmon->regs[F_GLOBAL_IRQ_ENABLE]; 536 537 /* Enable interrupts */ 538 if (bwmon->data->quirks & BWMON_HAS_GLOBAL_IRQ) 539 regmap_field_write(global_irq_en, 540 BWMON_V4_GLOBAL_IRQ_ENABLE_ENABLE); 541 542 regmap_field_write(bwmon->regs[F_IRQ_ENABLE], irq_enable); 543 544 /* Enable bwmon */ 545 regmap_field_write(bwmon->regs[F_ENABLE], BWMON_ENABLE_ENABLE); 546 } 547 548 static unsigned int bwmon_kbps_to_count(struct icc_bwmon *bwmon, 549 unsigned int kbps) 550 { 551 return kbps / bwmon->data->count_unit_kb; 552 } 553 554 static void bwmon_set_threshold(struct icc_bwmon *bwmon, 555 struct regmap_field *reg, unsigned int kbps) 556 { 557 unsigned int thres; 558 559 thres = mult_frac(bwmon_kbps_to_count(bwmon, kbps), 560 bwmon->data->sample_ms, MSEC_PER_SEC); 561 regmap_field_write(reg, thres); 562 } 563 564 static void bwmon_start(struct icc_bwmon *bwmon) 565 { 566 const struct icc_bwmon_data *data = bwmon->data; 567 int window; 568 569 bwmon_clear_counters(bwmon, true); 570 571 window = mult_frac(bwmon->data->sample_ms, HW_TIMER_HZ, MSEC_PER_SEC); 572 /* Maximum sampling window: 0xffffff for v4 and 0xfffff for v5 */ 573 regmap_field_write(bwmon->regs[F_SAMPLE_WINDOW], window); 574 575 bwmon_set_threshold(bwmon, bwmon->regs[F_THRESHOLD_HIGH], 576 data->default_highbw_kbps); 577 bwmon_set_threshold(bwmon, bwmon->regs[F_THRESHOLD_MED], 578 data->default_medbw_kbps); 579 bwmon_set_threshold(bwmon, bwmon->regs[F_THRESHOLD_LOW], 580 data->default_lowbw_kbps); 581 582 regmap_field_write(bwmon->regs[F_THRESHOLD_COUNT_ZONE0], 583 BWMON_THRESHOLD_COUNT_ZONE0_DEFAULT); 584 regmap_field_write(bwmon->regs[F_THRESHOLD_COUNT_ZONE1], 585 data->zone1_thres_count); 586 regmap_field_write(bwmon->regs[F_THRESHOLD_COUNT_ZONE2], 587 BWMON_THRESHOLD_COUNT_ZONE2_DEFAULT); 588 regmap_field_write(bwmon->regs[F_THRESHOLD_COUNT_ZONE3], 589 data->zone3_thres_count); 590 591 regmap_field_write(bwmon->regs[F_ZONE_ACTIONS_ZONE0], 592 BWMON_ZONE_ACTIONS_ZONE0); 593 regmap_field_write(bwmon->regs[F_ZONE_ACTIONS_ZONE1], 594 BWMON_ZONE_ACTIONS_ZONE1); 595 regmap_field_write(bwmon->regs[F_ZONE_ACTIONS_ZONE2], 596 BWMON_ZONE_ACTIONS_ZONE2); 597 regmap_field_write(bwmon->regs[F_ZONE_ACTIONS_ZONE3], 598 BWMON_ZONE_ACTIONS_ZONE3); 599 600 bwmon_clear_irq(bwmon); 601 bwmon_enable(bwmon, BWMON_IRQ_ENABLE_MASK); 602 } 603 604 static irqreturn_t bwmon_intr(int irq, void *dev_id) 605 { 606 struct icc_bwmon *bwmon = dev_id; 607 unsigned int status, max; 608 int zone; 609 610 if (regmap_field_read(bwmon->regs[F_IRQ_STATUS], &status)) 611 return IRQ_NONE; 612 613 status &= BWMON_IRQ_ENABLE_MASK; 614 if (!status) { 615 /* 616 * Only zone 1 and zone 3 interrupts are enabled but zone 2 617 * threshold could be hit and trigger interrupt even if not 618 * enabled. 619 * Such spurious interrupt might come with valuable max count or 620 * not, so solution would be to always check all 621 * BWMON_ZONE_MAX() registers to find the highest value. 622 * Such case is currently ignored. 623 */ 624 return IRQ_NONE; 625 } 626 627 bwmon_disable(bwmon); 628 629 zone = get_bitmask_order(status) - 1; 630 /* 631 * Zone max bytes count register returns count units within sampling 632 * window. Downstream kernel for BWMONv4 (called BWMON type 2 in 633 * downstream) always increments the max bytes count by one. 634 */ 635 if (regmap_field_read(bwmon->regs[F_ZONE0_MAX + zone], &max)) 636 return IRQ_NONE; 637 638 max += 1; 639 max *= bwmon->data->count_unit_kb; 640 bwmon->target_kbps = mult_frac(max, MSEC_PER_SEC, bwmon->data->sample_ms); 641 642 return IRQ_WAKE_THREAD; 643 } 644 645 static irqreturn_t bwmon_intr_thread(int irq, void *dev_id) 646 { 647 struct icc_bwmon *bwmon = dev_id; 648 unsigned int irq_enable = 0; 649 struct dev_pm_opp *opp, *target_opp; 650 unsigned int bw_kbps, up_kbps, down_kbps; 651 652 bw_kbps = bwmon->target_kbps; 653 654 target_opp = dev_pm_opp_find_bw_ceil(bwmon->dev, &bw_kbps, 0); 655 if (IS_ERR(target_opp) && PTR_ERR(target_opp) == -ERANGE) 656 target_opp = dev_pm_opp_find_bw_floor(bwmon->dev, &bw_kbps, 0); 657 658 bwmon->target_kbps = bw_kbps; 659 660 bw_kbps--; 661 opp = dev_pm_opp_find_bw_floor(bwmon->dev, &bw_kbps, 0); 662 if (IS_ERR(opp) && PTR_ERR(opp) == -ERANGE) 663 down_kbps = bwmon->target_kbps; 664 else 665 down_kbps = bw_kbps; 666 667 up_kbps = bwmon->target_kbps + 1; 668 669 if (bwmon->target_kbps >= bwmon->max_bw_kbps) 670 irq_enable = BIT(1); 671 else if (bwmon->target_kbps <= bwmon->min_bw_kbps) 672 irq_enable = BIT(3); 673 else 674 irq_enable = BWMON_IRQ_ENABLE_MASK; 675 676 bwmon_set_threshold(bwmon, bwmon->regs[F_THRESHOLD_HIGH], 677 up_kbps); 678 bwmon_set_threshold(bwmon, bwmon->regs[F_THRESHOLD_MED], 679 down_kbps); 680 bwmon_clear_counters(bwmon, false); 681 bwmon_clear_irq(bwmon); 682 bwmon_enable(bwmon, irq_enable); 683 684 if (bwmon->target_kbps == bwmon->current_kbps) 685 goto out; 686 687 dev_pm_opp_set_opp(bwmon->dev, target_opp); 688 bwmon->current_kbps = bwmon->target_kbps; 689 690 out: 691 dev_pm_opp_put(target_opp); 692 if (!IS_ERR(opp)) 693 dev_pm_opp_put(opp); 694 695 return IRQ_HANDLED; 696 } 697 698 static int bwmon_init_regmap(struct platform_device *pdev, 699 struct icc_bwmon *bwmon) 700 { 701 struct device *dev = &pdev->dev; 702 void __iomem *base; 703 struct regmap *map; 704 int ret; 705 706 /* Map the monitor base */ 707 base = devm_platform_ioremap_resource(pdev, 0); 708 if (IS_ERR(base)) 709 return dev_err_probe(dev, PTR_ERR(base), 710 "failed to map bwmon registers\n"); 711 712 map = devm_regmap_init_mmio(dev, base, bwmon->data->regmap_cfg); 713 if (IS_ERR(map)) 714 return dev_err_probe(dev, PTR_ERR(map), 715 "failed to initialize regmap\n"); 716 717 BUILD_BUG_ON(ARRAY_SIZE(msm8998_bwmon_global_reg_fields) != F_NUM_GLOBAL_FIELDS); 718 BUILD_BUG_ON(ARRAY_SIZE(msm8998_bwmon_reg_fields) != F_NUM_FIELDS); 719 BUILD_BUG_ON(ARRAY_SIZE(sdm845_cpu_bwmon_reg_fields) != F_NUM_FIELDS); 720 BUILD_BUG_ON(ARRAY_SIZE(sdm845_llcc_bwmon_reg_fields) != F_NUM_FIELDS); 721 722 ret = devm_regmap_field_bulk_alloc(dev, map, bwmon->regs, 723 bwmon->data->regmap_fields, 724 F_NUM_FIELDS); 725 if (ret) 726 return ret; 727 728 if (bwmon->data->global_regmap_cfg) { 729 /* Map the global base, if separate */ 730 base = devm_platform_ioremap_resource(pdev, 1); 731 if (IS_ERR(base)) 732 return dev_err_probe(dev, PTR_ERR(base), 733 "failed to map bwmon global registers\n"); 734 735 map = devm_regmap_init_mmio(dev, base, bwmon->data->global_regmap_cfg); 736 if (IS_ERR(map)) 737 return dev_err_probe(dev, PTR_ERR(map), 738 "failed to initialize global regmap\n"); 739 740 ret = devm_regmap_field_bulk_alloc(dev, map, bwmon->global_regs, 741 bwmon->data->global_regmap_fields, 742 F_NUM_GLOBAL_FIELDS); 743 } 744 745 return ret; 746 } 747 748 static int bwmon_probe(struct platform_device *pdev) 749 { 750 struct device *dev = &pdev->dev; 751 struct dev_pm_opp *opp; 752 struct icc_bwmon *bwmon; 753 int ret; 754 755 bwmon = devm_kzalloc(dev, sizeof(*bwmon), GFP_KERNEL); 756 if (!bwmon) 757 return -ENOMEM; 758 759 bwmon->data = of_device_get_match_data(dev); 760 761 ret = bwmon_init_regmap(pdev, bwmon); 762 if (ret) 763 return ret; 764 765 bwmon->irq = platform_get_irq(pdev, 0); 766 if (bwmon->irq < 0) 767 return bwmon->irq; 768 769 ret = devm_pm_opp_of_add_table(dev); 770 if (ret) 771 return dev_err_probe(dev, ret, "failed to add OPP table\n"); 772 773 bwmon->max_bw_kbps = UINT_MAX; 774 opp = dev_pm_opp_find_bw_floor(dev, &bwmon->max_bw_kbps, 0); 775 if (IS_ERR(opp)) 776 return dev_err_probe(dev, PTR_ERR(opp), "failed to find max peak bandwidth\n"); 777 778 bwmon->min_bw_kbps = 0; 779 opp = dev_pm_opp_find_bw_ceil(dev, &bwmon->min_bw_kbps, 0); 780 if (IS_ERR(opp)) 781 return dev_err_probe(dev, PTR_ERR(opp), "failed to find min peak bandwidth\n"); 782 783 bwmon->dev = dev; 784 785 bwmon_disable(bwmon); 786 ret = devm_request_threaded_irq(dev, bwmon->irq, bwmon_intr, 787 bwmon_intr_thread, 788 IRQF_ONESHOT, dev_name(dev), bwmon); 789 if (ret) 790 return dev_err_probe(dev, ret, "failed to request IRQ\n"); 791 792 platform_set_drvdata(pdev, bwmon); 793 bwmon_start(bwmon); 794 795 return 0; 796 } 797 798 static int bwmon_remove(struct platform_device *pdev) 799 { 800 struct icc_bwmon *bwmon = platform_get_drvdata(pdev); 801 802 bwmon_disable(bwmon); 803 804 return 0; 805 } 806 807 static const struct icc_bwmon_data msm8998_bwmon_data = { 808 .sample_ms = 4, 809 .count_unit_kb = 1024, 810 .default_highbw_kbps = 4800 * 1024, /* 4.8 GBps */ 811 .default_medbw_kbps = 512 * 1024, /* 512 MBps */ 812 .default_lowbw_kbps = 0, 813 .zone1_thres_count = 16, 814 .zone3_thres_count = 1, 815 .quirks = BWMON_HAS_GLOBAL_IRQ, 816 .regmap_fields = msm8998_bwmon_reg_fields, 817 .regmap_cfg = &msm8998_bwmon_regmap_cfg, 818 .global_regmap_fields = msm8998_bwmon_global_reg_fields, 819 .global_regmap_cfg = &msm8998_bwmon_global_regmap_cfg, 820 }; 821 822 static const struct icc_bwmon_data sdm845_cpu_bwmon_data = { 823 .sample_ms = 4, 824 .count_unit_kb = 64, 825 .default_highbw_kbps = 4800 * 1024, /* 4.8 GBps */ 826 .default_medbw_kbps = 512 * 1024, /* 512 MBps */ 827 .default_lowbw_kbps = 0, 828 .zone1_thres_count = 16, 829 .zone3_thres_count = 1, 830 .quirks = BWMON_HAS_GLOBAL_IRQ, 831 .regmap_fields = sdm845_cpu_bwmon_reg_fields, 832 .regmap_cfg = &sdm845_cpu_bwmon_regmap_cfg, 833 }; 834 835 static const struct icc_bwmon_data sdm845_llcc_bwmon_data = { 836 .sample_ms = 4, 837 .count_unit_kb = 1024, 838 .default_highbw_kbps = 800 * 1024, /* 800 MBps */ 839 .default_medbw_kbps = 256 * 1024, /* 256 MBps */ 840 .default_lowbw_kbps = 0, 841 .zone1_thres_count = 16, 842 .zone3_thres_count = 1, 843 .regmap_fields = sdm845_llcc_bwmon_reg_fields, 844 .regmap_cfg = &sdm845_llcc_bwmon_regmap_cfg, 845 }; 846 847 static const struct icc_bwmon_data sc7280_llcc_bwmon_data = { 848 .sample_ms = 4, 849 .count_unit_kb = 64, 850 .default_highbw_kbps = 800 * 1024, /* 800 MBps */ 851 .default_medbw_kbps = 256 * 1024, /* 256 MBps */ 852 .default_lowbw_kbps = 0, 853 .zone1_thres_count = 16, 854 .zone3_thres_count = 1, 855 .quirks = BWMON_NEEDS_FORCE_CLEAR, 856 .regmap_fields = sdm845_llcc_bwmon_reg_fields, 857 .regmap_cfg = &sdm845_llcc_bwmon_regmap_cfg, 858 }; 859 860 static const struct of_device_id bwmon_of_match[] = { 861 /* BWMONv4, separate monitor and global register spaces */ 862 { .compatible = "qcom,msm8998-bwmon", .data = &msm8998_bwmon_data }, 863 /* BWMONv4, unified register space */ 864 { .compatible = "qcom,sdm845-bwmon", .data = &sdm845_cpu_bwmon_data }, 865 /* BWMONv5 */ 866 { .compatible = "qcom,sdm845-llcc-bwmon", .data = &sdm845_llcc_bwmon_data }, 867 { .compatible = "qcom,sc7280-llcc-bwmon", .data = &sc7280_llcc_bwmon_data }, 868 869 /* Compatibles kept for legacy reasons */ 870 { .compatible = "qcom,sc7280-cpu-bwmon", .data = &sdm845_cpu_bwmon_data }, 871 { .compatible = "qcom,sc8280xp-cpu-bwmon", .data = &sdm845_cpu_bwmon_data }, 872 { .compatible = "qcom,sm8550-cpu-bwmon", .data = &sdm845_cpu_bwmon_data }, 873 {} 874 }; 875 MODULE_DEVICE_TABLE(of, bwmon_of_match); 876 877 static struct platform_driver bwmon_driver = { 878 .probe = bwmon_probe, 879 .remove = bwmon_remove, 880 .driver = { 881 .name = "qcom-bwmon", 882 .of_match_table = bwmon_of_match, 883 }, 884 }; 885 module_platform_driver(bwmon_driver); 886 887 MODULE_AUTHOR("Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>"); 888 MODULE_DESCRIPTION("QCOM BWMON driver"); 889 MODULE_LICENSE("GPL"); 890