1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 14 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 15 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 16 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 17 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 18 * USE OR OTHER DEALINGS IN THE SOFTWARE. 19 * 20 * The above copyright notice and this permission notice (including the 21 * next paragraph) shall be included in all copies or substantial portions 22 * of the Software. 23 * 24 */ 25 /* 26 * Authors: Dave Airlie <airlied@redhat.com> 27 */ 28 #ifndef __AST_DRV_H__ 29 #define __AST_DRV_H__ 30 31 #include <linux/i2c.h> 32 #include <linux/i2c-algo-bit.h> 33 #include <linux/io.h> 34 #include <linux/types.h> 35 36 #include <drm/drm_connector.h> 37 #include <drm/drm_crtc.h> 38 #include <drm/drm_encoder.h> 39 #include <drm/drm_mode.h> 40 #include <drm/drm_framebuffer.h> 41 42 #define DRIVER_AUTHOR "Dave Airlie" 43 44 #define DRIVER_NAME "ast" 45 #define DRIVER_DESC "AST" 46 #define DRIVER_DATE "20120228" 47 48 #define DRIVER_MAJOR 0 49 #define DRIVER_MINOR 1 50 #define DRIVER_PATCHLEVEL 0 51 52 #define PCI_CHIP_AST2000 0x2000 53 #define PCI_CHIP_AST2100 0x2010 54 55 56 enum ast_chip { 57 AST2000, 58 AST2100, 59 AST1100, 60 AST2200, 61 AST2150, 62 AST2300, 63 AST2400, 64 AST2500, 65 AST2600, 66 }; 67 68 enum ast_tx_chip { 69 AST_TX_NONE, 70 AST_TX_SIL164, 71 AST_TX_DP501, 72 AST_TX_ASTDP, 73 }; 74 75 #define AST_TX_NONE_BIT BIT(AST_TX_NONE) 76 #define AST_TX_SIL164_BIT BIT(AST_TX_SIL164) 77 #define AST_TX_DP501_BIT BIT(AST_TX_DP501) 78 #define AST_TX_ASTDP_BIT BIT(AST_TX_ASTDP) 79 80 #define AST_DRAM_512Mx16 0 81 #define AST_DRAM_1Gx16 1 82 #define AST_DRAM_512Mx32 2 83 #define AST_DRAM_1Gx32 3 84 #define AST_DRAM_2Gx16 6 85 #define AST_DRAM_4Gx16 7 86 #define AST_DRAM_8Gx16 8 87 88 /* 89 * Hardware cursor 90 */ 91 92 #define AST_MAX_HWC_WIDTH 64 93 #define AST_MAX_HWC_HEIGHT 64 94 95 #define AST_HWC_SIZE (AST_MAX_HWC_WIDTH * AST_MAX_HWC_HEIGHT * 2) 96 #define AST_HWC_SIGNATURE_SIZE 32 97 98 /* define for signature structure */ 99 #define AST_HWC_SIGNATURE_CHECKSUM 0x00 100 #define AST_HWC_SIGNATURE_SizeX 0x04 101 #define AST_HWC_SIGNATURE_SizeY 0x08 102 #define AST_HWC_SIGNATURE_X 0x0C 103 #define AST_HWC_SIGNATURE_Y 0x10 104 #define AST_HWC_SIGNATURE_HOTSPOTX 0x14 105 #define AST_HWC_SIGNATURE_HOTSPOTY 0x18 106 107 /* 108 * Planes 109 */ 110 111 struct ast_plane { 112 struct drm_plane base; 113 114 void __iomem *vaddr; 115 u64 offset; 116 unsigned long size; 117 }; 118 119 static inline struct ast_plane *to_ast_plane(struct drm_plane *plane) 120 { 121 return container_of(plane, struct ast_plane, base); 122 } 123 124 /* 125 * Connector with i2c channel 126 */ 127 128 struct ast_i2c_chan { 129 struct i2c_adapter adapter; 130 struct drm_device *dev; 131 struct i2c_algo_bit_data bit; 132 }; 133 134 struct ast_vga_connector { 135 struct drm_connector base; 136 struct ast_i2c_chan *i2c; 137 }; 138 139 static inline struct ast_vga_connector * 140 to_ast_vga_connector(struct drm_connector *connector) 141 { 142 return container_of(connector, struct ast_vga_connector, base); 143 } 144 145 struct ast_sil164_connector { 146 struct drm_connector base; 147 struct ast_i2c_chan *i2c; 148 }; 149 150 static inline struct ast_sil164_connector * 151 to_ast_sil164_connector(struct drm_connector *connector) 152 { 153 return container_of(connector, struct ast_sil164_connector, base); 154 } 155 156 /* 157 * Device 158 */ 159 160 struct ast_device { 161 struct drm_device base; 162 163 struct mutex ioregs_lock; /* Protects access to I/O registers in ioregs */ 164 void __iomem *regs; 165 void __iomem *ioregs; 166 void __iomem *dp501_fw_buf; 167 168 enum ast_chip chip; 169 bool vga2_clone; 170 uint32_t dram_bus_width; 171 uint32_t dram_type; 172 uint32_t mclk; 173 174 void __iomem *vram; 175 unsigned long vram_base; 176 unsigned long vram_size; 177 unsigned long vram_fb_available; 178 179 struct ast_plane primary_plane; 180 struct ast_plane cursor_plane; 181 struct drm_crtc crtc; 182 struct { 183 struct { 184 struct drm_encoder encoder; 185 struct ast_vga_connector vga_connector; 186 } vga; 187 struct { 188 struct drm_encoder encoder; 189 struct ast_sil164_connector sil164_connector; 190 } sil164; 191 struct { 192 struct drm_encoder encoder; 193 struct drm_connector connector; 194 } dp501; 195 struct { 196 struct drm_encoder encoder; 197 struct drm_connector connector; 198 } astdp; 199 } output; 200 201 bool support_wide_screen; 202 enum { 203 ast_use_p2a, 204 ast_use_dt, 205 ast_use_defaults 206 } config_mode; 207 208 unsigned long tx_chip_types; /* bitfield of enum ast_chip_type */ 209 u8 *dp501_fw_addr; 210 const struct firmware *dp501_fw; /* dp501 fw */ 211 }; 212 213 static inline struct ast_device *to_ast_device(struct drm_device *dev) 214 { 215 return container_of(dev, struct ast_device, base); 216 } 217 218 struct ast_device *ast_device_create(const struct drm_driver *drv, 219 struct pci_dev *pdev, 220 unsigned long flags); 221 222 #define AST_IO_AR_PORT_WRITE (0x40) 223 #define AST_IO_MISC_PORT_WRITE (0x42) 224 #define AST_IO_VGA_ENABLE_PORT (0x43) 225 #define AST_IO_SEQ_PORT (0x44) 226 #define AST_IO_DAC_INDEX_READ (0x47) 227 #define AST_IO_DAC_INDEX_WRITE (0x48) 228 #define AST_IO_DAC_DATA (0x49) 229 #define AST_IO_GR_PORT (0x4E) 230 #define AST_IO_CRTC_PORT (0x54) 231 #define AST_IO_INPUT_STATUS1_READ (0x5A) 232 #define AST_IO_MISC_PORT_READ (0x4C) 233 234 #define AST_IO_MM_OFFSET (0x380) 235 236 #define AST_IO_VGAIR1_VREFRESH BIT(3) 237 238 #define AST_IO_VGACRCB_HWC_ENABLED BIT(1) 239 #define AST_IO_VGACRCB_HWC_16BPP BIT(0) /* set: ARGB4444, cleared: 2bpp palette */ 240 241 static inline u32 ast_read32(struct ast_device *ast, u32 reg) 242 { 243 return ioread32(ast->regs + reg); 244 } 245 246 static inline void ast_write32(struct ast_device *ast, u32 reg, u32 val) 247 { 248 iowrite32(val, ast->regs + reg); 249 } 250 251 static inline u8 ast_io_read8(struct ast_device *ast, u32 reg) 252 { 253 return ioread8(ast->ioregs + reg); 254 } 255 256 static inline void ast_io_write8(struct ast_device *ast, u32 reg, u8 val) 257 { 258 iowrite8(val, ast->ioregs + reg); 259 } 260 261 static inline void ast_set_index_reg(struct ast_device *ast, 262 uint32_t base, uint8_t index, 263 uint8_t val) 264 { 265 ast_io_write8(ast, base, index); 266 ++base; 267 ast_io_write8(ast, base, val); 268 } 269 270 void ast_set_index_reg_mask(struct ast_device *ast, 271 uint32_t base, uint8_t index, 272 uint8_t mask, uint8_t val); 273 uint8_t ast_get_index_reg(struct ast_device *ast, 274 uint32_t base, uint8_t index); 275 uint8_t ast_get_index_reg_mask(struct ast_device *ast, 276 uint32_t base, uint8_t index, uint8_t mask); 277 278 static inline void ast_open_key(struct ast_device *ast) 279 { 280 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x80, 0xA8); 281 } 282 283 #define AST_VIDMEM_SIZE_8M 0x00800000 284 #define AST_VIDMEM_SIZE_16M 0x01000000 285 #define AST_VIDMEM_SIZE_32M 0x02000000 286 #define AST_VIDMEM_SIZE_64M 0x04000000 287 #define AST_VIDMEM_SIZE_128M 0x08000000 288 289 #define AST_VIDMEM_DEFAULT_SIZE AST_VIDMEM_SIZE_8M 290 291 struct ast_vbios_stdtable { 292 u8 misc; 293 u8 seq[4]; 294 u8 crtc[25]; 295 u8 ar[20]; 296 u8 gr[9]; 297 }; 298 299 struct ast_vbios_enhtable { 300 u32 ht; 301 u32 hde; 302 u32 hfp; 303 u32 hsync; 304 u32 vt; 305 u32 vde; 306 u32 vfp; 307 u32 vsync; 308 u32 dclk_index; 309 u32 flags; 310 u32 refresh_rate; 311 u32 refresh_rate_index; 312 u32 mode_id; 313 }; 314 315 struct ast_vbios_dclk_info { 316 u8 param1; 317 u8 param2; 318 u8 param3; 319 }; 320 321 struct ast_vbios_mode_info { 322 const struct ast_vbios_stdtable *std_table; 323 const struct ast_vbios_enhtable *enh_table; 324 }; 325 326 struct ast_crtc_state { 327 struct drm_crtc_state base; 328 329 /* Last known format of primary plane */ 330 const struct drm_format_info *format; 331 332 struct ast_vbios_mode_info vbios_mode_info; 333 }; 334 335 #define to_ast_crtc_state(state) container_of(state, struct ast_crtc_state, base) 336 337 int ast_mode_config_init(struct ast_device *ast); 338 339 #define AST_MM_ALIGN_SHIFT 4 340 #define AST_MM_ALIGN_MASK ((1 << AST_MM_ALIGN_SHIFT) - 1) 341 342 #define AST_DP501_FW_VERSION_MASK GENMASK(7, 4) 343 #define AST_DP501_FW_VERSION_1 BIT(4) 344 #define AST_DP501_PNP_CONNECTED BIT(1) 345 346 #define AST_DP501_DEFAULT_DCLK 65 347 348 #define AST_DP501_GBL_VERSION 0xf000 349 #define AST_DP501_PNPMONITOR 0xf010 350 #define AST_DP501_LINKRATE 0xf014 351 #define AST_DP501_EDID_DATA 0xf020 352 353 /* 354 * Display Transmitter Type: 355 */ 356 #define TX_TYPE_MASK GENMASK(3, 1) 357 #define NO_TX (0 << 1) 358 #define ITE66121_VBIOS_TX (1 << 1) 359 #define SI164_VBIOS_TX (2 << 1) 360 #define CH7003_VBIOS_TX (3 << 1) 361 #define DP501_VBIOS_TX (4 << 1) 362 #define ANX9807_VBIOS_TX (5 << 1) 363 #define TX_FW_EMBEDDED_FW_TX (6 << 1) 364 #define ASTDP_DPMCU_TX (7 << 1) 365 366 #define AST_VRAM_INIT_STATUS_MASK GENMASK(7, 6) 367 //#define AST_VRAM_INIT_BY_BMC BIT(7) 368 //#define AST_VRAM_INIT_READY BIT(6) 369 370 /* Define for Soc scratched reg used on ASTDP */ 371 #define AST_DP_PHY_SLEEP BIT(4) 372 #define AST_DP_VIDEO_ENABLE BIT(0) 373 374 #define AST_DP_POWER_ON true 375 #define AST_DP_POWER_OFF false 376 377 /* 378 * CRD1[b5]: DP MCU FW is executing 379 * CRDC[b0]: DP link success 380 * CRDF[b0]: DP HPD 381 * CRE5[b0]: Host reading EDID process is done 382 */ 383 #define ASTDP_MCU_FW_EXECUTING BIT(5) 384 #define ASTDP_LINK_SUCCESS BIT(0) 385 #define ASTDP_HPD BIT(0) 386 #define ASTDP_HOST_EDID_READ_DONE BIT(0) 387 #define ASTDP_HOST_EDID_READ_DONE_MASK GENMASK(0, 0) 388 389 /* 390 * CRB8[b1]: Enable VSYNC off 391 * CRB8[b0]: Enable HSYNC off 392 */ 393 #define AST_DPMS_VSYNC_OFF BIT(1) 394 #define AST_DPMS_HSYNC_OFF BIT(0) 395 396 /* 397 * CRDF[b4]: Mirror of AST_DP_VIDEO_ENABLE 398 * Precondition: A. ~AST_DP_PHY_SLEEP && 399 * B. DP_HPD && 400 * C. DP_LINK_SUCCESS 401 */ 402 #define ASTDP_MIRROR_VIDEO_ENABLE BIT(4) 403 404 #define ASTDP_EDID_READ_POINTER_MASK GENMASK(7, 0) 405 #define ASTDP_EDID_VALID_FLAG_MASK GENMASK(0, 0) 406 #define ASTDP_EDID_READ_DATA_MASK GENMASK(7, 0) 407 408 /* 409 * ASTDP setmode registers: 410 * CRE0[7:0]: MISC0 ((0x00: 18-bpp) or (0x20: 24-bpp) 411 * CRE1[7:0]: MISC1 (default: 0x00) 412 * CRE2[7:0]: video format index (0x00 ~ 0x20 or 0x40 ~ 0x50) 413 */ 414 #define ASTDP_MISC0_24bpp BIT(5) 415 #define ASTDP_MISC1 0 416 #define ASTDP_AND_CLEAR_MASK 0x00 417 418 /* 419 * ASTDP resoultion table: 420 * EX: ASTDP_A_B_C: 421 * A: Resolution 422 * B: Refresh Rate 423 * C: Misc information, such as CVT, Reduce Blanked 424 */ 425 #define ASTDP_640x480_60 0x00 426 #define ASTDP_640x480_72 0x01 427 #define ASTDP_640x480_75 0x02 428 #define ASTDP_640x480_85 0x03 429 #define ASTDP_800x600_56 0x04 430 #define ASTDP_800x600_60 0x05 431 #define ASTDP_800x600_72 0x06 432 #define ASTDP_800x600_75 0x07 433 #define ASTDP_800x600_85 0x08 434 #define ASTDP_1024x768_60 0x09 435 #define ASTDP_1024x768_70 0x0A 436 #define ASTDP_1024x768_75 0x0B 437 #define ASTDP_1024x768_85 0x0C 438 #define ASTDP_1280x1024_60 0x0D 439 #define ASTDP_1280x1024_75 0x0E 440 #define ASTDP_1280x1024_85 0x0F 441 #define ASTDP_1600x1200_60 0x10 442 #define ASTDP_320x240_60 0x11 443 #define ASTDP_400x300_60 0x12 444 #define ASTDP_512x384_60 0x13 445 #define ASTDP_1920x1200_60 0x14 446 #define ASTDP_1920x1080_60 0x15 447 #define ASTDP_1280x800_60 0x16 448 #define ASTDP_1280x800_60_RB 0x17 449 #define ASTDP_1440x900_60 0x18 450 #define ASTDP_1440x900_60_RB 0x19 451 #define ASTDP_1680x1050_60 0x1A 452 #define ASTDP_1680x1050_60_RB 0x1B 453 #define ASTDP_1600x900_60 0x1C 454 #define ASTDP_1600x900_60_RB 0x1D 455 #define ASTDP_1366x768_60 0x1E 456 #define ASTDP_1152x864_75 0x1F 457 458 int ast_mm_init(struct ast_device *ast); 459 460 /* ast post */ 461 void ast_enable_vga(struct drm_device *dev); 462 void ast_enable_mmio(struct drm_device *dev); 463 bool ast_is_vga_enabled(struct drm_device *dev); 464 void ast_post_gpu(struct drm_device *dev); 465 u32 ast_mindwm(struct ast_device *ast, u32 r); 466 void ast_moutdwm(struct ast_device *ast, u32 r, u32 v); 467 void ast_patch_ahb_2500(struct ast_device *ast); 468 /* ast dp501 */ 469 void ast_set_dp501_video_output(struct drm_device *dev, u8 mode); 470 bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 size); 471 bool ast_dp501_read_edid(struct drm_device *dev, u8 *ediddata); 472 u8 ast_get_dp501_max_clk(struct drm_device *dev); 473 void ast_init_3rdtx(struct drm_device *dev); 474 475 /* ast_i2c.c */ 476 struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev); 477 478 /* aspeed DP */ 479 int ast_astdp_read_edid(struct drm_device *dev, u8 *ediddata); 480 void ast_dp_launch(struct drm_device *dev); 481 void ast_dp_power_on_off(struct drm_device *dev, bool no); 482 void ast_dp_set_on_off(struct drm_device *dev, bool no); 483 void ast_dp_set_mode(struct drm_crtc *crtc, struct ast_vbios_mode_info *vbios_mode); 484 485 #endif 486