1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * drivers/i2c/busses/i2c-tegra.c 4 * 5 * Copyright (C) 2010 Google, Inc. 6 * Author: Colin Cross <ccross@android.com> 7 */ 8 9 #include <linux/acpi.h> 10 #include <linux/bitfield.h> 11 #include <linux/clk.h> 12 #include <linux/delay.h> 13 #include <linux/dmaengine.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/err.h> 16 #include <linux/i2c.h> 17 #include <linux/init.h> 18 #include <linux/interrupt.h> 19 #include <linux/io.h> 20 #include <linux/iopoll.h> 21 #include <linux/irq.h> 22 #include <linux/kernel.h> 23 #include <linux/ktime.h> 24 #include <linux/module.h> 25 #include <linux/of_device.h> 26 #include <linux/pinctrl/consumer.h> 27 #include <linux/platform_device.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/reset.h> 30 31 #define BYTES_PER_FIFO_WORD 4 32 33 #define I2C_CNFG 0x000 34 #define I2C_CNFG_DEBOUNCE_CNT GENMASK(14, 12) 35 #define I2C_CNFG_PACKET_MODE_EN BIT(10) 36 #define I2C_CNFG_NEW_MASTER_FSM BIT(11) 37 #define I2C_CNFG_MULTI_MASTER_MODE BIT(17) 38 #define I2C_STATUS 0x01c 39 #define I2C_SL_CNFG 0x020 40 #define I2C_SL_CNFG_NACK BIT(1) 41 #define I2C_SL_CNFG_NEWSL BIT(2) 42 #define I2C_SL_ADDR1 0x02c 43 #define I2C_SL_ADDR2 0x030 44 #define I2C_TLOW_SEXT 0x034 45 #define I2C_TX_FIFO 0x050 46 #define I2C_RX_FIFO 0x054 47 #define I2C_PACKET_TRANSFER_STATUS 0x058 48 #define I2C_FIFO_CONTROL 0x05c 49 #define I2C_FIFO_CONTROL_TX_FLUSH BIT(1) 50 #define I2C_FIFO_CONTROL_RX_FLUSH BIT(0) 51 #define I2C_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 5) 52 #define I2C_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 2) 53 #define I2C_FIFO_STATUS 0x060 54 #define I2C_FIFO_STATUS_TX GENMASK(7, 4) 55 #define I2C_FIFO_STATUS_RX GENMASK(3, 0) 56 #define I2C_INT_MASK 0x064 57 #define I2C_INT_STATUS 0x068 58 #define I2C_INT_BUS_CLR_DONE BIT(11) 59 #define I2C_INT_PACKET_XFER_COMPLETE BIT(7) 60 #define I2C_INT_NO_ACK BIT(3) 61 #define I2C_INT_ARBITRATION_LOST BIT(2) 62 #define I2C_INT_TX_FIFO_DATA_REQ BIT(1) 63 #define I2C_INT_RX_FIFO_DATA_REQ BIT(0) 64 #define I2C_CLK_DIVISOR 0x06c 65 #define I2C_CLK_DIVISOR_STD_FAST_MODE GENMASK(31, 16) 66 #define I2C_CLK_DIVISOR_HSMODE GENMASK(15, 0) 67 68 #define DVC_CTRL_REG1 0x000 69 #define DVC_CTRL_REG1_INTR_EN BIT(10) 70 #define DVC_CTRL_REG3 0x008 71 #define DVC_CTRL_REG3_SW_PROG BIT(26) 72 #define DVC_CTRL_REG3_I2C_DONE_INTR_EN BIT(30) 73 #define DVC_STATUS 0x00c 74 #define DVC_STATUS_I2C_DONE_INTR BIT(30) 75 76 #define I2C_ERR_NONE 0x00 77 #define I2C_ERR_NO_ACK BIT(0) 78 #define I2C_ERR_ARBITRATION_LOST BIT(1) 79 #define I2C_ERR_UNKNOWN_INTERRUPT BIT(2) 80 #define I2C_ERR_RX_BUFFER_OVERFLOW BIT(3) 81 82 #define PACKET_HEADER0_HEADER_SIZE GENMASK(29, 28) 83 #define PACKET_HEADER0_PACKET_ID GENMASK(23, 16) 84 #define PACKET_HEADER0_CONT_ID GENMASK(15, 12) 85 #define PACKET_HEADER0_PROTOCOL GENMASK(7, 4) 86 #define PACKET_HEADER0_PROTOCOL_I2C 1 87 88 #define I2C_HEADER_CONT_ON_NAK BIT(21) 89 #define I2C_HEADER_READ BIT(19) 90 #define I2C_HEADER_10BIT_ADDR BIT(18) 91 #define I2C_HEADER_IE_ENABLE BIT(17) 92 #define I2C_HEADER_REPEAT_START BIT(16) 93 #define I2C_HEADER_CONTINUE_XFER BIT(15) 94 #define I2C_HEADER_SLAVE_ADDR_SHIFT 1 95 96 #define I2C_BUS_CLEAR_CNFG 0x084 97 #define I2C_BC_SCLK_THRESHOLD GENMASK(23, 16) 98 #define I2C_BC_STOP_COND BIT(2) 99 #define I2C_BC_TERMINATE BIT(1) 100 #define I2C_BC_ENABLE BIT(0) 101 #define I2C_BUS_CLEAR_STATUS 0x088 102 #define I2C_BC_STATUS BIT(0) 103 104 #define I2C_CONFIG_LOAD 0x08c 105 #define I2C_MSTR_CONFIG_LOAD BIT(0) 106 107 #define I2C_CLKEN_OVERRIDE 0x090 108 #define I2C_MST_CORE_CLKEN_OVR BIT(0) 109 110 #define I2C_INTERFACE_TIMING_0 0x094 111 #define I2C_INTERFACE_TIMING_THIGH GENMASK(13, 8) 112 #define I2C_INTERFACE_TIMING_TLOW GENMASK(5, 0) 113 #define I2C_INTERFACE_TIMING_1 0x098 114 #define I2C_INTERFACE_TIMING_TBUF GENMASK(29, 24) 115 #define I2C_INTERFACE_TIMING_TSU_STO GENMASK(21, 16) 116 #define I2C_INTERFACE_TIMING_THD_STA GENMASK(13, 8) 117 #define I2C_INTERFACE_TIMING_TSU_STA GENMASK(5, 0) 118 119 #define I2C_HS_INTERFACE_TIMING_0 0x09c 120 #define I2C_HS_INTERFACE_TIMING_THIGH GENMASK(13, 8) 121 #define I2C_HS_INTERFACE_TIMING_TLOW GENMASK(5, 0) 122 #define I2C_HS_INTERFACE_TIMING_1 0x0a0 123 #define I2C_HS_INTERFACE_TIMING_TSU_STO GENMASK(21, 16) 124 #define I2C_HS_INTERFACE_TIMING_THD_STA GENMASK(13, 8) 125 #define I2C_HS_INTERFACE_TIMING_TSU_STA GENMASK(5, 0) 126 127 #define I2C_MST_FIFO_CONTROL 0x0b4 128 #define I2C_MST_FIFO_CONTROL_RX_FLUSH BIT(0) 129 #define I2C_MST_FIFO_CONTROL_TX_FLUSH BIT(1) 130 #define I2C_MST_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 4) 131 #define I2C_MST_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 16) 132 133 #define I2C_MST_FIFO_STATUS 0x0b8 134 #define I2C_MST_FIFO_STATUS_TX GENMASK(23, 16) 135 #define I2C_MST_FIFO_STATUS_RX GENMASK(7, 0) 136 137 /* configuration load timeout in microseconds */ 138 #define I2C_CONFIG_LOAD_TIMEOUT 1000000 139 140 /* packet header size in bytes */ 141 #define I2C_PACKET_HEADER_SIZE 12 142 143 /* 144 * I2C Controller will use PIO mode for transfers up to 32 bytes in order to 145 * avoid DMA overhead, otherwise external APB DMA controller will be used. 146 * Note that the actual MAX PIO length is 20 bytes because 32 bytes include 147 * I2C_PACKET_HEADER_SIZE. 148 */ 149 #define I2C_PIO_MODE_PREFERRED_LEN 32 150 151 /* 152 * msg_end_type: The bus control which needs to be sent at end of transfer. 153 * @MSG_END_STOP: Send stop pulse. 154 * @MSG_END_REPEAT_START: Send repeat-start. 155 * @MSG_END_CONTINUE: Don't send stop or repeat-start. 156 */ 157 enum msg_end_type { 158 MSG_END_STOP, 159 MSG_END_REPEAT_START, 160 MSG_END_CONTINUE, 161 }; 162 163 /** 164 * struct tegra_i2c_hw_feature : per hardware generation features 165 * @has_continue_xfer_support: continue-transfer supported 166 * @has_per_pkt_xfer_complete_irq: Has enable/disable capability for transfer 167 * completion interrupt on per packet basis. 168 * @has_config_load_reg: Has the config load register to load the new 169 * configuration. 170 * @clk_divisor_hs_mode: Clock divisor in HS mode. 171 * @clk_divisor_std_mode: Clock divisor in standard mode. It is 172 * applicable if there is no fast clock source i.e. single clock 173 * source. 174 * @clk_divisor_fast_mode: Clock divisor in fast mode. It is 175 * applicable if there is no fast clock source i.e. single clock 176 * source. 177 * @clk_divisor_fast_plus_mode: Clock divisor in fast mode plus. It is 178 * applicable if there is no fast clock source (i.e. single 179 * clock source). 180 * @has_multi_master_mode: The I2C controller supports running in single-master 181 * or multi-master mode. 182 * @has_slcg_override_reg: The I2C controller supports a register that 183 * overrides the second level clock gating. 184 * @has_mst_fifo: The I2C controller contains the new MST FIFO interface that 185 * provides additional features and allows for longer messages to 186 * be transferred in one go. 187 * @quirks: I2C adapter quirks for limiting write/read transfer size and not 188 * allowing 0 length transfers. 189 * @supports_bus_clear: Bus Clear support to recover from bus hang during 190 * SDA stuck low from device for some unknown reasons. 191 * @has_apb_dma: Support of APBDMA on corresponding Tegra chip. 192 * @tlow_std_mode: Low period of the clock in standard mode. 193 * @thigh_std_mode: High period of the clock in standard mode. 194 * @tlow_fast_fastplus_mode: Low period of the clock in fast/fast-plus modes. 195 * @thigh_fast_fastplus_mode: High period of the clock in fast/fast-plus modes. 196 * @setup_hold_time_std_mode: Setup and hold time for start and stop conditions 197 * in standard mode. 198 * @setup_hold_time_fast_fast_plus_mode: Setup and hold time for start and stop 199 * conditions in fast/fast-plus modes. 200 * @setup_hold_time_hs_mode: Setup and hold time for start and stop conditions 201 * in HS mode. 202 * @has_interface_timing_reg: Has interface timing register to program the tuned 203 * timing settings. 204 */ 205 struct tegra_i2c_hw_feature { 206 bool has_continue_xfer_support; 207 bool has_per_pkt_xfer_complete_irq; 208 bool has_config_load_reg; 209 u32 clk_divisor_hs_mode; 210 u32 clk_divisor_std_mode; 211 u32 clk_divisor_fast_mode; 212 u32 clk_divisor_fast_plus_mode; 213 bool has_multi_master_mode; 214 bool has_slcg_override_reg; 215 bool has_mst_fifo; 216 const struct i2c_adapter_quirks *quirks; 217 bool supports_bus_clear; 218 bool has_apb_dma; 219 u32 tlow_std_mode; 220 u32 thigh_std_mode; 221 u32 tlow_fast_fastplus_mode; 222 u32 thigh_fast_fastplus_mode; 223 u32 setup_hold_time_std_mode; 224 u32 setup_hold_time_fast_fast_plus_mode; 225 u32 setup_hold_time_hs_mode; 226 bool has_interface_timing_reg; 227 }; 228 229 /** 230 * struct tegra_i2c_dev - per device I2C context 231 * @dev: device reference for power management 232 * @hw: Tegra I2C HW feature 233 * @adapter: core I2C layer adapter information 234 * @div_clk: clock reference for div clock of I2C controller 235 * @clocks: array of I2C controller clocks 236 * @nclocks: number of clocks in the array 237 * @rst: reset control for the I2C controller 238 * @base: ioremapped registers cookie 239 * @base_phys: physical base address of the I2C controller 240 * @cont_id: I2C controller ID, used for packet header 241 * @irq: IRQ number of transfer complete interrupt 242 * @is_dvc: identifies the DVC I2C controller, has a different register layout 243 * @is_vi: identifies the VI I2C controller, has a different register layout 244 * @msg_complete: transfer completion notifier 245 * @msg_buf_remaining: size of unsent data in the message buffer 246 * @msg_len: length of message in current transfer 247 * @msg_err: error code for completed message 248 * @msg_buf: pointer to current message data 249 * @msg_read: indicates that the transfer is a read access 250 * @timings: i2c timings information like bus frequency 251 * @multimaster_mode: indicates that I2C controller is in multi-master mode 252 * @dma_chan: DMA channel 253 * @dma_phys: handle to DMA resources 254 * @dma_buf: pointer to allocated DMA buffer 255 * @dma_buf_size: DMA buffer size 256 * @dma_mode: indicates active DMA transfer 257 * @dma_complete: DMA completion notifier 258 * @atomic_mode: indicates active atomic transfer 259 */ 260 struct tegra_i2c_dev { 261 struct device *dev; 262 struct i2c_adapter adapter; 263 264 const struct tegra_i2c_hw_feature *hw; 265 struct reset_control *rst; 266 unsigned int cont_id; 267 unsigned int irq; 268 269 phys_addr_t base_phys; 270 void __iomem *base; 271 272 struct clk_bulk_data clocks[2]; 273 unsigned int nclocks; 274 275 struct clk *div_clk; 276 struct i2c_timings timings; 277 278 struct completion msg_complete; 279 size_t msg_buf_remaining; 280 unsigned int msg_len; 281 int msg_err; 282 u8 *msg_buf; 283 284 struct completion dma_complete; 285 struct dma_chan *dma_chan; 286 unsigned int dma_buf_size; 287 struct device *dma_dev; 288 dma_addr_t dma_phys; 289 void *dma_buf; 290 291 bool multimaster_mode; 292 bool atomic_mode; 293 bool dma_mode; 294 bool msg_read; 295 bool is_dvc; 296 bool is_vi; 297 }; 298 299 #define IS_DVC(dev) (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && (dev)->is_dvc) 300 #define IS_VI(dev) (IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) && (dev)->is_vi) 301 302 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, 303 unsigned int reg) 304 { 305 writel_relaxed(val, i2c_dev->base + reg); 306 } 307 308 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned int reg) 309 { 310 return readl_relaxed(i2c_dev->base + reg); 311 } 312 313 /* 314 * If necessary, i2c_writel() and i2c_readl() will offset the register 315 * in order to talk to the I2C block inside the DVC block. 316 */ 317 static u32 tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev, unsigned int reg) 318 { 319 if (IS_DVC(i2c_dev)) 320 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40; 321 else if (IS_VI(i2c_dev)) 322 reg = 0xc00 + (reg << 2); 323 324 return reg; 325 } 326 327 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned int reg) 328 { 329 writel_relaxed(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); 330 331 /* read back register to make sure that register writes completed */ 332 if (reg != I2C_TX_FIFO) 333 readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); 334 else if (IS_VI(i2c_dev)) 335 readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, I2C_INT_STATUS)); 336 } 337 338 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned int reg) 339 { 340 return readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); 341 } 342 343 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data, 344 unsigned int reg, unsigned int len) 345 { 346 writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); 347 } 348 349 static void i2c_writesl_vi(struct tegra_i2c_dev *i2c_dev, void *data, 350 unsigned int reg, unsigned int len) 351 { 352 u32 *data32 = data; 353 354 /* 355 * VI I2C controller has known hardware bug where writes get stuck 356 * when immediate multiple writes happen to TX_FIFO register. 357 * Recommended software work around is to read I2C register after 358 * each write to TX_FIFO register to flush out the data. 359 */ 360 while (len--) 361 i2c_writel(i2c_dev, *data32++, reg); 362 } 363 364 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data, 365 unsigned int reg, unsigned int len) 366 { 367 readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); 368 } 369 370 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask) 371 { 372 u32 int_mask; 373 374 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) & ~mask; 375 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK); 376 } 377 378 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask) 379 { 380 u32 int_mask; 381 382 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) | mask; 383 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK); 384 } 385 386 static void tegra_i2c_dma_complete(void *args) 387 { 388 struct tegra_i2c_dev *i2c_dev = args; 389 390 complete(&i2c_dev->dma_complete); 391 } 392 393 static int tegra_i2c_dma_submit(struct tegra_i2c_dev *i2c_dev, size_t len) 394 { 395 struct dma_async_tx_descriptor *dma_desc; 396 enum dma_transfer_direction dir; 397 398 dev_dbg(i2c_dev->dev, "starting DMA for length: %zu\n", len); 399 400 reinit_completion(&i2c_dev->dma_complete); 401 402 dir = i2c_dev->msg_read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV; 403 404 dma_desc = dmaengine_prep_slave_single(i2c_dev->dma_chan, i2c_dev->dma_phys, 405 len, dir, DMA_PREP_INTERRUPT | 406 DMA_CTRL_ACK); 407 if (!dma_desc) { 408 dev_err(i2c_dev->dev, "failed to get %s DMA descriptor\n", 409 i2c_dev->msg_read ? "RX" : "TX"); 410 return -EINVAL; 411 } 412 413 dma_desc->callback = tegra_i2c_dma_complete; 414 dma_desc->callback_param = i2c_dev; 415 416 dmaengine_submit(dma_desc); 417 dma_async_issue_pending(i2c_dev->dma_chan); 418 419 return 0; 420 } 421 422 static void tegra_i2c_release_dma(struct tegra_i2c_dev *i2c_dev) 423 { 424 if (i2c_dev->dma_buf) { 425 dma_free_coherent(i2c_dev->dma_dev, i2c_dev->dma_buf_size, 426 i2c_dev->dma_buf, i2c_dev->dma_phys); 427 i2c_dev->dma_buf = NULL; 428 } 429 430 if (i2c_dev->dma_chan) { 431 dma_release_channel(i2c_dev->dma_chan); 432 i2c_dev->dma_chan = NULL; 433 } 434 } 435 436 static int tegra_i2c_init_dma(struct tegra_i2c_dev *i2c_dev) 437 { 438 dma_addr_t dma_phys; 439 u32 *dma_buf; 440 int err; 441 442 if (IS_VI(i2c_dev)) 443 return 0; 444 445 if (!i2c_dev->hw->has_apb_dma) { 446 if (!IS_ENABLED(CONFIG_TEGRA20_APB_DMA)) { 447 dev_dbg(i2c_dev->dev, "APB DMA support not enabled\n"); 448 return 0; 449 } 450 } else if (!IS_ENABLED(CONFIG_TEGRA186_GPC_DMA)) { 451 dev_dbg(i2c_dev->dev, "GPC DMA support not enabled\n"); 452 return 0; 453 } 454 455 /* 456 * The same channel will be used for both RX and TX. 457 * Keeping the name as "tx" for backward compatibility 458 * with existing devicetrees. 459 */ 460 i2c_dev->dma_chan = dma_request_chan(i2c_dev->dev, "tx"); 461 if (IS_ERR(i2c_dev->dma_chan)) { 462 err = PTR_ERR(i2c_dev->dma_chan); 463 goto err_out; 464 } 465 466 i2c_dev->dma_dev = i2c_dev->dma_chan->device->dev; 467 i2c_dev->dma_buf_size = i2c_dev->hw->quirks->max_write_len + 468 I2C_PACKET_HEADER_SIZE; 469 470 dma_buf = dma_alloc_coherent(i2c_dev->dma_dev, i2c_dev->dma_buf_size, 471 &dma_phys, GFP_KERNEL | __GFP_NOWARN); 472 if (!dma_buf) { 473 dev_err(i2c_dev->dev, "failed to allocate DMA buffer\n"); 474 err = -ENOMEM; 475 goto err_out; 476 } 477 478 i2c_dev->dma_buf = dma_buf; 479 i2c_dev->dma_phys = dma_phys; 480 481 return 0; 482 483 err_out: 484 tegra_i2c_release_dma(i2c_dev); 485 if (err != -EPROBE_DEFER) { 486 dev_err(i2c_dev->dev, "cannot use DMA: %d\n", err); 487 dev_err(i2c_dev->dev, "falling back to PIO\n"); 488 return 0; 489 } 490 491 return err; 492 } 493 494 /* 495 * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller) 496 * block. This block is identical to the rest of the I2C blocks, except that 497 * it only supports master mode, it has registers moved around, and it needs 498 * some extra init to get it into I2C mode. The register moves are handled 499 * by i2c_readl() and i2c_writel(). 500 */ 501 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev) 502 { 503 u32 val; 504 505 val = dvc_readl(i2c_dev, DVC_CTRL_REG3); 506 val |= DVC_CTRL_REG3_SW_PROG; 507 val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN; 508 dvc_writel(i2c_dev, val, DVC_CTRL_REG3); 509 510 val = dvc_readl(i2c_dev, DVC_CTRL_REG1); 511 val |= DVC_CTRL_REG1_INTR_EN; 512 dvc_writel(i2c_dev, val, DVC_CTRL_REG1); 513 } 514 515 static void tegra_i2c_vi_init(struct tegra_i2c_dev *i2c_dev) 516 { 517 u32 value; 518 519 value = FIELD_PREP(I2C_INTERFACE_TIMING_THIGH, 2) | 520 FIELD_PREP(I2C_INTERFACE_TIMING_TLOW, 4); 521 i2c_writel(i2c_dev, value, I2C_INTERFACE_TIMING_0); 522 523 value = FIELD_PREP(I2C_INTERFACE_TIMING_TBUF, 4) | 524 FIELD_PREP(I2C_INTERFACE_TIMING_TSU_STO, 7) | 525 FIELD_PREP(I2C_INTERFACE_TIMING_THD_STA, 4) | 526 FIELD_PREP(I2C_INTERFACE_TIMING_TSU_STA, 4); 527 i2c_writel(i2c_dev, value, I2C_INTERFACE_TIMING_1); 528 529 value = FIELD_PREP(I2C_HS_INTERFACE_TIMING_THIGH, 3) | 530 FIELD_PREP(I2C_HS_INTERFACE_TIMING_TLOW, 8); 531 i2c_writel(i2c_dev, value, I2C_HS_INTERFACE_TIMING_0); 532 533 value = FIELD_PREP(I2C_HS_INTERFACE_TIMING_TSU_STO, 11) | 534 FIELD_PREP(I2C_HS_INTERFACE_TIMING_THD_STA, 11) | 535 FIELD_PREP(I2C_HS_INTERFACE_TIMING_TSU_STA, 11); 536 i2c_writel(i2c_dev, value, I2C_HS_INTERFACE_TIMING_1); 537 538 value = FIELD_PREP(I2C_BC_SCLK_THRESHOLD, 9) | I2C_BC_STOP_COND; 539 i2c_writel(i2c_dev, value, I2C_BUS_CLEAR_CNFG); 540 541 i2c_writel(i2c_dev, 0x0, I2C_TLOW_SEXT); 542 } 543 544 static int tegra_i2c_poll_register(struct tegra_i2c_dev *i2c_dev, 545 u32 reg, u32 mask, u32 delay_us, 546 u32 timeout_us) 547 { 548 void __iomem *addr = i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg); 549 u32 val; 550 551 if (!i2c_dev->atomic_mode) 552 return readl_relaxed_poll_timeout(addr, val, !(val & mask), 553 delay_us, timeout_us); 554 555 return readl_relaxed_poll_timeout_atomic(addr, val, !(val & mask), 556 delay_us, timeout_us); 557 } 558 559 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev) 560 { 561 u32 mask, val, offset; 562 int err; 563 564 if (i2c_dev->hw->has_mst_fifo) { 565 mask = I2C_MST_FIFO_CONTROL_TX_FLUSH | 566 I2C_MST_FIFO_CONTROL_RX_FLUSH; 567 offset = I2C_MST_FIFO_CONTROL; 568 } else { 569 mask = I2C_FIFO_CONTROL_TX_FLUSH | 570 I2C_FIFO_CONTROL_RX_FLUSH; 571 offset = I2C_FIFO_CONTROL; 572 } 573 574 val = i2c_readl(i2c_dev, offset); 575 val |= mask; 576 i2c_writel(i2c_dev, val, offset); 577 578 err = tegra_i2c_poll_register(i2c_dev, offset, mask, 1000, 1000000); 579 if (err) { 580 dev_err(i2c_dev->dev, "failed to flush FIFO\n"); 581 return err; 582 } 583 584 return 0; 585 } 586 587 static int tegra_i2c_wait_for_config_load(struct tegra_i2c_dev *i2c_dev) 588 { 589 int err; 590 591 if (!i2c_dev->hw->has_config_load_reg) 592 return 0; 593 594 i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, I2C_CONFIG_LOAD); 595 596 err = tegra_i2c_poll_register(i2c_dev, I2C_CONFIG_LOAD, 0xffffffff, 597 1000, I2C_CONFIG_LOAD_TIMEOUT); 598 if (err) { 599 dev_err(i2c_dev->dev, "failed to load config\n"); 600 return err; 601 } 602 603 return 0; 604 } 605 606 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) 607 { 608 u32 val, clk_divisor, clk_multiplier, tsu_thd, tlow, thigh, non_hs_mode; 609 acpi_handle handle = ACPI_HANDLE(i2c_dev->dev); 610 struct i2c_timings *t = &i2c_dev->timings; 611 int err; 612 613 /* 614 * The reset shouldn't ever fail in practice. The failure will be a 615 * sign of a severe problem that needs to be resolved. Still we don't 616 * want to fail the initialization completely because this may break 617 * kernel boot up since voltage regulators use I2C. Hence, we will 618 * emit a noisy warning on error, which won't stay unnoticed and 619 * won't hose machine entirely. 620 */ 621 if (handle) 622 err = acpi_evaluate_object(handle, "_RST", NULL, NULL); 623 else 624 err = reset_control_reset(i2c_dev->rst); 625 626 WARN_ON_ONCE(err); 627 628 if (IS_DVC(i2c_dev)) 629 tegra_dvc_init(i2c_dev); 630 631 val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN | 632 FIELD_PREP(I2C_CNFG_DEBOUNCE_CNT, 2); 633 634 if (i2c_dev->hw->has_multi_master_mode) 635 val |= I2C_CNFG_MULTI_MASTER_MODE; 636 637 i2c_writel(i2c_dev, val, I2C_CNFG); 638 i2c_writel(i2c_dev, 0, I2C_INT_MASK); 639 640 if (IS_VI(i2c_dev)) 641 tegra_i2c_vi_init(i2c_dev); 642 643 switch (t->bus_freq_hz) { 644 case I2C_MAX_STANDARD_MODE_FREQ + 1 ... I2C_MAX_FAST_MODE_PLUS_FREQ: 645 default: 646 tlow = i2c_dev->hw->tlow_fast_fastplus_mode; 647 thigh = i2c_dev->hw->thigh_fast_fastplus_mode; 648 tsu_thd = i2c_dev->hw->setup_hold_time_fast_fast_plus_mode; 649 650 if (t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ) 651 non_hs_mode = i2c_dev->hw->clk_divisor_fast_plus_mode; 652 else 653 non_hs_mode = i2c_dev->hw->clk_divisor_fast_mode; 654 break; 655 656 case 0 ... I2C_MAX_STANDARD_MODE_FREQ: 657 tlow = i2c_dev->hw->tlow_std_mode; 658 thigh = i2c_dev->hw->thigh_std_mode; 659 tsu_thd = i2c_dev->hw->setup_hold_time_std_mode; 660 non_hs_mode = i2c_dev->hw->clk_divisor_std_mode; 661 break; 662 } 663 664 /* make sure clock divisor programmed correctly */ 665 clk_divisor = FIELD_PREP(I2C_CLK_DIVISOR_HSMODE, 666 i2c_dev->hw->clk_divisor_hs_mode) | 667 FIELD_PREP(I2C_CLK_DIVISOR_STD_FAST_MODE, non_hs_mode); 668 i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR); 669 670 if (i2c_dev->hw->has_interface_timing_reg) { 671 val = FIELD_PREP(I2C_INTERFACE_TIMING_THIGH, thigh) | 672 FIELD_PREP(I2C_INTERFACE_TIMING_TLOW, tlow); 673 i2c_writel(i2c_dev, val, I2C_INTERFACE_TIMING_0); 674 } 675 676 /* 677 * Configure setup and hold times only when tsu_thd is non-zero. 678 * Otherwise, preserve the chip default values. 679 */ 680 if (i2c_dev->hw->has_interface_timing_reg && tsu_thd) 681 i2c_writel(i2c_dev, tsu_thd, I2C_INTERFACE_TIMING_1); 682 683 clk_multiplier = (tlow + thigh + 2) * (non_hs_mode + 1); 684 685 err = clk_set_rate(i2c_dev->div_clk, 686 t->bus_freq_hz * clk_multiplier); 687 if (err) { 688 dev_err(i2c_dev->dev, "failed to set div-clk rate: %d\n", err); 689 return err; 690 } 691 692 if (!IS_DVC(i2c_dev) && !IS_VI(i2c_dev)) { 693 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG); 694 695 sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL; 696 i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG); 697 i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1); 698 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2); 699 } 700 701 err = tegra_i2c_flush_fifos(i2c_dev); 702 if (err) 703 return err; 704 705 if (i2c_dev->multimaster_mode && i2c_dev->hw->has_slcg_override_reg) 706 i2c_writel(i2c_dev, I2C_MST_CORE_CLKEN_OVR, I2C_CLKEN_OVERRIDE); 707 708 err = tegra_i2c_wait_for_config_load(i2c_dev); 709 if (err) 710 return err; 711 712 return 0; 713 } 714 715 static int tegra_i2c_disable_packet_mode(struct tegra_i2c_dev *i2c_dev) 716 { 717 u32 cnfg; 718 719 /* 720 * NACK interrupt is generated before the I2C controller generates 721 * the STOP condition on the bus. So, wait for 2 clock periods 722 * before disabling the controller so that the STOP condition has 723 * been delivered properly. 724 */ 725 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->timings.bus_freq_hz)); 726 727 cnfg = i2c_readl(i2c_dev, I2C_CNFG); 728 if (cnfg & I2C_CNFG_PACKET_MODE_EN) 729 i2c_writel(i2c_dev, cnfg & ~I2C_CNFG_PACKET_MODE_EN, I2C_CNFG); 730 731 return tegra_i2c_wait_for_config_load(i2c_dev); 732 } 733 734 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev) 735 { 736 size_t buf_remaining = i2c_dev->msg_buf_remaining; 737 unsigned int words_to_transfer, rx_fifo_avail; 738 u8 *buf = i2c_dev->msg_buf; 739 u32 val; 740 741 /* 742 * Catch overflow due to message fully sent before the check for 743 * RX FIFO availability. 744 */ 745 if (WARN_ON_ONCE(!(i2c_dev->msg_buf_remaining))) 746 return -EINVAL; 747 748 if (i2c_dev->hw->has_mst_fifo) { 749 val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS); 750 rx_fifo_avail = FIELD_GET(I2C_MST_FIFO_STATUS_RX, val); 751 } else { 752 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS); 753 rx_fifo_avail = FIELD_GET(I2C_FIFO_STATUS_RX, val); 754 } 755 756 /* round down to exclude partial word at the end of buffer */ 757 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD; 758 if (words_to_transfer > rx_fifo_avail) 759 words_to_transfer = rx_fifo_avail; 760 761 i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer); 762 763 buf += words_to_transfer * BYTES_PER_FIFO_WORD; 764 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD; 765 rx_fifo_avail -= words_to_transfer; 766 767 /* 768 * If there is a partial word at the end of buffer, handle it 769 * manually to prevent overwriting past the end of buffer. 770 */ 771 if (rx_fifo_avail > 0 && buf_remaining > 0) { 772 /* 773 * buf_remaining > 3 check not needed as rx_fifo_avail == 0 774 * when (words_to_transfer was > rx_fifo_avail) earlier 775 * in this function. 776 */ 777 val = i2c_readl(i2c_dev, I2C_RX_FIFO); 778 val = cpu_to_le32(val); 779 memcpy(buf, &val, buf_remaining); 780 buf_remaining = 0; 781 rx_fifo_avail--; 782 } 783 784 /* RX FIFO must be drained, otherwise it's an Overflow case. */ 785 if (WARN_ON_ONCE(rx_fifo_avail)) 786 return -EINVAL; 787 788 i2c_dev->msg_buf_remaining = buf_remaining; 789 i2c_dev->msg_buf = buf; 790 791 return 0; 792 } 793 794 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev) 795 { 796 size_t buf_remaining = i2c_dev->msg_buf_remaining; 797 unsigned int words_to_transfer, tx_fifo_avail; 798 u8 *buf = i2c_dev->msg_buf; 799 u32 val; 800 801 if (i2c_dev->hw->has_mst_fifo) { 802 val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS); 803 tx_fifo_avail = FIELD_GET(I2C_MST_FIFO_STATUS_TX, val); 804 } else { 805 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS); 806 tx_fifo_avail = FIELD_GET(I2C_FIFO_STATUS_TX, val); 807 } 808 809 /* round down to exclude partial word at the end of buffer */ 810 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD; 811 812 /* 813 * This hunk pushes 4 bytes at a time into the TX FIFO. 814 * 815 * It's very common to have < 4 bytes, hence there is no word 816 * to push if we have less than 4 bytes to transfer. 817 */ 818 if (words_to_transfer) { 819 if (words_to_transfer > tx_fifo_avail) 820 words_to_transfer = tx_fifo_avail; 821 822 /* 823 * Update state before writing to FIFO. Note that this may 824 * cause us to finish writing all bytes (AKA buf_remaining 825 * goes to 0), hence we have a potential for an interrupt 826 * (PACKET_XFER_COMPLETE is not maskable), but GIC interrupt 827 * is disabled at this point. 828 */ 829 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD; 830 tx_fifo_avail -= words_to_transfer; 831 832 i2c_dev->msg_buf_remaining = buf_remaining; 833 i2c_dev->msg_buf = buf + words_to_transfer * BYTES_PER_FIFO_WORD; 834 835 if (IS_VI(i2c_dev)) 836 i2c_writesl_vi(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer); 837 else 838 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer); 839 840 buf += words_to_transfer * BYTES_PER_FIFO_WORD; 841 } 842 843 /* 844 * If there is a partial word at the end of buffer, handle it manually 845 * to prevent reading past the end of buffer, which could cross a page 846 * boundary and fault. 847 */ 848 if (tx_fifo_avail > 0 && buf_remaining > 0) { 849 /* 850 * buf_remaining > 3 check not needed as tx_fifo_avail == 0 851 * when (words_to_transfer was > tx_fifo_avail) earlier 852 * in this function for non-zero words_to_transfer. 853 */ 854 memcpy(&val, buf, buf_remaining); 855 val = le32_to_cpu(val); 856 857 i2c_dev->msg_buf_remaining = 0; 858 i2c_dev->msg_buf = NULL; 859 860 i2c_writel(i2c_dev, val, I2C_TX_FIFO); 861 } 862 863 return 0; 864 } 865 866 static irqreturn_t tegra_i2c_isr(int irq, void *dev_id) 867 { 868 const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST; 869 struct tegra_i2c_dev *i2c_dev = dev_id; 870 u32 status; 871 872 status = i2c_readl(i2c_dev, I2C_INT_STATUS); 873 874 if (status == 0) { 875 dev_warn(i2c_dev->dev, "IRQ status 0 %08x %08x %08x\n", 876 i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS), 877 i2c_readl(i2c_dev, I2C_STATUS), 878 i2c_readl(i2c_dev, I2C_CNFG)); 879 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT; 880 goto err; 881 } 882 883 if (status & status_err) { 884 tegra_i2c_disable_packet_mode(i2c_dev); 885 if (status & I2C_INT_NO_ACK) 886 i2c_dev->msg_err |= I2C_ERR_NO_ACK; 887 if (status & I2C_INT_ARBITRATION_LOST) 888 i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST; 889 goto err; 890 } 891 892 /* 893 * I2C transfer is terminated during the bus clear, so skip 894 * processing the other interrupts. 895 */ 896 if (i2c_dev->hw->supports_bus_clear && (status & I2C_INT_BUS_CLR_DONE)) 897 goto err; 898 899 if (!i2c_dev->dma_mode) { 900 if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) { 901 if (tegra_i2c_empty_rx_fifo(i2c_dev)) { 902 /* 903 * Overflow error condition: message fully sent, 904 * with no XFER_COMPLETE interrupt but hardware 905 * asks to transfer more. 906 */ 907 i2c_dev->msg_err |= I2C_ERR_RX_BUFFER_OVERFLOW; 908 goto err; 909 } 910 } 911 912 if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) { 913 if (i2c_dev->msg_buf_remaining) 914 tegra_i2c_fill_tx_fifo(i2c_dev); 915 else 916 tegra_i2c_mask_irq(i2c_dev, 917 I2C_INT_TX_FIFO_DATA_REQ); 918 } 919 } 920 921 i2c_writel(i2c_dev, status, I2C_INT_STATUS); 922 if (IS_DVC(i2c_dev)) 923 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS); 924 925 /* 926 * During message read XFER_COMPLETE interrupt is triggered prior to 927 * DMA completion and during message write XFER_COMPLETE interrupt is 928 * triggered after DMA completion. 929 * 930 * PACKETS_XFER_COMPLETE indicates completion of all bytes of transfer, 931 * so forcing msg_buf_remaining to 0 in DMA mode. 932 */ 933 if (status & I2C_INT_PACKET_XFER_COMPLETE) { 934 if (i2c_dev->dma_mode) 935 i2c_dev->msg_buf_remaining = 0; 936 /* 937 * Underflow error condition: XFER_COMPLETE before message 938 * fully sent. 939 */ 940 if (WARN_ON_ONCE(i2c_dev->msg_buf_remaining)) { 941 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT; 942 goto err; 943 } 944 complete(&i2c_dev->msg_complete); 945 } 946 goto done; 947 err: 948 /* mask all interrupts on error */ 949 tegra_i2c_mask_irq(i2c_dev, 950 I2C_INT_NO_ACK | 951 I2C_INT_ARBITRATION_LOST | 952 I2C_INT_PACKET_XFER_COMPLETE | 953 I2C_INT_TX_FIFO_DATA_REQ | 954 I2C_INT_RX_FIFO_DATA_REQ); 955 956 if (i2c_dev->hw->supports_bus_clear) 957 tegra_i2c_mask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE); 958 959 i2c_writel(i2c_dev, status, I2C_INT_STATUS); 960 961 if (IS_DVC(i2c_dev)) 962 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS); 963 964 if (i2c_dev->dma_mode) { 965 dmaengine_terminate_async(i2c_dev->dma_chan); 966 complete(&i2c_dev->dma_complete); 967 } 968 969 complete(&i2c_dev->msg_complete); 970 done: 971 return IRQ_HANDLED; 972 } 973 974 static void tegra_i2c_config_fifo_trig(struct tegra_i2c_dev *i2c_dev, 975 size_t len) 976 { 977 struct dma_slave_config slv_config = {0}; 978 u32 val, reg, dma_burst, reg_offset; 979 int err; 980 981 if (i2c_dev->hw->has_mst_fifo) 982 reg = I2C_MST_FIFO_CONTROL; 983 else 984 reg = I2C_FIFO_CONTROL; 985 986 if (i2c_dev->dma_mode) { 987 if (len & 0xF) 988 dma_burst = 1; 989 else if (len & 0x10) 990 dma_burst = 4; 991 else 992 dma_burst = 8; 993 994 if (i2c_dev->msg_read) { 995 reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_RX_FIFO); 996 997 slv_config.src_addr = i2c_dev->base_phys + reg_offset; 998 slv_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 999 slv_config.src_maxburst = dma_burst; 1000 1001 if (i2c_dev->hw->has_mst_fifo) 1002 val = I2C_MST_FIFO_CONTROL_RX_TRIG(dma_burst); 1003 else 1004 val = I2C_FIFO_CONTROL_RX_TRIG(dma_burst); 1005 } else { 1006 reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_TX_FIFO); 1007 1008 slv_config.dst_addr = i2c_dev->base_phys + reg_offset; 1009 slv_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1010 slv_config.dst_maxburst = dma_burst; 1011 1012 if (i2c_dev->hw->has_mst_fifo) 1013 val = I2C_MST_FIFO_CONTROL_TX_TRIG(dma_burst); 1014 else 1015 val = I2C_FIFO_CONTROL_TX_TRIG(dma_burst); 1016 } 1017 1018 slv_config.device_fc = true; 1019 err = dmaengine_slave_config(i2c_dev->dma_chan, &slv_config); 1020 if (err) { 1021 dev_err(i2c_dev->dev, "DMA config failed: %d\n", err); 1022 dev_err(i2c_dev->dev, "falling back to PIO\n"); 1023 1024 tegra_i2c_release_dma(i2c_dev); 1025 i2c_dev->dma_mode = false; 1026 } else { 1027 goto out; 1028 } 1029 } 1030 1031 if (i2c_dev->hw->has_mst_fifo) 1032 val = I2C_MST_FIFO_CONTROL_TX_TRIG(8) | 1033 I2C_MST_FIFO_CONTROL_RX_TRIG(1); 1034 else 1035 val = I2C_FIFO_CONTROL_TX_TRIG(8) | 1036 I2C_FIFO_CONTROL_RX_TRIG(1); 1037 out: 1038 i2c_writel(i2c_dev, val, reg); 1039 } 1040 1041 static unsigned long tegra_i2c_poll_completion(struct tegra_i2c_dev *i2c_dev, 1042 struct completion *complete, 1043 unsigned int timeout_ms) 1044 { 1045 ktime_t ktime = ktime_get(); 1046 ktime_t ktimeout = ktime_add_ms(ktime, timeout_ms); 1047 1048 do { 1049 u32 status = i2c_readl(i2c_dev, I2C_INT_STATUS); 1050 1051 if (status) 1052 tegra_i2c_isr(i2c_dev->irq, i2c_dev); 1053 1054 if (completion_done(complete)) { 1055 s64 delta = ktime_ms_delta(ktimeout, ktime); 1056 1057 return msecs_to_jiffies(delta) ?: 1; 1058 } 1059 1060 ktime = ktime_get(); 1061 1062 } while (ktime_before(ktime, ktimeout)); 1063 1064 return 0; 1065 } 1066 1067 static unsigned long tegra_i2c_wait_completion(struct tegra_i2c_dev *i2c_dev, 1068 struct completion *complete, 1069 unsigned int timeout_ms) 1070 { 1071 unsigned long ret; 1072 1073 if (i2c_dev->atomic_mode) { 1074 ret = tegra_i2c_poll_completion(i2c_dev, complete, timeout_ms); 1075 } else { 1076 enable_irq(i2c_dev->irq); 1077 ret = wait_for_completion_timeout(complete, 1078 msecs_to_jiffies(timeout_ms)); 1079 disable_irq(i2c_dev->irq); 1080 1081 /* 1082 * Under some rare circumstances (like running KASAN + 1083 * NFS root) CPU, which handles interrupt, may stuck in 1084 * uninterruptible state for a significant time. In this 1085 * case we will get timeout if I2C transfer is running on 1086 * a sibling CPU, despite of IRQ being raised. 1087 * 1088 * In order to handle this rare condition, the IRQ status 1089 * needs to be checked after timeout. 1090 */ 1091 if (ret == 0) 1092 ret = tegra_i2c_poll_completion(i2c_dev, complete, 0); 1093 } 1094 1095 return ret; 1096 } 1097 1098 static int tegra_i2c_issue_bus_clear(struct i2c_adapter *adap) 1099 { 1100 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 1101 u32 val, time_left; 1102 int err; 1103 1104 reinit_completion(&i2c_dev->msg_complete); 1105 1106 val = FIELD_PREP(I2C_BC_SCLK_THRESHOLD, 9) | I2C_BC_STOP_COND | 1107 I2C_BC_TERMINATE; 1108 i2c_writel(i2c_dev, val, I2C_BUS_CLEAR_CNFG); 1109 1110 err = tegra_i2c_wait_for_config_load(i2c_dev); 1111 if (err) 1112 return err; 1113 1114 val |= I2C_BC_ENABLE; 1115 i2c_writel(i2c_dev, val, I2C_BUS_CLEAR_CNFG); 1116 tegra_i2c_unmask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE); 1117 1118 time_left = tegra_i2c_wait_completion(i2c_dev, &i2c_dev->msg_complete, 50); 1119 tegra_i2c_mask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE); 1120 1121 if (time_left == 0) { 1122 dev_err(i2c_dev->dev, "failed to clear bus\n"); 1123 return -ETIMEDOUT; 1124 } 1125 1126 val = i2c_readl(i2c_dev, I2C_BUS_CLEAR_STATUS); 1127 if (!(val & I2C_BC_STATUS)) { 1128 dev_err(i2c_dev->dev, "un-recovered arbitration lost\n"); 1129 return -EIO; 1130 } 1131 1132 return -EAGAIN; 1133 } 1134 1135 static void tegra_i2c_push_packet_header(struct tegra_i2c_dev *i2c_dev, 1136 struct i2c_msg *msg, 1137 enum msg_end_type end_state) 1138 { 1139 u32 *dma_buf = i2c_dev->dma_buf; 1140 u32 packet_header; 1141 1142 packet_header = FIELD_PREP(PACKET_HEADER0_HEADER_SIZE, 0) | 1143 FIELD_PREP(PACKET_HEADER0_PROTOCOL, 1144 PACKET_HEADER0_PROTOCOL_I2C) | 1145 FIELD_PREP(PACKET_HEADER0_CONT_ID, i2c_dev->cont_id) | 1146 FIELD_PREP(PACKET_HEADER0_PACKET_ID, 1); 1147 1148 if (i2c_dev->dma_mode && !i2c_dev->msg_read) 1149 *dma_buf++ = packet_header; 1150 else 1151 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); 1152 1153 packet_header = i2c_dev->msg_len - 1; 1154 1155 if (i2c_dev->dma_mode && !i2c_dev->msg_read) 1156 *dma_buf++ = packet_header; 1157 else 1158 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); 1159 1160 packet_header = I2C_HEADER_IE_ENABLE; 1161 1162 if (end_state == MSG_END_CONTINUE) 1163 packet_header |= I2C_HEADER_CONTINUE_XFER; 1164 else if (end_state == MSG_END_REPEAT_START) 1165 packet_header |= I2C_HEADER_REPEAT_START; 1166 1167 if (msg->flags & I2C_M_TEN) { 1168 packet_header |= msg->addr; 1169 packet_header |= I2C_HEADER_10BIT_ADDR; 1170 } else { 1171 packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT; 1172 } 1173 1174 if (msg->flags & I2C_M_IGNORE_NAK) 1175 packet_header |= I2C_HEADER_CONT_ON_NAK; 1176 1177 if (msg->flags & I2C_M_RD) 1178 packet_header |= I2C_HEADER_READ; 1179 1180 if (i2c_dev->dma_mode && !i2c_dev->msg_read) 1181 *dma_buf++ = packet_header; 1182 else 1183 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); 1184 } 1185 1186 static int tegra_i2c_error_recover(struct tegra_i2c_dev *i2c_dev, 1187 struct i2c_msg *msg) 1188 { 1189 if (i2c_dev->msg_err == I2C_ERR_NONE) 1190 return 0; 1191 1192 tegra_i2c_init(i2c_dev); 1193 1194 /* start recovery upon arbitration loss in single master mode */ 1195 if (i2c_dev->msg_err == I2C_ERR_ARBITRATION_LOST) { 1196 if (!i2c_dev->multimaster_mode) 1197 return i2c_recover_bus(&i2c_dev->adapter); 1198 1199 return -EAGAIN; 1200 } 1201 1202 if (i2c_dev->msg_err == I2C_ERR_NO_ACK) { 1203 if (msg->flags & I2C_M_IGNORE_NAK) 1204 return 0; 1205 1206 return -EREMOTEIO; 1207 } 1208 1209 return -EIO; 1210 } 1211 1212 static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev, 1213 struct i2c_msg *msg, 1214 enum msg_end_type end_state) 1215 { 1216 unsigned long time_left, xfer_time = 100; 1217 size_t xfer_size; 1218 u32 int_mask; 1219 int err; 1220 1221 err = tegra_i2c_flush_fifos(i2c_dev); 1222 if (err) 1223 return err; 1224 1225 i2c_dev->msg_buf = msg->buf; 1226 i2c_dev->msg_len = msg->len; 1227 1228 i2c_dev->msg_err = I2C_ERR_NONE; 1229 i2c_dev->msg_read = !!(msg->flags & I2C_M_RD); 1230 reinit_completion(&i2c_dev->msg_complete); 1231 1232 /* 1233 * For SMBUS block read command, read only 1 byte in the first transfer. 1234 * Adjust that 1 byte for the next transfer in the msg buffer and msg 1235 * length. 1236 */ 1237 if (msg->flags & I2C_M_RECV_LEN) { 1238 if (end_state == MSG_END_CONTINUE) { 1239 i2c_dev->msg_len = 1; 1240 } else { 1241 i2c_dev->msg_buf += 1; 1242 i2c_dev->msg_len -= 1; 1243 } 1244 } 1245 1246 i2c_dev->msg_buf_remaining = i2c_dev->msg_len; 1247 1248 if (i2c_dev->msg_read) 1249 xfer_size = i2c_dev->msg_len; 1250 else 1251 xfer_size = i2c_dev->msg_len + I2C_PACKET_HEADER_SIZE; 1252 1253 xfer_size = ALIGN(xfer_size, BYTES_PER_FIFO_WORD); 1254 1255 i2c_dev->dma_mode = xfer_size > I2C_PIO_MODE_PREFERRED_LEN && 1256 i2c_dev->dma_buf && !i2c_dev->atomic_mode; 1257 1258 tegra_i2c_config_fifo_trig(i2c_dev, xfer_size); 1259 1260 /* 1261 * Transfer time in mSec = Total bits / transfer rate 1262 * Total bits = 9 bits per byte (including ACK bit) + Start & stop bits 1263 */ 1264 xfer_time += DIV_ROUND_CLOSEST(((xfer_size * 9) + 2) * MSEC_PER_SEC, 1265 i2c_dev->timings.bus_freq_hz); 1266 1267 int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST; 1268 tegra_i2c_unmask_irq(i2c_dev, int_mask); 1269 1270 if (i2c_dev->dma_mode) { 1271 if (i2c_dev->msg_read) { 1272 dma_sync_single_for_device(i2c_dev->dma_dev, 1273 i2c_dev->dma_phys, 1274 xfer_size, DMA_FROM_DEVICE); 1275 1276 err = tegra_i2c_dma_submit(i2c_dev, xfer_size); 1277 if (err) 1278 return err; 1279 } else { 1280 dma_sync_single_for_cpu(i2c_dev->dma_dev, 1281 i2c_dev->dma_phys, 1282 xfer_size, DMA_TO_DEVICE); 1283 } 1284 } 1285 1286 tegra_i2c_push_packet_header(i2c_dev, msg, end_state); 1287 1288 if (!i2c_dev->msg_read) { 1289 if (i2c_dev->dma_mode) { 1290 memcpy(i2c_dev->dma_buf + I2C_PACKET_HEADER_SIZE, 1291 msg->buf, i2c_dev->msg_len); 1292 1293 dma_sync_single_for_device(i2c_dev->dma_dev, 1294 i2c_dev->dma_phys, 1295 xfer_size, DMA_TO_DEVICE); 1296 1297 err = tegra_i2c_dma_submit(i2c_dev, xfer_size); 1298 if (err) 1299 return err; 1300 } else { 1301 tegra_i2c_fill_tx_fifo(i2c_dev); 1302 } 1303 } 1304 1305 if (i2c_dev->hw->has_per_pkt_xfer_complete_irq) 1306 int_mask |= I2C_INT_PACKET_XFER_COMPLETE; 1307 1308 if (!i2c_dev->dma_mode) { 1309 if (msg->flags & I2C_M_RD) 1310 int_mask |= I2C_INT_RX_FIFO_DATA_REQ; 1311 else if (i2c_dev->msg_buf_remaining) 1312 int_mask |= I2C_INT_TX_FIFO_DATA_REQ; 1313 } 1314 1315 tegra_i2c_unmask_irq(i2c_dev, int_mask); 1316 dev_dbg(i2c_dev->dev, "unmasked IRQ: %02x\n", 1317 i2c_readl(i2c_dev, I2C_INT_MASK)); 1318 1319 if (i2c_dev->dma_mode) { 1320 time_left = tegra_i2c_wait_completion(i2c_dev, 1321 &i2c_dev->dma_complete, 1322 xfer_time); 1323 1324 /* 1325 * Synchronize DMA first, since dmaengine_terminate_sync() 1326 * performs synchronization after the transfer's termination 1327 * and we want to get a completion if transfer succeeded. 1328 */ 1329 dmaengine_synchronize(i2c_dev->dma_chan); 1330 dmaengine_terminate_sync(i2c_dev->dma_chan); 1331 1332 if (!time_left && !completion_done(&i2c_dev->dma_complete)) { 1333 dev_err(i2c_dev->dev, "DMA transfer timed out\n"); 1334 tegra_i2c_init(i2c_dev); 1335 return -ETIMEDOUT; 1336 } 1337 1338 if (i2c_dev->msg_read && i2c_dev->msg_err == I2C_ERR_NONE) { 1339 dma_sync_single_for_cpu(i2c_dev->dma_dev, 1340 i2c_dev->dma_phys, 1341 xfer_size, DMA_FROM_DEVICE); 1342 1343 memcpy(i2c_dev->msg_buf, i2c_dev->dma_buf, i2c_dev->msg_len); 1344 } 1345 } 1346 1347 time_left = tegra_i2c_wait_completion(i2c_dev, &i2c_dev->msg_complete, 1348 xfer_time); 1349 1350 tegra_i2c_mask_irq(i2c_dev, int_mask); 1351 1352 if (time_left == 0) { 1353 dev_err(i2c_dev->dev, "I2C transfer timed out\n"); 1354 tegra_i2c_init(i2c_dev); 1355 return -ETIMEDOUT; 1356 } 1357 1358 dev_dbg(i2c_dev->dev, "transfer complete: %lu %d %d\n", 1359 time_left, completion_done(&i2c_dev->msg_complete), 1360 i2c_dev->msg_err); 1361 1362 i2c_dev->dma_mode = false; 1363 1364 err = tegra_i2c_error_recover(i2c_dev, msg); 1365 if (err) 1366 return err; 1367 1368 return 0; 1369 } 1370 1371 static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], 1372 int num) 1373 { 1374 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 1375 int i, ret; 1376 1377 ret = pm_runtime_get_sync(i2c_dev->dev); 1378 if (ret < 0) { 1379 dev_err(i2c_dev->dev, "runtime resume failed %d\n", ret); 1380 pm_runtime_put_noidle(i2c_dev->dev); 1381 return ret; 1382 } 1383 1384 for (i = 0; i < num; i++) { 1385 enum msg_end_type end_type = MSG_END_STOP; 1386 1387 if (i < (num - 1)) { 1388 /* check whether follow up message is coming */ 1389 if (msgs[i + 1].flags & I2C_M_NOSTART) 1390 end_type = MSG_END_CONTINUE; 1391 else 1392 end_type = MSG_END_REPEAT_START; 1393 } 1394 /* If M_RECV_LEN use ContinueXfer to read the first byte */ 1395 if (msgs[i].flags & I2C_M_RECV_LEN) { 1396 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], MSG_END_CONTINUE); 1397 if (ret) 1398 break; 1399 /* Set the msg length from first byte */ 1400 msgs[i].len += msgs[i].buf[0]; 1401 dev_dbg(i2c_dev->dev, "reading %d bytes\n", msgs[i].len); 1402 } 1403 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type); 1404 if (ret) 1405 break; 1406 } 1407 1408 pm_runtime_put(i2c_dev->dev); 1409 1410 return ret ?: i; 1411 } 1412 1413 static int tegra_i2c_xfer_atomic(struct i2c_adapter *adap, 1414 struct i2c_msg msgs[], int num) 1415 { 1416 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 1417 int ret; 1418 1419 i2c_dev->atomic_mode = true; 1420 ret = tegra_i2c_xfer(adap, msgs, num); 1421 i2c_dev->atomic_mode = false; 1422 1423 return ret; 1424 } 1425 1426 static u32 tegra_i2c_func(struct i2c_adapter *adap) 1427 { 1428 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 1429 u32 ret = I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) | 1430 I2C_FUNC_10BIT_ADDR | I2C_FUNC_PROTOCOL_MANGLING; 1431 1432 if (i2c_dev->hw->has_continue_xfer_support) 1433 ret |= I2C_FUNC_NOSTART | I2C_FUNC_SMBUS_READ_BLOCK_DATA; 1434 1435 return ret; 1436 } 1437 1438 static const struct i2c_algorithm tegra_i2c_algo = { 1439 .master_xfer = tegra_i2c_xfer, 1440 .master_xfer_atomic = tegra_i2c_xfer_atomic, 1441 .functionality = tegra_i2c_func, 1442 }; 1443 1444 /* payload size is only 12 bit */ 1445 static const struct i2c_adapter_quirks tegra_i2c_quirks = { 1446 .flags = I2C_AQ_NO_ZERO_LEN, 1447 .max_read_len = SZ_4K, 1448 .max_write_len = SZ_4K - I2C_PACKET_HEADER_SIZE, 1449 }; 1450 1451 static const struct i2c_adapter_quirks tegra194_i2c_quirks = { 1452 .flags = I2C_AQ_NO_ZERO_LEN, 1453 .max_write_len = SZ_64K - I2C_PACKET_HEADER_SIZE, 1454 }; 1455 1456 static struct i2c_bus_recovery_info tegra_i2c_recovery_info = { 1457 .recover_bus = tegra_i2c_issue_bus_clear, 1458 }; 1459 1460 static const struct tegra_i2c_hw_feature tegra20_i2c_hw = { 1461 .has_continue_xfer_support = false, 1462 .has_per_pkt_xfer_complete_irq = false, 1463 .clk_divisor_hs_mode = 3, 1464 .clk_divisor_std_mode = 0, 1465 .clk_divisor_fast_mode = 0, 1466 .clk_divisor_fast_plus_mode = 0, 1467 .has_config_load_reg = false, 1468 .has_multi_master_mode = false, 1469 .has_slcg_override_reg = false, 1470 .has_mst_fifo = false, 1471 .quirks = &tegra_i2c_quirks, 1472 .supports_bus_clear = false, 1473 .has_apb_dma = true, 1474 .tlow_std_mode = 0x4, 1475 .thigh_std_mode = 0x2, 1476 .tlow_fast_fastplus_mode = 0x4, 1477 .thigh_fast_fastplus_mode = 0x2, 1478 .setup_hold_time_std_mode = 0x0, 1479 .setup_hold_time_fast_fast_plus_mode = 0x0, 1480 .setup_hold_time_hs_mode = 0x0, 1481 .has_interface_timing_reg = false, 1482 }; 1483 1484 static const struct tegra_i2c_hw_feature tegra30_i2c_hw = { 1485 .has_continue_xfer_support = true, 1486 .has_per_pkt_xfer_complete_irq = false, 1487 .clk_divisor_hs_mode = 3, 1488 .clk_divisor_std_mode = 0, 1489 .clk_divisor_fast_mode = 0, 1490 .clk_divisor_fast_plus_mode = 0, 1491 .has_config_load_reg = false, 1492 .has_multi_master_mode = false, 1493 .has_slcg_override_reg = false, 1494 .has_mst_fifo = false, 1495 .quirks = &tegra_i2c_quirks, 1496 .supports_bus_clear = false, 1497 .has_apb_dma = true, 1498 .tlow_std_mode = 0x4, 1499 .thigh_std_mode = 0x2, 1500 .tlow_fast_fastplus_mode = 0x4, 1501 .thigh_fast_fastplus_mode = 0x2, 1502 .setup_hold_time_std_mode = 0x0, 1503 .setup_hold_time_fast_fast_plus_mode = 0x0, 1504 .setup_hold_time_hs_mode = 0x0, 1505 .has_interface_timing_reg = false, 1506 }; 1507 1508 static const struct tegra_i2c_hw_feature tegra114_i2c_hw = { 1509 .has_continue_xfer_support = true, 1510 .has_per_pkt_xfer_complete_irq = true, 1511 .clk_divisor_hs_mode = 1, 1512 .clk_divisor_std_mode = 0x19, 1513 .clk_divisor_fast_mode = 0x19, 1514 .clk_divisor_fast_plus_mode = 0x10, 1515 .has_config_load_reg = false, 1516 .has_multi_master_mode = false, 1517 .has_slcg_override_reg = false, 1518 .has_mst_fifo = false, 1519 .quirks = &tegra_i2c_quirks, 1520 .supports_bus_clear = true, 1521 .has_apb_dma = true, 1522 .tlow_std_mode = 0x4, 1523 .thigh_std_mode = 0x2, 1524 .tlow_fast_fastplus_mode = 0x4, 1525 .thigh_fast_fastplus_mode = 0x2, 1526 .setup_hold_time_std_mode = 0x0, 1527 .setup_hold_time_fast_fast_plus_mode = 0x0, 1528 .setup_hold_time_hs_mode = 0x0, 1529 .has_interface_timing_reg = false, 1530 }; 1531 1532 static const struct tegra_i2c_hw_feature tegra124_i2c_hw = { 1533 .has_continue_xfer_support = true, 1534 .has_per_pkt_xfer_complete_irq = true, 1535 .clk_divisor_hs_mode = 1, 1536 .clk_divisor_std_mode = 0x19, 1537 .clk_divisor_fast_mode = 0x19, 1538 .clk_divisor_fast_plus_mode = 0x10, 1539 .has_config_load_reg = true, 1540 .has_multi_master_mode = false, 1541 .has_slcg_override_reg = true, 1542 .has_mst_fifo = false, 1543 .quirks = &tegra_i2c_quirks, 1544 .supports_bus_clear = true, 1545 .has_apb_dma = true, 1546 .tlow_std_mode = 0x4, 1547 .thigh_std_mode = 0x2, 1548 .tlow_fast_fastplus_mode = 0x4, 1549 .thigh_fast_fastplus_mode = 0x2, 1550 .setup_hold_time_std_mode = 0x0, 1551 .setup_hold_time_fast_fast_plus_mode = 0x0, 1552 .setup_hold_time_hs_mode = 0x0, 1553 .has_interface_timing_reg = true, 1554 }; 1555 1556 static const struct tegra_i2c_hw_feature tegra210_i2c_hw = { 1557 .has_continue_xfer_support = true, 1558 .has_per_pkt_xfer_complete_irq = true, 1559 .clk_divisor_hs_mode = 1, 1560 .clk_divisor_std_mode = 0x19, 1561 .clk_divisor_fast_mode = 0x19, 1562 .clk_divisor_fast_plus_mode = 0x10, 1563 .has_config_load_reg = true, 1564 .has_multi_master_mode = false, 1565 .has_slcg_override_reg = true, 1566 .has_mst_fifo = false, 1567 .quirks = &tegra_i2c_quirks, 1568 .supports_bus_clear = true, 1569 .has_apb_dma = true, 1570 .tlow_std_mode = 0x4, 1571 .thigh_std_mode = 0x2, 1572 .tlow_fast_fastplus_mode = 0x4, 1573 .thigh_fast_fastplus_mode = 0x2, 1574 .setup_hold_time_std_mode = 0, 1575 .setup_hold_time_fast_fast_plus_mode = 0, 1576 .setup_hold_time_hs_mode = 0, 1577 .has_interface_timing_reg = true, 1578 }; 1579 1580 static const struct tegra_i2c_hw_feature tegra186_i2c_hw = { 1581 .has_continue_xfer_support = true, 1582 .has_per_pkt_xfer_complete_irq = true, 1583 .clk_divisor_hs_mode = 1, 1584 .clk_divisor_std_mode = 0x16, 1585 .clk_divisor_fast_mode = 0x19, 1586 .clk_divisor_fast_plus_mode = 0x10, 1587 .has_config_load_reg = true, 1588 .has_multi_master_mode = false, 1589 .has_slcg_override_reg = true, 1590 .has_mst_fifo = false, 1591 .quirks = &tegra_i2c_quirks, 1592 .supports_bus_clear = true, 1593 .has_apb_dma = false, 1594 .tlow_std_mode = 0x4, 1595 .thigh_std_mode = 0x3, 1596 .tlow_fast_fastplus_mode = 0x4, 1597 .thigh_fast_fastplus_mode = 0x2, 1598 .setup_hold_time_std_mode = 0, 1599 .setup_hold_time_fast_fast_plus_mode = 0, 1600 .setup_hold_time_hs_mode = 0, 1601 .has_interface_timing_reg = true, 1602 }; 1603 1604 static const struct tegra_i2c_hw_feature tegra194_i2c_hw = { 1605 .has_continue_xfer_support = true, 1606 .has_per_pkt_xfer_complete_irq = true, 1607 .clk_divisor_hs_mode = 1, 1608 .clk_divisor_std_mode = 0x4f, 1609 .clk_divisor_fast_mode = 0x3c, 1610 .clk_divisor_fast_plus_mode = 0x16, 1611 .has_config_load_reg = true, 1612 .has_multi_master_mode = true, 1613 .has_slcg_override_reg = true, 1614 .has_mst_fifo = true, 1615 .quirks = &tegra194_i2c_quirks, 1616 .supports_bus_clear = true, 1617 .has_apb_dma = false, 1618 .tlow_std_mode = 0x8, 1619 .thigh_std_mode = 0x7, 1620 .tlow_fast_fastplus_mode = 0x2, 1621 .thigh_fast_fastplus_mode = 0x2, 1622 .setup_hold_time_std_mode = 0x08080808, 1623 .setup_hold_time_fast_fast_plus_mode = 0x02020202, 1624 .setup_hold_time_hs_mode = 0x090909, 1625 .has_interface_timing_reg = true, 1626 }; 1627 1628 static const struct of_device_id tegra_i2c_of_match[] = { 1629 { .compatible = "nvidia,tegra194-i2c", .data = &tegra194_i2c_hw, }, 1630 { .compatible = "nvidia,tegra186-i2c", .data = &tegra186_i2c_hw, }, 1631 #if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) 1632 { .compatible = "nvidia,tegra210-i2c-vi", .data = &tegra210_i2c_hw, }, 1633 #endif 1634 { .compatible = "nvidia,tegra210-i2c", .data = &tegra210_i2c_hw, }, 1635 { .compatible = "nvidia,tegra124-i2c", .data = &tegra124_i2c_hw, }, 1636 { .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_hw, }, 1637 { .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, }, 1638 { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, }, 1639 #if IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) 1640 { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_hw, }, 1641 #endif 1642 {}, 1643 }; 1644 MODULE_DEVICE_TABLE(of, tegra_i2c_of_match); 1645 1646 static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev) 1647 { 1648 struct device_node *np = i2c_dev->dev->of_node; 1649 bool multi_mode; 1650 1651 i2c_parse_fw_timings(i2c_dev->dev, &i2c_dev->timings, true); 1652 1653 multi_mode = device_property_read_bool(i2c_dev->dev, "multi-master"); 1654 i2c_dev->multimaster_mode = multi_mode; 1655 1656 if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && 1657 of_device_is_compatible(np, "nvidia,tegra20-i2c-dvc")) 1658 i2c_dev->is_dvc = true; 1659 1660 if (IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) && 1661 of_device_is_compatible(np, "nvidia,tegra210-i2c-vi")) 1662 i2c_dev->is_vi = true; 1663 } 1664 1665 static int tegra_i2c_init_reset(struct tegra_i2c_dev *i2c_dev) 1666 { 1667 if (ACPI_HANDLE(i2c_dev->dev)) 1668 return 0; 1669 1670 i2c_dev->rst = devm_reset_control_get_exclusive(i2c_dev->dev, "i2c"); 1671 if (IS_ERR(i2c_dev->rst)) 1672 return dev_err_probe(i2c_dev->dev, PTR_ERR(i2c_dev->rst), 1673 "failed to get reset control\n"); 1674 1675 return 0; 1676 } 1677 1678 static int tegra_i2c_init_clocks(struct tegra_i2c_dev *i2c_dev) 1679 { 1680 int err; 1681 1682 if (ACPI_HANDLE(i2c_dev->dev)) 1683 return 0; 1684 1685 i2c_dev->clocks[i2c_dev->nclocks++].id = "div-clk"; 1686 1687 if (i2c_dev->hw == &tegra20_i2c_hw || i2c_dev->hw == &tegra30_i2c_hw) 1688 i2c_dev->clocks[i2c_dev->nclocks++].id = "fast-clk"; 1689 1690 if (IS_VI(i2c_dev)) 1691 i2c_dev->clocks[i2c_dev->nclocks++].id = "slow"; 1692 1693 err = devm_clk_bulk_get(i2c_dev->dev, i2c_dev->nclocks, 1694 i2c_dev->clocks); 1695 if (err) 1696 return err; 1697 1698 err = clk_bulk_prepare(i2c_dev->nclocks, i2c_dev->clocks); 1699 if (err) 1700 return err; 1701 1702 i2c_dev->div_clk = i2c_dev->clocks[0].clk; 1703 1704 if (!i2c_dev->multimaster_mode) 1705 return 0; 1706 1707 err = clk_enable(i2c_dev->div_clk); 1708 if (err) { 1709 dev_err(i2c_dev->dev, "failed to enable div-clk: %d\n", err); 1710 goto unprepare_clocks; 1711 } 1712 1713 return 0; 1714 1715 unprepare_clocks: 1716 clk_bulk_unprepare(i2c_dev->nclocks, i2c_dev->clocks); 1717 1718 return err; 1719 } 1720 1721 static void tegra_i2c_release_clocks(struct tegra_i2c_dev *i2c_dev) 1722 { 1723 if (i2c_dev->multimaster_mode) 1724 clk_disable(i2c_dev->div_clk); 1725 1726 clk_bulk_unprepare(i2c_dev->nclocks, i2c_dev->clocks); 1727 } 1728 1729 static int tegra_i2c_init_hardware(struct tegra_i2c_dev *i2c_dev) 1730 { 1731 int ret; 1732 1733 ret = pm_runtime_get_sync(i2c_dev->dev); 1734 if (ret < 0) 1735 dev_err(i2c_dev->dev, "runtime resume failed: %d\n", ret); 1736 else 1737 ret = tegra_i2c_init(i2c_dev); 1738 1739 pm_runtime_put_sync(i2c_dev->dev); 1740 1741 return ret; 1742 } 1743 1744 static int tegra_i2c_probe(struct platform_device *pdev) 1745 { 1746 struct tegra_i2c_dev *i2c_dev; 1747 struct resource *res; 1748 int err; 1749 1750 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); 1751 if (!i2c_dev) 1752 return -ENOMEM; 1753 1754 platform_set_drvdata(pdev, i2c_dev); 1755 1756 init_completion(&i2c_dev->msg_complete); 1757 init_completion(&i2c_dev->dma_complete); 1758 1759 i2c_dev->hw = device_get_match_data(&pdev->dev); 1760 i2c_dev->cont_id = pdev->id; 1761 i2c_dev->dev = &pdev->dev; 1762 1763 i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1764 if (IS_ERR(i2c_dev->base)) 1765 return PTR_ERR(i2c_dev->base); 1766 1767 i2c_dev->base_phys = res->start; 1768 1769 err = platform_get_irq(pdev, 0); 1770 if (err < 0) 1771 return err; 1772 1773 i2c_dev->irq = err; 1774 1775 /* interrupt will be enabled during of transfer time */ 1776 irq_set_status_flags(i2c_dev->irq, IRQ_NOAUTOEN); 1777 1778 err = devm_request_threaded_irq(i2c_dev->dev, i2c_dev->irq, 1779 NULL, tegra_i2c_isr, 1780 IRQF_NO_SUSPEND | IRQF_ONESHOT, 1781 dev_name(i2c_dev->dev), i2c_dev); 1782 if (err) 1783 return err; 1784 1785 tegra_i2c_parse_dt(i2c_dev); 1786 1787 err = tegra_i2c_init_reset(i2c_dev); 1788 if (err) 1789 return err; 1790 1791 err = tegra_i2c_init_clocks(i2c_dev); 1792 if (err) 1793 return err; 1794 1795 err = tegra_i2c_init_dma(i2c_dev); 1796 if (err) 1797 goto release_clocks; 1798 1799 /* 1800 * VI I2C is in VE power domain which is not always ON and not 1801 * IRQ-safe. Thus, IRQ-safe device shouldn't be attached to a 1802 * non IRQ-safe domain because this prevents powering off the power 1803 * domain. 1804 * 1805 * VI I2C device shouldn't be marked as IRQ-safe because VI I2C won't 1806 * be used for atomic transfers. 1807 */ 1808 if (!IS_VI(i2c_dev)) 1809 pm_runtime_irq_safe(i2c_dev->dev); 1810 1811 pm_runtime_enable(i2c_dev->dev); 1812 1813 err = tegra_i2c_init_hardware(i2c_dev); 1814 if (err) 1815 goto release_rpm; 1816 1817 i2c_set_adapdata(&i2c_dev->adapter, i2c_dev); 1818 i2c_dev->adapter.dev.of_node = i2c_dev->dev->of_node; 1819 i2c_dev->adapter.dev.parent = i2c_dev->dev; 1820 i2c_dev->adapter.retries = 1; 1821 i2c_dev->adapter.timeout = 6 * HZ; 1822 i2c_dev->adapter.quirks = i2c_dev->hw->quirks; 1823 i2c_dev->adapter.owner = THIS_MODULE; 1824 i2c_dev->adapter.class = I2C_CLASS_DEPRECATED; 1825 i2c_dev->adapter.algo = &tegra_i2c_algo; 1826 i2c_dev->adapter.nr = pdev->id; 1827 ACPI_COMPANION_SET(&i2c_dev->adapter.dev, ACPI_COMPANION(&pdev->dev)); 1828 1829 if (i2c_dev->hw->supports_bus_clear) 1830 i2c_dev->adapter.bus_recovery_info = &tegra_i2c_recovery_info; 1831 1832 strscpy(i2c_dev->adapter.name, dev_name(i2c_dev->dev), 1833 sizeof(i2c_dev->adapter.name)); 1834 1835 err = i2c_add_numbered_adapter(&i2c_dev->adapter); 1836 if (err) 1837 goto release_rpm; 1838 1839 return 0; 1840 1841 release_rpm: 1842 pm_runtime_disable(i2c_dev->dev); 1843 1844 tegra_i2c_release_dma(i2c_dev); 1845 release_clocks: 1846 tegra_i2c_release_clocks(i2c_dev); 1847 1848 return err; 1849 } 1850 1851 static void tegra_i2c_remove(struct platform_device *pdev) 1852 { 1853 struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev); 1854 1855 i2c_del_adapter(&i2c_dev->adapter); 1856 pm_runtime_force_suspend(i2c_dev->dev); 1857 1858 tegra_i2c_release_dma(i2c_dev); 1859 tegra_i2c_release_clocks(i2c_dev); 1860 } 1861 1862 static int __maybe_unused tegra_i2c_runtime_resume(struct device *dev) 1863 { 1864 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); 1865 int err; 1866 1867 err = pinctrl_pm_select_default_state(dev); 1868 if (err) 1869 return err; 1870 1871 err = clk_bulk_enable(i2c_dev->nclocks, i2c_dev->clocks); 1872 if (err) 1873 return err; 1874 1875 /* 1876 * VI I2C device is attached to VE power domain which goes through 1877 * power ON/OFF during runtime PM resume/suspend, meaning that 1878 * controller needs to be re-initialized after power ON. 1879 */ 1880 if (IS_VI(i2c_dev)) { 1881 err = tegra_i2c_init(i2c_dev); 1882 if (err) 1883 goto disable_clocks; 1884 } 1885 1886 return 0; 1887 1888 disable_clocks: 1889 clk_bulk_disable(i2c_dev->nclocks, i2c_dev->clocks); 1890 1891 return err; 1892 } 1893 1894 static int __maybe_unused tegra_i2c_runtime_suspend(struct device *dev) 1895 { 1896 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); 1897 1898 clk_bulk_disable(i2c_dev->nclocks, i2c_dev->clocks); 1899 1900 return pinctrl_pm_select_idle_state(dev); 1901 } 1902 1903 static int __maybe_unused tegra_i2c_suspend(struct device *dev) 1904 { 1905 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); 1906 int err; 1907 1908 i2c_mark_adapter_suspended(&i2c_dev->adapter); 1909 1910 if (!pm_runtime_status_suspended(dev)) { 1911 err = tegra_i2c_runtime_suspend(dev); 1912 if (err) 1913 return err; 1914 } 1915 1916 return 0; 1917 } 1918 1919 static int __maybe_unused tegra_i2c_resume(struct device *dev) 1920 { 1921 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); 1922 int err; 1923 1924 /* 1925 * We need to ensure that clocks are enabled so that registers can be 1926 * restored in tegra_i2c_init(). 1927 */ 1928 err = tegra_i2c_runtime_resume(dev); 1929 if (err) 1930 return err; 1931 1932 err = tegra_i2c_init(i2c_dev); 1933 if (err) 1934 return err; 1935 1936 /* 1937 * In case we are runtime suspended, disable clocks again so that we 1938 * don't unbalance the clock reference counts during the next runtime 1939 * resume transition. 1940 */ 1941 if (pm_runtime_status_suspended(dev)) { 1942 err = tegra_i2c_runtime_suspend(dev); 1943 if (err) 1944 return err; 1945 } 1946 1947 i2c_mark_adapter_resumed(&i2c_dev->adapter); 1948 1949 return 0; 1950 } 1951 1952 static const struct dev_pm_ops tegra_i2c_pm = { 1953 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_i2c_suspend, tegra_i2c_resume) 1954 SET_RUNTIME_PM_OPS(tegra_i2c_runtime_suspend, tegra_i2c_runtime_resume, 1955 NULL) 1956 }; 1957 1958 static const struct acpi_device_id tegra_i2c_acpi_match[] = { 1959 {.id = "NVDA0101", .driver_data = (kernel_ulong_t)&tegra210_i2c_hw}, 1960 {.id = "NVDA0201", .driver_data = (kernel_ulong_t)&tegra186_i2c_hw}, 1961 {.id = "NVDA0301", .driver_data = (kernel_ulong_t)&tegra194_i2c_hw}, 1962 { } 1963 }; 1964 MODULE_DEVICE_TABLE(acpi, tegra_i2c_acpi_match); 1965 1966 static struct platform_driver tegra_i2c_driver = { 1967 .probe = tegra_i2c_probe, 1968 .remove_new = tegra_i2c_remove, 1969 .driver = { 1970 .name = "tegra-i2c", 1971 .of_match_table = tegra_i2c_of_match, 1972 .acpi_match_table = tegra_i2c_acpi_match, 1973 .pm = &tegra_i2c_pm, 1974 }, 1975 }; 1976 module_platform_driver(tegra_i2c_driver); 1977 1978 MODULE_DESCRIPTION("NVIDIA Tegra I2C Bus Controller driver"); 1979 MODULE_AUTHOR("Colin Cross"); 1980 MODULE_LICENSE("GPL v2"); 1981