1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012 Invensense, Inc. 4 */ 5 6 #ifndef INV_MPU_IIO_H_ 7 #define INV_MPU_IIO_H_ 8 9 #include <linux/i2c.h> 10 #include <linux/i2c-mux.h> 11 #include <linux/mutex.h> 12 #include <linux/iio/iio.h> 13 #include <linux/iio/buffer.h> 14 #include <linux/regmap.h> 15 #include <linux/iio/sysfs.h> 16 #include <linux/iio/kfifo_buf.h> 17 #include <linux/iio/trigger.h> 18 #include <linux/iio/triggered_buffer.h> 19 #include <linux/iio/trigger_consumer.h> 20 #include <linux/platform_data/invensense_mpu6050.h> 21 22 /** 23 * struct inv_mpu6050_reg_map - Notable registers. 24 * @sample_rate_div: Divider applied to gyro output rate. 25 * @lpf: Configures internal low pass filter. 26 * @accel_lpf: Configures accelerometer low pass filter. 27 * @user_ctrl: Enables/resets the FIFO. 28 * @fifo_en: Determines which data will appear in FIFO. 29 * @gyro_config: gyro config register. 30 * @accl_config: accel config register 31 * @fifo_count_h: Upper byte of FIFO count. 32 * @fifo_r_w: FIFO register. 33 * @raw_gyro: Address of first gyro register. 34 * @raw_accl: Address of first accel register. 35 * @temperature: temperature register 36 * @int_enable: Interrupt enable register. 37 * @int_status: Interrupt status register. 38 * @pwr_mgmt_1: Controls chip's power state and clock source. 39 * @pwr_mgmt_2: Controls power state of individual sensors. 40 * @int_pin_cfg; Controls interrupt pin configuration. 41 * @accl_offset: Controls the accelerometer calibration offset. 42 * @gyro_offset: Controls the gyroscope calibration offset. 43 * @i2c_if: Controls the i2c interface 44 */ 45 struct inv_mpu6050_reg_map { 46 u8 sample_rate_div; 47 u8 lpf; 48 u8 accel_lpf; 49 u8 user_ctrl; 50 u8 fifo_en; 51 u8 gyro_config; 52 u8 accl_config; 53 u8 fifo_count_h; 54 u8 fifo_r_w; 55 u8 raw_gyro; 56 u8 raw_accl; 57 u8 temperature; 58 u8 int_enable; 59 u8 int_status; 60 u8 pwr_mgmt_1; 61 u8 pwr_mgmt_2; 62 u8 int_pin_cfg; 63 u8 accl_offset; 64 u8 gyro_offset; 65 u8 i2c_if; 66 }; 67 68 /*device enum */ 69 enum inv_devices { 70 INV_MPU6050, 71 INV_MPU6500, 72 INV_MPU6515, 73 INV_MPU6880, 74 INV_MPU6000, 75 INV_MPU9150, 76 INV_MPU9250, 77 INV_MPU9255, 78 INV_ICM20608, 79 INV_ICM20608D, 80 INV_ICM20609, 81 INV_ICM20689, 82 INV_ICM20600, 83 INV_ICM20602, 84 INV_ICM20690, 85 INV_IAM20680, 86 INV_NUM_PARTS 87 }; 88 89 /* chip sensors mask: accelerometer, gyroscope, temperature, magnetometer */ 90 #define INV_MPU6050_SENSOR_ACCL BIT(0) 91 #define INV_MPU6050_SENSOR_GYRO BIT(1) 92 #define INV_MPU6050_SENSOR_TEMP BIT(2) 93 #define INV_MPU6050_SENSOR_MAGN BIT(3) 94 95 /** 96 * struct inv_mpu6050_chip_config - Cached chip configuration data. 97 * @clk: selected chip clock 98 * @fsr: Full scale range. 99 * @lpf: Digital low pass filter frequency. 100 * @accl_fs: accel full scale range. 101 * @accl_en: accel engine enabled 102 * @gyro_en: gyro engine enabled 103 * @temp_en: temperature sensor enabled 104 * @magn_en: magn engine (i2c master) enabled 105 * @accl_fifo_enable: enable accel data output 106 * @gyro_fifo_enable: enable gyro data output 107 * @temp_fifo_enable: enable temp data output 108 * @magn_fifo_enable: enable magn data output 109 * @divider: chip sample rate divider (sample rate divider - 1) 110 */ 111 struct inv_mpu6050_chip_config { 112 unsigned int clk:3; 113 unsigned int fsr:2; 114 unsigned int lpf:3; 115 unsigned int accl_fs:2; 116 unsigned int accl_en:1; 117 unsigned int gyro_en:1; 118 unsigned int temp_en:1; 119 unsigned int magn_en:1; 120 unsigned int accl_fifo_enable:1; 121 unsigned int gyro_fifo_enable:1; 122 unsigned int temp_fifo_enable:1; 123 unsigned int magn_fifo_enable:1; 124 u8 divider; 125 u8 user_ctrl; 126 }; 127 128 /* 129 * Maximum of 6 + 6 + 2 + 7 (for MPU9x50) = 21 round up to 24 and plus 8. 130 * May be less if fewer channels are enabled, as long as the timestamp 131 * remains 8 byte aligned 132 */ 133 #define INV_MPU6050_OUTPUT_DATA_SIZE 32 134 135 /** 136 * struct inv_mpu6050_hw - Other important hardware information. 137 * @whoami: Self identification byte from WHO_AM_I register 138 * @name: name of the chip. 139 * @reg: register map of the chip. 140 * @config: configuration of the chip. 141 * @fifo_size: size of the FIFO in bytes. 142 * @temp: offset and scale to apply to raw temperature. 143 */ 144 struct inv_mpu6050_hw { 145 u8 whoami; 146 u8 *name; 147 const struct inv_mpu6050_reg_map *reg; 148 const struct inv_mpu6050_chip_config *config; 149 size_t fifo_size; 150 struct { 151 int offset; 152 int scale; 153 } temp; 154 struct { 155 unsigned int accel; 156 unsigned int gyro; 157 } startup_time; 158 }; 159 160 /* 161 * struct inv_mpu6050_state - Driver state variables. 162 * @lock: Chip access lock. 163 * @trig: IIO trigger. 164 * @chip_config: Cached attribute information. 165 * @reg: Map of important registers. 166 * @hw: Other hardware-specific information. 167 * @chip_type: chip type. 168 * @plat_data: platform data (deprecated in favor of @orientation). 169 * @orientation: sensor chip orientation relative to main hardware. 170 * @map regmap pointer. 171 * @irq interrupt number. 172 * @irq_mask the int_pin_cfg mask to configure interrupt type. 173 * @chip_period: chip internal period estimation (~1kHz). 174 * @it_timestamp: timestamp from previous interrupt. 175 * @data_timestamp: timestamp for next data sample. 176 * @vdd_supply: VDD voltage regulator for the chip. 177 * @vddio_supply I/O voltage regulator for the chip. 178 * @magn_disabled: magnetometer disabled for backward compatibility reason. 179 * @magn_raw_to_gauss: coefficient to convert mag raw value to Gauss. 180 * @magn_orient: magnetometer sensor chip orientation if available. 181 * @suspended_sensors: sensors mask of sensors turned off for suspend 182 * @data: dma safe buffer used for bulk reads. 183 */ 184 struct inv_mpu6050_state { 185 struct mutex lock; 186 struct iio_trigger *trig; 187 struct inv_mpu6050_chip_config chip_config; 188 const struct inv_mpu6050_reg_map *reg; 189 const struct inv_mpu6050_hw *hw; 190 enum inv_devices chip_type; 191 struct i2c_mux_core *muxc; 192 struct i2c_client *mux_client; 193 struct inv_mpu6050_platform_data plat_data; 194 struct iio_mount_matrix orientation; 195 struct regmap *map; 196 int irq; 197 u8 irq_mask; 198 unsigned skip_samples; 199 s64 chip_period; 200 s64 it_timestamp; 201 s64 data_timestamp; 202 struct regulator *vdd_supply; 203 struct regulator *vddio_supply; 204 bool magn_disabled; 205 s32 magn_raw_to_gauss[3]; 206 struct iio_mount_matrix magn_orient; 207 unsigned int suspended_sensors; 208 u8 data[INV_MPU6050_OUTPUT_DATA_SIZE] __aligned(IIO_DMA_MINALIGN); 209 }; 210 211 /*register and associated bit definition*/ 212 #define INV_MPU6050_REG_ACCEL_OFFSET 0x06 213 #define INV_MPU6050_REG_GYRO_OFFSET 0x13 214 215 #define INV_MPU6050_REG_SAMPLE_RATE_DIV 0x19 216 #define INV_MPU6050_REG_CONFIG 0x1A 217 #define INV_MPU6050_REG_GYRO_CONFIG 0x1B 218 #define INV_MPU6050_REG_ACCEL_CONFIG 0x1C 219 220 #define INV_MPU6050_REG_FIFO_EN 0x23 221 #define INV_MPU6050_BIT_SLAVE_0 0x01 222 #define INV_MPU6050_BIT_SLAVE_1 0x02 223 #define INV_MPU6050_BIT_SLAVE_2 0x04 224 #define INV_MPU6050_BIT_ACCEL_OUT 0x08 225 #define INV_MPU6050_BITS_GYRO_OUT 0x70 226 #define INV_MPU6050_BIT_TEMP_OUT 0x80 227 228 #define INV_MPU6050_REG_I2C_MST_CTRL 0x24 229 #define INV_MPU6050_BITS_I2C_MST_CLK_400KHZ 0x0D 230 #define INV_MPU6050_BIT_I2C_MST_P_NSR 0x10 231 #define INV_MPU6050_BIT_SLV3_FIFO_EN 0x20 232 #define INV_MPU6050_BIT_WAIT_FOR_ES 0x40 233 #define INV_MPU6050_BIT_MULT_MST_EN 0x80 234 235 /* control I2C slaves from 0 to 3 */ 236 #define INV_MPU6050_REG_I2C_SLV_ADDR(_x) (0x25 + 3 * (_x)) 237 #define INV_MPU6050_BIT_I2C_SLV_RNW 0x80 238 239 #define INV_MPU6050_REG_I2C_SLV_REG(_x) (0x26 + 3 * (_x)) 240 241 #define INV_MPU6050_REG_I2C_SLV_CTRL(_x) (0x27 + 3 * (_x)) 242 #define INV_MPU6050_BIT_SLV_GRP 0x10 243 #define INV_MPU6050_BIT_SLV_REG_DIS 0x20 244 #define INV_MPU6050_BIT_SLV_BYTE_SW 0x40 245 #define INV_MPU6050_BIT_SLV_EN 0x80 246 247 /* I2C master delay register */ 248 #define INV_MPU6050_REG_I2C_SLV4_CTRL 0x34 249 #define INV_MPU6050_BITS_I2C_MST_DLY(_x) ((_x) & 0x1F) 250 251 #define INV_MPU6050_REG_I2C_MST_STATUS 0x36 252 #define INV_MPU6050_BIT_I2C_SLV0_NACK 0x01 253 #define INV_MPU6050_BIT_I2C_SLV1_NACK 0x02 254 #define INV_MPU6050_BIT_I2C_SLV2_NACK 0x04 255 #define INV_MPU6050_BIT_I2C_SLV3_NACK 0x08 256 257 #define INV_MPU6050_REG_INT_ENABLE 0x38 258 #define INV_MPU6050_BIT_DATA_RDY_EN 0x01 259 #define INV_MPU6050_BIT_DMP_INT_EN 0x02 260 261 #define INV_MPU6050_REG_RAW_ACCEL 0x3B 262 #define INV_MPU6050_REG_TEMPERATURE 0x41 263 #define INV_MPU6050_REG_RAW_GYRO 0x43 264 265 #define INV_MPU6050_REG_INT_STATUS 0x3A 266 #define INV_MPU6050_BIT_FIFO_OVERFLOW_INT 0x10 267 #define INV_MPU6050_BIT_RAW_DATA_RDY_INT 0x01 268 269 #define INV_MPU6050_REG_EXT_SENS_DATA 0x49 270 271 /* I2C slaves data output from 0 to 3 */ 272 #define INV_MPU6050_REG_I2C_SLV_DO(_x) (0x63 + (_x)) 273 274 #define INV_MPU6050_REG_I2C_MST_DELAY_CTRL 0x67 275 #define INV_MPU6050_BIT_I2C_SLV0_DLY_EN 0x01 276 #define INV_MPU6050_BIT_I2C_SLV1_DLY_EN 0x02 277 #define INV_MPU6050_BIT_I2C_SLV2_DLY_EN 0x04 278 #define INV_MPU6050_BIT_I2C_SLV3_DLY_EN 0x08 279 #define INV_MPU6050_BIT_DELAY_ES_SHADOW 0x80 280 281 #define INV_MPU6050_REG_SIGNAL_PATH_RESET 0x68 282 #define INV_MPU6050_BIT_TEMP_RST BIT(0) 283 #define INV_MPU6050_BIT_ACCEL_RST BIT(1) 284 #define INV_MPU6050_BIT_GYRO_RST BIT(2) 285 286 #define INV_MPU6050_REG_USER_CTRL 0x6A 287 #define INV_MPU6050_BIT_SIG_COND_RST 0x01 288 #define INV_MPU6050_BIT_FIFO_RST 0x04 289 #define INV_MPU6050_BIT_DMP_RST 0x08 290 #define INV_MPU6050_BIT_I2C_MST_EN 0x20 291 #define INV_MPU6050_BIT_FIFO_EN 0x40 292 #define INV_MPU6050_BIT_DMP_EN 0x80 293 #define INV_MPU6050_BIT_I2C_IF_DIS 0x10 294 295 #define INV_MPU6050_REG_PWR_MGMT_1 0x6B 296 #define INV_MPU6050_BIT_H_RESET 0x80 297 #define INV_MPU6050_BIT_SLEEP 0x40 298 #define INV_MPU6050_BIT_TEMP_DIS 0x08 299 #define INV_MPU6050_BIT_CLK_MASK 0x7 300 301 #define INV_MPU6050_REG_PWR_MGMT_2 0x6C 302 #define INV_MPU6050_BIT_PWR_ACCL_STBY 0x38 303 #define INV_MPU6050_BIT_PWR_GYRO_STBY 0x07 304 305 /* ICM20602 register */ 306 #define INV_ICM20602_REG_I2C_IF 0x70 307 #define INV_ICM20602_BIT_I2C_IF_DIS 0x40 308 309 #define INV_MPU6050_REG_FIFO_COUNT_H 0x72 310 #define INV_MPU6050_REG_FIFO_R_W 0x74 311 312 #define INV_MPU6050_BYTES_PER_3AXIS_SENSOR 6 313 #define INV_MPU6050_FIFO_COUNT_BYTE 2 314 315 /* MPU9X50 9-axis magnetometer */ 316 #define INV_MPU9X50_BYTES_MAGN 7 317 318 /* FIFO temperature sample size */ 319 #define INV_MPU6050_BYTES_PER_TEMP_SENSOR 2 320 321 /* mpu6500 registers */ 322 #define INV_MPU6500_REG_ACCEL_CONFIG_2 0x1D 323 #define INV_ICM20689_BITS_FIFO_SIZE_MAX 0xC0 324 #define INV_MPU6500_REG_ACCEL_OFFSET 0x77 325 326 /* delay time in milliseconds */ 327 #define INV_MPU6050_POWER_UP_TIME 100 328 #define INV_MPU6050_TEMP_UP_TIME 100 329 #define INV_MPU6050_ACCEL_STARTUP_TIME 20 330 #define INV_MPU6050_GYRO_STARTUP_TIME 60 331 #define INV_MPU6050_GYRO_DOWN_TIME 150 332 #define INV_MPU6050_SUSPEND_DELAY_MS 2000 333 334 #define INV_MPU6500_GYRO_STARTUP_TIME 70 335 #define INV_MPU6500_ACCEL_STARTUP_TIME 30 336 337 #define INV_ICM20602_GYRO_STARTUP_TIME 100 338 #define INV_ICM20602_ACCEL_STARTUP_TIME 20 339 340 #define INV_ICM20690_GYRO_STARTUP_TIME 80 341 #define INV_ICM20690_ACCEL_STARTUP_TIME 10 342 343 344 /* delay time in microseconds */ 345 #define INV_MPU6050_REG_UP_TIME_MIN 5000 346 #define INV_MPU6050_REG_UP_TIME_MAX 10000 347 348 #define INV_MPU6050_TEMP_OFFSET 12420 349 #define INV_MPU6050_TEMP_SCALE 2941176 350 #define INV_MPU6050_MAX_GYRO_FS_PARAM 3 351 #define INV_MPU6050_MAX_ACCL_FS_PARAM 3 352 #define INV_MPU6050_THREE_AXIS 3 353 #define INV_MPU6050_GYRO_CONFIG_FSR_SHIFT 3 354 #define INV_ICM20690_GYRO_CONFIG_FSR_SHIFT 2 355 #define INV_MPU6050_ACCL_CONFIG_FSR_SHIFT 3 356 357 #define INV_MPU6500_TEMP_OFFSET 7011 358 #define INV_MPU6500_TEMP_SCALE 2995178 359 360 #define INV_ICM20608_TEMP_OFFSET 8170 361 #define INV_ICM20608_TEMP_SCALE 3059976 362 363 #define INV_MPU6050_REG_INT_PIN_CFG 0x37 364 #define INV_MPU6050_ACTIVE_HIGH 0x00 365 #define INV_MPU6050_ACTIVE_LOW 0x80 366 /* enable level triggering */ 367 #define INV_MPU6050_LATCH_INT_EN 0x20 368 #define INV_MPU6050_BIT_BYPASS_EN 0x2 369 370 /* Allowed timestamp period jitter in percent */ 371 #define INV_MPU6050_TS_PERIOD_JITTER 4 372 373 /* init parameters */ 374 #define INV_MPU6050_MAX_FIFO_RATE 1000 375 #define INV_MPU6050_MIN_FIFO_RATE 4 376 377 /* chip internal frequency: 1KHz */ 378 #define INV_MPU6050_INTERNAL_FREQ_HZ 1000 379 /* return the frequency divider (chip sample rate divider + 1) */ 380 #define INV_MPU6050_FREQ_DIVIDER(st) \ 381 ((st)->chip_config.divider + 1) 382 /* chip sample rate divider to fifo rate */ 383 #define INV_MPU6050_FIFO_RATE_TO_DIVIDER(fifo_rate) \ 384 ((INV_MPU6050_INTERNAL_FREQ_HZ / (fifo_rate)) - 1) 385 #define INV_MPU6050_DIVIDER_TO_FIFO_RATE(divider) \ 386 (INV_MPU6050_INTERNAL_FREQ_HZ / ((divider) + 1)) 387 388 #define INV_MPU6050_REG_WHOAMI 117 389 390 #define INV_MPU6000_WHOAMI_VALUE 0x68 391 #define INV_MPU6050_WHOAMI_VALUE 0x68 392 #define INV_MPU6500_WHOAMI_VALUE 0x70 393 #define INV_MPU6880_WHOAMI_VALUE 0x78 394 #define INV_MPU9150_WHOAMI_VALUE 0x68 395 #define INV_MPU9250_WHOAMI_VALUE 0x71 396 #define INV_MPU9255_WHOAMI_VALUE 0x73 397 #define INV_MPU6515_WHOAMI_VALUE 0x74 398 #define INV_ICM20608_WHOAMI_VALUE 0xAF 399 #define INV_ICM20608D_WHOAMI_VALUE 0xAE 400 #define INV_ICM20609_WHOAMI_VALUE 0xA6 401 #define INV_ICM20689_WHOAMI_VALUE 0x98 402 #define INV_ICM20600_WHOAMI_VALUE 0x11 403 #define INV_ICM20602_WHOAMI_VALUE 0x12 404 #define INV_ICM20690_WHOAMI_VALUE 0x20 405 #define INV_IAM20680_WHOAMI_VALUE 0xA9 406 407 /* scan element definition for generic MPU6xxx devices */ 408 enum inv_mpu6050_scan { 409 INV_MPU6050_SCAN_ACCL_X, 410 INV_MPU6050_SCAN_ACCL_Y, 411 INV_MPU6050_SCAN_ACCL_Z, 412 INV_MPU6050_SCAN_TEMP, 413 INV_MPU6050_SCAN_GYRO_X, 414 INV_MPU6050_SCAN_GYRO_Y, 415 INV_MPU6050_SCAN_GYRO_Z, 416 INV_MPU6050_SCAN_TIMESTAMP, 417 418 INV_MPU9X50_SCAN_MAGN_X = INV_MPU6050_SCAN_GYRO_Z + 1, 419 INV_MPU9X50_SCAN_MAGN_Y, 420 INV_MPU9X50_SCAN_MAGN_Z, 421 INV_MPU9X50_SCAN_TIMESTAMP, 422 }; 423 424 enum inv_mpu6050_filter_e { 425 INV_MPU6050_FILTER_NOLPF2 = 0, 426 INV_MPU6050_FILTER_200HZ, 427 INV_MPU6050_FILTER_100HZ, 428 INV_MPU6050_FILTER_45HZ, 429 INV_MPU6050_FILTER_20HZ, 430 INV_MPU6050_FILTER_10HZ, 431 INV_MPU6050_FILTER_5HZ, 432 INV_MPU6050_FILTER_NOLPF, 433 NUM_MPU6050_FILTER 434 }; 435 436 /* IIO attribute address */ 437 enum INV_MPU6050_IIO_ATTR_ADDR { 438 ATTR_GYRO_MATRIX, 439 ATTR_ACCL_MATRIX, 440 }; 441 442 enum inv_mpu6050_accl_fs_e { 443 INV_MPU6050_FS_02G = 0, 444 INV_MPU6050_FS_04G, 445 INV_MPU6050_FS_08G, 446 INV_MPU6050_FS_16G, 447 NUM_ACCL_FSR 448 }; 449 450 enum inv_mpu6050_fsr_e { 451 INV_MPU6050_FSR_250DPS = 0, 452 INV_MPU6050_FSR_500DPS, 453 INV_MPU6050_FSR_1000DPS, 454 INV_MPU6050_FSR_2000DPS, 455 NUM_MPU6050_FSR 456 }; 457 458 enum inv_mpu6050_clock_sel_e { 459 INV_CLK_INTERNAL = 0, 460 INV_CLK_PLL, 461 NUM_CLK 462 }; 463 464 irqreturn_t inv_mpu6050_read_fifo(int irq, void *p); 465 int inv_mpu6050_probe_trigger(struct iio_dev *indio_dev, int irq_type); 466 int inv_mpu6050_prepare_fifo(struct inv_mpu6050_state *st, bool enable); 467 int inv_mpu6050_switch_engine(struct inv_mpu6050_state *st, bool en, 468 unsigned int mask); 469 int inv_mpu6050_write_reg(struct inv_mpu6050_state *st, int reg, u8 val); 470 int inv_mpu_acpi_create_mux_client(struct i2c_client *client); 471 void inv_mpu_acpi_delete_mux_client(struct i2c_client *client); 472 int inv_mpu_core_probe(struct regmap *regmap, int irq, const char *name, 473 int (*inv_mpu_bus_setup)(struct iio_dev *), int chip_type); 474 extern const struct dev_pm_ops inv_mpu_pmops; 475 476 #endif 477