1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J784S4 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_main { 9 msmc_ram: sram@70000000 { 10 compatible = "mmio-sram"; 11 reg = <0x00 0x70000000 0x00 0x800000>; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 ranges = <0x00 0x00 0x70000000 0x800000>; 15 16 atf-sram@0 { 17 reg = <0x00 0x20000>; 18 }; 19 20 tifs-sram@1f0000 { 21 reg = <0x1f0000 0x10000>; 22 }; 23 24 l3cache-sram@200000 { 25 reg = <0x200000 0x200000>; 26 }; 27 }; 28 29 gic500: interrupt-controller@1800000 { 30 compatible = "arm,gic-v3"; 31 #address-cells = <2>; 32 #size-cells = <2>; 33 ranges; 34 #interrupt-cells = <3>; 35 interrupt-controller; 36 reg = <0x00 0x01800000 0x00 0x200000>, /* GICD */ 37 <0x00 0x01900000 0x00 0x100000>, /* GICR */ 38 <0x00 0x6f000000 0x00 0x2000>, /* GICC */ 39 <0x00 0x6f010000 0x00 0x1000>, /* GICH */ 40 <0x00 0x6f020000 0x00 0x2000>; /* GICV */ 41 42 /* vcpumntirq: virtual CPU interface maintenance interrupt */ 43 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 44 45 gic_its: msi-controller@1820000 { 46 compatible = "arm,gic-v3-its"; 47 reg = <0x00 0x01820000 0x00 0x10000>; 48 socionext,synquacer-pre-its = <0x1000000 0x400000>; 49 msi-controller; 50 #msi-cells = <1>; 51 }; 52 }; 53 54 main_gpio_intr: interrupt-controller@a00000 { 55 compatible = "ti,sci-intr"; 56 reg = <0x00 0x00a00000 0x00 0x800>; 57 ti,intr-trigger-type = <1>; 58 interrupt-controller; 59 interrupt-parent = <&gic500>; 60 #interrupt-cells = <1>; 61 ti,sci = <&sms>; 62 ti,sci-dev-id = <10>; 63 ti,interrupt-ranges = <8 360 56>; 64 }; 65 66 main_pmx0: pinctrl@11c000 { 67 compatible = "pinctrl-single"; 68 /* Proxy 0 addressing */ 69 reg = <0x00 0x11c000 0x00 0x120>; 70 #pinctrl-cells = <1>; 71 pinctrl-single,register-width = <32>; 72 pinctrl-single,function-mask = <0xffffffff>; 73 }; 74 75 /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ 76 main_timerio_input: pinctrl@104200 { 77 compatible = "pinctrl-single"; 78 reg = <0x00 0x104200 0x00 0x50>; 79 #pinctrl-cells = <1>; 80 pinctrl-single,register-width = <32>; 81 pinctrl-single,function-mask = <0x00000007>; 82 }; 83 84 /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ 85 main_timerio_output: pinctrl@104280 { 86 compatible = "pinctrl-single"; 87 reg = <0x00 0x104280 0x00 0x20>; 88 #pinctrl-cells = <1>; 89 pinctrl-single,register-width = <32>; 90 pinctrl-single,function-mask = <0x0000001f>; 91 }; 92 93 main_crypto: crypto@4e00000 { 94 compatible = "ti,j721e-sa2ul"; 95 reg = <0x00 0x4e00000 0x00 0x1200>; 96 power-domains = <&k3_pds 369 TI_SCI_PD_EXCLUSIVE>; 97 #address-cells = <2>; 98 #size-cells = <2>; 99 ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>; 100 101 dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>, 102 <&main_udmap 0x4a41>; 103 dma-names = "tx", "rx1", "rx2"; 104 105 rng: rng@4e10000 { 106 compatible = "inside-secure,safexcel-eip76"; 107 reg = <0x00 0x4e10000 0x00 0x7d>; 108 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 109 }; 110 }; 111 112 main_timer0: timer@2400000 { 113 compatible = "ti,am654-timer"; 114 reg = <0x00 0x2400000 0x00 0x400>; 115 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 116 clocks = <&k3_clks 97 2>; 117 clock-names = "fck"; 118 assigned-clocks = <&k3_clks 97 2>; 119 assigned-clock-parents = <&k3_clks 97 3>; 120 power-domains = <&k3_pds 97 TI_SCI_PD_EXCLUSIVE>; 121 ti,timer-pwm; 122 }; 123 124 main_timer1: timer@2410000 { 125 compatible = "ti,am654-timer"; 126 reg = <0x00 0x2410000 0x00 0x400>; 127 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 128 clocks = <&k3_clks 98 2>; 129 clock-names = "fck"; 130 assigned-clocks = <&k3_clks 98 2>; 131 assigned-clock-parents = <&k3_clks 98 3>; 132 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; 133 ti,timer-pwm; 134 }; 135 136 main_timer2: timer@2420000 { 137 compatible = "ti,am654-timer"; 138 reg = <0x00 0x2420000 0x00 0x400>; 139 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 140 clocks = <&k3_clks 99 2>; 141 clock-names = "fck"; 142 assigned-clocks = <&k3_clks 99 2>; 143 assigned-clock-parents = <&k3_clks 99 3>; 144 power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>; 145 ti,timer-pwm; 146 }; 147 148 main_timer3: timer@2430000 { 149 compatible = "ti,am654-timer"; 150 reg = <0x00 0x2430000 0x00 0x400>; 151 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 152 clocks = <&k3_clks 100 2>; 153 clock-names = "fck"; 154 assigned-clocks = <&k3_clks 100 2>; 155 assigned-clock-parents = <&k3_clks 100 3>; 156 power-domains = <&k3_pds 100 TI_SCI_PD_EXCLUSIVE>; 157 ti,timer-pwm; 158 }; 159 160 main_timer4: timer@2440000 { 161 compatible = "ti,am654-timer"; 162 reg = <0x00 0x2440000 0x00 0x400>; 163 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 164 clocks = <&k3_clks 101 2>; 165 clock-names = "fck"; 166 assigned-clocks = <&k3_clks 101 2>; 167 assigned-clock-parents = <&k3_clks 101 3>; 168 power-domains = <&k3_pds 101 TI_SCI_PD_EXCLUSIVE>; 169 ti,timer-pwm; 170 }; 171 172 main_timer5: timer@2450000 { 173 compatible = "ti,am654-timer"; 174 reg = <0x00 0x2450000 0x00 0x400>; 175 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 176 clocks = <&k3_clks 102 2>; 177 clock-names = "fck"; 178 assigned-clocks = <&k3_clks 102 2>; 179 assigned-clock-parents = <&k3_clks 102 3>; 180 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 181 ti,timer-pwm; 182 }; 183 184 main_timer6: timer@2460000 { 185 compatible = "ti,am654-timer"; 186 reg = <0x00 0x2460000 0x00 0x400>; 187 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 188 clocks = <&k3_clks 103 2>; 189 clock-names = "fck"; 190 assigned-clocks = <&k3_clks 103 2>; 191 assigned-clock-parents = <&k3_clks 103 3>; 192 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 193 ti,timer-pwm; 194 }; 195 196 main_timer7: timer@2470000 { 197 compatible = "ti,am654-timer"; 198 reg = <0x00 0x2470000 0x00 0x400>; 199 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 200 clocks = <&k3_clks 104 2>; 201 clock-names = "fck"; 202 assigned-clocks = <&k3_clks 104 2>; 203 assigned-clock-parents = <&k3_clks 104 3>; 204 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 205 ti,timer-pwm; 206 }; 207 208 main_timer8: timer@2480000 { 209 compatible = "ti,am654-timer"; 210 reg = <0x00 0x2480000 0x00 0x400>; 211 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 212 clocks = <&k3_clks 105 2>; 213 clock-names = "fck"; 214 assigned-clocks = <&k3_clks 105 2>; 215 assigned-clock-parents = <&k3_clks 105 3>; 216 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 217 ti,timer-pwm; 218 }; 219 220 main_timer9: timer@2490000 { 221 compatible = "ti,am654-timer"; 222 reg = <0x00 0x2490000 0x00 0x400>; 223 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 224 clocks = <&k3_clks 106 2>; 225 clock-names = "fck"; 226 assigned-clocks = <&k3_clks 106 2>; 227 assigned-clock-parents = <&k3_clks 106 3>; 228 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; 229 ti,timer-pwm; 230 }; 231 232 main_timer10: timer@24a0000 { 233 compatible = "ti,am654-timer"; 234 reg = <0x00 0x24a0000 0x00 0x400>; 235 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 236 clocks = <&k3_clks 107 2>; 237 clock-names = "fck"; 238 assigned-clocks = <&k3_clks 107 2>; 239 assigned-clock-parents = <&k3_clks 107 3>; 240 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; 241 ti,timer-pwm; 242 }; 243 244 main_timer11: timer@24b0000 { 245 compatible = "ti,am654-timer"; 246 reg = <0x00 0x24b0000 0x00 0x400>; 247 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 248 clocks = <&k3_clks 108 2>; 249 clock-names = "fck"; 250 assigned-clocks = <&k3_clks 108 2>; 251 assigned-clock-parents = <&k3_clks 108 3>; 252 power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>; 253 ti,timer-pwm; 254 }; 255 256 main_timer12: timer@24c0000 { 257 compatible = "ti,am654-timer"; 258 reg = <0x00 0x24c0000 0x00 0x400>; 259 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 260 clocks = <&k3_clks 109 2>; 261 clock-names = "fck"; 262 assigned-clocks = <&k3_clks 109 2>; 263 assigned-clock-parents = <&k3_clks 109 3>; 264 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; 265 ti,timer-pwm; 266 }; 267 268 main_timer13: timer@24d0000 { 269 compatible = "ti,am654-timer"; 270 reg = <0x00 0x24d0000 0x00 0x400>; 271 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 272 clocks = <&k3_clks 110 2>; 273 clock-names = "fck"; 274 assigned-clocks = <&k3_clks 110 2>; 275 assigned-clock-parents = <&k3_clks 110 3>; 276 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; 277 ti,timer-pwm; 278 }; 279 280 main_timer14: timer@24e0000 { 281 compatible = "ti,am654-timer"; 282 reg = <0x00 0x24e0000 0x00 0x400>; 283 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 284 clocks = <&k3_clks 111 2>; 285 clock-names = "fck"; 286 assigned-clocks = <&k3_clks 111 2>; 287 assigned-clock-parents = <&k3_clks 111 3>; 288 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 289 ti,timer-pwm; 290 }; 291 292 main_timer15: timer@24f0000 { 293 compatible = "ti,am654-timer"; 294 reg = <0x00 0x24f0000 0x00 0x400>; 295 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 296 clocks = <&k3_clks 112 2>; 297 clock-names = "fck"; 298 assigned-clocks = <&k3_clks 112 2>; 299 assigned-clock-parents = <&k3_clks 112 3>; 300 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; 301 ti,timer-pwm; 302 }; 303 304 main_timer16: timer@2500000 { 305 compatible = "ti,am654-timer"; 306 reg = <0x00 0x2500000 0x00 0x400>; 307 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 308 clocks = <&k3_clks 113 2>; 309 clock-names = "fck"; 310 assigned-clocks = <&k3_clks 113 2>; 311 assigned-clock-parents = <&k3_clks 113 3>; 312 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; 313 ti,timer-pwm; 314 }; 315 316 main_timer17: timer@2510000 { 317 compatible = "ti,am654-timer"; 318 reg = <0x00 0x2510000 0x00 0x400>; 319 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 320 clocks = <&k3_clks 114 2>; 321 clock-names = "fck"; 322 assigned-clocks = <&k3_clks 114 2>; 323 assigned-clock-parents = <&k3_clks 114 3>; 324 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 325 ti,timer-pwm; 326 }; 327 328 main_timer18: timer@2520000 { 329 compatible = "ti,am654-timer"; 330 reg = <0x00 0x2520000 0x00 0x400>; 331 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 332 clocks = <&k3_clks 115 2>; 333 clock-names = "fck"; 334 assigned-clocks = <&k3_clks 115 2>; 335 assigned-clock-parents = <&k3_clks 115 3>; 336 power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>; 337 ti,timer-pwm; 338 }; 339 340 main_timer19: timer@2530000 { 341 compatible = "ti,am654-timer"; 342 reg = <0x00 0x2530000 0x00 0x400>; 343 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 344 clocks = <&k3_clks 116 2>; 345 clock-names = "fck"; 346 assigned-clocks = <&k3_clks 116 2>; 347 assigned-clock-parents = <&k3_clks 116 3>; 348 power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>; 349 ti,timer-pwm; 350 }; 351 352 main_uart0: serial@2800000 { 353 compatible = "ti,j721e-uart", "ti,am654-uart"; 354 reg = <0x00 0x02800000 0x00 0x200>; 355 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 356 current-speed = <115200>; 357 clocks = <&k3_clks 146 0>; 358 clock-names = "fclk"; 359 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 360 status = "disabled"; 361 }; 362 363 main_uart1: serial@2810000 { 364 compatible = "ti,j721e-uart", "ti,am654-uart"; 365 reg = <0x00 0x02810000 0x00 0x200>; 366 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 367 current-speed = <115200>; 368 clocks = <&k3_clks 388 0>; 369 clock-names = "fclk"; 370 power-domains = <&k3_pds 388 TI_SCI_PD_EXCLUSIVE>; 371 status = "disabled"; 372 }; 373 374 main_uart2: serial@2820000 { 375 compatible = "ti,j721e-uart", "ti,am654-uart"; 376 reg = <0x00 0x02820000 0x00 0x200>; 377 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 378 current-speed = <115200>; 379 clocks = <&k3_clks 389 0>; 380 clock-names = "fclk"; 381 power-domains = <&k3_pds 389 TI_SCI_PD_EXCLUSIVE>; 382 status = "disabled"; 383 }; 384 385 main_uart3: serial@2830000 { 386 compatible = "ti,j721e-uart", "ti,am654-uart"; 387 reg = <0x00 0x02830000 0x00 0x200>; 388 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 389 current-speed = <115200>; 390 clocks = <&k3_clks 390 0>; 391 clock-names = "fclk"; 392 power-domains = <&k3_pds 390 TI_SCI_PD_EXCLUSIVE>; 393 status = "disabled"; 394 }; 395 396 main_uart4: serial@2840000 { 397 compatible = "ti,j721e-uart", "ti,am654-uart"; 398 reg = <0x00 0x02840000 0x00 0x200>; 399 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 400 current-speed = <115200>; 401 clocks = <&k3_clks 391 0>; 402 clock-names = "fclk"; 403 power-domains = <&k3_pds 391 TI_SCI_PD_EXCLUSIVE>; 404 status = "disabled"; 405 }; 406 407 main_uart5: serial@2850000 { 408 compatible = "ti,j721e-uart", "ti,am654-uart"; 409 reg = <0x00 0x02850000 0x00 0x200>; 410 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 411 current-speed = <115200>; 412 clocks = <&k3_clks 392 0>; 413 clock-names = "fclk"; 414 power-domains = <&k3_pds 392 TI_SCI_PD_EXCLUSIVE>; 415 status = "disabled"; 416 }; 417 418 main_uart6: serial@2860000 { 419 compatible = "ti,j721e-uart", "ti,am654-uart"; 420 reg = <0x00 0x02860000 0x00 0x200>; 421 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 422 current-speed = <115200>; 423 clocks = <&k3_clks 393 0>; 424 clock-names = "fclk"; 425 power-domains = <&k3_pds 393 TI_SCI_PD_EXCLUSIVE>; 426 status = "disabled"; 427 }; 428 429 main_uart7: serial@2870000 { 430 compatible = "ti,j721e-uart", "ti,am654-uart"; 431 reg = <0x00 0x02870000 0x00 0x200>; 432 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 433 current-speed = <115200>; 434 clocks = <&k3_clks 394 0>; 435 clock-names = "fclk"; 436 power-domains = <&k3_pds 394 TI_SCI_PD_EXCLUSIVE>; 437 status = "disabled"; 438 }; 439 440 main_uart8: serial@2880000 { 441 compatible = "ti,j721e-uart", "ti,am654-uart"; 442 reg = <0x00 0x02880000 0x00 0x200>; 443 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 444 current-speed = <115200>; 445 clocks = <&k3_clks 395 0>; 446 clock-names = "fclk"; 447 power-domains = <&k3_pds 395 TI_SCI_PD_EXCLUSIVE>; 448 status = "disabled"; 449 }; 450 451 main_uart9: serial@2890000 { 452 compatible = "ti,j721e-uart", "ti,am654-uart"; 453 reg = <0x00 0x02890000 0x00 0x200>; 454 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 455 current-speed = <115200>; 456 clocks = <&k3_clks 396 0>; 457 clock-names = "fclk"; 458 power-domains = <&k3_pds 396 TI_SCI_PD_EXCLUSIVE>; 459 status = "disabled"; 460 }; 461 462 main_gpio0: gpio@600000 { 463 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 464 reg = <0x00 0x00600000 0x00 0x100>; 465 gpio-controller; 466 #gpio-cells = <2>; 467 interrupt-parent = <&main_gpio_intr>; 468 interrupts = <145>, <146>, <147>, <148>, <149>; 469 interrupt-controller; 470 #interrupt-cells = <2>; 471 ti,ngpio = <66>; 472 ti,davinci-gpio-unbanked = <0>; 473 power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>; 474 clocks = <&k3_clks 163 0>; 475 clock-names = "gpio"; 476 status = "disabled"; 477 }; 478 479 main_gpio2: gpio@610000 { 480 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 481 reg = <0x00 0x00610000 0x00 0x100>; 482 gpio-controller; 483 #gpio-cells = <2>; 484 interrupt-parent = <&main_gpio_intr>; 485 interrupts = <154>, <155>, <156>, <157>, <158>; 486 interrupt-controller; 487 #interrupt-cells = <2>; 488 ti,ngpio = <66>; 489 ti,davinci-gpio-unbanked = <0>; 490 power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>; 491 clocks = <&k3_clks 164 0>; 492 clock-names = "gpio"; 493 status = "disabled"; 494 }; 495 496 main_gpio4: gpio@620000 { 497 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 498 reg = <0x00 0x00620000 0x00 0x100>; 499 gpio-controller; 500 #gpio-cells = <2>; 501 interrupt-parent = <&main_gpio_intr>; 502 interrupts = <163>, <164>, <165>, <166>, <167>; 503 interrupt-controller; 504 #interrupt-cells = <2>; 505 ti,ngpio = <66>; 506 ti,davinci-gpio-unbanked = <0>; 507 power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>; 508 clocks = <&k3_clks 165 0>; 509 clock-names = "gpio"; 510 status = "disabled"; 511 }; 512 513 main_gpio6: gpio@630000 { 514 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 515 reg = <0x00 0x00630000 0x00 0x100>; 516 gpio-controller; 517 #gpio-cells = <2>; 518 interrupt-parent = <&main_gpio_intr>; 519 interrupts = <172>, <173>, <174>, <175>, <176>; 520 interrupt-controller; 521 #interrupt-cells = <2>; 522 ti,ngpio = <66>; 523 ti,davinci-gpio-unbanked = <0>; 524 power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>; 525 clocks = <&k3_clks 166 0>; 526 clock-names = "gpio"; 527 status = "disabled"; 528 }; 529 530 main_i2c0: i2c@2000000 { 531 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 532 reg = <0x00 0x02000000 0x00 0x100>; 533 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 534 #address-cells = <1>; 535 #size-cells = <0>; 536 clocks = <&k3_clks 270 2>; 537 clock-names = "fck"; 538 power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>; 539 status = "disabled"; 540 }; 541 542 main_i2c1: i2c@2010000 { 543 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 544 reg = <0x00 0x02010000 0x00 0x100>; 545 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 546 #address-cells = <1>; 547 #size-cells = <0>; 548 clocks = <&k3_clks 271 2>; 549 clock-names = "fck"; 550 power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>; 551 status = "disabled"; 552 }; 553 554 main_i2c2: i2c@2020000 { 555 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 556 reg = <0x00 0x02020000 0x00 0x100>; 557 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 558 #address-cells = <1>; 559 #size-cells = <0>; 560 clocks = <&k3_clks 272 2>; 561 clock-names = "fck"; 562 power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>; 563 status = "disabled"; 564 }; 565 566 main_i2c3: i2c@2030000 { 567 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 568 reg = <0x00 0x02030000 0x00 0x100>; 569 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 570 #address-cells = <1>; 571 #size-cells = <0>; 572 clocks = <&k3_clks 273 2>; 573 clock-names = "fck"; 574 power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>; 575 status = "disabled"; 576 }; 577 578 main_i2c4: i2c@2040000 { 579 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 580 reg = <0x00 0x02040000 0x00 0x100>; 581 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 582 #address-cells = <1>; 583 #size-cells = <0>; 584 clocks = <&k3_clks 274 2>; 585 clock-names = "fck"; 586 power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>; 587 status = "disabled"; 588 }; 589 590 main_i2c5: i2c@2050000 { 591 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 592 reg = <0x00 0x02050000 0x00 0x100>; 593 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 594 #address-cells = <1>; 595 #size-cells = <0>; 596 clocks = <&k3_clks 275 2>; 597 clock-names = "fck"; 598 power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>; 599 status = "disabled"; 600 }; 601 602 main_i2c6: i2c@2060000 { 603 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 604 reg = <0x00 0x02060000 0x00 0x100>; 605 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 606 #address-cells = <1>; 607 #size-cells = <0>; 608 clocks = <&k3_clks 276 2>; 609 clock-names = "fck"; 610 power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; 611 status = "disabled"; 612 }; 613 614 main_sdhci0: mmc@4f80000 { 615 compatible = "ti,j721e-sdhci-8bit"; 616 reg = <0x00 0x04f80000 0x00 0x1000>, 617 <0x00 0x04f88000 0x00 0x400>; 618 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 619 power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>; 620 clocks = <&k3_clks 140 1>, <&k3_clks 140 2>; 621 clock-names = "clk_ahb", "clk_xin"; 622 assigned-clocks = <&k3_clks 140 2>; 623 assigned-clock-parents = <&k3_clks 140 3>; 624 bus-width = <8>; 625 ti,otap-del-sel-legacy = <0x0>; 626 ti,otap-del-sel-mmc-hs = <0x0>; 627 ti,otap-del-sel-ddr52 = <0x6>; 628 ti,otap-del-sel-hs200 = <0x8>; 629 ti,otap-del-sel-hs400 = <0x5>; 630 ti,itap-del-sel-legacy = <0x10>; 631 ti,itap-del-sel-mmc-hs = <0xa>; 632 ti,strobe-sel = <0x77>; 633 ti,clkbuf-sel = <0x7>; 634 ti,trm-icp = <0x8>; 635 mmc-ddr-1_8v; 636 mmc-hs200-1_8v; 637 mmc-hs400-1_8v; 638 dma-coherent; 639 status = "disabled"; 640 }; 641 642 main_sdhci1: mmc@4fb0000 { 643 compatible = "ti,j721e-sdhci-4bit"; 644 reg = <0x00 0x04fb0000 0x00 0x1000>, 645 <0x00 0x04fb8000 0x00 0x400>; 646 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 647 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 648 clocks = <&k3_clks 141 3>, <&k3_clks 141 4>; 649 clock-names = "clk_ahb", "clk_xin"; 650 assigned-clocks = <&k3_clks 141 4>; 651 assigned-clock-parents = <&k3_clks 141 5>; 652 bus-width = <4>; 653 ti,otap-del-sel-legacy = <0x0>; 654 ti,otap-del-sel-sd-hs = <0x0>; 655 ti,otap-del-sel-sdr12 = <0xf>; 656 ti,otap-del-sel-sdr25 = <0xf>; 657 ti,otap-del-sel-sdr50 = <0xc>; 658 ti,otap-del-sel-sdr104 = <0x5>; 659 ti,otap-del-sel-ddr50 = <0xc>; 660 ti,itap-del-sel-legacy = <0x0>; 661 ti,itap-del-sel-sd-hs = <0x0>; 662 ti,itap-del-sel-sdr12 = <0x0>; 663 ti,itap-del-sel-sdr25 = <0x0>; 664 ti,clkbuf-sel = <0x7>; 665 ti,trm-icp = <0x8>; 666 dma-coherent; 667 sdhci-caps-mask = <0x00000003 0x00000000>; 668 no-1-8-v; 669 status = "disabled"; 670 }; 671 672 main_navss: bus@30000000 { 673 compatible = "simple-bus"; 674 #address-cells = <2>; 675 #size-cells = <2>; 676 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; 677 ti,sci-dev-id = <280>; 678 dma-coherent; 679 dma-ranges; 680 681 main_navss_intr: interrupt-controller@310e0000 { 682 compatible = "ti,sci-intr"; 683 reg = <0x00 0x310e0000 0x00 0x4000>; 684 ti,intr-trigger-type = <4>; 685 interrupt-controller; 686 interrupt-parent = <&gic500>; 687 #interrupt-cells = <1>; 688 ti,sci = <&sms>; 689 ti,sci-dev-id = <283>; 690 ti,interrupt-ranges = <0 64 64>, 691 <64 448 64>, 692 <128 672 64>; 693 }; 694 695 main_udmass_inta: msi-controller@33d00000 { 696 compatible = "ti,sci-inta"; 697 reg = <0x00 0x33d00000 0x00 0x100000>; 698 interrupt-controller; 699 #interrupt-cells = <0>; 700 interrupt-parent = <&main_navss_intr>; 701 msi-controller; 702 ti,sci = <&sms>; 703 ti,sci-dev-id = <321>; 704 ti,interrupt-ranges = <0 0 256>; 705 }; 706 707 secure_proxy_main: mailbox@32c00000 { 708 compatible = "ti,am654-secure-proxy"; 709 #mbox-cells = <1>; 710 reg-names = "target_data", "rt", "scfg"; 711 reg = <0x00 0x32c00000 0x00 0x100000>, 712 <0x00 0x32400000 0x00 0x100000>, 713 <0x00 0x32800000 0x00 0x100000>; 714 interrupt-names = "rx_011"; 715 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 716 }; 717 718 hwspinlock: hwlock@30e00000 { 719 compatible = "ti,am654-hwspinlock"; 720 reg = <0x00 0x30e00000 0x00 0x1000>; 721 #hwlock-cells = <1>; 722 }; 723 724 mailbox0_cluster0: mailbox@31f80000 { 725 compatible = "ti,am654-mailbox"; 726 reg = <0x00 0x31f80000 0x00 0x200>; 727 #mbox-cells = <1>; 728 ti,mbox-num-users = <4>; 729 ti,mbox-num-fifos = <16>; 730 interrupt-parent = <&main_navss_intr>; 731 status = "disabled"; 732 }; 733 734 mailbox0_cluster1: mailbox@31f81000 { 735 compatible = "ti,am654-mailbox"; 736 reg = <0x00 0x31f81000 0x00 0x200>; 737 #mbox-cells = <1>; 738 ti,mbox-num-users = <4>; 739 ti,mbox-num-fifos = <16>; 740 interrupt-parent = <&main_navss_intr>; 741 status = "disabled"; 742 }; 743 744 mailbox0_cluster2: mailbox@31f82000 { 745 compatible = "ti,am654-mailbox"; 746 reg = <0x00 0x31f82000 0x00 0x200>; 747 #mbox-cells = <1>; 748 ti,mbox-num-users = <4>; 749 ti,mbox-num-fifos = <16>; 750 interrupt-parent = <&main_navss_intr>; 751 status = "disabled"; 752 }; 753 754 mailbox0_cluster3: mailbox@31f83000 { 755 compatible = "ti,am654-mailbox"; 756 reg = <0x00 0x31f83000 0x00 0x200>; 757 #mbox-cells = <1>; 758 ti,mbox-num-users = <4>; 759 ti,mbox-num-fifos = <16>; 760 interrupt-parent = <&main_navss_intr>; 761 status = "disabled"; 762 }; 763 764 mailbox0_cluster4: mailbox@31f84000 { 765 compatible = "ti,am654-mailbox"; 766 reg = <0x00 0x31f84000 0x00 0x200>; 767 #mbox-cells = <1>; 768 ti,mbox-num-users = <4>; 769 ti,mbox-num-fifos = <16>; 770 interrupt-parent = <&main_navss_intr>; 771 status = "disabled"; 772 }; 773 774 mailbox0_cluster5: mailbox@31f85000 { 775 compatible = "ti,am654-mailbox"; 776 reg = <0x00 0x31f85000 0x00 0x200>; 777 #mbox-cells = <1>; 778 ti,mbox-num-users = <4>; 779 ti,mbox-num-fifos = <16>; 780 interrupt-parent = <&main_navss_intr>; 781 status = "disabled"; 782 }; 783 784 mailbox0_cluster6: mailbox@31f86000 { 785 compatible = "ti,am654-mailbox"; 786 reg = <0x00 0x31f86000 0x00 0x200>; 787 #mbox-cells = <1>; 788 ti,mbox-num-users = <4>; 789 ti,mbox-num-fifos = <16>; 790 interrupt-parent = <&main_navss_intr>; 791 status = "disabled"; 792 }; 793 794 mailbox0_cluster7: mailbox@31f87000 { 795 compatible = "ti,am654-mailbox"; 796 reg = <0x00 0x31f87000 0x00 0x200>; 797 #mbox-cells = <1>; 798 ti,mbox-num-users = <4>; 799 ti,mbox-num-fifos = <16>; 800 interrupt-parent = <&main_navss_intr>; 801 status = "disabled"; 802 }; 803 804 mailbox0_cluster8: mailbox@31f88000 { 805 compatible = "ti,am654-mailbox"; 806 reg = <0x00 0x31f88000 0x00 0x200>; 807 #mbox-cells = <1>; 808 ti,mbox-num-users = <4>; 809 ti,mbox-num-fifos = <16>; 810 interrupt-parent = <&main_navss_intr>; 811 status = "disabled"; 812 }; 813 814 mailbox0_cluster9: mailbox@31f89000 { 815 compatible = "ti,am654-mailbox"; 816 reg = <0x00 0x31f89000 0x00 0x200>; 817 #mbox-cells = <1>; 818 ti,mbox-num-users = <4>; 819 ti,mbox-num-fifos = <16>; 820 interrupt-parent = <&main_navss_intr>; 821 status = "disabled"; 822 }; 823 824 mailbox0_cluster10: mailbox@31f8a000 { 825 compatible = "ti,am654-mailbox"; 826 reg = <0x00 0x31f8a000 0x00 0x200>; 827 #mbox-cells = <1>; 828 ti,mbox-num-users = <4>; 829 ti,mbox-num-fifos = <16>; 830 interrupt-parent = <&main_navss_intr>; 831 status = "disabled"; 832 }; 833 834 mailbox0_cluster11: mailbox@31f8b000 { 835 compatible = "ti,am654-mailbox"; 836 reg = <0x00 0x31f8b000 0x00 0x200>; 837 #mbox-cells = <1>; 838 ti,mbox-num-users = <4>; 839 ti,mbox-num-fifos = <16>; 840 interrupt-parent = <&main_navss_intr>; 841 status = "disabled"; 842 }; 843 844 mailbox1_cluster0: mailbox@31f90000 { 845 compatible = "ti,am654-mailbox"; 846 reg = <0x00 0x31f90000 0x00 0x200>; 847 #mbox-cells = <1>; 848 ti,mbox-num-users = <4>; 849 ti,mbox-num-fifos = <16>; 850 interrupt-parent = <&main_navss_intr>; 851 status = "disabled"; 852 }; 853 854 mailbox1_cluster1: mailbox@31f91000 { 855 compatible = "ti,am654-mailbox"; 856 reg = <0x00 0x31f91000 0x00 0x200>; 857 #mbox-cells = <1>; 858 ti,mbox-num-users = <4>; 859 ti,mbox-num-fifos = <16>; 860 interrupt-parent = <&main_navss_intr>; 861 status = "disabled"; 862 }; 863 864 mailbox1_cluster2: mailbox@31f92000 { 865 compatible = "ti,am654-mailbox"; 866 reg = <0x00 0x31f92000 0x00 0x200>; 867 #mbox-cells = <1>; 868 ti,mbox-num-users = <4>; 869 ti,mbox-num-fifos = <16>; 870 interrupt-parent = <&main_navss_intr>; 871 status = "disabled"; 872 }; 873 874 mailbox1_cluster3: mailbox@31f93000 { 875 compatible = "ti,am654-mailbox"; 876 reg = <0x00 0x31f93000 0x00 0x200>; 877 #mbox-cells = <1>; 878 ti,mbox-num-users = <4>; 879 ti,mbox-num-fifos = <16>; 880 interrupt-parent = <&main_navss_intr>; 881 status = "disabled"; 882 }; 883 884 mailbox1_cluster4: mailbox@31f94000 { 885 compatible = "ti,am654-mailbox"; 886 reg = <0x00 0x31f94000 0x00 0x200>; 887 #mbox-cells = <1>; 888 ti,mbox-num-users = <4>; 889 ti,mbox-num-fifos = <16>; 890 interrupt-parent = <&main_navss_intr>; 891 status = "disabled"; 892 }; 893 894 mailbox1_cluster5: mailbox@31f95000 { 895 compatible = "ti,am654-mailbox"; 896 reg = <0x00 0x31f95000 0x00 0x200>; 897 #mbox-cells = <1>; 898 ti,mbox-num-users = <4>; 899 ti,mbox-num-fifos = <16>; 900 interrupt-parent = <&main_navss_intr>; 901 status = "disabled"; 902 }; 903 904 mailbox1_cluster6: mailbox@31f96000 { 905 compatible = "ti,am654-mailbox"; 906 reg = <0x00 0x31f96000 0x00 0x200>; 907 #mbox-cells = <1>; 908 ti,mbox-num-users = <4>; 909 ti,mbox-num-fifos = <16>; 910 interrupt-parent = <&main_navss_intr>; 911 status = "disabled"; 912 }; 913 914 mailbox1_cluster7: mailbox@31f97000 { 915 compatible = "ti,am654-mailbox"; 916 reg = <0x00 0x31f97000 0x00 0x200>; 917 #mbox-cells = <1>; 918 ti,mbox-num-users = <4>; 919 ti,mbox-num-fifos = <16>; 920 interrupt-parent = <&main_navss_intr>; 921 status = "disabled"; 922 }; 923 924 mailbox1_cluster8: mailbox@31f98000 { 925 compatible = "ti,am654-mailbox"; 926 reg = <0x00 0x31f98000 0x00 0x200>; 927 #mbox-cells = <1>; 928 ti,mbox-num-users = <4>; 929 ti,mbox-num-fifos = <16>; 930 interrupt-parent = <&main_navss_intr>; 931 status = "disabled"; 932 }; 933 934 mailbox1_cluster9: mailbox@31f99000 { 935 compatible = "ti,am654-mailbox"; 936 reg = <0x00 0x31f99000 0x00 0x200>; 937 #mbox-cells = <1>; 938 ti,mbox-num-users = <4>; 939 ti,mbox-num-fifos = <16>; 940 interrupt-parent = <&main_navss_intr>; 941 status = "disabled"; 942 }; 943 944 mailbox1_cluster10: mailbox@31f9a000 { 945 compatible = "ti,am654-mailbox"; 946 reg = <0x00 0x31f9a000 0x00 0x200>; 947 #mbox-cells = <1>; 948 ti,mbox-num-users = <4>; 949 ti,mbox-num-fifos = <16>; 950 interrupt-parent = <&main_navss_intr>; 951 status = "disabled"; 952 }; 953 954 mailbox1_cluster11: mailbox@31f9b000 { 955 compatible = "ti,am654-mailbox"; 956 reg = <0x00 0x31f9b000 0x00 0x200>; 957 #mbox-cells = <1>; 958 ti,mbox-num-users = <4>; 959 ti,mbox-num-fifos = <16>; 960 interrupt-parent = <&main_navss_intr>; 961 status = "disabled"; 962 }; 963 964 main_ringacc: ringacc@3c000000 { 965 compatible = "ti,am654-navss-ringacc"; 966 reg = <0x00 0x3c000000 0x00 0x400000>, 967 <0x00 0x38000000 0x00 0x400000>, 968 <0x00 0x31120000 0x00 0x100>, 969 <0x00 0x33000000 0x00 0x40000>; 970 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 971 ti,num-rings = <1024>; 972 ti,sci-rm-range-gp-rings = <0x1>; 973 ti,sci = <&sms>; 974 ti,sci-dev-id = <315>; 975 msi-parent = <&main_udmass_inta>; 976 }; 977 978 main_udmap: dma-controller@31150000 { 979 compatible = "ti,j721e-navss-main-udmap"; 980 reg = <0x00 0x31150000 0x00 0x100>, 981 <0x00 0x34000000 0x00 0x80000>, 982 <0x00 0x35000000 0x00 0x200000>; 983 reg-names = "gcfg", "rchanrt", "tchanrt"; 984 msi-parent = <&main_udmass_inta>; 985 #dma-cells = <1>; 986 987 ti,sci = <&sms>; 988 ti,sci-dev-id = <319>; 989 ti,ringacc = <&main_ringacc>; 990 991 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 992 <0x0f>, /* TX_HCHAN */ 993 <0x10>; /* TX_UHCHAN */ 994 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 995 <0x0b>, /* RX_HCHAN */ 996 <0x0c>; /* RX_UHCHAN */ 997 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 998 }; 999 1000 cpts@310d0000 { 1001 compatible = "ti,j721e-cpts"; 1002 reg = <0x00 0x310d0000 0x00 0x400>; 1003 reg-names = "cpts"; 1004 clocks = <&k3_clks 282 0>; 1005 clock-names = "cpts"; 1006 assigned-clocks = <&k3_clks 62 3>; /* CPTS_RFT_CLK */ 1007 assigned-clock-parents = <&k3_clks 62 5>; /* MAIN_0_HSDIV6_CLK */ 1008 interrupts-extended = <&main_navss_intr 391>; 1009 interrupt-names = "cpts"; 1010 ti,cpts-periodic-outputs = <6>; 1011 ti,cpts-ext-ts-inputs = <8>; 1012 }; 1013 }; 1014 1015 main_mcan0: can@2701000 { 1016 compatible = "bosch,m_can"; 1017 reg = <0x00 0x02701000 0x00 0x200>, 1018 <0x00 0x02708000 0x00 0x8000>; 1019 reg-names = "m_can", "message_ram"; 1020 power-domains = <&k3_pds 245 TI_SCI_PD_EXCLUSIVE>; 1021 clocks = <&k3_clks 245 6>, <&k3_clks 245 1>; 1022 clock-names = "hclk", "cclk"; 1023 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1024 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 1025 interrupt-names = "int0", "int1"; 1026 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1027 status = "disabled"; 1028 }; 1029 1030 main_mcan1: can@2711000 { 1031 compatible = "bosch,m_can"; 1032 reg = <0x00 0x02711000 0x00 0x200>, 1033 <0x00 0x02718000 0x00 0x8000>; 1034 reg-names = "m_can", "message_ram"; 1035 power-domains = <&k3_pds 246 TI_SCI_PD_EXCLUSIVE>; 1036 clocks = <&k3_clks 246 6>, <&k3_clks 246 1>; 1037 clock-names = "hclk", "cclk"; 1038 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 1039 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 1040 interrupt-names = "int0", "int1"; 1041 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1042 status = "disabled"; 1043 }; 1044 1045 main_mcan2: can@2721000 { 1046 compatible = "bosch,m_can"; 1047 reg = <0x00 0x02721000 0x00 0x200>, 1048 <0x00 0x02728000 0x00 0x8000>; 1049 reg-names = "m_can", "message_ram"; 1050 power-domains = <&k3_pds 247 TI_SCI_PD_EXCLUSIVE>; 1051 clocks = <&k3_clks 247 6>, <&k3_clks 247 1>; 1052 clock-names = "hclk", "cclk"; 1053 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1054 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 1055 interrupt-names = "int0", "int1"; 1056 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1057 status = "disabled"; 1058 }; 1059 1060 main_mcan3: can@2731000 { 1061 compatible = "bosch,m_can"; 1062 reg = <0x00 0x02731000 0x00 0x200>, 1063 <0x00 0x02738000 0x00 0x8000>; 1064 reg-names = "m_can", "message_ram"; 1065 power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>; 1066 clocks = <&k3_clks 248 6>, <&k3_clks 248 1>; 1067 clock-names = "hclk", "cclk"; 1068 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1069 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 1070 interrupt-names = "int0", "int1"; 1071 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1072 status = "disabled"; 1073 }; 1074 1075 main_mcan4: can@2741000 { 1076 compatible = "bosch,m_can"; 1077 reg = <0x00 0x02741000 0x00 0x200>, 1078 <0x00 0x02748000 0x00 0x8000>; 1079 reg-names = "m_can", "message_ram"; 1080 power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; 1081 clocks = <&k3_clks 249 6>, <&k3_clks 249 1>; 1082 clock-names = "hclk", "cclk"; 1083 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1084 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 1085 interrupt-names = "int0", "int1"; 1086 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1087 status = "disabled"; 1088 }; 1089 1090 main_mcan5: can@2751000 { 1091 compatible = "bosch,m_can"; 1092 reg = <0x00 0x02751000 0x00 0x200>, 1093 <0x00 0x02758000 0x00 0x8000>; 1094 reg-names = "m_can", "message_ram"; 1095 power-domains = <&k3_pds 250 TI_SCI_PD_EXCLUSIVE>; 1096 clocks = <&k3_clks 250 6>, <&k3_clks 250 1>; 1097 clock-names = "hclk", "cclk"; 1098 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 1099 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1100 interrupt-names = "int0", "int1"; 1101 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1102 status = "disabled"; 1103 }; 1104 1105 main_mcan6: can@2761000 { 1106 compatible = "bosch,m_can"; 1107 reg = <0x00 0x02761000 0x00 0x200>, 1108 <0x00 0x02768000 0x00 0x8000>; 1109 reg-names = "m_can", "message_ram"; 1110 power-domains = <&k3_pds 251 TI_SCI_PD_EXCLUSIVE>; 1111 clocks = <&k3_clks 251 6>, <&k3_clks 251 1>; 1112 clock-names = "hclk", "cclk"; 1113 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1114 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 1115 interrupt-names = "int0", "int1"; 1116 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1117 status = "disabled"; 1118 }; 1119 1120 main_mcan7: can@2771000 { 1121 compatible = "bosch,m_can"; 1122 reg = <0x00 0x02771000 0x00 0x200>, 1123 <0x00 0x02778000 0x00 0x8000>; 1124 reg-names = "m_can", "message_ram"; 1125 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; 1126 clocks = <&k3_clks 252 6>, <&k3_clks 252 1>; 1127 clock-names = "hclk", "cclk"; 1128 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1129 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1130 interrupt-names = "int0", "int1"; 1131 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1132 status = "disabled"; 1133 }; 1134 1135 main_mcan8: can@2781000 { 1136 compatible = "bosch,m_can"; 1137 reg = <0x00 0x02781000 0x00 0x200>, 1138 <0x00 0x02788000 0x00 0x8000>; 1139 reg-names = "m_can", "message_ram"; 1140 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; 1141 clocks = <&k3_clks 253 6>, <&k3_clks 253 1>; 1142 clock-names = "hclk", "cclk"; 1143 interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 1144 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>; 1145 interrupt-names = "int0", "int1"; 1146 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1147 status = "disabled"; 1148 }; 1149 1150 main_mcan9: can@2791000 { 1151 compatible = "bosch,m_can"; 1152 reg = <0x00 0x02791000 0x00 0x200>, 1153 <0x00 0x02798000 0x00 0x8000>; 1154 reg-names = "m_can", "message_ram"; 1155 power-domains = <&k3_pds 254 TI_SCI_PD_EXCLUSIVE>; 1156 clocks = <&k3_clks 254 6>, <&k3_clks 254 1>; 1157 clock-names = "hclk", "cclk"; 1158 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>, 1159 <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 1160 interrupt-names = "int0", "int1"; 1161 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1162 status = "disabled"; 1163 }; 1164 1165 main_mcan10: can@27a1000 { 1166 compatible = "bosch,m_can"; 1167 reg = <0x00 0x027a1000 0x00 0x200>, 1168 <0x00 0x027a8000 0x00 0x8000>; 1169 reg-names = "m_can", "message_ram"; 1170 power-domains = <&k3_pds 255 TI_SCI_PD_EXCLUSIVE>; 1171 clocks = <&k3_clks 255 6>, <&k3_clks 255 1>; 1172 clock-names = "hclk", "cclk"; 1173 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>, 1174 <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1175 interrupt-names = "int0", "int1"; 1176 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1177 status = "disabled"; 1178 }; 1179 1180 main_mcan11: can@27b1000 { 1181 compatible = "bosch,m_can"; 1182 reg = <0x00 0x027b1000 0x00 0x200>, 1183 <0x00 0x027b8000 0x00 0x8000>; 1184 reg-names = "m_can", "message_ram"; 1185 power-domains = <&k3_pds 256 TI_SCI_PD_EXCLUSIVE>; 1186 clocks = <&k3_clks 256 6>, <&k3_clks 256 1>; 1187 clock-names = "hclk", "cclk"; 1188 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>, 1189 <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1190 interrupt-names = "int0", "int1"; 1191 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1192 status = "disabled"; 1193 }; 1194 1195 main_mcan12: can@27c1000 { 1196 compatible = "bosch,m_can"; 1197 reg = <0x00 0x027c1000 0x00 0x200>, 1198 <0x00 0x027c8000 0x00 0x8000>; 1199 reg-names = "m_can", "message_ram"; 1200 power-domains = <&k3_pds 257 TI_SCI_PD_EXCLUSIVE>; 1201 clocks = <&k3_clks 257 6>, <&k3_clks 257 1>; 1202 clock-names = "hclk", "cclk"; 1203 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 1204 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>; 1205 interrupt-names = "int0", "int1"; 1206 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1207 status = "disabled"; 1208 }; 1209 1210 main_mcan13: can@27d1000 { 1211 compatible = "bosch,m_can"; 1212 reg = <0x00 0x027d1000 0x00 0x200>, 1213 <0x00 0x027d8000 0x00 0x8000>; 1214 reg-names = "m_can", "message_ram"; 1215 power-domains = <&k3_pds 258 TI_SCI_PD_EXCLUSIVE>; 1216 clocks = <&k3_clks 258 6>, <&k3_clks 258 1>; 1217 clock-names = "hclk", "cclk"; 1218 interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 1219 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>; 1220 interrupt-names = "int0", "int1"; 1221 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1222 status = "disabled"; 1223 }; 1224 1225 main_mcan14: can@2681000 { 1226 compatible = "bosch,m_can"; 1227 reg = <0x00 0x02681000 0x00 0x200>, 1228 <0x00 0x02688000 0x00 0x8000>; 1229 reg-names = "m_can", "message_ram"; 1230 power-domains = <&k3_pds 259 TI_SCI_PD_EXCLUSIVE>; 1231 clocks = <&k3_clks 259 6>, <&k3_clks 259 1>; 1232 clock-names = "hclk", "cclk"; 1233 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 1234 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>; 1235 interrupt-names = "int0", "int1"; 1236 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1237 status = "disabled"; 1238 }; 1239 1240 main_mcan15: can@2691000 { 1241 compatible = "bosch,m_can"; 1242 reg = <0x00 0x02691000 0x00 0x200>, 1243 <0x00 0x02698000 0x00 0x8000>; 1244 reg-names = "m_can", "message_ram"; 1245 power-domains = <&k3_pds 260 TI_SCI_PD_EXCLUSIVE>; 1246 clocks = <&k3_clks 260 6>, <&k3_clks 260 1>; 1247 clock-names = "hclk", "cclk"; 1248 interrupts = <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 1249 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>; 1250 interrupt-names = "int0", "int1"; 1251 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1252 status = "disabled"; 1253 }; 1254 1255 main_mcan16: can@26a1000 { 1256 compatible = "bosch,m_can"; 1257 reg = <0x00 0x026a1000 0x00 0x200>, 1258 <0x00 0x026a8000 0x00 0x8000>; 1259 reg-names = "m_can", "message_ram"; 1260 power-domains = <&k3_pds 261 TI_SCI_PD_EXCLUSIVE>; 1261 clocks = <&k3_clks 261 6>, <&k3_clks 261 1>; 1262 clock-names = "hclk", "cclk"; 1263 interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 1264 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>; 1265 interrupt-names = "int0", "int1"; 1266 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1267 status = "disabled"; 1268 }; 1269 1270 main_mcan17: can@26b1000 { 1271 compatible = "bosch,m_can"; 1272 reg = <0x00 0x026b1000 0x00 0x200>, 1273 <0x00 0x026b8000 0x00 0x8000>; 1274 reg-names = "m_can", "message_ram"; 1275 power-domains = <&k3_pds 262 TI_SCI_PD_EXCLUSIVE>; 1276 clocks = <&k3_clks 262 6>, <&k3_clks 262 1>; 1277 clock-names = "hclk", "cclk"; 1278 interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>, 1279 <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>; 1280 interrupt-names = "int0", "int1"; 1281 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1282 status = "disabled"; 1283 }; 1284 1285 main_spi0: spi@2100000 { 1286 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1287 reg = <0x00 0x02100000 0x00 0x400>; 1288 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 1289 #address-cells = <1>; 1290 #size-cells = <0>; 1291 power-domains = <&k3_pds 376 TI_SCI_PD_EXCLUSIVE>; 1292 clocks = <&k3_clks 376 1>; 1293 status = "disabled"; 1294 }; 1295 1296 main_spi1: spi@2110000 { 1297 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1298 reg = <0x00 0x02110000 0x00 0x400>; 1299 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 1300 #address-cells = <1>; 1301 #size-cells = <0>; 1302 power-domains = <&k3_pds 377 TI_SCI_PD_EXCLUSIVE>; 1303 clocks = <&k3_clks 377 1>; 1304 status = "disabled"; 1305 }; 1306 1307 main_spi2: spi@2120000 { 1308 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1309 reg = <0x00 0x02120000 0x00 0x400>; 1310 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1311 #address-cells = <1>; 1312 #size-cells = <0>; 1313 power-domains = <&k3_pds 378 TI_SCI_PD_EXCLUSIVE>; 1314 clocks = <&k3_clks 378 1>; 1315 status = "disabled"; 1316 }; 1317 1318 main_spi3: spi@2130000 { 1319 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1320 reg = <0x00 0x02130000 0x00 0x400>; 1321 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 1322 #address-cells = <1>; 1323 #size-cells = <0>; 1324 power-domains = <&k3_pds 379 TI_SCI_PD_EXCLUSIVE>; 1325 clocks = <&k3_clks 379 1>; 1326 status = "disabled"; 1327 }; 1328 1329 main_spi4: spi@2140000 { 1330 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1331 reg = <0x00 0x02140000 0x00 0x400>; 1332 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 1333 #address-cells = <1>; 1334 #size-cells = <0>; 1335 power-domains = <&k3_pds 380 TI_SCI_PD_EXCLUSIVE>; 1336 clocks = <&k3_clks 380 1>; 1337 status = "disabled"; 1338 }; 1339 1340 main_spi5: spi@2150000 { 1341 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1342 reg = <0x00 0x02150000 0x00 0x400>; 1343 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 1344 #address-cells = <1>; 1345 #size-cells = <0>; 1346 power-domains = <&k3_pds 381 TI_SCI_PD_EXCLUSIVE>; 1347 clocks = <&k3_clks 381 1>; 1348 status = "disabled"; 1349 }; 1350 1351 main_spi6: spi@2160000 { 1352 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1353 reg = <0x00 0x02160000 0x00 0x400>; 1354 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1355 #address-cells = <1>; 1356 #size-cells = <0>; 1357 power-domains = <&k3_pds 382 TI_SCI_PD_EXCLUSIVE>; 1358 clocks = <&k3_clks 382 1>; 1359 status = "disabled"; 1360 }; 1361 1362 main_spi7: spi@2170000 { 1363 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1364 reg = <0x00 0x02170000 0x00 0x400>; 1365 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 1366 #address-cells = <1>; 1367 #size-cells = <0>; 1368 power-domains = <&k3_pds 383 TI_SCI_PD_EXCLUSIVE>; 1369 clocks = <&k3_clks 383 1>; 1370 status = "disabled"; 1371 }; 1372 1373 main_r5fss0: r5fss@5c00000 { 1374 compatible = "ti,j721s2-r5fss"; 1375 ti,cluster-mode = <1>; 1376 #address-cells = <1>; 1377 #size-cells = <1>; 1378 ranges = <0x5c00000 0x00 0x5c00000 0x20000>, 1379 <0x5d00000 0x00 0x5d00000 0x20000>; 1380 power-domains = <&k3_pds 336 TI_SCI_PD_EXCLUSIVE>; 1381 1382 main_r5fss0_core0: r5f@5c00000 { 1383 compatible = "ti,j721s2-r5f"; 1384 reg = <0x5c00000 0x00010000>, 1385 <0x5c10000 0x00010000>; 1386 reg-names = "atcm", "btcm"; 1387 ti,sci = <&sms>; 1388 ti,sci-dev-id = <339>; 1389 ti,sci-proc-ids = <0x06 0xff>; 1390 resets = <&k3_reset 339 1>; 1391 firmware-name = "j784s4-main-r5f0_0-fw"; 1392 ti,atcm-enable = <1>; 1393 ti,btcm-enable = <1>; 1394 ti,loczrama = <1>; 1395 }; 1396 1397 main_r5fss0_core1: r5f@5d00000 { 1398 compatible = "ti,j721s2-r5f"; 1399 reg = <0x5d00000 0x00010000>, 1400 <0x5d10000 0x00010000>; 1401 reg-names = "atcm", "btcm"; 1402 ti,sci = <&sms>; 1403 ti,sci-dev-id = <340>; 1404 ti,sci-proc-ids = <0x07 0xff>; 1405 resets = <&k3_reset 340 1>; 1406 firmware-name = "j784s4-main-r5f0_1-fw"; 1407 ti,atcm-enable = <1>; 1408 ti,btcm-enable = <1>; 1409 ti,loczrama = <1>; 1410 }; 1411 }; 1412 1413 main_r5fss1: r5fss@5e00000 { 1414 compatible = "ti,j721s2-r5fss"; 1415 ti,cluster-mode = <1>; 1416 #address-cells = <1>; 1417 #size-cells = <1>; 1418 ranges = <0x5e00000 0x00 0x5e00000 0x20000>, 1419 <0x5f00000 0x00 0x5f00000 0x20000>; 1420 power-domains = <&k3_pds 337 TI_SCI_PD_EXCLUSIVE>; 1421 1422 main_r5fss1_core0: r5f@5e00000 { 1423 compatible = "ti,j721s2-r5f"; 1424 reg = <0x5e00000 0x00010000>, 1425 <0x5e10000 0x00010000>; 1426 reg-names = "atcm", "btcm"; 1427 ti,sci = <&sms>; 1428 ti,sci-dev-id = <341>; 1429 ti,sci-proc-ids = <0x08 0xff>; 1430 resets = <&k3_reset 341 1>; 1431 firmware-name = "j784s4-main-r5f1_0-fw"; 1432 ti,atcm-enable = <1>; 1433 ti,btcm-enable = <1>; 1434 ti,loczrama = <1>; 1435 }; 1436 1437 main_r5fss1_core1: r5f@5f00000 { 1438 compatible = "ti,j721s2-r5f"; 1439 reg = <0x5f00000 0x00010000>, 1440 <0x5f10000 0x00010000>; 1441 reg-names = "atcm", "btcm"; 1442 ti,sci = <&sms>; 1443 ti,sci-dev-id = <342>; 1444 ti,sci-proc-ids = <0x09 0xff>; 1445 resets = <&k3_reset 342 1>; 1446 firmware-name = "j784s4-main-r5f1_1-fw"; 1447 ti,atcm-enable = <1>; 1448 ti,btcm-enable = <1>; 1449 ti,loczrama = <1>; 1450 }; 1451 }; 1452 1453 main_r5fss2: r5fss@5900000 { 1454 compatible = "ti,j721s2-r5fss"; 1455 ti,cluster-mode = <1>; 1456 #address-cells = <1>; 1457 #size-cells = <1>; 1458 ranges = <0x5900000 0x00 0x5900000 0x20000>, 1459 <0x5a00000 0x00 0x5a00000 0x20000>; 1460 power-domains = <&k3_pds 338 TI_SCI_PD_EXCLUSIVE>; 1461 1462 main_r5fss2_core0: r5f@5900000 { 1463 compatible = "ti,j721s2-r5f"; 1464 reg = <0x5900000 0x00010000>, 1465 <0x5910000 0x00010000>; 1466 reg-names = "atcm", "btcm"; 1467 ti,sci = <&sms>; 1468 ti,sci-dev-id = <343>; 1469 ti,sci-proc-ids = <0x0a 0xff>; 1470 resets = <&k3_reset 343 1>; 1471 firmware-name = "j784s4-main-r5f2_0-fw"; 1472 ti,atcm-enable = <1>; 1473 ti,btcm-enable = <1>; 1474 ti,loczrama = <1>; 1475 }; 1476 1477 main_r5fss2_core1: r5f@5a00000 { 1478 compatible = "ti,j721s2-r5f"; 1479 reg = <0x5a00000 0x00010000>, 1480 <0x5a10000 0x00010000>; 1481 reg-names = "atcm", "btcm"; 1482 ti,sci = <&sms>; 1483 ti,sci-dev-id = <344>; 1484 ti,sci-proc-ids = <0x0b 0xff>; 1485 resets = <&k3_reset 344 1>; 1486 firmware-name = "j784s4-main-r5f2_1-fw"; 1487 ti,atcm-enable = <1>; 1488 ti,btcm-enable = <1>; 1489 ti,loczrama = <1>; 1490 }; 1491 }; 1492 1493 c71_0: dsp@64800000 { 1494 compatible = "ti,j721s2-c71-dsp"; 1495 reg = <0x00 0x64800000 0x00 0x00080000>, 1496 <0x00 0x64e00000 0x00 0x0000c000>; 1497 reg-names = "l2sram", "l1dram"; 1498 ti,sci = <&sms>; 1499 ti,sci-dev-id = <30>; 1500 ti,sci-proc-ids = <0x30 0xff>; 1501 resets = <&k3_reset 30 1>; 1502 firmware-name = "j784s4-c71_0-fw"; 1503 }; 1504 1505 c71_1: dsp@65800000 { 1506 compatible = "ti,j721s2-c71-dsp"; 1507 reg = <0x00 0x65800000 0x00 0x00080000>, 1508 <0x00 0x65e00000 0x00 0x0000c000>; 1509 reg-names = "l2sram", "l1dram"; 1510 ti,sci = <&sms>; 1511 ti,sci-dev-id = <33>; 1512 ti,sci-proc-ids = <0x31 0xff>; 1513 resets = <&k3_reset 33 1>; 1514 firmware-name = "j784s4-c71_1-fw"; 1515 }; 1516 1517 c71_2: dsp@66800000 { 1518 compatible = "ti,j721s2-c71-dsp"; 1519 reg = <0x00 0x66800000 0x00 0x00080000>, 1520 <0x00 0x66e00000 0x00 0x0000c000>; 1521 reg-names = "l2sram", "l1dram"; 1522 ti,sci = <&sms>; 1523 ti,sci-dev-id = <37>; 1524 ti,sci-proc-ids = <0x32 0xff>; 1525 resets = <&k3_reset 37 1>; 1526 firmware-name = "j784s4-c71_2-fw"; 1527 }; 1528 1529 c71_3: dsp@67800000 { 1530 compatible = "ti,j721s2-c71-dsp"; 1531 reg = <0x00 0x67800000 0x00 0x00080000>, 1532 <0x00 0x67e00000 0x00 0x0000c000>; 1533 reg-names = "l2sram", "l1dram"; 1534 ti,sci = <&sms>; 1535 ti,sci-dev-id = <40>; 1536 ti,sci-proc-ids = <0x33 0xff>; 1537 resets = <&k3_reset 40 1>; 1538 firmware-name = "j784s4-c71_3-fw"; 1539 }; 1540}; 1541