1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Freescale MPC85xx/MPC86xx RapidIO RMU support 4 * 5 * Copyright 2009 Sysgo AG 6 * Thomas Moll <thomas.moll@sysgo.com> 7 * - fixed maintenance access routines, check for aligned access 8 * 9 * Copyright 2009 Integrated Device Technology, Inc. 10 * Alex Bounine <alexandre.bounine@idt.com> 11 * - Added Port-Write message handling 12 * - Added Machine Check exception handling 13 * 14 * Copyright (C) 2007, 2008, 2010, 2011 Freescale Semiconductor, Inc. 15 * Zhang Wei <wei.zhang@freescale.com> 16 * Lian Minghuan-B31939 <Minghuan.Lian@freescale.com> 17 * Liu Gang <Gang.Liu@freescale.com> 18 * 19 * Copyright 2005 MontaVista Software, Inc. 20 * Matt Porter <mporter@kernel.crashing.org> 21 */ 22 23 #include <linux/types.h> 24 #include <linux/dma-mapping.h> 25 #include <linux/interrupt.h> 26 #include <linux/of_address.h> 27 #include <linux/of_irq.h> 28 #include <linux/of_platform.h> 29 #include <linux/slab.h> 30 31 #include "fsl_rio.h" 32 33 #define GET_RMM_HANDLE(mport) \ 34 (((struct rio_priv *)(mport->priv))->rmm_handle) 35 36 /* RapidIO definition irq, which read from OF-tree */ 37 #define IRQ_RIO_PW(m) (((struct fsl_rio_pw *)(m))->pwirq) 38 #define IRQ_RIO_BELL(m) (((struct fsl_rio_dbell *)(m))->bellirq) 39 #define IRQ_RIO_TX(m) (((struct fsl_rmu *)(GET_RMM_HANDLE(m)))->txirq) 40 #define IRQ_RIO_RX(m) (((struct fsl_rmu *)(GET_RMM_HANDLE(m)))->rxirq) 41 42 #define RIO_MIN_TX_RING_SIZE 2 43 #define RIO_MAX_TX_RING_SIZE 2048 44 #define RIO_MIN_RX_RING_SIZE 2 45 #define RIO_MAX_RX_RING_SIZE 2048 46 47 #define RIO_IPWMR_SEN 0x00100000 48 #define RIO_IPWMR_QFIE 0x00000100 49 #define RIO_IPWMR_EIE 0x00000020 50 #define RIO_IPWMR_CQ 0x00000002 51 #define RIO_IPWMR_PWE 0x00000001 52 53 #define RIO_IPWSR_QF 0x00100000 54 #define RIO_IPWSR_TE 0x00000080 55 #define RIO_IPWSR_QFI 0x00000010 56 #define RIO_IPWSR_PWD 0x00000008 57 #define RIO_IPWSR_PWB 0x00000004 58 59 #define RIO_EPWISR 0x10010 60 /* EPWISR Error match value */ 61 #define RIO_EPWISR_PINT1 0x80000000 62 #define RIO_EPWISR_PINT2 0x40000000 63 #define RIO_EPWISR_MU 0x00000002 64 #define RIO_EPWISR_PW 0x00000001 65 66 #define IPWSR_CLEAR 0x98 67 #define OMSR_CLEAR 0x1cb3 68 #define IMSR_CLEAR 0x491 69 #define IDSR_CLEAR 0x91 70 #define ODSR_CLEAR 0x1c00 71 #define LTLEECSR_ENABLE_ALL 0xFFC000FC 72 #define RIO_LTLEECSR 0x060c 73 74 #define RIO_IM0SR 0x64 75 #define RIO_IM1SR 0x164 76 #define RIO_OM0SR 0x4 77 #define RIO_OM1SR 0x104 78 79 #define RIO_DBELL_WIN_SIZE 0x1000 80 81 #define RIO_MSG_OMR_MUI 0x00000002 82 #define RIO_MSG_OSR_TE 0x00000080 83 #define RIO_MSG_OSR_QOI 0x00000020 84 #define RIO_MSG_OSR_QFI 0x00000010 85 #define RIO_MSG_OSR_MUB 0x00000004 86 #define RIO_MSG_OSR_EOMI 0x00000002 87 #define RIO_MSG_OSR_QEI 0x00000001 88 89 #define RIO_MSG_IMR_MI 0x00000002 90 #define RIO_MSG_ISR_TE 0x00000080 91 #define RIO_MSG_ISR_QFI 0x00000010 92 #define RIO_MSG_ISR_DIQI 0x00000001 93 94 #define RIO_MSG_DESC_SIZE 32 95 #define RIO_MSG_BUFFER_SIZE 4096 96 97 #define DOORBELL_DMR_DI 0x00000002 98 #define DOORBELL_DSR_TE 0x00000080 99 #define DOORBELL_DSR_QFI 0x00000010 100 #define DOORBELL_DSR_DIQI 0x00000001 101 102 #define DOORBELL_MESSAGE_SIZE 0x08 103 104 static DEFINE_SPINLOCK(fsl_rio_doorbell_lock); 105 106 struct rio_msg_regs { 107 u32 omr; 108 u32 osr; 109 u32 pad1; 110 u32 odqdpar; 111 u32 pad2; 112 u32 osar; 113 u32 odpr; 114 u32 odatr; 115 u32 odcr; 116 u32 pad3; 117 u32 odqepar; 118 u32 pad4[13]; 119 u32 imr; 120 u32 isr; 121 u32 pad5; 122 u32 ifqdpar; 123 u32 pad6; 124 u32 ifqepar; 125 }; 126 127 struct rio_dbell_regs { 128 u32 odmr; 129 u32 odsr; 130 u32 pad1[4]; 131 u32 oddpr; 132 u32 oddatr; 133 u32 pad2[3]; 134 u32 odretcr; 135 u32 pad3[12]; 136 u32 dmr; 137 u32 dsr; 138 u32 pad4; 139 u32 dqdpar; 140 u32 pad5; 141 u32 dqepar; 142 }; 143 144 struct rio_pw_regs { 145 u32 pwmr; 146 u32 pwsr; 147 u32 epwqbar; 148 u32 pwqbar; 149 }; 150 151 152 struct rio_tx_desc { 153 u32 pad1; 154 u32 saddr; 155 u32 dport; 156 u32 dattr; 157 u32 pad2; 158 u32 pad3; 159 u32 dwcnt; 160 u32 pad4; 161 }; 162 163 struct rio_msg_tx_ring { 164 void *virt; 165 dma_addr_t phys; 166 void *virt_buffer[RIO_MAX_TX_RING_SIZE]; 167 dma_addr_t phys_buffer[RIO_MAX_TX_RING_SIZE]; 168 int tx_slot; 169 int size; 170 void *dev_id; 171 }; 172 173 struct rio_msg_rx_ring { 174 void *virt; 175 dma_addr_t phys; 176 void *virt_buffer[RIO_MAX_RX_RING_SIZE]; 177 int rx_slot; 178 int size; 179 void *dev_id; 180 }; 181 182 struct fsl_rmu { 183 struct rio_msg_regs __iomem *msg_regs; 184 struct rio_msg_tx_ring msg_tx_ring; 185 struct rio_msg_rx_ring msg_rx_ring; 186 int txirq; 187 int rxirq; 188 }; 189 190 struct rio_dbell_msg { 191 u16 pad1; 192 u16 tid; 193 u16 sid; 194 u16 info; 195 }; 196 197 /** 198 * fsl_rio_tx_handler - MPC85xx outbound message interrupt handler 199 * @irq: Linux interrupt number 200 * @dev_instance: Pointer to interrupt-specific data 201 * 202 * Handles outbound message interrupts. Executes a register outbound 203 * mailbox event handler and acks the interrupt occurrence. 204 */ 205 static irqreturn_t 206 fsl_rio_tx_handler(int irq, void *dev_instance) 207 { 208 int osr; 209 struct rio_mport *port = (struct rio_mport *)dev_instance; 210 struct fsl_rmu *rmu = GET_RMM_HANDLE(port); 211 212 osr = in_be32(&rmu->msg_regs->osr); 213 214 if (osr & RIO_MSG_OSR_TE) { 215 pr_info("RIO: outbound message transmission error\n"); 216 out_be32(&rmu->msg_regs->osr, RIO_MSG_OSR_TE); 217 goto out; 218 } 219 220 if (osr & RIO_MSG_OSR_QOI) { 221 pr_info("RIO: outbound message queue overflow\n"); 222 out_be32(&rmu->msg_regs->osr, RIO_MSG_OSR_QOI); 223 goto out; 224 } 225 226 if (osr & RIO_MSG_OSR_EOMI) { 227 u32 dqp = in_be32(&rmu->msg_regs->odqdpar); 228 int slot = (dqp - rmu->msg_tx_ring.phys) >> 5; 229 if (port->outb_msg[0].mcback != NULL) { 230 port->outb_msg[0].mcback(port, rmu->msg_tx_ring.dev_id, 231 -1, 232 slot); 233 } 234 /* Ack the end-of-message interrupt */ 235 out_be32(&rmu->msg_regs->osr, RIO_MSG_OSR_EOMI); 236 } 237 238 out: 239 return IRQ_HANDLED; 240 } 241 242 /** 243 * fsl_rio_rx_handler - MPC85xx inbound message interrupt handler 244 * @irq: Linux interrupt number 245 * @dev_instance: Pointer to interrupt-specific data 246 * 247 * Handles inbound message interrupts. Executes a registered inbound 248 * mailbox event handler and acks the interrupt occurrence. 249 */ 250 static irqreturn_t 251 fsl_rio_rx_handler(int irq, void *dev_instance) 252 { 253 int isr; 254 struct rio_mport *port = (struct rio_mport *)dev_instance; 255 struct fsl_rmu *rmu = GET_RMM_HANDLE(port); 256 257 isr = in_be32(&rmu->msg_regs->isr); 258 259 if (isr & RIO_MSG_ISR_TE) { 260 pr_info("RIO: inbound message reception error\n"); 261 out_be32((void *)&rmu->msg_regs->isr, RIO_MSG_ISR_TE); 262 goto out; 263 } 264 265 /* XXX Need to check/dispatch until queue empty */ 266 if (isr & RIO_MSG_ISR_DIQI) { 267 /* 268 * Can receive messages for any mailbox/letter to that 269 * mailbox destination. So, make the callback with an 270 * unknown/invalid mailbox number argument. 271 */ 272 if (port->inb_msg[0].mcback != NULL) 273 port->inb_msg[0].mcback(port, rmu->msg_rx_ring.dev_id, 274 -1, 275 -1); 276 277 /* Ack the queueing interrupt */ 278 out_be32(&rmu->msg_regs->isr, RIO_MSG_ISR_DIQI); 279 } 280 281 out: 282 return IRQ_HANDLED; 283 } 284 285 /** 286 * fsl_rio_dbell_handler - MPC85xx doorbell interrupt handler 287 * @irq: Linux interrupt number 288 * @dev_instance: Pointer to interrupt-specific data 289 * 290 * Handles doorbell interrupts. Parses a list of registered 291 * doorbell event handlers and executes a matching event handler. 292 */ 293 static irqreturn_t 294 fsl_rio_dbell_handler(int irq, void *dev_instance) 295 { 296 int dsr; 297 struct fsl_rio_dbell *fsl_dbell = (struct fsl_rio_dbell *)dev_instance; 298 int i; 299 300 dsr = in_be32(&fsl_dbell->dbell_regs->dsr); 301 302 if (dsr & DOORBELL_DSR_TE) { 303 pr_info("RIO: doorbell reception error\n"); 304 out_be32(&fsl_dbell->dbell_regs->dsr, DOORBELL_DSR_TE); 305 goto out; 306 } 307 308 if (dsr & DOORBELL_DSR_QFI) { 309 pr_info("RIO: doorbell queue full\n"); 310 out_be32(&fsl_dbell->dbell_regs->dsr, DOORBELL_DSR_QFI); 311 } 312 313 /* XXX Need to check/dispatch until queue empty */ 314 if (dsr & DOORBELL_DSR_DIQI) { 315 struct rio_dbell_msg *dmsg = 316 fsl_dbell->dbell_ring.virt + 317 (in_be32(&fsl_dbell->dbell_regs->dqdpar) & 0xfff); 318 struct rio_dbell *dbell; 319 int found = 0; 320 321 pr_debug 322 ("RIO: processing doorbell," 323 " sid %2.2x tid %2.2x info %4.4x\n", 324 dmsg->sid, dmsg->tid, dmsg->info); 325 326 for (i = 0; i < MAX_PORT_NUM; i++) { 327 if (fsl_dbell->mport[i]) { 328 list_for_each_entry(dbell, 329 &fsl_dbell->mport[i]->dbells, node) { 330 if ((dbell->res->start 331 <= dmsg->info) 332 && (dbell->res->end 333 >= dmsg->info)) { 334 found = 1; 335 break; 336 } 337 } 338 if (found && dbell->dinb) { 339 dbell->dinb(fsl_dbell->mport[i], 340 dbell->dev_id, dmsg->sid, 341 dmsg->tid, 342 dmsg->info); 343 break; 344 } 345 } 346 } 347 348 if (!found) { 349 pr_debug 350 ("RIO: spurious doorbell," 351 " sid %2.2x tid %2.2x info %4.4x\n", 352 dmsg->sid, dmsg->tid, 353 dmsg->info); 354 } 355 setbits32(&fsl_dbell->dbell_regs->dmr, DOORBELL_DMR_DI); 356 out_be32(&fsl_dbell->dbell_regs->dsr, DOORBELL_DSR_DIQI); 357 } 358 359 out: 360 return IRQ_HANDLED; 361 } 362 363 void msg_unit_error_handler(void) 364 { 365 366 /*XXX: Error recovery is not implemented, we just clear errors */ 367 out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR), 0); 368 369 out_be32((u32 *)(rmu_regs_win + RIO_IM0SR), IMSR_CLEAR); 370 out_be32((u32 *)(rmu_regs_win + RIO_IM1SR), IMSR_CLEAR); 371 out_be32((u32 *)(rmu_regs_win + RIO_OM0SR), OMSR_CLEAR); 372 out_be32((u32 *)(rmu_regs_win + RIO_OM1SR), OMSR_CLEAR); 373 374 out_be32(&dbell->dbell_regs->odsr, ODSR_CLEAR); 375 out_be32(&dbell->dbell_regs->dsr, IDSR_CLEAR); 376 377 out_be32(&pw->pw_regs->pwsr, IPWSR_CLEAR); 378 } 379 380 /** 381 * fsl_rio_port_write_handler - MPC85xx port write interrupt handler 382 * @irq: Linux interrupt number 383 * @dev_instance: Pointer to interrupt-specific data 384 * 385 * Handles port write interrupts. Parses a list of registered 386 * port write event handlers and executes a matching event handler. 387 */ 388 static irqreturn_t 389 fsl_rio_port_write_handler(int irq, void *dev_instance) 390 { 391 u32 ipwmr, ipwsr; 392 struct fsl_rio_pw *pw = (struct fsl_rio_pw *)dev_instance; 393 u32 epwisr, tmp; 394 395 epwisr = in_be32(rio_regs_win + RIO_EPWISR); 396 if (!(epwisr & RIO_EPWISR_PW)) 397 goto pw_done; 398 399 ipwmr = in_be32(&pw->pw_regs->pwmr); 400 ipwsr = in_be32(&pw->pw_regs->pwsr); 401 402 #ifdef DEBUG_PW 403 pr_debug("PW Int->IPWMR: 0x%08x IPWSR: 0x%08x (", ipwmr, ipwsr); 404 if (ipwsr & RIO_IPWSR_QF) 405 pr_debug(" QF"); 406 if (ipwsr & RIO_IPWSR_TE) 407 pr_debug(" TE"); 408 if (ipwsr & RIO_IPWSR_QFI) 409 pr_debug(" QFI"); 410 if (ipwsr & RIO_IPWSR_PWD) 411 pr_debug(" PWD"); 412 if (ipwsr & RIO_IPWSR_PWB) 413 pr_debug(" PWB"); 414 pr_debug(" )\n"); 415 #endif 416 /* Schedule deferred processing if PW was received */ 417 if (ipwsr & RIO_IPWSR_QFI) { 418 /* Save PW message (if there is room in FIFO), 419 * otherwise discard it. 420 */ 421 if (kfifo_avail(&pw->pw_fifo) >= RIO_PW_MSG_SIZE) { 422 pw->port_write_msg.msg_count++; 423 kfifo_in(&pw->pw_fifo, pw->port_write_msg.virt, 424 RIO_PW_MSG_SIZE); 425 } else { 426 pw->port_write_msg.discard_count++; 427 pr_debug("RIO: ISR Discarded Port-Write Msg(s) (%d)\n", 428 pw->port_write_msg.discard_count); 429 } 430 /* Clear interrupt and issue Clear Queue command. This allows 431 * another port-write to be received. 432 */ 433 out_be32(&pw->pw_regs->pwsr, RIO_IPWSR_QFI); 434 out_be32(&pw->pw_regs->pwmr, ipwmr | RIO_IPWMR_CQ); 435 436 schedule_work(&pw->pw_work); 437 } 438 439 if ((ipwmr & RIO_IPWMR_EIE) && (ipwsr & RIO_IPWSR_TE)) { 440 pw->port_write_msg.err_count++; 441 pr_debug("RIO: Port-Write Transaction Err (%d)\n", 442 pw->port_write_msg.err_count); 443 /* Clear Transaction Error: port-write controller should be 444 * disabled when clearing this error 445 */ 446 out_be32(&pw->pw_regs->pwmr, ipwmr & ~RIO_IPWMR_PWE); 447 out_be32(&pw->pw_regs->pwsr, RIO_IPWSR_TE); 448 out_be32(&pw->pw_regs->pwmr, ipwmr); 449 } 450 451 if (ipwsr & RIO_IPWSR_PWD) { 452 pw->port_write_msg.discard_count++; 453 pr_debug("RIO: Port Discarded Port-Write Msg(s) (%d)\n", 454 pw->port_write_msg.discard_count); 455 out_be32(&pw->pw_regs->pwsr, RIO_IPWSR_PWD); 456 } 457 458 pw_done: 459 if (epwisr & RIO_EPWISR_PINT1) { 460 tmp = in_be32(rio_regs_win + RIO_LTLEDCSR); 461 pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp); 462 fsl_rio_port_error_handler(0); 463 } 464 465 if (epwisr & RIO_EPWISR_PINT2) { 466 tmp = in_be32(rio_regs_win + RIO_LTLEDCSR); 467 pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp); 468 fsl_rio_port_error_handler(1); 469 } 470 471 if (epwisr & RIO_EPWISR_MU) { 472 tmp = in_be32(rio_regs_win + RIO_LTLEDCSR); 473 pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp); 474 msg_unit_error_handler(); 475 } 476 477 return IRQ_HANDLED; 478 } 479 480 static void fsl_pw_dpc(struct work_struct *work) 481 { 482 struct fsl_rio_pw *pw = container_of(work, struct fsl_rio_pw, pw_work); 483 union rio_pw_msg msg_buffer; 484 int i; 485 486 /* 487 * Process port-write messages 488 */ 489 while (kfifo_out_spinlocked(&pw->pw_fifo, (unsigned char *)&msg_buffer, 490 RIO_PW_MSG_SIZE, &pw->pw_fifo_lock)) { 491 #ifdef DEBUG_PW 492 { 493 u32 i; 494 pr_debug("%s : Port-Write Message:", __func__); 495 for (i = 0; i < RIO_PW_MSG_SIZE/sizeof(u32); i++) { 496 if ((i%4) == 0) 497 pr_debug("\n0x%02x: 0x%08x", i*4, 498 msg_buffer.raw[i]); 499 else 500 pr_debug(" 0x%08x", msg_buffer.raw[i]); 501 } 502 pr_debug("\n"); 503 } 504 #endif 505 /* Pass the port-write message to RIO core for processing */ 506 for (i = 0; i < MAX_PORT_NUM; i++) { 507 if (pw->mport[i]) 508 rio_inb_pwrite_handler(pw->mport[i], 509 &msg_buffer); 510 } 511 } 512 } 513 514 /** 515 * fsl_rio_pw_enable - enable/disable port-write interface init 516 * @mport: Master port implementing the port write unit 517 * @enable: 1=enable; 0=disable port-write message handling 518 */ 519 int fsl_rio_pw_enable(struct rio_mport *mport, int enable) 520 { 521 u32 rval; 522 523 rval = in_be32(&pw->pw_regs->pwmr); 524 525 if (enable) 526 rval |= RIO_IPWMR_PWE; 527 else 528 rval &= ~RIO_IPWMR_PWE; 529 530 out_be32(&pw->pw_regs->pwmr, rval); 531 532 return 0; 533 } 534 535 /** 536 * fsl_rio_port_write_init - MPC85xx port write interface init 537 * @mport: Master port implementing the port write unit 538 * 539 * Initializes port write unit hardware and DMA buffer 540 * ring. Called from fsl_rio_setup(). Returns %0 on success 541 * or %-ENOMEM on failure. 542 */ 543 544 int fsl_rio_port_write_init(struct fsl_rio_pw *pw) 545 { 546 int rc = 0; 547 548 /* Following configurations require a disabled port write controller */ 549 out_be32(&pw->pw_regs->pwmr, 550 in_be32(&pw->pw_regs->pwmr) & ~RIO_IPWMR_PWE); 551 552 /* Initialize port write */ 553 pw->port_write_msg.virt = dma_alloc_coherent(pw->dev, 554 RIO_PW_MSG_SIZE, 555 &pw->port_write_msg.phys, GFP_KERNEL); 556 if (!pw->port_write_msg.virt) { 557 pr_err("RIO: unable allocate port write queue\n"); 558 return -ENOMEM; 559 } 560 561 pw->port_write_msg.err_count = 0; 562 pw->port_write_msg.discard_count = 0; 563 564 /* Point dequeue/enqueue pointers at first entry */ 565 out_be32(&pw->pw_regs->epwqbar, 0); 566 out_be32(&pw->pw_regs->pwqbar, (u32) pw->port_write_msg.phys); 567 568 pr_debug("EIPWQBAR: 0x%08x IPWQBAR: 0x%08x\n", 569 in_be32(&pw->pw_regs->epwqbar), 570 in_be32(&pw->pw_regs->pwqbar)); 571 572 /* Clear interrupt status IPWSR */ 573 out_be32(&pw->pw_regs->pwsr, 574 (RIO_IPWSR_TE | RIO_IPWSR_QFI | RIO_IPWSR_PWD)); 575 576 /* Configure port write controller for snooping enable all reporting, 577 clear queue full */ 578 out_be32(&pw->pw_regs->pwmr, 579 RIO_IPWMR_SEN | RIO_IPWMR_QFIE | RIO_IPWMR_EIE | RIO_IPWMR_CQ); 580 581 582 /* Hook up port-write handler */ 583 rc = request_irq(IRQ_RIO_PW(pw), fsl_rio_port_write_handler, 584 IRQF_SHARED, "port-write", (void *)pw); 585 if (rc < 0) { 586 pr_err("MPC85xx RIO: unable to request inbound doorbell irq"); 587 goto err_out; 588 } 589 /* Enable Error Interrupt */ 590 out_be32((u32 *)(rio_regs_win + RIO_LTLEECSR), LTLEECSR_ENABLE_ALL); 591 592 INIT_WORK(&pw->pw_work, fsl_pw_dpc); 593 spin_lock_init(&pw->pw_fifo_lock); 594 if (kfifo_alloc(&pw->pw_fifo, RIO_PW_MSG_SIZE * 32, GFP_KERNEL)) { 595 pr_err("FIFO allocation failed\n"); 596 rc = -ENOMEM; 597 goto err_out_irq; 598 } 599 600 pr_debug("IPWMR: 0x%08x IPWSR: 0x%08x\n", 601 in_be32(&pw->pw_regs->pwmr), 602 in_be32(&pw->pw_regs->pwsr)); 603 604 return rc; 605 606 err_out_irq: 607 free_irq(IRQ_RIO_PW(pw), (void *)pw); 608 err_out: 609 dma_free_coherent(pw->dev, RIO_PW_MSG_SIZE, 610 pw->port_write_msg.virt, 611 pw->port_write_msg.phys); 612 return rc; 613 } 614 615 /** 616 * fsl_rio_doorbell_send - Send a MPC85xx doorbell message 617 * @mport: RapidIO master port info 618 * @index: ID of RapidIO interface 619 * @destid: Destination ID of target device 620 * @data: 16-bit info field of RapidIO doorbell message 621 * 622 * Sends a MPC85xx doorbell message. Returns %0 on success or 623 * %-EINVAL on failure. 624 */ 625 int fsl_rio_doorbell_send(struct rio_mport *mport, 626 int index, u16 destid, u16 data) 627 { 628 unsigned long flags; 629 630 pr_debug("fsl_doorbell_send: index %d destid %4.4x data %4.4x\n", 631 index, destid, data); 632 633 spin_lock_irqsave(&fsl_rio_doorbell_lock, flags); 634 635 /* In the serial version silicons, such as MPC8548, MPC8641, 636 * below operations is must be. 637 */ 638 out_be32(&dbell->dbell_regs->odmr, 0x00000000); 639 out_be32(&dbell->dbell_regs->odretcr, 0x00000004); 640 out_be32(&dbell->dbell_regs->oddpr, destid << 16); 641 out_be32(&dbell->dbell_regs->oddatr, (index << 20) | data); 642 out_be32(&dbell->dbell_regs->odmr, 0x00000001); 643 644 spin_unlock_irqrestore(&fsl_rio_doorbell_lock, flags); 645 646 return 0; 647 } 648 649 /** 650 * fsl_add_outb_message - Add message to the MPC85xx outbound message queue 651 * @mport: Master port with outbound message queue 652 * @rdev: Target of outbound message 653 * @mbox: Outbound mailbox 654 * @buffer: Message to add to outbound queue 655 * @len: Length of message 656 * 657 * Adds the @buffer message to the MPC85xx outbound message queue. Returns 658 * %0 on success or %-EINVAL on failure. 659 */ 660 int 661 fsl_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox, 662 void *buffer, size_t len) 663 { 664 struct fsl_rmu *rmu = GET_RMM_HANDLE(mport); 665 u32 omr; 666 struct rio_tx_desc *desc = (struct rio_tx_desc *)rmu->msg_tx_ring.virt 667 + rmu->msg_tx_ring.tx_slot; 668 int ret = 0; 669 670 pr_debug("RIO: fsl_add_outb_message(): destid %4.4x mbox %d buffer " \ 671 "%p len %8.8zx\n", rdev->destid, mbox, buffer, len); 672 if ((len < 8) || (len > RIO_MAX_MSG_SIZE)) { 673 ret = -EINVAL; 674 goto out; 675 } 676 677 /* Copy and clear rest of buffer */ 678 memcpy(rmu->msg_tx_ring.virt_buffer[rmu->msg_tx_ring.tx_slot], buffer, 679 len); 680 if (len < (RIO_MAX_MSG_SIZE - 4)) 681 memset(rmu->msg_tx_ring.virt_buffer[rmu->msg_tx_ring.tx_slot] 682 + len, 0, RIO_MAX_MSG_SIZE - len); 683 684 /* Set mbox field for message, and set destid */ 685 desc->dport = (rdev->destid << 16) | (mbox & 0x3); 686 687 /* Enable EOMI interrupt and priority */ 688 desc->dattr = 0x28000000 | ((mport->index) << 20); 689 690 /* Set transfer size aligned to next power of 2 (in double words) */ 691 desc->dwcnt = is_power_of_2(len) ? len : 1 << get_bitmask_order(len); 692 693 /* Set snooping and source buffer address */ 694 desc->saddr = 0x00000004 695 | rmu->msg_tx_ring.phys_buffer[rmu->msg_tx_ring.tx_slot]; 696 697 /* Increment enqueue pointer */ 698 omr = in_be32(&rmu->msg_regs->omr); 699 out_be32(&rmu->msg_regs->omr, omr | RIO_MSG_OMR_MUI); 700 701 /* Go to next descriptor */ 702 if (++rmu->msg_tx_ring.tx_slot == rmu->msg_tx_ring.size) 703 rmu->msg_tx_ring.tx_slot = 0; 704 705 out: 706 return ret; 707 } 708 709 /** 710 * fsl_open_outb_mbox - Initialize MPC85xx outbound mailbox 711 * @mport: Master port implementing the outbound message unit 712 * @dev_id: Device specific pointer to pass on event 713 * @mbox: Mailbox to open 714 * @entries: Number of entries in the outbound mailbox ring 715 * 716 * Initializes buffer ring, request the outbound message interrupt, 717 * and enables the outbound message unit. Returns %0 on success and 718 * %-EINVAL or %-ENOMEM on failure. 719 */ 720 int 721 fsl_open_outb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries) 722 { 723 int i, j, rc = 0; 724 struct rio_priv *priv = mport->priv; 725 struct fsl_rmu *rmu = GET_RMM_HANDLE(mport); 726 727 if ((entries < RIO_MIN_TX_RING_SIZE) || 728 (entries > RIO_MAX_TX_RING_SIZE) || (!is_power_of_2(entries))) { 729 rc = -EINVAL; 730 goto out; 731 } 732 733 /* Initialize shadow copy ring */ 734 rmu->msg_tx_ring.dev_id = dev_id; 735 rmu->msg_tx_ring.size = entries; 736 737 for (i = 0; i < rmu->msg_tx_ring.size; i++) { 738 rmu->msg_tx_ring.virt_buffer[i] = 739 dma_alloc_coherent(priv->dev, RIO_MSG_BUFFER_SIZE, 740 &rmu->msg_tx_ring.phys_buffer[i], GFP_KERNEL); 741 if (!rmu->msg_tx_ring.virt_buffer[i]) { 742 rc = -ENOMEM; 743 for (j = 0; j < rmu->msg_tx_ring.size; j++) 744 if (rmu->msg_tx_ring.virt_buffer[j]) 745 dma_free_coherent(priv->dev, 746 RIO_MSG_BUFFER_SIZE, 747 rmu->msg_tx_ring. 748 virt_buffer[j], 749 rmu->msg_tx_ring. 750 phys_buffer[j]); 751 goto out; 752 } 753 } 754 755 /* Initialize outbound message descriptor ring */ 756 rmu->msg_tx_ring.virt = dma_alloc_coherent(priv->dev, 757 rmu->msg_tx_ring.size * RIO_MSG_DESC_SIZE, 758 &rmu->msg_tx_ring.phys, 759 GFP_KERNEL); 760 if (!rmu->msg_tx_ring.virt) { 761 rc = -ENOMEM; 762 goto out_dma; 763 } 764 rmu->msg_tx_ring.tx_slot = 0; 765 766 /* Point dequeue/enqueue pointers at first entry in ring */ 767 out_be32(&rmu->msg_regs->odqdpar, rmu->msg_tx_ring.phys); 768 out_be32(&rmu->msg_regs->odqepar, rmu->msg_tx_ring.phys); 769 770 /* Configure for snooping */ 771 out_be32(&rmu->msg_regs->osar, 0x00000004); 772 773 /* Clear interrupt status */ 774 out_be32(&rmu->msg_regs->osr, 0x000000b3); 775 776 /* Hook up outbound message handler */ 777 rc = request_irq(IRQ_RIO_TX(mport), fsl_rio_tx_handler, 0, 778 "msg_tx", (void *)mport); 779 if (rc < 0) 780 goto out_irq; 781 782 /* 783 * Configure outbound message unit 784 * Snooping 785 * Interrupts (all enabled, except QEIE) 786 * Chaining mode 787 * Disable 788 */ 789 out_be32(&rmu->msg_regs->omr, 0x00100220); 790 791 /* Set number of entries */ 792 out_be32(&rmu->msg_regs->omr, 793 in_be32(&rmu->msg_regs->omr) | 794 ((get_bitmask_order(entries) - 2) << 12)); 795 796 /* Now enable the unit */ 797 out_be32(&rmu->msg_regs->omr, in_be32(&rmu->msg_regs->omr) | 0x1); 798 799 out: 800 return rc; 801 802 out_irq: 803 dma_free_coherent(priv->dev, 804 rmu->msg_tx_ring.size * RIO_MSG_DESC_SIZE, 805 rmu->msg_tx_ring.virt, rmu->msg_tx_ring.phys); 806 807 out_dma: 808 for (i = 0; i < rmu->msg_tx_ring.size; i++) 809 dma_free_coherent(priv->dev, RIO_MSG_BUFFER_SIZE, 810 rmu->msg_tx_ring.virt_buffer[i], 811 rmu->msg_tx_ring.phys_buffer[i]); 812 813 return rc; 814 } 815 816 /** 817 * fsl_close_outb_mbox - Shut down MPC85xx outbound mailbox 818 * @mport: Master port implementing the outbound message unit 819 * @mbox: Mailbox to close 820 * 821 * Disables the outbound message unit, free all buffers, and 822 * frees the outbound message interrupt. 823 */ 824 void fsl_close_outb_mbox(struct rio_mport *mport, int mbox) 825 { 826 struct rio_priv *priv = mport->priv; 827 struct fsl_rmu *rmu = GET_RMM_HANDLE(mport); 828 829 /* Disable inbound message unit */ 830 out_be32(&rmu->msg_regs->omr, 0); 831 832 /* Free ring */ 833 dma_free_coherent(priv->dev, 834 rmu->msg_tx_ring.size * RIO_MSG_DESC_SIZE, 835 rmu->msg_tx_ring.virt, rmu->msg_tx_ring.phys); 836 837 /* Free interrupt */ 838 free_irq(IRQ_RIO_TX(mport), (void *)mport); 839 } 840 841 /** 842 * fsl_open_inb_mbox - Initialize MPC85xx inbound mailbox 843 * @mport: Master port implementing the inbound message unit 844 * @dev_id: Device specific pointer to pass on event 845 * @mbox: Mailbox to open 846 * @entries: Number of entries in the inbound mailbox ring 847 * 848 * Initializes buffer ring, request the inbound message interrupt, 849 * and enables the inbound message unit. Returns %0 on success 850 * and %-EINVAL or %-ENOMEM on failure. 851 */ 852 int 853 fsl_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries) 854 { 855 int i, rc = 0; 856 struct rio_priv *priv = mport->priv; 857 struct fsl_rmu *rmu = GET_RMM_HANDLE(mport); 858 859 if ((entries < RIO_MIN_RX_RING_SIZE) || 860 (entries > RIO_MAX_RX_RING_SIZE) || (!is_power_of_2(entries))) { 861 rc = -EINVAL; 862 goto out; 863 } 864 865 /* Initialize client buffer ring */ 866 rmu->msg_rx_ring.dev_id = dev_id; 867 rmu->msg_rx_ring.size = entries; 868 rmu->msg_rx_ring.rx_slot = 0; 869 for (i = 0; i < rmu->msg_rx_ring.size; i++) 870 rmu->msg_rx_ring.virt_buffer[i] = NULL; 871 872 /* Initialize inbound message ring */ 873 rmu->msg_rx_ring.virt = dma_alloc_coherent(priv->dev, 874 rmu->msg_rx_ring.size * RIO_MAX_MSG_SIZE, 875 &rmu->msg_rx_ring.phys, GFP_KERNEL); 876 if (!rmu->msg_rx_ring.virt) { 877 rc = -ENOMEM; 878 goto out; 879 } 880 881 /* Point dequeue/enqueue pointers at first entry in ring */ 882 out_be32(&rmu->msg_regs->ifqdpar, (u32) rmu->msg_rx_ring.phys); 883 out_be32(&rmu->msg_regs->ifqepar, (u32) rmu->msg_rx_ring.phys); 884 885 /* Clear interrupt status */ 886 out_be32(&rmu->msg_regs->isr, 0x00000091); 887 888 /* Hook up inbound message handler */ 889 rc = request_irq(IRQ_RIO_RX(mport), fsl_rio_rx_handler, 0, 890 "msg_rx", (void *)mport); 891 if (rc < 0) { 892 dma_free_coherent(priv->dev, 893 rmu->msg_rx_ring.size * RIO_MAX_MSG_SIZE, 894 rmu->msg_rx_ring.virt, rmu->msg_rx_ring.phys); 895 goto out; 896 } 897 898 /* 899 * Configure inbound message unit: 900 * Snooping 901 * 4KB max message size 902 * Unmask all interrupt sources 903 * Disable 904 */ 905 out_be32(&rmu->msg_regs->imr, 0x001b0060); 906 907 /* Set number of queue entries */ 908 setbits32(&rmu->msg_regs->imr, (get_bitmask_order(entries) - 2) << 12); 909 910 /* Now enable the unit */ 911 setbits32(&rmu->msg_regs->imr, 0x1); 912 913 out: 914 return rc; 915 } 916 917 /** 918 * fsl_close_inb_mbox - Shut down MPC85xx inbound mailbox 919 * @mport: Master port implementing the inbound message unit 920 * @mbox: Mailbox to close 921 * 922 * Disables the inbound message unit, free all buffers, and 923 * frees the inbound message interrupt. 924 */ 925 void fsl_close_inb_mbox(struct rio_mport *mport, int mbox) 926 { 927 struct rio_priv *priv = mport->priv; 928 struct fsl_rmu *rmu = GET_RMM_HANDLE(mport); 929 930 /* Disable inbound message unit */ 931 out_be32(&rmu->msg_regs->imr, 0); 932 933 /* Free ring */ 934 dma_free_coherent(priv->dev, rmu->msg_rx_ring.size * RIO_MAX_MSG_SIZE, 935 rmu->msg_rx_ring.virt, rmu->msg_rx_ring.phys); 936 937 /* Free interrupt */ 938 free_irq(IRQ_RIO_RX(mport), (void *)mport); 939 } 940 941 /** 942 * fsl_add_inb_buffer - Add buffer to the MPC85xx inbound message queue 943 * @mport: Master port implementing the inbound message unit 944 * @mbox: Inbound mailbox number 945 * @buf: Buffer to add to inbound queue 946 * 947 * Adds the @buf buffer to the MPC85xx inbound message queue. Returns 948 * %0 on success or %-EINVAL on failure. 949 */ 950 int fsl_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf) 951 { 952 int rc = 0; 953 struct fsl_rmu *rmu = GET_RMM_HANDLE(mport); 954 955 pr_debug("RIO: fsl_add_inb_buffer(), msg_rx_ring.rx_slot %d\n", 956 rmu->msg_rx_ring.rx_slot); 957 958 if (rmu->msg_rx_ring.virt_buffer[rmu->msg_rx_ring.rx_slot]) { 959 printk(KERN_ERR 960 "RIO: error adding inbound buffer %d, buffer exists\n", 961 rmu->msg_rx_ring.rx_slot); 962 rc = -EINVAL; 963 goto out; 964 } 965 966 rmu->msg_rx_ring.virt_buffer[rmu->msg_rx_ring.rx_slot] = buf; 967 if (++rmu->msg_rx_ring.rx_slot == rmu->msg_rx_ring.size) 968 rmu->msg_rx_ring.rx_slot = 0; 969 970 out: 971 return rc; 972 } 973 974 /** 975 * fsl_get_inb_message - Fetch inbound message from the MPC85xx message unit 976 * @mport: Master port implementing the inbound message unit 977 * @mbox: Inbound mailbox number 978 * 979 * Gets the next available inbound message from the inbound message queue. 980 * A pointer to the message is returned on success or NULL on failure. 981 */ 982 void *fsl_get_inb_message(struct rio_mport *mport, int mbox) 983 { 984 struct fsl_rmu *rmu = GET_RMM_HANDLE(mport); 985 u32 phys_buf; 986 void *virt_buf; 987 void *buf = NULL; 988 int buf_idx; 989 990 phys_buf = in_be32(&rmu->msg_regs->ifqdpar); 991 992 /* If no more messages, then bail out */ 993 if (phys_buf == in_be32(&rmu->msg_regs->ifqepar)) 994 goto out2; 995 996 virt_buf = rmu->msg_rx_ring.virt + (phys_buf 997 - rmu->msg_rx_ring.phys); 998 buf_idx = (phys_buf - rmu->msg_rx_ring.phys) / RIO_MAX_MSG_SIZE; 999 buf = rmu->msg_rx_ring.virt_buffer[buf_idx]; 1000 1001 if (!buf) { 1002 printk(KERN_ERR 1003 "RIO: inbound message copy failed, no buffers\n"); 1004 goto out1; 1005 } 1006 1007 /* Copy max message size, caller is expected to allocate that big */ 1008 memcpy(buf, virt_buf, RIO_MAX_MSG_SIZE); 1009 1010 /* Clear the available buffer */ 1011 rmu->msg_rx_ring.virt_buffer[buf_idx] = NULL; 1012 1013 out1: 1014 setbits32(&rmu->msg_regs->imr, RIO_MSG_IMR_MI); 1015 1016 out2: 1017 return buf; 1018 } 1019 1020 /** 1021 * fsl_rio_doorbell_init - MPC85xx doorbell interface init 1022 * @mport: Master port implementing the inbound doorbell unit 1023 * 1024 * Initializes doorbell unit hardware and inbound DMA buffer 1025 * ring. Called from fsl_rio_setup(). Returns %0 on success 1026 * or %-ENOMEM on failure. 1027 */ 1028 int fsl_rio_doorbell_init(struct fsl_rio_dbell *dbell) 1029 { 1030 int rc = 0; 1031 1032 /* Initialize inbound doorbells */ 1033 dbell->dbell_ring.virt = dma_alloc_coherent(dbell->dev, 512 * 1034 DOORBELL_MESSAGE_SIZE, &dbell->dbell_ring.phys, GFP_KERNEL); 1035 if (!dbell->dbell_ring.virt) { 1036 printk(KERN_ERR "RIO: unable allocate inbound doorbell ring\n"); 1037 rc = -ENOMEM; 1038 goto out; 1039 } 1040 1041 /* Point dequeue/enqueue pointers at first entry in ring */ 1042 out_be32(&dbell->dbell_regs->dqdpar, (u32) dbell->dbell_ring.phys); 1043 out_be32(&dbell->dbell_regs->dqepar, (u32) dbell->dbell_ring.phys); 1044 1045 /* Clear interrupt status */ 1046 out_be32(&dbell->dbell_regs->dsr, 0x00000091); 1047 1048 /* Hook up doorbell handler */ 1049 rc = request_irq(IRQ_RIO_BELL(dbell), fsl_rio_dbell_handler, 0, 1050 "dbell_rx", (void *)dbell); 1051 if (rc < 0) { 1052 dma_free_coherent(dbell->dev, 512 * DOORBELL_MESSAGE_SIZE, 1053 dbell->dbell_ring.virt, dbell->dbell_ring.phys); 1054 printk(KERN_ERR 1055 "MPC85xx RIO: unable to request inbound doorbell irq"); 1056 goto out; 1057 } 1058 1059 /* Configure doorbells for snooping, 512 entries, and enable */ 1060 out_be32(&dbell->dbell_regs->dmr, 0x00108161); 1061 1062 out: 1063 return rc; 1064 } 1065 1066 int fsl_rio_setup_rmu(struct rio_mport *mport, struct device_node *node) 1067 { 1068 struct rio_priv *priv; 1069 struct fsl_rmu *rmu; 1070 u64 msg_start; 1071 1072 if (!mport || !mport->priv) 1073 return -EINVAL; 1074 1075 priv = mport->priv; 1076 1077 if (!node) { 1078 dev_warn(priv->dev, "Can't get %pOF property 'fsl,rmu'\n", 1079 priv->dev->of_node); 1080 return -EINVAL; 1081 } 1082 1083 rmu = kzalloc(sizeof(struct fsl_rmu), GFP_KERNEL); 1084 if (!rmu) 1085 return -ENOMEM; 1086 1087 if (of_property_read_reg(node, 0, &msg_start, NULL)) { 1088 pr_err("%pOF: unable to find 'reg' property of message-unit\n", 1089 node); 1090 kfree(rmu); 1091 return -ENOMEM; 1092 } 1093 rmu->msg_regs = (struct rio_msg_regs *) 1094 (rmu_regs_win + (u32)msg_start); 1095 1096 rmu->txirq = irq_of_parse_and_map(node, 0); 1097 rmu->rxirq = irq_of_parse_and_map(node, 1); 1098 printk(KERN_INFO "%pOF: txirq: %d, rxirq %d\n", 1099 node, rmu->txirq, rmu->rxirq); 1100 1101 priv->rmm_handle = rmu; 1102 1103 rio_init_dbell_res(&mport->riores[RIO_DOORBELL_RESOURCE], 0, 0xffff); 1104 rio_init_mbox_res(&mport->riores[RIO_INB_MBOX_RESOURCE], 0, 0); 1105 rio_init_mbox_res(&mport->riores[RIO_OUTB_MBOX_RESOURCE], 0, 0); 1106 1107 return 0; 1108 } 1109