1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 4 * Copyright (C) 2011-2012 John Crispin <john@phrozen.org> 5 * Copyright (C) 2013-2015 Lantiq Beteiligungs-GmbH & Co.KG 6 */ 7 8 #include <linux/ioport.h> 9 #include <linux/export.h> 10 #include <linux/clkdev.h> 11 #include <linux/spinlock.h> 12 #include <linux/of.h> 13 #include <linux/of_platform.h> 14 #include <linux/of_address.h> 15 16 #include <lantiq_soc.h> 17 18 #include "../clk.h" 19 #include "../prom.h" 20 21 /* clock control register for legacy */ 22 #define CGU_IFCCR 0x0018 23 #define CGU_IFCCR_VR9 0x0024 24 /* system clock register for legacy */ 25 #define CGU_SYS 0x0010 26 /* pci control register */ 27 #define CGU_PCICR 0x0034 28 #define CGU_PCICR_VR9 0x0038 29 /* ephy configuration register */ 30 #define CGU_EPHY 0x10 31 32 /* Legacy PMU register for ar9, ase, danube */ 33 /* power control register */ 34 #define PMU_PWDCR 0x1C 35 /* power status register */ 36 #define PMU_PWDSR 0x20 37 /* power control register */ 38 #define PMU_PWDCR1 0x24 39 /* power status register */ 40 #define PMU_PWDSR1 0x28 41 /* power control register */ 42 #define PWDCR(x) ((x) ? (PMU_PWDCR1) : (PMU_PWDCR)) 43 /* power status register */ 44 #define PWDSR(x) ((x) ? (PMU_PWDSR1) : (PMU_PWDSR)) 45 46 47 /* PMU register for ar10 and grx390 */ 48 49 /* First register set */ 50 #define PMU_CLK_SR 0x20 /* status */ 51 #define PMU_CLK_CR_A 0x24 /* Enable */ 52 #define PMU_CLK_CR_B 0x28 /* Disable */ 53 /* Second register set */ 54 #define PMU_CLK_SR1 0x30 /* status */ 55 #define PMU_CLK_CR1_A 0x34 /* Enable */ 56 #define PMU_CLK_CR1_B 0x38 /* Disable */ 57 /* Third register set */ 58 #define PMU_ANA_SR 0x40 /* status */ 59 #define PMU_ANA_CR_A 0x44 /* Enable */ 60 #define PMU_ANA_CR_B 0x48 /* Disable */ 61 62 /* Status */ 63 static u32 pmu_clk_sr[] = { 64 PMU_CLK_SR, 65 PMU_CLK_SR1, 66 PMU_ANA_SR, 67 }; 68 69 /* Enable */ 70 static u32 pmu_clk_cr_a[] = { 71 PMU_CLK_CR_A, 72 PMU_CLK_CR1_A, 73 PMU_ANA_CR_A, 74 }; 75 76 /* Disable */ 77 static u32 pmu_clk_cr_b[] = { 78 PMU_CLK_CR_B, 79 PMU_CLK_CR1_B, 80 PMU_ANA_CR_B, 81 }; 82 83 #define PWDCR_EN_XRX(x) (pmu_clk_cr_a[(x)]) 84 #define PWDCR_DIS_XRX(x) (pmu_clk_cr_b[(x)]) 85 #define PWDSR_XRX(x) (pmu_clk_sr[(x)]) 86 87 /* clock gates that we can en/disable */ 88 #define PMU_USB0_P BIT(0) 89 #define PMU_ASE_SDIO BIT(2) /* ASE special */ 90 #define PMU_PCI BIT(4) 91 #define PMU_DMA BIT(5) 92 #define PMU_USB0 BIT(6) 93 #define PMU_ASC0 BIT(7) 94 #define PMU_EPHY BIT(7) /* ase */ 95 #define PMU_USIF BIT(7) /* from vr9 until grx390 */ 96 #define PMU_SPI BIT(8) 97 #define PMU_DFE BIT(9) 98 #define PMU_EBU BIT(10) 99 #define PMU_STP BIT(11) 100 #define PMU_GPT BIT(12) 101 #define PMU_AHBS BIT(13) /* vr9 */ 102 #define PMU_FPI BIT(14) 103 #define PMU_AHBM BIT(15) 104 #define PMU_SDIO BIT(16) /* danube, ar9, vr9 */ 105 #define PMU_ASC1 BIT(17) 106 #define PMU_PPE_QSB BIT(18) 107 #define PMU_PPE_SLL01 BIT(19) 108 #define PMU_DEU BIT(20) 109 #define PMU_PPE_TC BIT(21) 110 #define PMU_PPE_EMA BIT(22) 111 #define PMU_PPE_DPLUM BIT(23) 112 #define PMU_PPE_DP BIT(23) 113 #define PMU_PPE_DPLUS BIT(24) 114 #define PMU_USB1_P BIT(26) 115 #define PMU_GPHY3 BIT(26) /* grx390 */ 116 #define PMU_USB1 BIT(27) 117 #define PMU_SWITCH BIT(28) 118 #define PMU_PPE_TOP BIT(29) 119 #define PMU_GPHY0 BIT(29) /* ar10, xrx390 */ 120 #define PMU_GPHY BIT(30) 121 #define PMU_GPHY1 BIT(30) /* ar10, xrx390 */ 122 #define PMU_PCIE_CLK BIT(31) 123 #define PMU_GPHY2 BIT(31) /* ar10, xrx390 */ 124 125 #define PMU1_PCIE_PHY BIT(0) /* vr9-specific,moved in ar10/grx390 */ 126 #define PMU1_PCIE_CTL BIT(1) 127 #define PMU1_PCIE_PDI BIT(4) 128 #define PMU1_PCIE_MSI BIT(5) 129 #define PMU1_CKE BIT(6) 130 #define PMU1_PCIE1_CTL BIT(17) 131 #define PMU1_PCIE1_PDI BIT(20) 132 #define PMU1_PCIE1_MSI BIT(21) 133 #define PMU1_PCIE2_CTL BIT(25) 134 #define PMU1_PCIE2_PDI BIT(26) 135 #define PMU1_PCIE2_MSI BIT(27) 136 137 #define PMU_ANALOG_USB0_P BIT(0) 138 #define PMU_ANALOG_USB1_P BIT(1) 139 #define PMU_ANALOG_PCIE0_P BIT(8) 140 #define PMU_ANALOG_PCIE1_P BIT(9) 141 #define PMU_ANALOG_PCIE2_P BIT(10) 142 #define PMU_ANALOG_DSL_AFE BIT(16) 143 #define PMU_ANALOG_DCDC_2V5 BIT(17) 144 #define PMU_ANALOG_DCDC_1VX BIT(18) 145 #define PMU_ANALOG_DCDC_1V0 BIT(19) 146 147 #define pmu_w32(x, y) ltq_w32((x), pmu_membase + (y)) 148 #define pmu_r32(x) ltq_r32(pmu_membase + (x)) 149 150 static void __iomem *pmu_membase; 151 void __iomem *ltq_cgu_membase; 152 void __iomem *ltq_ebu_membase; 153 154 static u32 ifccr = CGU_IFCCR; 155 static u32 pcicr = CGU_PCICR; 156 157 static DEFINE_SPINLOCK(g_pmu_lock); 158 159 /* legacy function kept alive to ease clkdev transition */ 160 void ltq_pmu_enable(unsigned int module) 161 { 162 int retry = 1000000; 163 164 spin_lock(&g_pmu_lock); 165 pmu_w32(pmu_r32(PMU_PWDCR) & ~module, PMU_PWDCR); 166 do {} while (--retry && (pmu_r32(PMU_PWDSR) & module)); 167 spin_unlock(&g_pmu_lock); 168 169 if (!retry) 170 panic("activating PMU module failed!"); 171 } 172 EXPORT_SYMBOL(ltq_pmu_enable); 173 174 /* legacy function kept alive to ease clkdev transition */ 175 void ltq_pmu_disable(unsigned int module) 176 { 177 int retry = 1000000; 178 179 spin_lock(&g_pmu_lock); 180 pmu_w32(pmu_r32(PMU_PWDCR) | module, PMU_PWDCR); 181 do {} while (--retry && (!(pmu_r32(PMU_PWDSR) & module))); 182 spin_unlock(&g_pmu_lock); 183 184 if (!retry) 185 pr_warn("deactivating PMU module failed!"); 186 } 187 EXPORT_SYMBOL(ltq_pmu_disable); 188 189 /* enable a hw clock */ 190 static int cgu_enable(struct clk *clk) 191 { 192 ltq_cgu_w32(ltq_cgu_r32(ifccr) | clk->bits, ifccr); 193 return 0; 194 } 195 196 /* disable a hw clock */ 197 static void cgu_disable(struct clk *clk) 198 { 199 ltq_cgu_w32(ltq_cgu_r32(ifccr) & ~clk->bits, ifccr); 200 } 201 202 /* enable a clock gate */ 203 static int pmu_enable(struct clk *clk) 204 { 205 int retry = 1000000; 206 207 if (of_machine_is_compatible("lantiq,ar10") 208 || of_machine_is_compatible("lantiq,grx390")) { 209 pmu_w32(clk->bits, PWDCR_EN_XRX(clk->module)); 210 do {} while (--retry && 211 (!(pmu_r32(PWDSR_XRX(clk->module)) & clk->bits))); 212 213 } else { 214 spin_lock(&g_pmu_lock); 215 pmu_w32(pmu_r32(PWDCR(clk->module)) & ~clk->bits, 216 PWDCR(clk->module)); 217 do {} while (--retry && 218 (pmu_r32(PWDSR(clk->module)) & clk->bits)); 219 spin_unlock(&g_pmu_lock); 220 } 221 222 if (!retry) 223 panic("activating PMU module failed!"); 224 225 return 0; 226 } 227 228 /* disable a clock gate */ 229 static void pmu_disable(struct clk *clk) 230 { 231 int retry = 1000000; 232 233 if (of_machine_is_compatible("lantiq,ar10") 234 || of_machine_is_compatible("lantiq,grx390")) { 235 pmu_w32(clk->bits, PWDCR_DIS_XRX(clk->module)); 236 do {} while (--retry && 237 (pmu_r32(PWDSR_XRX(clk->module)) & clk->bits)); 238 } else { 239 spin_lock(&g_pmu_lock); 240 pmu_w32(pmu_r32(PWDCR(clk->module)) | clk->bits, 241 PWDCR(clk->module)); 242 do {} while (--retry && 243 (!(pmu_r32(PWDSR(clk->module)) & clk->bits))); 244 spin_unlock(&g_pmu_lock); 245 } 246 247 if (!retry) 248 pr_warn("deactivating PMU module failed!"); 249 } 250 251 /* the pci enable helper */ 252 static int pci_enable(struct clk *clk) 253 { 254 unsigned int val = ltq_cgu_r32(ifccr); 255 /* set bus clock speed */ 256 if (of_machine_is_compatible("lantiq,ar9") || 257 of_machine_is_compatible("lantiq,vr9")) { 258 val &= ~0x1f00000; 259 if (clk->rate == CLOCK_33M) 260 val |= 0xe00000; 261 else 262 val |= 0x700000; /* 62.5M */ 263 } else { 264 val &= ~0xf00000; 265 if (clk->rate == CLOCK_33M) 266 val |= 0x800000; 267 else 268 val |= 0x400000; /* 62.5M */ 269 } 270 ltq_cgu_w32(val, ifccr); 271 pmu_enable(clk); 272 return 0; 273 } 274 275 /* enable the external clock as a source */ 276 static int pci_ext_enable(struct clk *clk) 277 { 278 ltq_cgu_w32(ltq_cgu_r32(ifccr) & ~(1 << 16), ifccr); 279 ltq_cgu_w32((1 << 30), pcicr); 280 return 0; 281 } 282 283 /* disable the external clock as a source */ 284 static void pci_ext_disable(struct clk *clk) 285 { 286 ltq_cgu_w32(ltq_cgu_r32(ifccr) | (1 << 16), ifccr); 287 ltq_cgu_w32((1 << 31) | (1 << 30), pcicr); 288 } 289 290 /* enable a clockout source */ 291 static int clkout_enable(struct clk *clk) 292 { 293 int i; 294 295 /* get the correct rate */ 296 for (i = 0; i < 4; i++) { 297 if (clk->rates[i] == clk->rate) { 298 int shift = 14 - (2 * clk->module); 299 int enable = 7 - clk->module; 300 unsigned int val = ltq_cgu_r32(ifccr); 301 302 val &= ~(3 << shift); 303 val |= i << shift; 304 val |= enable; 305 ltq_cgu_w32(val, ifccr); 306 return 0; 307 } 308 } 309 return -1; 310 } 311 312 /* manage the clock gates via PMU */ 313 static void clkdev_add_pmu(const char *dev, const char *con, bool deactivate, 314 unsigned int module, unsigned int bits) 315 { 316 struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); 317 318 clk->cl.dev_id = dev; 319 clk->cl.con_id = con; 320 clk->cl.clk = clk; 321 clk->enable = pmu_enable; 322 clk->disable = pmu_disable; 323 clk->module = module; 324 clk->bits = bits; 325 if (deactivate) { 326 /* 327 * Disable it during the initialization. Module should enable 328 * when used 329 */ 330 pmu_disable(clk); 331 } 332 clkdev_add(&clk->cl); 333 } 334 335 /* manage the clock generator */ 336 static void clkdev_add_cgu(const char *dev, const char *con, 337 unsigned int bits) 338 { 339 struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); 340 341 clk->cl.dev_id = dev; 342 clk->cl.con_id = con; 343 clk->cl.clk = clk; 344 clk->enable = cgu_enable; 345 clk->disable = cgu_disable; 346 clk->bits = bits; 347 clkdev_add(&clk->cl); 348 } 349 350 /* pci needs its own enable function as the setup is a bit more complex */ 351 static unsigned long valid_pci_rates[] = {CLOCK_33M, CLOCK_62_5M, 0}; 352 353 static void clkdev_add_pci(void) 354 { 355 struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); 356 struct clk *clk_ext = kzalloc(sizeof(struct clk), GFP_KERNEL); 357 358 /* main pci clock */ 359 clk->cl.dev_id = "17000000.pci"; 360 clk->cl.con_id = NULL; 361 clk->cl.clk = clk; 362 clk->rate = CLOCK_33M; 363 clk->rates = valid_pci_rates; 364 clk->enable = pci_enable; 365 clk->disable = pmu_disable; 366 clk->module = 0; 367 clk->bits = PMU_PCI; 368 clkdev_add(&clk->cl); 369 370 /* use internal/external bus clock */ 371 clk_ext->cl.dev_id = "17000000.pci"; 372 clk_ext->cl.con_id = "external"; 373 clk_ext->cl.clk = clk_ext; 374 clk_ext->enable = pci_ext_enable; 375 clk_ext->disable = pci_ext_disable; 376 clkdev_add(&clk_ext->cl); 377 } 378 379 /* xway socs can generate clocks on gpio pins */ 380 static unsigned long valid_clkout_rates[4][5] = { 381 {CLOCK_32_768K, CLOCK_1_536M, CLOCK_2_5M, CLOCK_12M, 0}, 382 {CLOCK_40M, CLOCK_12M, CLOCK_24M, CLOCK_48M, 0}, 383 {CLOCK_25M, CLOCK_40M, CLOCK_30M, CLOCK_60M, 0}, 384 {CLOCK_12M, CLOCK_50M, CLOCK_32_768K, CLOCK_25M, 0}, 385 }; 386 387 static void clkdev_add_clkout(void) 388 { 389 int i; 390 391 for (i = 0; i < 4; i++) { 392 struct clk *clk; 393 char *name; 394 395 name = kzalloc(sizeof("clkout0"), GFP_KERNEL); 396 sprintf(name, "clkout%d", i); 397 398 clk = kzalloc(sizeof(struct clk), GFP_KERNEL); 399 clk->cl.dev_id = "1f103000.cgu"; 400 clk->cl.con_id = name; 401 clk->cl.clk = clk; 402 clk->rate = 0; 403 clk->rates = valid_clkout_rates[i]; 404 clk->enable = clkout_enable; 405 clk->module = i; 406 clkdev_add(&clk->cl); 407 } 408 } 409 410 /* bring up all register ranges that we need for basic system control */ 411 void __init ltq_soc_init(void) 412 { 413 struct resource res_pmu, res_cgu, res_ebu; 414 struct device_node *np_pmu = 415 of_find_compatible_node(NULL, NULL, "lantiq,pmu-xway"); 416 struct device_node *np_cgu = 417 of_find_compatible_node(NULL, NULL, "lantiq,cgu-xway"); 418 struct device_node *np_ebu = 419 of_find_compatible_node(NULL, NULL, "lantiq,ebu-xway"); 420 421 /* check if all the core register ranges are available */ 422 if (!np_pmu || !np_cgu || !np_ebu) 423 panic("Failed to load core nodes from devicetree"); 424 425 if (of_address_to_resource(np_pmu, 0, &res_pmu) || 426 of_address_to_resource(np_cgu, 0, &res_cgu) || 427 of_address_to_resource(np_ebu, 0, &res_ebu)) 428 panic("Failed to get core resources"); 429 430 if (!request_mem_region(res_pmu.start, resource_size(&res_pmu), 431 res_pmu.name) || 432 !request_mem_region(res_cgu.start, resource_size(&res_cgu), 433 res_cgu.name) || 434 !request_mem_region(res_ebu.start, resource_size(&res_ebu), 435 res_ebu.name)) 436 pr_err("Failed to request core resources"); 437 438 pmu_membase = ioremap(res_pmu.start, resource_size(&res_pmu)); 439 ltq_cgu_membase = ioremap(res_cgu.start, 440 resource_size(&res_cgu)); 441 ltq_ebu_membase = ioremap(res_ebu.start, 442 resource_size(&res_ebu)); 443 if (!pmu_membase || !ltq_cgu_membase || !ltq_ebu_membase) 444 panic("Failed to remap core resources"); 445 446 /* make sure to unprotect the memory region where flash is located */ 447 ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0); 448 449 /* add our generic xway clocks */ 450 clkdev_add_pmu("10000000.fpi", NULL, 0, 0, PMU_FPI); 451 clkdev_add_pmu("1e100a00.gptu", NULL, 1, 0, PMU_GPT); 452 clkdev_add_pmu("1e100bb0.stp", NULL, 1, 0, PMU_STP); 453 clkdev_add_pmu("1e100c00.serial", NULL, 0, 0, PMU_ASC1); 454 clkdev_add_pmu("1e104100.dma", NULL, 1, 0, PMU_DMA); 455 clkdev_add_pmu("1e100800.spi", NULL, 1, 0, PMU_SPI); 456 clkdev_add_pmu("1e105300.ebu", NULL, 0, 0, PMU_EBU); 457 clkdev_add_clkout(); 458 459 /* add the soc dependent clocks */ 460 if (of_machine_is_compatible("lantiq,vr9")) { 461 ifccr = CGU_IFCCR_VR9; 462 pcicr = CGU_PCICR_VR9; 463 } else { 464 clkdev_add_pmu("1e180000.etop", NULL, 1, 0, PMU_PPE); 465 } 466 467 if (!of_machine_is_compatible("lantiq,ase")) 468 clkdev_add_pci(); 469 470 if (of_machine_is_compatible("lantiq,grx390") || 471 of_machine_is_compatible("lantiq,ar10")) { 472 clkdev_add_pmu("1e108000.switch", "gphy0", 0, 0, PMU_GPHY0); 473 clkdev_add_pmu("1e108000.switch", "gphy1", 0, 0, PMU_GPHY1); 474 clkdev_add_pmu("1e108000.switch", "gphy2", 0, 0, PMU_GPHY2); 475 clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 2, PMU_ANALOG_USB0_P); 476 clkdev_add_pmu("1f203034.usb2-phy", "phy", 1, 2, PMU_ANALOG_USB1_P); 477 /* rc 0 */ 478 clkdev_add_pmu("1f106800.phy", "phy", 1, 2, PMU_ANALOG_PCIE0_P); 479 clkdev_add_pmu("1d900000.pcie", "msi", 1, 1, PMU1_PCIE_MSI); 480 clkdev_add_pmu("1f106800.phy", "pdi", 1, 1, PMU1_PCIE_PDI); 481 clkdev_add_pmu("1d900000.pcie", "ctl", 1, 1, PMU1_PCIE_CTL); 482 /* rc 1 */ 483 clkdev_add_pmu("1f700400.phy", "phy", 1, 2, PMU_ANALOG_PCIE1_P); 484 clkdev_add_pmu("19000000.pcie", "msi", 1, 1, PMU1_PCIE1_MSI); 485 clkdev_add_pmu("1f700400.phy", "pdi", 1, 1, PMU1_PCIE1_PDI); 486 clkdev_add_pmu("19000000.pcie", "ctl", 1, 1, PMU1_PCIE1_CTL); 487 } 488 489 if (of_machine_is_compatible("lantiq,ase")) { 490 if (ltq_cgu_r32(CGU_SYS) & (1 << 5)) 491 clkdev_add_static(CLOCK_266M, CLOCK_133M, 492 CLOCK_133M, CLOCK_266M); 493 else 494 clkdev_add_static(CLOCK_133M, CLOCK_133M, 495 CLOCK_133M, CLOCK_133M); 496 clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0); 497 clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P); 498 clkdev_add_pmu("1e180000.etop", "ppe", 1, 0, PMU_PPE); 499 clkdev_add_cgu("1e180000.etop", "ephycgu", CGU_EPHY); 500 clkdev_add_pmu("1e180000.etop", "ephy", 1, 0, PMU_EPHY); 501 clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_ASE_SDIO); 502 clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE); 503 } else if (of_machine_is_compatible("lantiq,grx390")) { 504 clkdev_add_static(ltq_grx390_cpu_hz(), ltq_grx390_fpi_hz(), 505 ltq_grx390_fpi_hz(), ltq_grx390_pp32_hz()); 506 clkdev_add_pmu("1e108000.switch", "gphy3", 0, 0, PMU_GPHY3); 507 clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0); 508 clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1); 509 /* rc 2 */ 510 clkdev_add_pmu("1f106a00.pcie", "phy", 1, 2, PMU_ANALOG_PCIE2_P); 511 clkdev_add_pmu("1a800000.pcie", "msi", 1, 1, PMU1_PCIE2_MSI); 512 clkdev_add_pmu("1f106a00.pcie", "pdi", 1, 1, PMU1_PCIE2_PDI); 513 clkdev_add_pmu("1a800000.pcie", "ctl", 1, 1, PMU1_PCIE2_CTL); 514 clkdev_add_pmu("1e10b308.eth", NULL, 0, 0, PMU_SWITCH | PMU_PPE_DP); 515 clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF); 516 clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU); 517 } else if (of_machine_is_compatible("lantiq,ar10")) { 518 clkdev_add_static(ltq_ar10_cpu_hz(), ltq_ar10_fpi_hz(), 519 ltq_ar10_fpi_hz(), ltq_ar10_pp32_hz()); 520 clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0); 521 clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1); 522 clkdev_add_pmu("1e10b308.eth", NULL, 0, 0, PMU_SWITCH | 523 PMU_PPE_DP | PMU_PPE_TC); 524 clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF); 525 clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU); 526 clkdev_add_pmu("1e116000.mei", "afe", 1, 2, PMU_ANALOG_DSL_AFE); 527 clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE); 528 } else if (of_machine_is_compatible("lantiq,vr9")) { 529 clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(), 530 ltq_vr9_fpi_hz(), ltq_vr9_pp32_hz()); 531 clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P); 532 clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0 | PMU_AHBM); 533 clkdev_add_pmu("1f203034.usb2-phy", "phy", 1, 0, PMU_USB1_P); 534 clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1 | PMU_AHBM); 535 clkdev_add_pmu("1f106800.phy", "phy", 1, 1, PMU1_PCIE_PHY); 536 clkdev_add_pmu("1d900000.pcie", "bus", 1, 0, PMU_PCIE_CLK); 537 clkdev_add_pmu("1d900000.pcie", "msi", 1, 1, PMU1_PCIE_MSI); 538 clkdev_add_pmu("1f106800.phy", "pdi", 1, 1, PMU1_PCIE_PDI); 539 clkdev_add_pmu("1d900000.pcie", "ctl", 1, 1, PMU1_PCIE_CTL); 540 clkdev_add_pmu(NULL, "ahb", 1, 0, PMU_AHBM | PMU_AHBS); 541 542 clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF); 543 clkdev_add_pmu("1e10b308.eth", NULL, 0, 0, 544 PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM | 545 PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 | 546 PMU_PPE_QSB | PMU_PPE_TOP); 547 clkdev_add_pmu("1e108000.switch", "gphy0", 0, 0, PMU_GPHY); 548 clkdev_add_pmu("1e108000.switch", "gphy1", 0, 0, PMU_GPHY); 549 clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO); 550 clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU); 551 clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE); 552 } else if (of_machine_is_compatible("lantiq,ar9")) { 553 clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(), 554 ltq_ar9_fpi_hz(), CLOCK_250M); 555 clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P); 556 clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0 | PMU_AHBM); 557 clkdev_add_pmu("1f203034.usb2-phy", "phy", 1, 0, PMU_USB1_P); 558 clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1 | PMU_AHBM); 559 clkdev_add_pmu("1e180000.etop", "switch", 1, 0, PMU_SWITCH); 560 clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO); 561 clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU); 562 clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE); 563 clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0); 564 } else { 565 clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(), 566 ltq_danube_fpi_hz(), ltq_danube_pp32_hz()); 567 clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0 | PMU_AHBM); 568 clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P); 569 clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO); 570 clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU); 571 clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE); 572 clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0); 573 } 574 } 575