1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2020 NXP
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/phy/phy-imx8-pcie.h>
9#include <dt-bindings/usb/pd.h>
10#include "imx8mm.dtsi"
11
12/ {
13	chosen {
14		stdout-path = &uart2;
15	};
16
17	memory@40000000 {
18		device_type = "memory";
19		reg = <0x0 0x40000000 0 0x80000000>;
20	};
21
22	hdmi-connector {
23		compatible = "hdmi-connector";
24		label = "hdmi";
25		type = "a";
26
27		port {
28			hdmi_connector_in: endpoint {
29				remote-endpoint = <&adv7533_out>;
30			};
31		};
32	};
33
34	leds {
35		compatible = "gpio-leds";
36		pinctrl-names = "default";
37		pinctrl-0 = <&pinctrl_gpio_led>;
38
39		status {
40			label = "status";
41			gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
42			default-state = "on";
43		};
44	};
45
46	pcie0_refclk: pcie0-refclk {
47		compatible = "fixed-clock";
48		#clock-cells = <0>;
49		clock-frequency = <100000000>;
50	};
51
52	reg_pcie0: regulator-pcie {
53		compatible = "regulator-fixed";
54		pinctrl-names = "default";
55		pinctrl-0 = <&pinctrl_pcie0_reg>;
56		regulator-name = "MPCIE_3V3";
57		regulator-min-microvolt = <3300000>;
58		regulator-max-microvolt = <3300000>;
59		gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
60		enable-active-high;
61	};
62
63	reg_usdhc2_vmmc: regulator-usdhc2 {
64		compatible = "regulator-fixed";
65		pinctrl-names = "default";
66		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
67		regulator-name = "VSD_3V3";
68		regulator-min-microvolt = <3300000>;
69		regulator-max-microvolt = <3300000>;
70		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
71		off-on-delay-us = <20000>;
72		enable-active-high;
73	};
74
75	backlight: backlight {
76		compatible = "pwm-backlight";
77		pwms = <&pwm1 0 5000000 0>;
78		brightness-levels = <0 255>;
79		num-interpolated-steps = <255>;
80		default-brightness-level = <250>;
81	};
82
83	ir-receiver {
84		compatible = "gpio-ir-receiver";
85		gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
86		pinctrl-names = "default";
87		pinctrl-0 = <&pinctrl_ir>;
88		linux,autosuspend-period = <125>;
89	};
90
91	audio_codec_bt_sco: audio-codec-bt-sco {
92		compatible = "linux,bt-sco";
93		#sound-dai-cells = <1>;
94	};
95
96	wm8524: audio-codec {
97		#sound-dai-cells = <0>;
98		compatible = "wlf,wm8524";
99		pinctrl-names = "default";
100		pinctrl-0 = <&pinctrl_gpio_wlf>;
101		wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
102	};
103
104	sound-bt-sco {
105		compatible = "simple-audio-card";
106		simple-audio-card,name = "bt-sco-audio";
107		simple-audio-card,format = "dsp_a";
108		simple-audio-card,bitclock-inversion;
109		simple-audio-card,frame-master = <&btcpu>;
110		simple-audio-card,bitclock-master = <&btcpu>;
111
112		btcpu: simple-audio-card,cpu {
113			sound-dai = <&sai2>;
114			dai-tdm-slot-num = <2>;
115			dai-tdm-slot-width = <16>;
116		};
117
118		simple-audio-card,codec {
119			sound-dai = <&audio_codec_bt_sco 1>;
120		};
121	};
122
123	sound-wm8524 {
124		compatible = "simple-audio-card";
125		simple-audio-card,name = "wm8524-audio";
126		simple-audio-card,format = "i2s";
127		simple-audio-card,frame-master = <&cpudai>;
128		simple-audio-card,bitclock-master = <&cpudai>;
129		simple-audio-card,widgets =
130			"Line", "Left Line Out Jack",
131			"Line", "Right Line Out Jack";
132		simple-audio-card,routing =
133			"Left Line Out Jack", "LINEVOUTL",
134			"Right Line Out Jack", "LINEVOUTR";
135
136		cpudai: simple-audio-card,cpu {
137			sound-dai = <&sai3>;
138			dai-tdm-slot-num = <2>;
139			dai-tdm-slot-width = <32>;
140		};
141
142		simple-audio-card,codec {
143			sound-dai = <&wm8524>;
144			clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
145		};
146	};
147};
148
149&A53_0 {
150	cpu-supply = <&buck2_reg>;
151};
152
153&A53_1 {
154	cpu-supply = <&buck2_reg>;
155};
156
157&A53_2 {
158	cpu-supply = <&buck2_reg>;
159};
160
161&A53_3 {
162	cpu-supply = <&buck2_reg>;
163};
164
165&fec1 {
166	pinctrl-names = "default";
167	pinctrl-0 = <&pinctrl_fec1>;
168	phy-mode = "rgmii-id";
169	phy-handle = <&ethphy0>;
170	fsl,magic-packet;
171	status = "okay";
172
173	mdio {
174		#address-cells = <1>;
175		#size-cells = <0>;
176
177		ethphy0: ethernet-phy@0 {
178			compatible = "ethernet-phy-ieee802.3-c22";
179			reg = <0>;
180			reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
181			reset-assert-us = <10000>;
182			qca,disable-smarteee;
183			vddio-supply = <&vddio>;
184
185			vddio: vddio-regulator {
186				regulator-min-microvolt = <1800000>;
187				regulator-max-microvolt = <1800000>;
188			};
189		};
190	};
191};
192
193&i2c1 {
194	clock-frequency = <400000>;
195	pinctrl-names = "default";
196	pinctrl-0 = <&pinctrl_i2c1>;
197	status = "okay";
198
199	pmic@4b {
200		compatible = "rohm,bd71847";
201		reg = <0x4b>;
202		pinctrl-names = "default";
203		pinctrl-0 = <&pinctrl_pmic>;
204		interrupt-parent = <&gpio1>;
205		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
206		rohm,reset-snvs-powered;
207
208		#clock-cells = <0>;
209		clocks = <&osc_32k>;
210		clock-output-names = "clk-32k-out";
211
212		regulators {
213			buck1_reg: BUCK1 {
214				regulator-name = "buck1";
215				regulator-min-microvolt = <700000>;
216				regulator-max-microvolt = <1300000>;
217				regulator-boot-on;
218				regulator-always-on;
219				regulator-ramp-delay = <1250>;
220			};
221
222			buck2_reg: BUCK2 {
223				regulator-name = "buck2";
224				regulator-min-microvolt = <700000>;
225				regulator-max-microvolt = <1300000>;
226				regulator-boot-on;
227				regulator-always-on;
228				regulator-ramp-delay = <1250>;
229				rohm,dvs-run-voltage = <1000000>;
230				rohm,dvs-idle-voltage = <900000>;
231			};
232
233			buck3_reg: BUCK3 {
234				// BUCK5 in datasheet
235				regulator-name = "buck3";
236				regulator-min-microvolt = <700000>;
237				regulator-max-microvolt = <1350000>;
238				regulator-boot-on;
239				regulator-always-on;
240			};
241
242			buck4_reg: BUCK4 {
243				// BUCK6 in datasheet
244				regulator-name = "buck4";
245				regulator-min-microvolt = <3000000>;
246				regulator-max-microvolt = <3300000>;
247				regulator-boot-on;
248				regulator-always-on;
249			};
250
251			buck5_reg: BUCK5 {
252				// BUCK7 in datasheet
253				regulator-name = "buck5";
254				regulator-min-microvolt = <1605000>;
255				regulator-max-microvolt = <1995000>;
256				regulator-boot-on;
257				regulator-always-on;
258			};
259
260			buck6_reg: BUCK6 {
261				// BUCK8 in datasheet
262				regulator-name = "buck6";
263				regulator-min-microvolt = <800000>;
264				regulator-max-microvolt = <1400000>;
265				regulator-boot-on;
266				regulator-always-on;
267			};
268
269			ldo1_reg: LDO1 {
270				regulator-name = "ldo1";
271				regulator-min-microvolt = <1600000>;
272				regulator-max-microvolt = <3300000>;
273				regulator-boot-on;
274				regulator-always-on;
275			};
276
277			ldo2_reg: LDO2 {
278				regulator-name = "ldo2";
279				regulator-min-microvolt = <800000>;
280				regulator-max-microvolt = <900000>;
281				regulator-boot-on;
282				regulator-always-on;
283			};
284
285			ldo3_reg: LDO3 {
286				regulator-name = "ldo3";
287				regulator-min-microvolt = <1800000>;
288				regulator-max-microvolt = <3300000>;
289				regulator-boot-on;
290				regulator-always-on;
291			};
292
293			ldo4_reg: LDO4 {
294				regulator-name = "ldo4";
295				regulator-min-microvolt = <900000>;
296				regulator-max-microvolt = <1800000>;
297				regulator-boot-on;
298				regulator-always-on;
299			};
300
301			ldo6_reg: LDO6 {
302				regulator-name = "ldo6";
303				regulator-min-microvolt = <900000>;
304				regulator-max-microvolt = <1800000>;
305				regulator-boot-on;
306				regulator-always-on;
307			};
308		};
309	};
310};
311
312&i2c2 {
313	clock-frequency = <400000>;
314	pinctrl-names = "default";
315	pinctrl-0 = <&pinctrl_i2c2>;
316	status = "okay";
317
318	hdmi@3d {
319		compatible = "adi,adv7535";
320		reg = <0x3d>, <0x3c>, <0x3e>, <0x3f>;
321		reg-names = "main", "cec", "edid", "packet";
322		adi,dsi-lanes = <4>;
323
324		adi,input-depth = <8>;
325		adi,input-colorspace = "rgb";
326		adi,input-clock = "1x";
327		adi,input-style = <1>;
328		adi,input-justification = "evenly";
329
330		ports {
331			#address-cells = <1>;
332			#size-cells = <0>;
333
334			port@0 {
335				reg = <0>;
336
337				adv7533_in: endpoint {
338					remote-endpoint = <&dsi_out>;
339				};
340			};
341
342			port@1 {
343				reg = <1>;
344
345				adv7533_out: endpoint {
346					remote-endpoint = <&hdmi_connector_in>;
347				};
348			};
349
350		};
351	};
352
353	ptn5110: tcpc@50 {
354		compatible = "nxp,ptn5110";
355		pinctrl-names = "default";
356		pinctrl-0 = <&pinctrl_typec1>;
357		reg = <0x50>;
358		interrupt-parent = <&gpio2>;
359		interrupts = <11 8>;
360		status = "okay";
361
362		port {
363			typec1_dr_sw: endpoint {
364				remote-endpoint = <&usb1_drd_sw>;
365			};
366		};
367
368		typec1_con: connector {
369			compatible = "usb-c-connector";
370			label = "USB-C";
371			power-role = "dual";
372			data-role = "dual";
373			try-power-role = "sink";
374			source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
375			sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
376				     PDO_VAR(5000, 20000, 3000)>;
377			op-sink-microwatt = <15000000>;
378			self-powered;
379		};
380	};
381};
382
383&i2c3 {
384	clock-frequency = <400000>;
385	pinctrl-names = "default";
386	pinctrl-0 = <&pinctrl_i2c3>;
387	status = "okay";
388
389	pca6416: gpio@20 {
390		compatible = "nxp,pca6416";
391		reg = <0x20>;
392		gpio-controller;
393		#gpio-cells = <2>;
394		vcc-supply = <&buck4_reg>;
395	};
396};
397
398&lcdif {
399	status = "okay";
400};
401
402&mipi_dsi {
403	samsung,esc-clock-frequency = <10000000>;
404	status = "okay";
405
406	ports {
407		port@1 {
408			reg = <1>;
409
410			dsi_out: endpoint {
411				remote-endpoint = <&adv7533_in>;
412				data-lanes = <1 2 3 4>;
413			};
414		};
415	};
416};
417
418&pcie_phy {
419	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
420	fsl,tx-deemph-gen1 = <0x2d>;
421	fsl,tx-deemph-gen2 = <0xf>;
422	clocks = <&pcie0_refclk>;
423	status = "okay";
424};
425
426&pcie0 {
427	pinctrl-names = "default";
428	pinctrl-0 = <&pinctrl_pcie0>;
429	reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
430	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
431		 <&clk IMX8MM_CLK_PCIE1_AUX>;
432	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
433			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
434	assigned-clock-rates = <10000000>, <250000000>;
435	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
436				 <&clk IMX8MM_SYS_PLL2_250M>;
437	vpcie-supply = <&reg_pcie0>;
438	status = "okay";
439};
440
441&sai2 {
442	#sound-dai-cells = <0>;
443	pinctrl-names = "default";
444	pinctrl-0 = <&pinctrl_sai2>;
445	assigned-clocks = <&clk IMX8MM_CLK_SAI2>;
446	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
447	assigned-clock-rates = <24576000>;
448	status = "okay";
449};
450
451&sai3 {
452	pinctrl-names = "default";
453	pinctrl-0 = <&pinctrl_sai3>;
454	assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
455	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
456	assigned-clock-rates = <24576000>;
457	status = "okay";
458};
459
460&snvs_pwrkey {
461	status = "okay";
462};
463
464&uart2 { /* console */
465	pinctrl-names = "default";
466	pinctrl-0 = <&pinctrl_uart2>;
467	status = "okay";
468};
469
470&usbphynop1 {
471	wakeup-source;
472};
473
474&usbotg1 {
475	dr_mode = "otg";
476	hnp-disable;
477	srp-disable;
478	adp-disable;
479	usb-role-switch;
480	disable-over-current;
481	samsung,picophy-pre-emp-curr-control = <3>;
482	samsung,picophy-dc-vol-level-adjust = <7>;
483	status = "okay";
484
485	port {
486		usb1_drd_sw: endpoint {
487			remote-endpoint = <&typec1_dr_sw>;
488		};
489	};
490};
491
492&usdhc2 {
493	assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
494	assigned-clock-rates = <200000000>;
495	pinctrl-names = "default", "state_100mhz", "state_200mhz";
496	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
497	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
498	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
499	cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
500	bus-width = <4>;
501	vmmc-supply = <&reg_usdhc2_vmmc>;
502	status = "okay";
503};
504
505&wdog1 {
506	pinctrl-names = "default";
507	pinctrl-0 = <&pinctrl_wdog>;
508	fsl,ext-reset-output;
509	status = "okay";
510};
511
512&pwm1 {
513	pinctrl-names = "default";
514	pinctrl-0 = <&pinctrl_backlight>;
515	status = "okay";
516};
517
518&iomuxc {
519	pinctrl_fec1: fec1grp {
520		fsl,pins = <
521			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3
522			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
523			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
524			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
525			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
526			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
527			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
528			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
529			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
530			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
531			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
532			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
533			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
534			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
535			MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22		0x19
536		>;
537	};
538
539	pinctrl_gpio_led: gpioledgrp {
540		fsl,pins = <
541			MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16	0x19
542		>;
543	};
544
545	pinctrl_ir: irgrp {
546		fsl,pins = <
547			MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13              0x4f
548		>;
549	};
550
551	pinctrl_gpio_wlf: gpiowlfgrp {
552		fsl,pins = <
553			MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21	0xd6
554		>;
555	};
556
557	pinctrl_i2c1: i2c1grp {
558		fsl,pins = <
559			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL			0x400001c3
560			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA			0x400001c3
561		>;
562	};
563
564	pinctrl_i2c2: i2c2grp {
565		fsl,pins = <
566			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL			0x400001c3
567			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA			0x400001c3
568		>;
569	};
570
571	pinctrl_i2c3: i2c3grp {
572		fsl,pins = <
573			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL			0x400001c3
574			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA			0x400001c3
575		>;
576	};
577
578	pinctrl_pcie0: pcie0grp {
579		fsl,pins = <
580			MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B    0x61
581			MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21       0x41
582		>;
583	};
584
585	pinctrl_pcie0_reg: pcie0reggrp {
586		fsl,pins = <
587			MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5       0x41
588		>;
589	};
590
591	pinctrl_pmic: pmicirqgrp {
592		fsl,pins = <
593			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x141
594		>;
595	};
596
597	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
598		fsl,pins = <
599			MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
600		>;
601	};
602
603	pinctrl_sai2: sai2grp {
604		fsl,pins = <
605			MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK      0xd6
606			MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC     0xd6
607			MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0    0xd6
608			MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0    0xd6
609		>;
610	};
611
612	pinctrl_sai3: sai3grp {
613		fsl,pins = <
614			MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6
615			MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6
616			MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK        0xd6
617			MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6
618		>;
619	};
620
621	pinctrl_typec1: typec1grp {
622		fsl,pins = <
623			MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11	0x159
624		>;
625	};
626
627	pinctrl_uart2: uart2grp {
628		fsl,pins = <
629			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
630			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
631		>;
632	};
633
634	pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {
635		fsl,pins = <
636			MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x1c4
637		>;
638	};
639
640	pinctrl_usdhc2: usdhc2grp {
641		fsl,pins = <
642			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
643			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
644			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
645			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
646			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
647			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
648			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
649		>;
650	};
651
652	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
653		fsl,pins = <
654			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x194
655			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4
656			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
657			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
658			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
659			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
660			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
661		>;
662	};
663
664	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
665		fsl,pins = <
666			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x196
667			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6
668			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
669			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
670			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
671			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
672			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
673		>;
674	};
675
676	pinctrl_wdog: wdoggrp {
677		fsl,pins = <
678			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0x166
679		>;
680	};
681
682	pinctrl_backlight: backlightgrp {
683		fsl,pins = <
684			MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT	0x06
685		>;
686	};
687};
688