1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // nau8821.c -- Nuvoton NAU88L21 audio codec driver 4 // 5 // Copyright 2021 Nuvoton Technology Corp. 6 // Author: John Hsu <kchsu0@nuvoton.com> 7 // Co-author: Seven Lee <wtli@nuvoton.com> 8 // 9 10 #include <linux/acpi.h> 11 #include <linux/clk.h> 12 #include <linux/delay.h> 13 #include <linux/init.h> 14 #include <linux/i2c.h> 15 #include <linux/module.h> 16 #include <linux/math64.h> 17 #include <linux/regmap.h> 18 #include <linux/slab.h> 19 #include <sound/core.h> 20 #include <sound/initval.h> 21 #include <sound/jack.h> 22 #include <sound/pcm.h> 23 #include <sound/pcm_params.h> 24 #include <sound/soc.h> 25 #include <sound/tlv.h> 26 #include "nau8821.h" 27 28 #define NAU_FREF_MAX 13500000 29 #define NAU_FVCO_MAX 100000000 30 #define NAU_FVCO_MIN 90000000 31 32 #define NAU8821_BUTTON SND_JACK_BTN_0 33 34 /* the maximum frequency of CLK_ADC and CLK_DAC */ 35 #define CLK_DA_AD_MAX 6144000 36 37 static int nau8821_configure_sysclk(struct nau8821 *nau8821, 38 int clk_id, unsigned int freq); 39 static bool nau8821_is_jack_inserted(struct regmap *regmap); 40 41 struct nau8821_fll { 42 int mclk_src; 43 int ratio; 44 int fll_frac; 45 int fll_int; 46 int clk_ref_div; 47 }; 48 49 struct nau8821_fll_attr { 50 unsigned int param; 51 unsigned int val; 52 }; 53 54 /* scaling for mclk from sysclk_src output */ 55 static const struct nau8821_fll_attr mclk_src_scaling[] = { 56 { 1, 0x0 }, 57 { 2, 0x2 }, 58 { 4, 0x3 }, 59 { 8, 0x4 }, 60 { 16, 0x5 }, 61 { 32, 0x6 }, 62 { 3, 0x7 }, 63 { 6, 0xa }, 64 { 12, 0xb }, 65 { 24, 0xc }, 66 { 48, 0xd }, 67 { 96, 0xe }, 68 { 5, 0xf }, 69 }; 70 71 /* ratio for input clk freq */ 72 static const struct nau8821_fll_attr fll_ratio[] = { 73 { 512000, 0x01 }, 74 { 256000, 0x02 }, 75 { 128000, 0x04 }, 76 { 64000, 0x08 }, 77 { 32000, 0x10 }, 78 { 8000, 0x20 }, 79 { 4000, 0x40 }, 80 }; 81 82 static const struct nau8821_fll_attr fll_pre_scalar[] = { 83 { 0, 0x0 }, 84 { 1, 0x1 }, 85 { 2, 0x2 }, 86 { 3, 0x3 }, 87 }; 88 89 /* over sampling rate */ 90 struct nau8821_osr_attr { 91 unsigned int osr; 92 unsigned int clk_src; 93 }; 94 95 static const struct nau8821_osr_attr osr_dac_sel[] = { 96 { 64, 2 }, /* OSR 64, SRC 1/4 */ 97 { 256, 0 }, /* OSR 256, SRC 1 */ 98 { 128, 1 }, /* OSR 128, SRC 1/2 */ 99 { 0, 0 }, 100 { 32, 3 }, /* OSR 32, SRC 1/8 */ 101 }; 102 103 static const struct nau8821_osr_attr osr_adc_sel[] = { 104 { 32, 3 }, /* OSR 32, SRC 1/8 */ 105 { 64, 2 }, /* OSR 64, SRC 1/4 */ 106 { 128, 1 }, /* OSR 128, SRC 1/2 */ 107 { 256, 0 }, /* OSR 256, SRC 1 */ 108 }; 109 110 struct nau8821_dmic_speed { 111 unsigned int param; 112 unsigned int val; 113 }; 114 115 static const struct nau8821_dmic_speed dmic_speed_sel[] = { 116 { 0, 0x0 }, /*SPEED 1, SRC 1 */ 117 { 1, 0x1 }, /*SPEED 2, SRC 1/2 */ 118 { 2, 0x2 }, /*SPEED 4, SRC 1/4 */ 119 { 3, 0x3 }, /*SPEED 8, SRC 1/8 */ 120 }; 121 122 static const struct reg_default nau8821_reg_defaults[] = { 123 { NAU8821_R01_ENA_CTRL, 0x00ff }, 124 { NAU8821_R03_CLK_DIVIDER, 0x0050 }, 125 { NAU8821_R04_FLL1, 0x0 }, 126 { NAU8821_R05_FLL2, 0x00bc }, 127 { NAU8821_R06_FLL3, 0x0008 }, 128 { NAU8821_R07_FLL4, 0x0010 }, 129 { NAU8821_R08_FLL5, 0x4000 }, 130 { NAU8821_R09_FLL6, 0x6900 }, 131 { NAU8821_R0A_FLL7, 0x0031 }, 132 { NAU8821_R0B_FLL8, 0x26e9 }, 133 { NAU8821_R0D_JACK_DET_CTRL, 0x0 }, 134 { NAU8821_R0F_INTERRUPT_MASK, 0x0 }, 135 { NAU8821_R12_INTERRUPT_DIS_CTRL, 0xffff }, 136 { NAU8821_R13_DMIC_CTRL, 0x0 }, 137 { NAU8821_R1A_GPIO12_CTRL, 0x0 }, 138 { NAU8821_R1B_TDM_CTRL, 0x0 }, 139 { NAU8821_R1C_I2S_PCM_CTRL1, 0x000a }, 140 { NAU8821_R1D_I2S_PCM_CTRL2, 0x8010 }, 141 { NAU8821_R1E_LEFT_TIME_SLOT, 0x0 }, 142 { NAU8821_R1F_RIGHT_TIME_SLOT, 0x0 }, 143 { NAU8821_R21_BIQ0_COF1, 0x0 }, 144 { NAU8821_R22_BIQ0_COF2, 0x0 }, 145 { NAU8821_R23_BIQ0_COF3, 0x0 }, 146 { NAU8821_R24_BIQ0_COF4, 0x0 }, 147 { NAU8821_R25_BIQ0_COF5, 0x0 }, 148 { NAU8821_R26_BIQ0_COF6, 0x0 }, 149 { NAU8821_R27_BIQ0_COF7, 0x0 }, 150 { NAU8821_R28_BIQ0_COF8, 0x0 }, 151 { NAU8821_R29_BIQ0_COF9, 0x0 }, 152 { NAU8821_R2A_BIQ0_COF10, 0x0 }, 153 { NAU8821_R2B_ADC_RATE, 0x0002 }, 154 { NAU8821_R2C_DAC_CTRL1, 0x0082 }, 155 { NAU8821_R2D_DAC_CTRL2, 0x0 }, 156 { NAU8821_R2F_DAC_DGAIN_CTRL, 0x0 }, 157 { NAU8821_R30_ADC_DGAIN_CTRL, 0x0 }, 158 { NAU8821_R31_MUTE_CTRL, 0x0 }, 159 { NAU8821_R32_HSVOL_CTRL, 0x0 }, 160 { NAU8821_R34_DACR_CTRL, 0xcfcf }, 161 { NAU8821_R35_ADC_DGAIN_CTRL1, 0xcfcf }, 162 { NAU8821_R36_ADC_DRC_KNEE_IP12, 0x1486 }, 163 { NAU8821_R37_ADC_DRC_KNEE_IP34, 0x0f12 }, 164 { NAU8821_R38_ADC_DRC_SLOPES, 0x25ff }, 165 { NAU8821_R39_ADC_DRC_ATKDCY, 0x3457 }, 166 { NAU8821_R3A_DAC_DRC_KNEE_IP12, 0x1486 }, 167 { NAU8821_R3B_DAC_DRC_KNEE_IP34, 0x0f12 }, 168 { NAU8821_R3C_DAC_DRC_SLOPES, 0x25f9 }, 169 { NAU8821_R3D_DAC_DRC_ATKDCY, 0x3457 }, 170 { NAU8821_R41_BIQ1_COF1, 0x0 }, 171 { NAU8821_R42_BIQ1_COF2, 0x0 }, 172 { NAU8821_R43_BIQ1_COF3, 0x0 }, 173 { NAU8821_R44_BIQ1_COF4, 0x0 }, 174 { NAU8821_R45_BIQ1_COF5, 0x0 }, 175 { NAU8821_R46_BIQ1_COF6, 0x0 }, 176 { NAU8821_R47_BIQ1_COF7, 0x0 }, 177 { NAU8821_R48_BIQ1_COF8, 0x0 }, 178 { NAU8821_R49_BIQ1_COF9, 0x0 }, 179 { NAU8821_R4A_BIQ1_COF10, 0x0 }, 180 { NAU8821_R4B_CLASSG_CTRL, 0x0 }, 181 { NAU8821_R4C_IMM_MODE_CTRL, 0x0 }, 182 { NAU8821_R4D_IMM_RMS_L, 0x0 }, 183 { NAU8821_R53_OTPDOUT_1, 0xaad8 }, 184 { NAU8821_R54_OTPDOUT_2, 0x0002 }, 185 { NAU8821_R55_MISC_CTRL, 0x0 }, 186 { NAU8821_R66_BIAS_ADJ, 0x0 }, 187 { NAU8821_R68_TRIM_SETTINGS, 0x0 }, 188 { NAU8821_R69_ANALOG_CONTROL_1, 0x0 }, 189 { NAU8821_R6A_ANALOG_CONTROL_2, 0x0 }, 190 { NAU8821_R6B_PGA_MUTE, 0x0 }, 191 { NAU8821_R71_ANALOG_ADC_1, 0x0011 }, 192 { NAU8821_R72_ANALOG_ADC_2, 0x0020 }, 193 { NAU8821_R73_RDAC, 0x0008 }, 194 { NAU8821_R74_MIC_BIAS, 0x0006 }, 195 { NAU8821_R76_BOOST, 0x0 }, 196 { NAU8821_R77_FEPGA, 0x0 }, 197 { NAU8821_R7E_PGA_GAIN, 0x0 }, 198 { NAU8821_R7F_POWER_UP_CONTROL, 0x0 }, 199 { NAU8821_R80_CHARGE_PUMP, 0x0 }, 200 }; 201 202 static bool nau8821_readable_reg(struct device *dev, unsigned int reg) 203 { 204 switch (reg) { 205 case NAU8821_R00_RESET ... NAU8821_R01_ENA_CTRL: 206 case NAU8821_R03_CLK_DIVIDER ... NAU8821_R0B_FLL8: 207 case NAU8821_R0D_JACK_DET_CTRL: 208 case NAU8821_R0F_INTERRUPT_MASK ... NAU8821_R13_DMIC_CTRL: 209 case NAU8821_R1A_GPIO12_CTRL ... NAU8821_R1F_RIGHT_TIME_SLOT: 210 case NAU8821_R21_BIQ0_COF1 ... NAU8821_R2D_DAC_CTRL2: 211 case NAU8821_R2F_DAC_DGAIN_CTRL ... NAU8821_R32_HSVOL_CTRL: 212 case NAU8821_R34_DACR_CTRL ... NAU8821_R3D_DAC_DRC_ATKDCY: 213 case NAU8821_R41_BIQ1_COF1 ... NAU8821_R4F_FUSE_CTRL3: 214 case NAU8821_R51_FUSE_CTRL1: 215 case NAU8821_R53_OTPDOUT_1 ... NAU8821_R55_MISC_CTRL: 216 case NAU8821_R58_I2C_DEVICE_ID ... NAU8821_R5A_SOFTWARE_RST: 217 case NAU8821_R66_BIAS_ADJ: 218 case NAU8821_R68_TRIM_SETTINGS ... NAU8821_R6B_PGA_MUTE: 219 case NAU8821_R71_ANALOG_ADC_1 ... NAU8821_R74_MIC_BIAS: 220 case NAU8821_R76_BOOST ... NAU8821_R77_FEPGA: 221 case NAU8821_R7E_PGA_GAIN ... NAU8821_R82_GENERAL_STATUS: 222 return true; 223 default: 224 return false; 225 } 226 } 227 228 static bool nau8821_writeable_reg(struct device *dev, unsigned int reg) 229 { 230 switch (reg) { 231 case NAU8821_R00_RESET ... NAU8821_R01_ENA_CTRL: 232 case NAU8821_R03_CLK_DIVIDER ... NAU8821_R0B_FLL8: 233 case NAU8821_R0D_JACK_DET_CTRL: 234 case NAU8821_R0F_INTERRUPT_MASK: 235 case NAU8821_R11_INT_CLR_KEY_STATUS ... NAU8821_R13_DMIC_CTRL: 236 case NAU8821_R1A_GPIO12_CTRL ... NAU8821_R1F_RIGHT_TIME_SLOT: 237 case NAU8821_R21_BIQ0_COF1 ... NAU8821_R2D_DAC_CTRL2: 238 case NAU8821_R2F_DAC_DGAIN_CTRL ... NAU8821_R32_HSVOL_CTRL: 239 case NAU8821_R34_DACR_CTRL ... NAU8821_R3D_DAC_DRC_ATKDCY: 240 case NAU8821_R41_BIQ1_COF1 ... NAU8821_R4C_IMM_MODE_CTRL: 241 case NAU8821_R4E_FUSE_CTRL2 ... NAU8821_R4F_FUSE_CTRL3: 242 case NAU8821_R51_FUSE_CTRL1: 243 case NAU8821_R55_MISC_CTRL: 244 case NAU8821_R5A_SOFTWARE_RST: 245 case NAU8821_R66_BIAS_ADJ: 246 case NAU8821_R68_TRIM_SETTINGS ... NAU8821_R6B_PGA_MUTE: 247 case NAU8821_R71_ANALOG_ADC_1 ... NAU8821_R74_MIC_BIAS: 248 case NAU8821_R76_BOOST ... NAU8821_R77_FEPGA: 249 case NAU8821_R7E_PGA_GAIN ... NAU8821_R80_CHARGE_PUMP: 250 return true; 251 default: 252 return false; 253 } 254 } 255 256 static bool nau8821_volatile_reg(struct device *dev, unsigned int reg) 257 { 258 switch (reg) { 259 case NAU8821_R00_RESET: 260 case NAU8821_R10_IRQ_STATUS ... NAU8821_R11_INT_CLR_KEY_STATUS: 261 case NAU8821_R21_BIQ0_COF1 ... NAU8821_R2A_BIQ0_COF10: 262 case NAU8821_R41_BIQ1_COF1 ... NAU8821_R4A_BIQ1_COF10: 263 case NAU8821_R4D_IMM_RMS_L: 264 case NAU8821_R53_OTPDOUT_1 ... NAU8821_R54_OTPDOUT_2: 265 case NAU8821_R58_I2C_DEVICE_ID ... NAU8821_R5A_SOFTWARE_RST: 266 case NAU8821_R81_CHARGE_PUMP_INPUT_READ ... NAU8821_R82_GENERAL_STATUS: 267 return true; 268 default: 269 return false; 270 } 271 } 272 273 static int nau8821_biq_coeff_get(struct snd_kcontrol *kcontrol, 274 struct snd_ctl_elem_value *ucontrol) 275 { 276 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 277 struct soc_bytes_ext *params = (void *)kcontrol->private_value; 278 279 if (!component->regmap) 280 return -EINVAL; 281 282 regmap_raw_read(component->regmap, NAU8821_R21_BIQ0_COF1, 283 ucontrol->value.bytes.data, params->max); 284 285 return 0; 286 } 287 288 static int nau8821_biq_coeff_put(struct snd_kcontrol *kcontrol, 289 struct snd_ctl_elem_value *ucontrol) 290 { 291 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 292 struct soc_bytes_ext *params = (void *)kcontrol->private_value; 293 void *data; 294 295 if (!component->regmap) 296 return -EINVAL; 297 298 data = kmemdup(ucontrol->value.bytes.data, 299 params->max, GFP_KERNEL | GFP_DMA); 300 if (!data) 301 return -ENOMEM; 302 303 regmap_raw_write(component->regmap, NAU8821_R21_BIQ0_COF1, 304 data, params->max); 305 306 kfree(data); 307 308 return 0; 309 } 310 311 static const char * const nau8821_adc_decimation[] = { 312 "32", "64", "128", "256" }; 313 314 static const struct soc_enum nau8821_adc_decimation_enum = 315 SOC_ENUM_SINGLE(NAU8821_R2B_ADC_RATE, NAU8821_ADC_SYNC_DOWN_SFT, 316 ARRAY_SIZE(nau8821_adc_decimation), nau8821_adc_decimation); 317 318 static const char * const nau8821_dac_oversampl[] = { 319 "64", "256", "128", "", "32" }; 320 321 static const struct soc_enum nau8821_dac_oversampl_enum = 322 SOC_ENUM_SINGLE(NAU8821_R2C_DAC_CTRL1, NAU8821_DAC_OVERSAMPLE_SFT, 323 ARRAY_SIZE(nau8821_dac_oversampl), nau8821_dac_oversampl); 324 325 static const char * const nau8821_adc_drc_noise_gate[] = { 326 "1:1", "2:1", "4:1", "8:1" }; 327 328 static const struct soc_enum nau8821_adc_drc_noise_gate_enum = 329 SOC_ENUM_SINGLE(NAU8821_R38_ADC_DRC_SLOPES, NAU8821_DRC_NG_SLP_ADC_SFT, 330 ARRAY_SIZE(nau8821_adc_drc_noise_gate), 331 nau8821_adc_drc_noise_gate); 332 333 static const char * const nau8821_adc_drc_expansion_slope[] = { 334 "1:1", "2:1", "4:1" }; 335 336 static const struct soc_enum nau8821_adc_drc_expansion_slope_enum = 337 SOC_ENUM_SINGLE(NAU8821_R38_ADC_DRC_SLOPES, NAU8821_DRC_EXP_SLP_ADC_SFT, 338 ARRAY_SIZE(nau8821_adc_drc_expansion_slope), 339 nau8821_adc_drc_expansion_slope); 340 341 static const char * const nau8821_adc_drc_lower_region[] = { 342 "0", "1:2", "1:4", "1:8", "1:16", "", "", "1:1" }; 343 344 static const struct soc_enum nau8821_adc_drc_lower_region_enum = 345 SOC_ENUM_SINGLE(NAU8821_R38_ADC_DRC_SLOPES, 346 NAU8821_DRC_CMP2_SLP_ADC_SFT, 347 ARRAY_SIZE(nau8821_adc_drc_lower_region), 348 nau8821_adc_drc_lower_region); 349 350 static const char * const nau8821_higher_region[] = { 351 "0", "1:2", "1:4", "1:8", "1:16", "", "", "1:1" }; 352 353 static const struct soc_enum nau8821_higher_region_enum = 354 SOC_ENUM_SINGLE(NAU8821_R38_ADC_DRC_SLOPES, 355 NAU8821_DRC_CMP1_SLP_ADC_SFT, 356 ARRAY_SIZE(nau8821_higher_region), 357 nau8821_higher_region); 358 359 static const char * const nau8821_limiter_slope[] = { 360 "0", "1:2", "1:4", "1:8", "1:16", "1:32", "1:64", "1:1" }; 361 362 static const struct soc_enum nau8821_limiter_slope_enum = 363 SOC_ENUM_SINGLE(NAU8821_R38_ADC_DRC_SLOPES, 364 NAU8821_DRC_LMT_SLP_ADC_SFT, ARRAY_SIZE(nau8821_limiter_slope), 365 nau8821_limiter_slope); 366 367 static const char * const nau8821_detection_attack_time[] = { 368 "Ts", "3Ts", "7Ts", "15Ts", "31Ts", "63Ts", "127Ts", "255Ts", 369 "", "511Ts" }; 370 371 static const struct soc_enum nau8821_detection_attack_time_enum = 372 SOC_ENUM_SINGLE(NAU8821_R39_ADC_DRC_ATKDCY, 373 NAU8821_DRC_PK_COEF1_ADC_SFT, 374 ARRAY_SIZE(nau8821_detection_attack_time), 375 nau8821_detection_attack_time); 376 377 static const char * const nau8821_detection_release_time[] = { 378 "63Ts", "127Ts", "255Ts", "511Ts", "1023Ts", "2047Ts", "4095Ts", 379 "8191Ts", "", "16383Ts" }; 380 381 static const struct soc_enum nau8821_detection_release_time_enum = 382 SOC_ENUM_SINGLE(NAU8821_R39_ADC_DRC_ATKDCY, 383 NAU8821_DRC_PK_COEF2_ADC_SFT, 384 ARRAY_SIZE(nau8821_detection_release_time), 385 nau8821_detection_release_time); 386 387 static const char * const nau8821_attack_time[] = { 388 "Ts", "3Ts", "7Ts", "15Ts", "31Ts", "63Ts", "127Ts", "255Ts", 389 "511Ts", "1023Ts", "2047Ts", "4095Ts", "8191Ts" }; 390 391 static const struct soc_enum nau8821_attack_time_enum = 392 SOC_ENUM_SINGLE(NAU8821_R39_ADC_DRC_ATKDCY, NAU8821_DRC_ATK_ADC_SFT, 393 ARRAY_SIZE(nau8821_attack_time), nau8821_attack_time); 394 395 static const char * const nau8821_decay_time[] = { 396 "63Ts", "127Ts", "255Ts", "511Ts", "1023Ts", "2047Ts", "4095Ts", 397 "8191Ts", "16383Ts", "32757Ts", "65535Ts" }; 398 399 static const struct soc_enum nau8821_decay_time_enum = 400 SOC_ENUM_SINGLE(NAU8821_R39_ADC_DRC_ATKDCY, NAU8821_DRC_DCY_ADC_SFT, 401 ARRAY_SIZE(nau8821_decay_time), nau8821_decay_time); 402 403 static const DECLARE_TLV_DB_MINMAX_MUTE(adc_vol_tlv, -6600, 2400); 404 static const DECLARE_TLV_DB_MINMAX_MUTE(sidetone_vol_tlv, -4200, 0); 405 static const DECLARE_TLV_DB_MINMAX(hp_vol_tlv, -900, 0); 406 static const DECLARE_TLV_DB_SCALE(playback_vol_tlv, -6600, 50, 1); 407 static const DECLARE_TLV_DB_MINMAX(fepga_gain_tlv, -100, 3600); 408 static const DECLARE_TLV_DB_MINMAX_MUTE(crosstalk_vol_tlv, -7000, 2400); 409 static const DECLARE_TLV_DB_MINMAX(drc_knee4_tlv, -9800, -3500); 410 static const DECLARE_TLV_DB_MINMAX(drc_knee3_tlv, -8100, -1800); 411 412 static const struct snd_kcontrol_new nau8821_controls[] = { 413 SOC_DOUBLE_TLV("Mic Volume", NAU8821_R35_ADC_DGAIN_CTRL1, 414 NAU8821_ADCL_CH_VOL_SFT, NAU8821_ADCR_CH_VOL_SFT, 415 0xff, 0, adc_vol_tlv), 416 SOC_DOUBLE_TLV("Headphone Bypass Volume", NAU8821_R30_ADC_DGAIN_CTRL, 417 12, 8, 0x0f, 0, sidetone_vol_tlv), 418 SOC_DOUBLE_TLV("Headphone Volume", NAU8821_R32_HSVOL_CTRL, 419 NAU8821_HPL_VOL_SFT, NAU8821_HPR_VOL_SFT, 0x3, 1, hp_vol_tlv), 420 SOC_DOUBLE_TLV("Digital Playback Volume", NAU8821_R34_DACR_CTRL, 421 NAU8821_DACL_CH_VOL_SFT, NAU8821_DACR_CH_VOL_SFT, 422 0xcf, 0, playback_vol_tlv), 423 SOC_DOUBLE_TLV("Frontend PGA Volume", NAU8821_R7E_PGA_GAIN, 424 NAU8821_PGA_GAIN_L_SFT, NAU8821_PGA_GAIN_R_SFT, 425 37, 0, fepga_gain_tlv), 426 SOC_DOUBLE_TLV("Headphone Crosstalk Volume", 427 NAU8821_R2F_DAC_DGAIN_CTRL, 428 0, 8, 0xff, 0, crosstalk_vol_tlv), 429 SOC_SINGLE_TLV("ADC DRC KNEE4", NAU8821_R37_ADC_DRC_KNEE_IP34, 430 NAU8821_DRC_KNEE4_IP_ADC_SFT, 0x3f, 1, drc_knee4_tlv), 431 SOC_SINGLE_TLV("ADC DRC KNEE3", NAU8821_R37_ADC_DRC_KNEE_IP34, 432 NAU8821_DRC_KNEE3_IP_ADC_SFT, 0x3f, 1, drc_knee3_tlv), 433 434 SOC_ENUM("ADC DRC Noise Gate", nau8821_adc_drc_noise_gate_enum), 435 SOC_ENUM("ADC DRC Expansion Slope", nau8821_adc_drc_expansion_slope_enum), 436 SOC_ENUM("ADC DRC Lower Region", nau8821_adc_drc_lower_region_enum), 437 SOC_ENUM("ADC DRC Higher Region", nau8821_higher_region_enum), 438 SOC_ENUM("ADC DRC Limiter Slope", nau8821_limiter_slope_enum), 439 SOC_ENUM("ADC DRC Peak Detection Attack Time", nau8821_detection_attack_time_enum), 440 SOC_ENUM("ADC DRC Peak Detection Release Time", nau8821_detection_release_time_enum), 441 SOC_ENUM("ADC DRC Attack Time", nau8821_attack_time_enum), 442 SOC_ENUM("ADC DRC Decay Time", nau8821_decay_time_enum), 443 SOC_SINGLE("DRC Enable Switch", NAU8821_R36_ADC_DRC_KNEE_IP12, 444 NAU8821_DRC_ENA_ADC_SFT, 1, 0), 445 446 SOC_ENUM("ADC Decimation Rate", nau8821_adc_decimation_enum), 447 SOC_ENUM("DAC Oversampling Rate", nau8821_dac_oversampl_enum), 448 SND_SOC_BYTES_EXT("BIQ Coefficients", 20, 449 nau8821_biq_coeff_get, nau8821_biq_coeff_put), 450 SOC_SINGLE("ADC Phase Switch", NAU8821_R1B_TDM_CTRL, 451 NAU8821_ADCPHS_SFT, 1, 0), 452 }; 453 454 static const struct snd_kcontrol_new nau8821_dmic_mode_switch = 455 SOC_DAPM_SINGLE("Switch", NAU8821_R13_DMIC_CTRL, 456 NAU8821_DMIC_EN_SFT, 1, 0); 457 458 static int dmic_clock_control(struct snd_soc_dapm_widget *w, 459 struct snd_kcontrol *k, int event) 460 { 461 struct snd_soc_component *component = 462 snd_soc_dapm_to_component(w->dapm); 463 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 464 int i, speed_selection = -1, clk_adc_src, clk_adc; 465 unsigned int clk_divider_r03; 466 467 /* The DMIC clock is gotten from adc clock divided by 468 * CLK_DMIC_SRC (1, 2, 4, 8). The clock has to be equal or 469 * less than nau8821->dmic_clk_threshold. 470 */ 471 regmap_read(nau8821->regmap, NAU8821_R03_CLK_DIVIDER, 472 &clk_divider_r03); 473 clk_adc_src = (clk_divider_r03 & NAU8821_CLK_ADC_SRC_MASK) 474 >> NAU8821_CLK_ADC_SRC_SFT; 475 clk_adc = (nau8821->fs * 256) >> clk_adc_src; 476 477 for (i = 0 ; i < 4 ; i++) 478 if ((clk_adc >> dmic_speed_sel[i].param) <= 479 nau8821->dmic_clk_threshold) { 480 speed_selection = dmic_speed_sel[i].val; 481 break; 482 } 483 if (i == 4) 484 return -EINVAL; 485 486 dev_dbg(nau8821->dev, 487 "clk_adc=%d, dmic_clk_threshold = %d, param=%d, val = %d\n", 488 clk_adc, nau8821->dmic_clk_threshold, 489 dmic_speed_sel[i].param, dmic_speed_sel[i].val); 490 regmap_update_bits(nau8821->regmap, NAU8821_R13_DMIC_CTRL, 491 NAU8821_DMIC_SRC_MASK, 492 (speed_selection << NAU8821_DMIC_SRC_SFT)); 493 494 return 0; 495 } 496 497 static int nau8821_left_adc_event(struct snd_soc_dapm_widget *w, 498 struct snd_kcontrol *kcontrol, int event) 499 { 500 struct snd_soc_component *component = 501 snd_soc_dapm_to_component(w->dapm); 502 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 503 504 switch (event) { 505 case SND_SOC_DAPM_POST_PMU: 506 msleep(125); 507 regmap_update_bits(nau8821->regmap, NAU8821_R01_ENA_CTRL, 508 NAU8821_EN_ADCL, NAU8821_EN_ADCL); 509 break; 510 case SND_SOC_DAPM_POST_PMD: 511 regmap_update_bits(nau8821->regmap, 512 NAU8821_R01_ENA_CTRL, NAU8821_EN_ADCL, 0); 513 break; 514 default: 515 return -EINVAL; 516 } 517 518 return 0; 519 } 520 521 static int nau8821_right_adc_event(struct snd_soc_dapm_widget *w, 522 struct snd_kcontrol *kcontrol, int event) 523 { 524 struct snd_soc_component *component = 525 snd_soc_dapm_to_component(w->dapm); 526 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 527 528 switch (event) { 529 case SND_SOC_DAPM_POST_PMU: 530 msleep(125); 531 regmap_update_bits(nau8821->regmap, NAU8821_R01_ENA_CTRL, 532 NAU8821_EN_ADCR, NAU8821_EN_ADCR); 533 break; 534 case SND_SOC_DAPM_POST_PMD: 535 regmap_update_bits(nau8821->regmap, 536 NAU8821_R01_ENA_CTRL, NAU8821_EN_ADCR, 0); 537 break; 538 default: 539 return -EINVAL; 540 } 541 542 return 0; 543 } 544 545 static int nau8821_pump_event(struct snd_soc_dapm_widget *w, 546 struct snd_kcontrol *kcontrol, int event) 547 { 548 struct snd_soc_component *component = 549 snd_soc_dapm_to_component(w->dapm); 550 struct nau8821 *nau8821 = 551 snd_soc_component_get_drvdata(component); 552 553 switch (event) { 554 case SND_SOC_DAPM_POST_PMU: 555 /* Prevent startup click by letting charge pump to ramp up */ 556 msleep(20); 557 regmap_update_bits(nau8821->regmap, NAU8821_R80_CHARGE_PUMP, 558 NAU8821_JAMNODCLOW, NAU8821_JAMNODCLOW); 559 break; 560 case SND_SOC_DAPM_PRE_PMD: 561 regmap_update_bits(nau8821->regmap, NAU8821_R80_CHARGE_PUMP, 562 NAU8821_JAMNODCLOW, 0); 563 break; 564 default: 565 return -EINVAL; 566 } 567 568 return 0; 569 } 570 571 static int nau8821_output_dac_event(struct snd_soc_dapm_widget *w, 572 struct snd_kcontrol *kcontrol, int event) 573 { 574 struct snd_soc_component *component = 575 snd_soc_dapm_to_component(w->dapm); 576 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 577 578 switch (event) { 579 case SND_SOC_DAPM_PRE_PMU: 580 /* Disables the TESTDAC to let DAC signal pass through. */ 581 regmap_update_bits(nau8821->regmap, NAU8821_R66_BIAS_ADJ, 582 NAU8821_BIAS_TESTDAC_EN, 0); 583 break; 584 case SND_SOC_DAPM_POST_PMD: 585 regmap_update_bits(nau8821->regmap, NAU8821_R66_BIAS_ADJ, 586 NAU8821_BIAS_TESTDAC_EN, NAU8821_BIAS_TESTDAC_EN); 587 break; 588 default: 589 return -EINVAL; 590 } 591 592 return 0; 593 } 594 595 static int system_clock_control(struct snd_soc_dapm_widget *w, 596 struct snd_kcontrol *k, int event) 597 { 598 struct snd_soc_component *component = 599 snd_soc_dapm_to_component(w->dapm); 600 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 601 602 if (SND_SOC_DAPM_EVENT_OFF(event)) { 603 dev_dbg(nau8821->dev, "system clock control : POWER OFF\n"); 604 /* Set clock source to disable or internal clock before the 605 * playback or capture end. Codec needs clock for Jack 606 * detection and button press if jack inserted; otherwise, 607 * the clock should be closed. 608 */ 609 if (nau8821_is_jack_inserted(nau8821->regmap)) { 610 nau8821_configure_sysclk(nau8821, 611 NAU8821_CLK_INTERNAL, 0); 612 } else { 613 nau8821_configure_sysclk(nau8821, NAU8821_CLK_DIS, 0); 614 } 615 } 616 return 0; 617 } 618 619 static const struct snd_soc_dapm_widget nau8821_dapm_widgets[] = { 620 SND_SOC_DAPM_SUPPLY("System Clock", SND_SOC_NOPM, 0, 0, 621 system_clock_control, SND_SOC_DAPM_POST_PMD), 622 SND_SOC_DAPM_SUPPLY("MICBIAS", NAU8821_R74_MIC_BIAS, 623 NAU8821_MICBIAS_POWERUP_SFT, 0, NULL, 0), 624 SND_SOC_DAPM_SUPPLY("DMIC Clock", SND_SOC_NOPM, 0, 0, 625 dmic_clock_control, SND_SOC_DAPM_POST_PMU), 626 SND_SOC_DAPM_ADC("ADCL Power", NULL, NAU8821_R72_ANALOG_ADC_2, 627 NAU8821_POWERUP_ADCL_SFT, 0), 628 SND_SOC_DAPM_ADC("ADCR Power", NULL, NAU8821_R72_ANALOG_ADC_2, 629 NAU8821_POWERUP_ADCR_SFT, 0), 630 SND_SOC_DAPM_PGA_S("Frontend PGA L", 1, NAU8821_R7F_POWER_UP_CONTROL, 631 NAU8821_PUP_PGA_L_SFT, 0, NULL, 0), 632 SND_SOC_DAPM_PGA_S("Frontend PGA R", 1, NAU8821_R7F_POWER_UP_CONTROL, 633 NAU8821_PUP_PGA_R_SFT, 0, NULL, 0), 634 SND_SOC_DAPM_PGA_S("ADCL Digital path", 0, NAU8821_R01_ENA_CTRL, 635 NAU8821_EN_ADCL_SFT, 0, nau8821_left_adc_event, 636 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 637 SND_SOC_DAPM_PGA_S("ADCR Digital path", 0, NAU8821_R01_ENA_CTRL, 638 NAU8821_EN_ADCR_SFT, 0, nau8821_right_adc_event, 639 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 640 SND_SOC_DAPM_SWITCH("DMIC Enable", SND_SOC_NOPM, 641 0, 0, &nau8821_dmic_mode_switch), 642 SND_SOC_DAPM_AIF_OUT("AIFTX", "Capture", 0, NAU8821_R1D_I2S_PCM_CTRL2, 643 NAU8821_I2S_TRISTATE_SFT, 1), 644 SND_SOC_DAPM_AIF_IN("AIFRX", "Playback", 0, SND_SOC_NOPM, 0, 0), 645 646 SND_SOC_DAPM_PGA_S("ADACL", 2, NAU8821_R73_RDAC, 647 NAU8821_DACL_EN_SFT, 0, NULL, 0), 648 SND_SOC_DAPM_PGA_S("ADACR", 2, NAU8821_R73_RDAC, 649 NAU8821_DACR_EN_SFT, 0, NULL, 0), 650 SND_SOC_DAPM_PGA_S("ADACL Clock", 3, NAU8821_R73_RDAC, 651 NAU8821_DACL_CLK_EN_SFT, 0, NULL, 0), 652 SND_SOC_DAPM_PGA_S("ADACR Clock", 3, NAU8821_R73_RDAC, 653 NAU8821_DACR_CLK_EN_SFT, 0, NULL, 0), 654 SND_SOC_DAPM_DAC("DDACR", NULL, NAU8821_R01_ENA_CTRL, 655 NAU8821_EN_DACR_SFT, 0), 656 SND_SOC_DAPM_DAC("DDACL", NULL, NAU8821_R01_ENA_CTRL, 657 NAU8821_EN_DACL_SFT, 0), 658 SND_SOC_DAPM_PGA_S("HP amp L", 0, NAU8821_R4B_CLASSG_CTRL, 659 NAU8821_CLASSG_LDAC_EN_SFT, 0, NULL, 0), 660 SND_SOC_DAPM_PGA_S("HP amp R", 0, NAU8821_R4B_CLASSG_CTRL, 661 NAU8821_CLASSG_RDAC_EN_SFT, 0, NULL, 0), 662 SND_SOC_DAPM_PGA_S("Charge Pump", 1, NAU8821_R80_CHARGE_PUMP, 663 NAU8821_CHANRGE_PUMP_EN_SFT, 0, nau8821_pump_event, 664 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 665 SND_SOC_DAPM_PGA_S("Output Driver R Stage 1", 4, 666 NAU8821_R7F_POWER_UP_CONTROL, 667 NAU8821_PUP_INTEG_R_SFT, 0, NULL, 0), 668 SND_SOC_DAPM_PGA_S("Output Driver L Stage 1", 4, 669 NAU8821_R7F_POWER_UP_CONTROL, 670 NAU8821_PUP_INTEG_L_SFT, 0, NULL, 0), 671 SND_SOC_DAPM_PGA_S("Output Driver R Stage 2", 5, 672 NAU8821_R7F_POWER_UP_CONTROL, 673 NAU8821_PUP_DRV_INSTG_R_SFT, 0, NULL, 0), 674 SND_SOC_DAPM_PGA_S("Output Driver L Stage 2", 5, 675 NAU8821_R7F_POWER_UP_CONTROL, 676 NAU8821_PUP_DRV_INSTG_L_SFT, 0, NULL, 0), 677 SND_SOC_DAPM_PGA_S("Output Driver R Stage 3", 6, 678 NAU8821_R7F_POWER_UP_CONTROL, 679 NAU8821_PUP_MAIN_DRV_R_SFT, 0, NULL, 0), 680 SND_SOC_DAPM_PGA_S("Output Driver L Stage 3", 6, 681 NAU8821_R7F_POWER_UP_CONTROL, 682 NAU8821_PUP_MAIN_DRV_L_SFT, 0, NULL, 0), 683 SND_SOC_DAPM_PGA_S("Output DACL", 7, 684 NAU8821_R80_CHARGE_PUMP, NAU8821_POWER_DOWN_DACL_SFT, 685 0, nau8821_output_dac_event, 686 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 687 SND_SOC_DAPM_PGA_S("Output DACR", 7, 688 NAU8821_R80_CHARGE_PUMP, NAU8821_POWER_DOWN_DACR_SFT, 689 0, nau8821_output_dac_event, 690 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 691 692 /* HPOL/R are ungrounded by disabling 16 Ohm pull-downs on playback */ 693 SND_SOC_DAPM_PGA_S("HPOL Pulldown", 8, 694 NAU8821_R0D_JACK_DET_CTRL, 695 NAU8821_SPKR_DWN1L_SFT, 0, NULL, 0), 696 SND_SOC_DAPM_PGA_S("HPOR Pulldown", 8, 697 NAU8821_R0D_JACK_DET_CTRL, 698 NAU8821_SPKR_DWN1R_SFT, 0, NULL, 0), 699 700 /* High current HPOL/R boost driver */ 701 SND_SOC_DAPM_PGA_S("HP Boost Driver", 9, 702 NAU8821_R76_BOOST, NAU8821_HP_BOOST_DIS_SFT, 1, NULL, 0), 703 SND_SOC_DAPM_PGA("Class G", NAU8821_R4B_CLASSG_CTRL, 704 NAU8821_CLASSG_EN_SFT, 0, NULL, 0), 705 706 SND_SOC_DAPM_INPUT("MICL"), 707 SND_SOC_DAPM_INPUT("MICR"), 708 SND_SOC_DAPM_INPUT("DMIC"), 709 SND_SOC_DAPM_OUTPUT("HPOL"), 710 SND_SOC_DAPM_OUTPUT("HPOR"), 711 }; 712 713 static const struct snd_soc_dapm_route nau8821_dapm_routes[] = { 714 {"DMIC Enable", "Switch", "DMIC"}, 715 {"DMIC Enable", NULL, "DMIC Clock"}, 716 717 {"Frontend PGA L", NULL, "MICL"}, 718 {"Frontend PGA R", NULL, "MICR"}, 719 {"Frontend PGA L", NULL, "MICBIAS"}, 720 {"Frontend PGA R", NULL, "MICBIAS"}, 721 722 {"ADCL Power", NULL, "Frontend PGA L"}, 723 {"ADCR Power", NULL, "Frontend PGA R"}, 724 725 {"ADCL Digital path", NULL, "ADCL Power"}, 726 {"ADCR Digital path", NULL, "ADCR Power"}, 727 {"ADCL Digital path", NULL, "DMIC Enable"}, 728 {"ADCR Digital path", NULL, "DMIC Enable"}, 729 730 {"AIFTX", NULL, "ADCL Digital path"}, 731 {"AIFTX", NULL, "ADCR Digital path"}, 732 733 {"AIFTX", NULL, "System Clock"}, 734 {"AIFRX", NULL, "System Clock"}, 735 736 {"DDACL", NULL, "AIFRX"}, 737 {"DDACR", NULL, "AIFRX"}, 738 739 {"HP amp L", NULL, "DDACL"}, 740 {"HP amp R", NULL, "DDACR"}, 741 742 {"Charge Pump", NULL, "HP amp L"}, 743 {"Charge Pump", NULL, "HP amp R"}, 744 745 {"ADACL", NULL, "Charge Pump"}, 746 {"ADACR", NULL, "Charge Pump"}, 747 {"ADACL Clock", NULL, "ADACL"}, 748 {"ADACR Clock", NULL, "ADACR"}, 749 750 {"Output Driver L Stage 1", NULL, "ADACL Clock"}, 751 {"Output Driver R Stage 1", NULL, "ADACR Clock"}, 752 {"Output Driver L Stage 2", NULL, "Output Driver L Stage 1"}, 753 {"Output Driver R Stage 2", NULL, "Output Driver R Stage 1"}, 754 {"Output Driver L Stage 3", NULL, "Output Driver L Stage 2"}, 755 {"Output Driver R Stage 3", NULL, "Output Driver R Stage 2"}, 756 {"Output DACL", NULL, "Output Driver L Stage 3"}, 757 {"Output DACR", NULL, "Output Driver R Stage 3"}, 758 759 {"HPOL Pulldown", NULL, "Output DACL"}, 760 {"HPOR Pulldown", NULL, "Output DACR"}, 761 {"HP Boost Driver", NULL, "HPOL Pulldown"}, 762 {"HP Boost Driver", NULL, "HPOR Pulldown"}, 763 764 {"Class G", NULL, "HP Boost Driver"}, 765 {"HPOL", NULL, "Class G"}, 766 {"HPOR", NULL, "Class G"}, 767 }; 768 769 static const struct nau8821_osr_attr * 770 nau8821_get_osr(struct nau8821 *nau8821, int stream) 771 { 772 unsigned int osr; 773 774 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 775 regmap_read(nau8821->regmap, NAU8821_R2C_DAC_CTRL1, &osr); 776 osr &= NAU8821_DAC_OVERSAMPLE_MASK; 777 if (osr >= ARRAY_SIZE(osr_dac_sel)) 778 return NULL; 779 return &osr_dac_sel[osr]; 780 } else { 781 regmap_read(nau8821->regmap, NAU8821_R2B_ADC_RATE, &osr); 782 osr &= NAU8821_ADC_SYNC_DOWN_MASK; 783 if (osr >= ARRAY_SIZE(osr_adc_sel)) 784 return NULL; 785 return &osr_adc_sel[osr]; 786 } 787 } 788 789 static int nau8821_dai_startup(struct snd_pcm_substream *substream, 790 struct snd_soc_dai *dai) 791 { 792 struct snd_soc_component *component = dai->component; 793 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 794 const struct nau8821_osr_attr *osr; 795 796 osr = nau8821_get_osr(nau8821, substream->stream); 797 if (!osr || !osr->osr) 798 return -EINVAL; 799 800 return snd_pcm_hw_constraint_minmax(substream->runtime, 801 SNDRV_PCM_HW_PARAM_RATE, 802 0, CLK_DA_AD_MAX / osr->osr); 803 } 804 805 static int nau8821_hw_params(struct snd_pcm_substream *substream, 806 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 807 { 808 struct snd_soc_component *component = dai->component; 809 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 810 unsigned int val_len = 0, ctrl_val, bclk_fs, clk_div; 811 const struct nau8821_osr_attr *osr; 812 813 nau8821->fs = params_rate(params); 814 /* CLK_DAC or CLK_ADC = OSR * FS 815 * DAC or ADC clock frequency is defined as Over Sampling Rate (OSR) 816 * multiplied by the audio sample rate (Fs). Note that the OSR and Fs 817 * values must be selected such that the maximum frequency is less 818 * than 6.144 MHz. 819 */ 820 osr = nau8821_get_osr(nau8821, substream->stream); 821 if (!osr || !osr->osr) 822 return -EINVAL; 823 if (nau8821->fs * osr->osr > CLK_DA_AD_MAX) 824 return -EINVAL; 825 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 826 regmap_update_bits(nau8821->regmap, NAU8821_R03_CLK_DIVIDER, 827 NAU8821_CLK_DAC_SRC_MASK, 828 osr->clk_src << NAU8821_CLK_DAC_SRC_SFT); 829 else 830 regmap_update_bits(nau8821->regmap, NAU8821_R03_CLK_DIVIDER, 831 NAU8821_CLK_ADC_SRC_MASK, 832 osr->clk_src << NAU8821_CLK_ADC_SRC_SFT); 833 834 /* make BCLK and LRC divde configuration if the codec as master. */ 835 regmap_read(nau8821->regmap, NAU8821_R1D_I2S_PCM_CTRL2, &ctrl_val); 836 if (ctrl_val & NAU8821_I2S_MS_MASTER) { 837 /* get the bclk and fs ratio */ 838 bclk_fs = snd_soc_params_to_bclk(params) / nau8821->fs; 839 if (bclk_fs <= 32) 840 clk_div = 3; 841 else if (bclk_fs <= 64) 842 clk_div = 2; 843 else if (bclk_fs <= 128) 844 clk_div = 1; 845 else { 846 return -EINVAL; 847 } 848 regmap_update_bits(nau8821->regmap, NAU8821_R1D_I2S_PCM_CTRL2, 849 NAU8821_I2S_LRC_DIV_MASK | NAU8821_I2S_BLK_DIV_MASK, 850 (clk_div << NAU8821_I2S_LRC_DIV_SFT) | clk_div); 851 } 852 853 switch (params_width(params)) { 854 case 16: 855 val_len |= NAU8821_I2S_DL_16; 856 break; 857 case 20: 858 val_len |= NAU8821_I2S_DL_20; 859 break; 860 case 24: 861 val_len |= NAU8821_I2S_DL_24; 862 break; 863 case 32: 864 val_len |= NAU8821_I2S_DL_32; 865 break; 866 default: 867 return -EINVAL; 868 } 869 870 regmap_update_bits(nau8821->regmap, NAU8821_R1C_I2S_PCM_CTRL1, 871 NAU8821_I2S_DL_MASK, val_len); 872 873 return 0; 874 } 875 876 static int nau8821_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 877 { 878 struct snd_soc_component *component = codec_dai->component; 879 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 880 unsigned int ctrl1_val = 0, ctrl2_val = 0; 881 882 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 883 case SND_SOC_DAIFMT_CBP_CFP: 884 ctrl2_val |= NAU8821_I2S_MS_MASTER; 885 break; 886 case SND_SOC_DAIFMT_CBC_CFC: 887 break; 888 default: 889 return -EINVAL; 890 } 891 892 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 893 case SND_SOC_DAIFMT_NB_NF: 894 break; 895 case SND_SOC_DAIFMT_IB_NF: 896 ctrl1_val |= NAU8821_I2S_BP_INV; 897 break; 898 default: 899 return -EINVAL; 900 } 901 902 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 903 case SND_SOC_DAIFMT_I2S: 904 ctrl1_val |= NAU8821_I2S_DF_I2S; 905 break; 906 case SND_SOC_DAIFMT_LEFT_J: 907 ctrl1_val |= NAU8821_I2S_DF_LEFT; 908 break; 909 case SND_SOC_DAIFMT_RIGHT_J: 910 ctrl1_val |= NAU8821_I2S_DF_RIGTH; 911 break; 912 case SND_SOC_DAIFMT_DSP_A: 913 ctrl1_val |= NAU8821_I2S_DF_PCM_AB; 914 break; 915 case SND_SOC_DAIFMT_DSP_B: 916 ctrl1_val |= NAU8821_I2S_DF_PCM_AB; 917 ctrl1_val |= NAU8821_I2S_PCMB_EN; 918 break; 919 default: 920 return -EINVAL; 921 } 922 923 regmap_update_bits(nau8821->regmap, NAU8821_R1C_I2S_PCM_CTRL1, 924 NAU8821_I2S_DL_MASK | NAU8821_I2S_DF_MASK | 925 NAU8821_I2S_BP_MASK | NAU8821_I2S_PCMB_MASK, ctrl1_val); 926 regmap_update_bits(nau8821->regmap, NAU8821_R1D_I2S_PCM_CTRL2, 927 NAU8821_I2S_MS_MASK, ctrl2_val); 928 929 return 0; 930 } 931 932 static int nau8821_digital_mute(struct snd_soc_dai *dai, int mute, 933 int direction) 934 { 935 struct snd_soc_component *component = dai->component; 936 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 937 unsigned int val = 0; 938 939 if (mute) 940 val = NAU8821_DAC_SOFT_MUTE; 941 942 return regmap_update_bits(nau8821->regmap, 943 NAU8821_R31_MUTE_CTRL, NAU8821_DAC_SOFT_MUTE, val); 944 } 945 946 static const struct snd_soc_dai_ops nau8821_dai_ops = { 947 .startup = nau8821_dai_startup, 948 .hw_params = nau8821_hw_params, 949 .set_fmt = nau8821_set_dai_fmt, 950 .mute_stream = nau8821_digital_mute, 951 .no_capture_mute = 1, 952 }; 953 954 #define NAU8821_RATES SNDRV_PCM_RATE_8000_192000 955 #define NAU8821_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \ 956 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) 957 958 static struct snd_soc_dai_driver nau8821_dai = { 959 .name = NUVOTON_CODEC_DAI, 960 .playback = { 961 .stream_name = "Playback", 962 .channels_min = 1, 963 .channels_max = 2, 964 .rates = NAU8821_RATES, 965 .formats = NAU8821_FORMATS, 966 }, 967 .capture = { 968 .stream_name = "Capture", 969 .channels_min = 1, 970 .channels_max = 2, 971 .rates = NAU8821_RATES, 972 .formats = NAU8821_FORMATS, 973 }, 974 .ops = &nau8821_dai_ops, 975 }; 976 977 978 static bool nau8821_is_jack_inserted(struct regmap *regmap) 979 { 980 bool active_high, is_high; 981 int status, jkdet; 982 983 regmap_read(regmap, NAU8821_R0D_JACK_DET_CTRL, &jkdet); 984 active_high = jkdet & NAU8821_JACK_POLARITY; 985 regmap_read(regmap, NAU8821_R82_GENERAL_STATUS, &status); 986 is_high = status & NAU8821_GPIO2_IN; 987 /* return jack connection status according to jack insertion logic 988 * active high or active low. 989 */ 990 return active_high == is_high; 991 } 992 993 static void nau8821_int_status_clear_all(struct regmap *regmap) 994 { 995 int active_irq, clear_irq, i; 996 997 /* Reset the intrruption status from rightmost bit if the corres- 998 * ponding irq event occurs. 999 */ 1000 regmap_read(regmap, NAU8821_R10_IRQ_STATUS, &active_irq); 1001 for (i = 0; i < NAU8821_REG_DATA_LEN; i++) { 1002 clear_irq = (0x1 << i); 1003 if (active_irq & clear_irq) 1004 regmap_write(regmap, 1005 NAU8821_R11_INT_CLR_KEY_STATUS, clear_irq); 1006 } 1007 } 1008 1009 static void nau8821_eject_jack(struct nau8821 *nau8821) 1010 { 1011 struct snd_soc_dapm_context *dapm = nau8821->dapm; 1012 struct regmap *regmap = nau8821->regmap; 1013 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm); 1014 1015 /* Detach 2kOhm Resistors from MICBIAS to MICGND */ 1016 regmap_update_bits(regmap, NAU8821_R74_MIC_BIAS, 1017 NAU8821_MICBIAS_JKR2, 0); 1018 /* HPL/HPR short to ground */ 1019 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL, 1020 NAU8821_SPKR_DWN1R | NAU8821_SPKR_DWN1L, 0); 1021 snd_soc_component_disable_pin(component, "MICBIAS"); 1022 snd_soc_dapm_sync(dapm); 1023 1024 /* Clear all interruption status */ 1025 nau8821_int_status_clear_all(regmap); 1026 1027 /* Enable the insertion interruption, disable the ejection inter- 1028 * ruption, and then bypass de-bounce circuit. 1029 */ 1030 regmap_update_bits(regmap, NAU8821_R12_INTERRUPT_DIS_CTRL, 1031 NAU8821_IRQ_EJECT_DIS | NAU8821_IRQ_INSERT_DIS, 1032 NAU8821_IRQ_EJECT_DIS); 1033 /* Mask unneeded IRQs: 1 - disable, 0 - enable */ 1034 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK, 1035 NAU8821_IRQ_EJECT_EN | NAU8821_IRQ_INSERT_EN, 1036 NAU8821_IRQ_EJECT_EN); 1037 1038 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL, 1039 NAU8821_JACK_DET_DB_BYPASS, NAU8821_JACK_DET_DB_BYPASS); 1040 1041 /* Close clock for jack type detection at manual mode */ 1042 if (dapm->bias_level < SND_SOC_BIAS_PREPARE) 1043 nau8821_configure_sysclk(nau8821, NAU8821_CLK_DIS, 0); 1044 1045 /* Recover to normal channel input */ 1046 regmap_update_bits(regmap, NAU8821_R2B_ADC_RATE, 1047 NAU8821_ADC_R_SRC_EN, 0); 1048 if (nau8821->key_enable) { 1049 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK, 1050 NAU8821_IRQ_KEY_RELEASE_EN | 1051 NAU8821_IRQ_KEY_PRESS_EN, 1052 NAU8821_IRQ_KEY_RELEASE_EN | 1053 NAU8821_IRQ_KEY_PRESS_EN); 1054 regmap_update_bits(regmap, 1055 NAU8821_R12_INTERRUPT_DIS_CTRL, 1056 NAU8821_IRQ_KEY_RELEASE_DIS | 1057 NAU8821_IRQ_KEY_PRESS_DIS, 1058 NAU8821_IRQ_KEY_RELEASE_DIS | 1059 NAU8821_IRQ_KEY_PRESS_DIS); 1060 } 1061 1062 } 1063 1064 static void nau8821_jdet_work(struct work_struct *work) 1065 { 1066 struct nau8821 *nau8821 = 1067 container_of(work, struct nau8821, jdet_work); 1068 struct snd_soc_dapm_context *dapm = nau8821->dapm; 1069 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm); 1070 struct regmap *regmap = nau8821->regmap; 1071 int jack_status_reg, mic_detected, event = 0, event_mask = 0; 1072 1073 snd_soc_component_force_enable_pin(component, "MICBIAS"); 1074 snd_soc_dapm_sync(dapm); 1075 msleep(20); 1076 1077 regmap_read(regmap, NAU8821_R58_I2C_DEVICE_ID, &jack_status_reg); 1078 mic_detected = !(jack_status_reg & NAU8821_KEYDET); 1079 if (mic_detected) { 1080 dev_dbg(nau8821->dev, "Headset connected\n"); 1081 event |= SND_JACK_HEADSET; 1082 1083 /* 2kOhm Resistor from MICBIAS to MICGND1 */ 1084 regmap_update_bits(regmap, NAU8821_R74_MIC_BIAS, 1085 NAU8821_MICBIAS_JKR2, NAU8821_MICBIAS_JKR2); 1086 /* Latch Right Channel Analog data 1087 * input into the Right Channel Filter 1088 */ 1089 regmap_update_bits(regmap, NAU8821_R2B_ADC_RATE, 1090 NAU8821_ADC_R_SRC_EN, NAU8821_ADC_R_SRC_EN); 1091 if (nau8821->key_enable) { 1092 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK, 1093 NAU8821_IRQ_KEY_RELEASE_EN | 1094 NAU8821_IRQ_KEY_PRESS_EN, 0); 1095 regmap_update_bits(regmap, 1096 NAU8821_R12_INTERRUPT_DIS_CTRL, 1097 NAU8821_IRQ_KEY_RELEASE_DIS | 1098 NAU8821_IRQ_KEY_PRESS_DIS, 0); 1099 } 1100 } else { 1101 dev_dbg(nau8821->dev, "Headphone connected\n"); 1102 event |= SND_JACK_HEADPHONE; 1103 snd_soc_component_disable_pin(component, "MICBIAS"); 1104 snd_soc_dapm_sync(dapm); 1105 } 1106 event_mask |= SND_JACK_HEADSET; 1107 snd_soc_jack_report(nau8821->jack, event, event_mask); 1108 } 1109 1110 /* Enable interruptions with internal clock. */ 1111 static void nau8821_setup_inserted_irq(struct nau8821 *nau8821) 1112 { 1113 struct regmap *regmap = nau8821->regmap; 1114 1115 /* Enable internal VCO needed for interruptions */ 1116 if (nau8821->dapm->bias_level < SND_SOC_BIAS_PREPARE) 1117 nau8821_configure_sysclk(nau8821, NAU8821_CLK_INTERNAL, 0); 1118 1119 /* Chip needs one FSCLK cycle in order to generate interruptions, 1120 * as we cannot guarantee one will be provided by the system. Turning 1121 * master mode on then off enables us to generate that FSCLK cycle 1122 * with a minimum of contention on the clock bus. 1123 */ 1124 regmap_update_bits(regmap, NAU8821_R1D_I2S_PCM_CTRL2, 1125 NAU8821_I2S_MS_MASK, NAU8821_I2S_MS_MASTER); 1126 regmap_update_bits(regmap, NAU8821_R1D_I2S_PCM_CTRL2, 1127 NAU8821_I2S_MS_MASK, NAU8821_I2S_MS_SLAVE); 1128 1129 /* Not bypass de-bounce circuit */ 1130 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL, 1131 NAU8821_JACK_DET_DB_BYPASS, 0); 1132 1133 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK, 1134 NAU8821_IRQ_EJECT_EN, 0); 1135 regmap_update_bits(regmap, NAU8821_R12_INTERRUPT_DIS_CTRL, 1136 NAU8821_IRQ_EJECT_DIS, 0); 1137 } 1138 1139 static irqreturn_t nau8821_interrupt(int irq, void *data) 1140 { 1141 struct nau8821 *nau8821 = (struct nau8821 *)data; 1142 struct regmap *regmap = nau8821->regmap; 1143 int active_irq, clear_irq = 0, event = 0, event_mask = 0; 1144 1145 if (regmap_read(regmap, NAU8821_R10_IRQ_STATUS, &active_irq)) { 1146 dev_err(nau8821->dev, "failed to read irq status\n"); 1147 return IRQ_NONE; 1148 } 1149 1150 dev_dbg(nau8821->dev, "IRQ %d\n", active_irq); 1151 1152 if ((active_irq & NAU8821_JACK_EJECT_IRQ_MASK) == 1153 NAU8821_JACK_EJECT_DETECTED) { 1154 regmap_update_bits(regmap, NAU8821_R71_ANALOG_ADC_1, 1155 NAU8821_MICDET_MASK, NAU8821_MICDET_DIS); 1156 nau8821_eject_jack(nau8821); 1157 event_mask |= SND_JACK_HEADSET; 1158 clear_irq = NAU8821_JACK_EJECT_IRQ_MASK; 1159 } else if (active_irq & NAU8821_KEY_SHORT_PRESS_IRQ) { 1160 event |= NAU8821_BUTTON; 1161 event_mask |= NAU8821_BUTTON; 1162 clear_irq = NAU8821_KEY_SHORT_PRESS_IRQ; 1163 } else if (active_irq & NAU8821_KEY_RELEASE_IRQ) { 1164 event_mask = NAU8821_BUTTON; 1165 clear_irq = NAU8821_KEY_RELEASE_IRQ; 1166 } else if ((active_irq & NAU8821_JACK_INSERT_IRQ_MASK) == 1167 NAU8821_JACK_INSERT_DETECTED) { 1168 regmap_update_bits(regmap, NAU8821_R71_ANALOG_ADC_1, 1169 NAU8821_MICDET_MASK, NAU8821_MICDET_EN); 1170 if (nau8821_is_jack_inserted(regmap)) { 1171 /* detect microphone and jack type */ 1172 cancel_work_sync(&nau8821->jdet_work); 1173 schedule_work(&nau8821->jdet_work); 1174 /* Turn off insertion interruption at manual mode */ 1175 regmap_update_bits(regmap, 1176 NAU8821_R12_INTERRUPT_DIS_CTRL, 1177 NAU8821_IRQ_INSERT_DIS, 1178 NAU8821_IRQ_INSERT_DIS); 1179 regmap_update_bits(regmap, 1180 NAU8821_R0F_INTERRUPT_MASK, 1181 NAU8821_IRQ_INSERT_EN, 1182 NAU8821_IRQ_INSERT_EN); 1183 nau8821_setup_inserted_irq(nau8821); 1184 } else { 1185 dev_warn(nau8821->dev, 1186 "Inserted IRQ fired but not connected\n"); 1187 nau8821_eject_jack(nau8821); 1188 } 1189 } 1190 1191 if (!clear_irq) 1192 clear_irq = active_irq; 1193 /* clears the rightmost interruption */ 1194 regmap_write(regmap, NAU8821_R11_INT_CLR_KEY_STATUS, clear_irq); 1195 1196 if (event_mask) 1197 snd_soc_jack_report(nau8821->jack, event, event_mask); 1198 1199 return IRQ_HANDLED; 1200 } 1201 1202 static const struct regmap_config nau8821_regmap_config = { 1203 .val_bits = NAU8821_REG_DATA_LEN, 1204 .reg_bits = NAU8821_REG_ADDR_LEN, 1205 1206 .max_register = NAU8821_REG_MAX, 1207 .readable_reg = nau8821_readable_reg, 1208 .writeable_reg = nau8821_writeable_reg, 1209 .volatile_reg = nau8821_volatile_reg, 1210 1211 .cache_type = REGCACHE_RBTREE, 1212 .reg_defaults = nau8821_reg_defaults, 1213 .num_reg_defaults = ARRAY_SIZE(nau8821_reg_defaults), 1214 }; 1215 1216 static int nau8821_component_probe(struct snd_soc_component *component) 1217 { 1218 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 1219 struct snd_soc_dapm_context *dapm = 1220 snd_soc_component_get_dapm(component); 1221 1222 nau8821->dapm = dapm; 1223 1224 return 0; 1225 } 1226 1227 /** 1228 * nau8821_calc_fll_param - Calculate FLL parameters. 1229 * @fll_in: external clock provided to codec. 1230 * @fs: sampling rate. 1231 * @fll_param: Pointer to structure of FLL parameters. 1232 * 1233 * Calculate FLL parameters to configure codec. 1234 * 1235 * Returns 0 for success or negative error code. 1236 */ 1237 static int nau8821_calc_fll_param(unsigned int fll_in, 1238 unsigned int fs, struct nau8821_fll *fll_param) 1239 { 1240 u64 fvco, fvco_max; 1241 unsigned int fref, i, fvco_sel; 1242 1243 /* Ensure the reference clock frequency (FREF) is <= 13.5MHz by 1244 * dividing freq_in by 1, 2, 4, or 8 using FLL pre-scalar. 1245 * FREF = freq_in / NAU8821_FLL_REF_DIV_MASK 1246 */ 1247 for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) { 1248 fref = fll_in >> fll_pre_scalar[i].param; 1249 if (fref <= NAU_FREF_MAX) 1250 break; 1251 } 1252 if (i == ARRAY_SIZE(fll_pre_scalar)) 1253 return -EINVAL; 1254 fll_param->clk_ref_div = fll_pre_scalar[i].val; 1255 1256 /* Choose the FLL ratio based on FREF */ 1257 for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) { 1258 if (fref >= fll_ratio[i].param) 1259 break; 1260 } 1261 if (i == ARRAY_SIZE(fll_ratio)) 1262 return -EINVAL; 1263 fll_param->ratio = fll_ratio[i].val; 1264 1265 /* Calculate the frequency of DCO (FDCO) given freq_out = 256 * Fs. 1266 * FDCO must be within the 90MHz - 100MHz or the FFL cannot be 1267 * guaranteed across the full range of operation. 1268 * FDCO = freq_out * 2 * mclk_src_scaling 1269 */ 1270 fvco_max = 0; 1271 fvco_sel = ARRAY_SIZE(mclk_src_scaling); 1272 for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) { 1273 fvco = 256ULL * fs * 2 * mclk_src_scaling[i].param; 1274 if (fvco > NAU_FVCO_MIN && fvco < NAU_FVCO_MAX && 1275 fvco_max < fvco) { 1276 fvco_max = fvco; 1277 fvco_sel = i; 1278 } 1279 } 1280 if (ARRAY_SIZE(mclk_src_scaling) == fvco_sel) 1281 return -EINVAL; 1282 fll_param->mclk_src = mclk_src_scaling[fvco_sel].val; 1283 1284 /* Calculate the FLL 10-bit integer input and the FLL 24-bit fractional 1285 * input based on FDCO, FREF and FLL ratio. 1286 */ 1287 fvco = div_u64(fvco_max << 24, fref * fll_param->ratio); 1288 fll_param->fll_int = (fvco >> 24) & 0x3ff; 1289 fll_param->fll_frac = fvco & 0xffffff; 1290 1291 return 0; 1292 } 1293 1294 static void nau8821_fll_apply(struct nau8821 *nau8821, 1295 struct nau8821_fll *fll_param) 1296 { 1297 struct regmap *regmap = nau8821->regmap; 1298 1299 regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER, 1300 NAU8821_CLK_SRC_MASK | NAU8821_CLK_MCLK_SRC_MASK, 1301 NAU8821_CLK_SRC_MCLK | fll_param->mclk_src); 1302 /* Make DSP operate at high speed for better performance. */ 1303 regmap_update_bits(regmap, NAU8821_R04_FLL1, 1304 NAU8821_FLL_RATIO_MASK | NAU8821_ICTRL_LATCH_MASK, 1305 fll_param->ratio | (0x6 << NAU8821_ICTRL_LATCH_SFT)); 1306 /* FLL 24-bit fractional input */ 1307 regmap_write(regmap, NAU8821_R0A_FLL7, 1308 (fll_param->fll_frac >> 16) & 0xff); 1309 regmap_write(regmap, NAU8821_R0B_FLL8, fll_param->fll_frac & 0xffff); 1310 /* FLL 10-bit integer input */ 1311 regmap_update_bits(regmap, NAU8821_R06_FLL3, 1312 NAU8821_FLL_INTEGER_MASK, fll_param->fll_int); 1313 /* FLL pre-scaler */ 1314 regmap_update_bits(regmap, NAU8821_R07_FLL4, 1315 NAU8821_HIGHBW_EN | NAU8821_FLL_REF_DIV_MASK, 1316 NAU8821_HIGHBW_EN | 1317 (fll_param->clk_ref_div << NAU8821_FLL_REF_DIV_SFT)); 1318 /* select divided VCO input */ 1319 regmap_update_bits(regmap, NAU8821_R08_FLL5, 1320 NAU8821_FLL_CLK_SW_MASK, NAU8821_FLL_CLK_SW_REF); 1321 /* Disable free-running mode */ 1322 regmap_update_bits(regmap, 1323 NAU8821_R09_FLL6, NAU8821_DCO_EN, 0); 1324 if (fll_param->fll_frac) { 1325 /* set FLL loop filter enable and cutoff frequency at 500Khz */ 1326 regmap_update_bits(regmap, NAU8821_R08_FLL5, 1327 NAU8821_FLL_PDB_DAC_EN | NAU8821_FLL_LOOP_FTR_EN | 1328 NAU8821_FLL_FTR_SW_MASK, 1329 NAU8821_FLL_PDB_DAC_EN | NAU8821_FLL_LOOP_FTR_EN | 1330 NAU8821_FLL_FTR_SW_FILTER); 1331 regmap_update_bits(regmap, NAU8821_R09_FLL6, 1332 NAU8821_SDM_EN | NAU8821_CUTOFF500, 1333 NAU8821_SDM_EN | NAU8821_CUTOFF500); 1334 } else { 1335 /* disable FLL loop filter and cutoff frequency */ 1336 regmap_update_bits(regmap, NAU8821_R08_FLL5, 1337 NAU8821_FLL_PDB_DAC_EN | NAU8821_FLL_LOOP_FTR_EN | 1338 NAU8821_FLL_FTR_SW_MASK, NAU8821_FLL_FTR_SW_ACCU); 1339 regmap_update_bits(regmap, NAU8821_R09_FLL6, 1340 NAU8821_SDM_EN | NAU8821_CUTOFF500, 0); 1341 } 1342 } 1343 1344 /** 1345 * nau8821_set_fll - FLL configuration of nau8821 1346 * @component: codec component 1347 * @pll_id: PLL requested 1348 * @source: clock source 1349 * @freq_in: frequency of input clock source 1350 * @freq_out: must be 256*Fs in order to achieve the best performance 1351 * 1352 * The FLL function can select BCLK or MCLK as the input clock source. 1353 * 1354 * Returns 0 if the parameters have been applied successfully 1355 * or negative error code. 1356 */ 1357 static int nau8821_set_fll(struct snd_soc_component *component, 1358 int pll_id, int source, unsigned int freq_in, unsigned int freq_out) 1359 { 1360 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 1361 struct nau8821_fll fll_set_param, *fll_param = &fll_set_param; 1362 int ret, fs; 1363 1364 fs = freq_out >> 8; 1365 ret = nau8821_calc_fll_param(freq_in, fs, fll_param); 1366 if (ret) { 1367 dev_err(nau8821->dev, 1368 "Unsupported input clock %d to output clock %d\n", 1369 freq_in, freq_out); 1370 return ret; 1371 } 1372 dev_dbg(nau8821->dev, 1373 "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n", 1374 fll_param->mclk_src, fll_param->ratio, fll_param->fll_frac, 1375 fll_param->fll_int, fll_param->clk_ref_div); 1376 1377 nau8821_fll_apply(nau8821, fll_param); 1378 mdelay(2); 1379 regmap_update_bits(nau8821->regmap, NAU8821_R03_CLK_DIVIDER, 1380 NAU8821_CLK_SRC_MASK, NAU8821_CLK_SRC_VCO); 1381 1382 return 0; 1383 } 1384 1385 static void nau8821_configure_mclk_as_sysclk(struct regmap *regmap) 1386 { 1387 regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER, 1388 NAU8821_CLK_SRC_MASK, NAU8821_CLK_SRC_MCLK); 1389 regmap_update_bits(regmap, NAU8821_R09_FLL6, 1390 NAU8821_DCO_EN, 0); 1391 /* Make DSP operate as default setting for power saving. */ 1392 regmap_update_bits(regmap, NAU8821_R04_FLL1, 1393 NAU8821_ICTRL_LATCH_MASK, 0); 1394 } 1395 1396 static int nau8821_configure_sysclk(struct nau8821 *nau8821, 1397 int clk_id, unsigned int freq) 1398 { 1399 struct regmap *regmap = nau8821->regmap; 1400 1401 switch (clk_id) { 1402 case NAU8821_CLK_DIS: 1403 /* Clock provided externally and disable internal VCO clock */ 1404 nau8821_configure_mclk_as_sysclk(regmap); 1405 break; 1406 case NAU8821_CLK_MCLK: 1407 nau8821_configure_mclk_as_sysclk(regmap); 1408 /* MCLK not changed by clock tree */ 1409 regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER, 1410 NAU8821_CLK_MCLK_SRC_MASK, 0); 1411 break; 1412 case NAU8821_CLK_INTERNAL: 1413 if (nau8821_is_jack_inserted(regmap)) { 1414 regmap_update_bits(regmap, NAU8821_R09_FLL6, 1415 NAU8821_DCO_EN, NAU8821_DCO_EN); 1416 regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER, 1417 NAU8821_CLK_SRC_MASK, NAU8821_CLK_SRC_VCO); 1418 /* Decrease the VCO frequency and make DSP operate 1419 * as default setting for power saving. 1420 */ 1421 regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER, 1422 NAU8821_CLK_MCLK_SRC_MASK, 0xf); 1423 regmap_update_bits(regmap, NAU8821_R04_FLL1, 1424 NAU8821_ICTRL_LATCH_MASK | 1425 NAU8821_FLL_RATIO_MASK, 0x10); 1426 regmap_update_bits(regmap, NAU8821_R09_FLL6, 1427 NAU8821_SDM_EN, NAU8821_SDM_EN); 1428 } 1429 break; 1430 case NAU8821_CLK_FLL_MCLK: 1431 /* Higher FLL reference input frequency can only set lower 1432 * gain error, such as 0000 for input reference from MCLK 1433 * 12.288Mhz. 1434 */ 1435 regmap_update_bits(regmap, NAU8821_R06_FLL3, 1436 NAU8821_FLL_CLK_SRC_MASK | NAU8821_GAIN_ERR_MASK, 1437 NAU8821_FLL_CLK_SRC_MCLK | 0); 1438 break; 1439 case NAU8821_CLK_FLL_BLK: 1440 /* If FLL reference input is from low frequency source, 1441 * higher error gain can apply such as 0xf which has 1442 * the most sensitive gain error correction threshold, 1443 * Therefore, FLL has the most accurate DCO to 1444 * target frequency. 1445 */ 1446 regmap_update_bits(regmap, NAU8821_R06_FLL3, 1447 NAU8821_FLL_CLK_SRC_MASK | NAU8821_GAIN_ERR_MASK, 1448 NAU8821_FLL_CLK_SRC_BLK | 1449 (0xf << NAU8821_GAIN_ERR_SFT)); 1450 break; 1451 case NAU8821_CLK_FLL_FS: 1452 /* If FLL reference input is from low frequency source, 1453 * higher error gain can apply such as 0xf which has 1454 * the most sensitive gain error correction threshold, 1455 * Therefore, FLL has the most accurate DCO to 1456 * target frequency. 1457 */ 1458 regmap_update_bits(regmap, NAU8821_R06_FLL3, 1459 NAU8821_FLL_CLK_SRC_MASK | NAU8821_GAIN_ERR_MASK, 1460 NAU8821_FLL_CLK_SRC_FS | 1461 (0xf << NAU8821_GAIN_ERR_SFT)); 1462 break; 1463 default: 1464 dev_err(nau8821->dev, "Invalid clock id (%d)\n", clk_id); 1465 return -EINVAL; 1466 } 1467 nau8821->clk_id = clk_id; 1468 dev_dbg(nau8821->dev, "Sysclk is %dHz and clock id is %d\n", freq, 1469 nau8821->clk_id); 1470 1471 return 0; 1472 } 1473 1474 static int nau8821_set_sysclk(struct snd_soc_component *component, int clk_id, 1475 int source, unsigned int freq, int dir) 1476 { 1477 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 1478 1479 return nau8821_configure_sysclk(nau8821, clk_id, freq); 1480 } 1481 1482 static int nau8821_resume_setup(struct nau8821 *nau8821) 1483 { 1484 struct regmap *regmap = nau8821->regmap; 1485 1486 /* Close clock when jack type detection at manual mode */ 1487 nau8821_configure_sysclk(nau8821, NAU8821_CLK_DIS, 0); 1488 if (nau8821->irq) { 1489 /* Clear all interruption status */ 1490 nau8821_int_status_clear_all(regmap); 1491 1492 /* Enable both insertion and ejection interruptions, and then 1493 * bypass de-bounce circuit. 1494 */ 1495 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK, 1496 NAU8821_IRQ_EJECT_EN | NAU8821_IRQ_INSERT_EN, 0); 1497 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL, 1498 NAU8821_JACK_DET_DB_BYPASS, 1499 NAU8821_JACK_DET_DB_BYPASS); 1500 regmap_update_bits(regmap, NAU8821_R12_INTERRUPT_DIS_CTRL, 1501 NAU8821_IRQ_INSERT_DIS | NAU8821_IRQ_EJECT_DIS, 0); 1502 } 1503 1504 return 0; 1505 } 1506 1507 static int nau8821_set_bias_level(struct snd_soc_component *component, 1508 enum snd_soc_bias_level level) 1509 { 1510 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 1511 struct regmap *regmap = nau8821->regmap; 1512 1513 switch (level) { 1514 case SND_SOC_BIAS_ON: 1515 break; 1516 1517 case SND_SOC_BIAS_PREPARE: 1518 break; 1519 1520 case SND_SOC_BIAS_STANDBY: 1521 /* Setup codec configuration after resume */ 1522 if (snd_soc_component_get_bias_level(component) == 1523 SND_SOC_BIAS_OFF) 1524 nau8821_resume_setup(nau8821); 1525 break; 1526 1527 case SND_SOC_BIAS_OFF: 1528 /* HPL/HPR short to ground */ 1529 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL, 1530 NAU8821_SPKR_DWN1R | NAU8821_SPKR_DWN1L, 0); 1531 if (nau8821->irq) { 1532 /* Reset the configuration of jack type for detection. 1533 * Detach 2kOhm Resistors from MICBIAS to MICGND1/2. 1534 */ 1535 regmap_update_bits(regmap, NAU8821_R74_MIC_BIAS, 1536 NAU8821_MICBIAS_JKR2, 0); 1537 /* Turn off all interruptions before system shutdown. 1538 * Keep theinterruption quiet before resume 1539 * setup completes. 1540 */ 1541 regmap_write(regmap, 1542 NAU8821_R12_INTERRUPT_DIS_CTRL, 0xffff); 1543 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK, 1544 NAU8821_IRQ_EJECT_EN | NAU8821_IRQ_INSERT_EN, 1545 NAU8821_IRQ_EJECT_EN | NAU8821_IRQ_INSERT_EN); 1546 } 1547 break; 1548 default: 1549 break; 1550 } 1551 1552 return 0; 1553 } 1554 1555 static int __maybe_unused nau8821_suspend(struct snd_soc_component *component) 1556 { 1557 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 1558 1559 if (nau8821->irq) 1560 disable_irq(nau8821->irq); 1561 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF); 1562 /* Power down codec power; don't support button wakeup */ 1563 snd_soc_component_disable_pin(component, "MICBIAS"); 1564 snd_soc_dapm_sync(nau8821->dapm); 1565 regcache_cache_only(nau8821->regmap, true); 1566 regcache_mark_dirty(nau8821->regmap); 1567 1568 return 0; 1569 } 1570 1571 static int __maybe_unused nau8821_resume(struct snd_soc_component *component) 1572 { 1573 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 1574 1575 regcache_cache_only(nau8821->regmap, false); 1576 regcache_sync(nau8821->regmap); 1577 if (nau8821->irq) 1578 enable_irq(nau8821->irq); 1579 1580 return 0; 1581 } 1582 1583 static const struct snd_soc_component_driver nau8821_component_driver = { 1584 .probe = nau8821_component_probe, 1585 .set_sysclk = nau8821_set_sysclk, 1586 .set_pll = nau8821_set_fll, 1587 .set_bias_level = nau8821_set_bias_level, 1588 .suspend = nau8821_suspend, 1589 .resume = nau8821_resume, 1590 .controls = nau8821_controls, 1591 .num_controls = ARRAY_SIZE(nau8821_controls), 1592 .dapm_widgets = nau8821_dapm_widgets, 1593 .num_dapm_widgets = ARRAY_SIZE(nau8821_dapm_widgets), 1594 .dapm_routes = nau8821_dapm_routes, 1595 .num_dapm_routes = ARRAY_SIZE(nau8821_dapm_routes), 1596 .suspend_bias_off = 1, 1597 .idle_bias_on = 1, 1598 .use_pmdown_time = 1, 1599 .endianness = 1, 1600 }; 1601 1602 /** 1603 * nau8821_enable_jack_detect - Specify a jack for event reporting 1604 * 1605 * @component: component to register the jack with 1606 * @jack: jack to use to report headset and button events on 1607 * 1608 * After this function has been called the headset insert/remove and button 1609 * events will be routed to the given jack. Jack can be null to stop 1610 * reporting. 1611 */ 1612 int nau8821_enable_jack_detect(struct snd_soc_component *component, 1613 struct snd_soc_jack *jack) 1614 { 1615 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 1616 int ret; 1617 1618 nau8821->jack = jack; 1619 /* Initiate jack detection work queue */ 1620 INIT_WORK(&nau8821->jdet_work, nau8821_jdet_work); 1621 ret = devm_request_threaded_irq(nau8821->dev, nau8821->irq, NULL, 1622 nau8821_interrupt, IRQF_TRIGGER_LOW | IRQF_ONESHOT, 1623 "nau8821", nau8821); 1624 if (ret) { 1625 dev_err(nau8821->dev, "Cannot request irq %d (%d)\n", 1626 nau8821->irq, ret); 1627 return ret; 1628 } 1629 1630 return ret; 1631 } 1632 EXPORT_SYMBOL_GPL(nau8821_enable_jack_detect); 1633 1634 static void nau8821_reset_chip(struct regmap *regmap) 1635 { 1636 regmap_write(regmap, NAU8821_R00_RESET, 0xffff); 1637 regmap_write(regmap, NAU8821_R00_RESET, 0xffff); 1638 } 1639 1640 static void nau8821_print_device_properties(struct nau8821 *nau8821) 1641 { 1642 struct device *dev = nau8821->dev; 1643 1644 dev_dbg(dev, "jkdet-enable: %d\n", nau8821->jkdet_enable); 1645 dev_dbg(dev, "jkdet-pull-enable: %d\n", nau8821->jkdet_pull_enable); 1646 dev_dbg(dev, "jkdet-pull-up: %d\n", nau8821->jkdet_pull_up); 1647 dev_dbg(dev, "jkdet-polarity: %d\n", nau8821->jkdet_polarity); 1648 dev_dbg(dev, "micbias-voltage: %d\n", nau8821->micbias_voltage); 1649 dev_dbg(dev, "vref-impedance: %d\n", nau8821->vref_impedance); 1650 dev_dbg(dev, "jack-insert-debounce: %d\n", 1651 nau8821->jack_insert_debounce); 1652 dev_dbg(dev, "jack-eject-debounce: %d\n", 1653 nau8821->jack_eject_debounce); 1654 dev_dbg(dev, "dmic-clk-threshold: %d\n", 1655 nau8821->dmic_clk_threshold); 1656 dev_dbg(dev, "key_enable: %d\n", nau8821->key_enable); 1657 } 1658 1659 static int nau8821_read_device_properties(struct device *dev, 1660 struct nau8821 *nau8821) 1661 { 1662 int ret; 1663 1664 nau8821->jkdet_enable = device_property_read_bool(dev, 1665 "nuvoton,jkdet-enable"); 1666 nau8821->jkdet_pull_enable = device_property_read_bool(dev, 1667 "nuvoton,jkdet-pull-enable"); 1668 nau8821->jkdet_pull_up = device_property_read_bool(dev, 1669 "nuvoton,jkdet-pull-up"); 1670 nau8821->key_enable = device_property_read_bool(dev, 1671 "nuvoton,key-enable"); 1672 ret = device_property_read_u32(dev, "nuvoton,jkdet-polarity", 1673 &nau8821->jkdet_polarity); 1674 if (ret) 1675 nau8821->jkdet_polarity = 1; 1676 ret = device_property_read_u32(dev, "nuvoton,micbias-voltage", 1677 &nau8821->micbias_voltage); 1678 if (ret) 1679 nau8821->micbias_voltage = 6; 1680 ret = device_property_read_u32(dev, "nuvoton,vref-impedance", 1681 &nau8821->vref_impedance); 1682 if (ret) 1683 nau8821->vref_impedance = 2; 1684 ret = device_property_read_u32(dev, "nuvoton,jack-insert-debounce", 1685 &nau8821->jack_insert_debounce); 1686 if (ret) 1687 nau8821->jack_insert_debounce = 7; 1688 ret = device_property_read_u32(dev, "nuvoton,jack-eject-debounce", 1689 &nau8821->jack_eject_debounce); 1690 if (ret) 1691 nau8821->jack_eject_debounce = 0; 1692 ret = device_property_read_u32(dev, "nuvoton,dmic-clk-threshold", 1693 &nau8821->dmic_clk_threshold); 1694 if (ret) 1695 nau8821->dmic_clk_threshold = 3072000; 1696 1697 return 0; 1698 } 1699 1700 static void nau8821_init_regs(struct nau8821 *nau8821) 1701 { 1702 struct regmap *regmap = nau8821->regmap; 1703 1704 /* Enable Bias/Vmid */ 1705 regmap_update_bits(regmap, NAU8821_R66_BIAS_ADJ, 1706 NAU8821_BIAS_VMID, NAU8821_BIAS_VMID); 1707 regmap_update_bits(regmap, NAU8821_R76_BOOST, 1708 NAU8821_GLOBAL_BIAS_EN, NAU8821_GLOBAL_BIAS_EN); 1709 /* VMID Tieoff setting and enable TESTDAC. 1710 * This sets the analog DAC inputs to a '0' input signal to avoid 1711 * any glitches due to power up transients in both the analog and 1712 * digital DAC circuit. 1713 */ 1714 regmap_update_bits(regmap, NAU8821_R66_BIAS_ADJ, 1715 NAU8821_BIAS_VMID_SEL_MASK | NAU8821_BIAS_TESTDAC_EN, 1716 (nau8821->vref_impedance << NAU8821_BIAS_VMID_SEL_SFT) | 1717 NAU8821_BIAS_TESTDAC_EN); 1718 /* Disable short Frame Sync detection logic */ 1719 regmap_update_bits(regmap, NAU8821_R1E_LEFT_TIME_SLOT, 1720 NAU8821_DIS_FS_SHORT_DET, NAU8821_DIS_FS_SHORT_DET); 1721 /* Disable Boost Driver, Automatic Short circuit protection enable */ 1722 regmap_update_bits(regmap, NAU8821_R76_BOOST, 1723 NAU8821_PRECHARGE_DIS | NAU8821_HP_BOOST_DIS | 1724 NAU8821_HP_BOOST_G_DIS | NAU8821_SHORT_SHUTDOWN_EN, 1725 NAU8821_PRECHARGE_DIS | NAU8821_HP_BOOST_DIS | 1726 NAU8821_HP_BOOST_G_DIS | NAU8821_SHORT_SHUTDOWN_EN); 1727 /* Class G timer 64ms */ 1728 regmap_update_bits(regmap, NAU8821_R4B_CLASSG_CTRL, 1729 NAU8821_CLASSG_TIMER_MASK, 1730 0x20 << NAU8821_CLASSG_TIMER_SFT); 1731 /* Class AB bias current to 2x, DAC Capacitor enable MSB/LSB */ 1732 regmap_update_bits(regmap, NAU8821_R6A_ANALOG_CONTROL_2, 1733 NAU8821_HP_NON_CLASSG_CURRENT_2xADJ | 1734 NAU8821_DAC_CAPACITOR_MSB | NAU8821_DAC_CAPACITOR_LSB, 1735 NAU8821_HP_NON_CLASSG_CURRENT_2xADJ | 1736 NAU8821_DAC_CAPACITOR_MSB | NAU8821_DAC_CAPACITOR_LSB); 1737 /* Disable DACR/L power */ 1738 regmap_update_bits(regmap, NAU8821_R80_CHARGE_PUMP, 1739 NAU8821_POWER_DOWN_DACR | NAU8821_POWER_DOWN_DACL, 0); 1740 /* DAC clock delay 2ns, VREF */ 1741 regmap_update_bits(regmap, NAU8821_R73_RDAC, 1742 NAU8821_DAC_CLK_DELAY_MASK | NAU8821_DAC_VREF_MASK, 1743 (0x2 << NAU8821_DAC_CLK_DELAY_SFT) | 1744 (0x3 << NAU8821_DAC_VREF_SFT)); 1745 1746 regmap_update_bits(regmap, NAU8821_R74_MIC_BIAS, 1747 NAU8821_MICBIAS_VOLTAGE_MASK, nau8821->micbias_voltage); 1748 /* Default oversampling/decimations settings are unusable 1749 * (audible hiss). Set it to something better. 1750 */ 1751 regmap_update_bits(regmap, NAU8821_R2B_ADC_RATE, 1752 NAU8821_ADC_SYNC_DOWN_MASK, NAU8821_ADC_SYNC_DOWN_64); 1753 regmap_update_bits(regmap, NAU8821_R2C_DAC_CTRL1, 1754 NAU8821_DAC_OVERSAMPLE_MASK, NAU8821_DAC_OVERSAMPLE_64); 1755 } 1756 1757 static int nau8821_setup_irq(struct nau8821 *nau8821) 1758 { 1759 struct regmap *regmap = nau8821->regmap; 1760 1761 /* Jack detection */ 1762 regmap_update_bits(regmap, NAU8821_R1A_GPIO12_CTRL, 1763 NAU8821_JKDET_OUTPUT_EN, 1764 nau8821->jkdet_enable ? 0 : NAU8821_JKDET_OUTPUT_EN); 1765 regmap_update_bits(regmap, NAU8821_R1A_GPIO12_CTRL, 1766 NAU8821_JKDET_PULL_EN, 1767 nau8821->jkdet_pull_enable ? 0 : NAU8821_JKDET_PULL_EN); 1768 regmap_update_bits(regmap, NAU8821_R1A_GPIO12_CTRL, 1769 NAU8821_JKDET_PULL_UP, 1770 nau8821->jkdet_pull_up ? NAU8821_JKDET_PULL_UP : 0); 1771 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL, 1772 NAU8821_JACK_POLARITY, 1773 /* jkdet_polarity - 1 is for active-low */ 1774 nau8821->jkdet_polarity ? 0 : NAU8821_JACK_POLARITY); 1775 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL, 1776 NAU8821_JACK_INSERT_DEBOUNCE_MASK, 1777 nau8821->jack_insert_debounce << 1778 NAU8821_JACK_INSERT_DEBOUNCE_SFT); 1779 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL, 1780 NAU8821_JACK_EJECT_DEBOUNCE_MASK, 1781 nau8821->jack_eject_debounce << 1782 NAU8821_JACK_EJECT_DEBOUNCE_SFT); 1783 /* Pull up IRQ pin */ 1784 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK, 1785 NAU8821_IRQ_PIN_PULL_UP | NAU8821_IRQ_PIN_PULL_EN | 1786 NAU8821_IRQ_OUTPUT_EN, NAU8821_IRQ_PIN_PULL_UP | 1787 NAU8821_IRQ_PIN_PULL_EN | NAU8821_IRQ_OUTPUT_EN); 1788 /* Disable interruption before codec initiation done */ 1789 /* Mask unneeded IRQs: 1 - disable, 0 - enable */ 1790 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK, 0x3f5, 0x3f5); 1791 1792 return 0; 1793 } 1794 1795 static int nau8821_i2c_probe(struct i2c_client *i2c) 1796 { 1797 struct device *dev = &i2c->dev; 1798 struct nau8821 *nau8821 = dev_get_platdata(&i2c->dev); 1799 int ret, value; 1800 1801 if (!nau8821) { 1802 nau8821 = devm_kzalloc(dev, sizeof(*nau8821), GFP_KERNEL); 1803 if (!nau8821) 1804 return -ENOMEM; 1805 nau8821_read_device_properties(dev, nau8821); 1806 } 1807 i2c_set_clientdata(i2c, nau8821); 1808 1809 nau8821->regmap = devm_regmap_init_i2c(i2c, &nau8821_regmap_config); 1810 if (IS_ERR(nau8821->regmap)) 1811 return PTR_ERR(nau8821->regmap); 1812 1813 nau8821->dev = dev; 1814 nau8821->irq = i2c->irq; 1815 nau8821_print_device_properties(nau8821); 1816 1817 nau8821_reset_chip(nau8821->regmap); 1818 ret = regmap_read(nau8821->regmap, NAU8821_R58_I2C_DEVICE_ID, &value); 1819 if (ret) { 1820 dev_err(dev, "Failed to read device id (%d)\n", ret); 1821 return ret; 1822 } 1823 nau8821_init_regs(nau8821); 1824 1825 if (i2c->irq) 1826 nau8821_setup_irq(nau8821); 1827 1828 ret = devm_snd_soc_register_component(&i2c->dev, 1829 &nau8821_component_driver, &nau8821_dai, 1); 1830 1831 return ret; 1832 } 1833 1834 static const struct i2c_device_id nau8821_i2c_ids[] = { 1835 { "nau8821", 0 }, 1836 { } 1837 }; 1838 MODULE_DEVICE_TABLE(i2c, nau8821_i2c_ids); 1839 1840 #ifdef CONFIG_OF 1841 static const struct of_device_id nau8821_of_ids[] = { 1842 { .compatible = "nuvoton,nau8821", }, 1843 {} 1844 }; 1845 MODULE_DEVICE_TABLE(of, nau8821_of_ids); 1846 #endif 1847 1848 #ifdef CONFIG_ACPI 1849 static const struct acpi_device_id nau8821_acpi_match[] = { 1850 { "NVTN2020", 0 }, 1851 {}, 1852 }; 1853 MODULE_DEVICE_TABLE(acpi, nau8821_acpi_match); 1854 #endif 1855 1856 static struct i2c_driver nau8821_driver = { 1857 .driver = { 1858 .name = "nau8821", 1859 .of_match_table = of_match_ptr(nau8821_of_ids), 1860 .acpi_match_table = ACPI_PTR(nau8821_acpi_match), 1861 }, 1862 .probe = nau8821_i2c_probe, 1863 .id_table = nau8821_i2c_ids, 1864 }; 1865 module_i2c_driver(nau8821_driver); 1866 1867 MODULE_DESCRIPTION("ASoC nau8821 driver"); 1868 MODULE_AUTHOR("John Hsu <kchsu0@nuvoton.com>"); 1869 MODULE_AUTHOR("Seven Lee <wtli@nuvoton.com>"); 1870 MODULE_LICENSE("GPL"); 1871