1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include "amdgpu.h" 27 #include "soc15_common.h" 28 #include "soc21.h" 29 #include "gc/gc_11_0_0_offset.h" 30 #include "gc/gc_11_0_0_sh_mask.h" 31 #include "gc/gc_11_0_0_default.h" 32 #include "v11_structs.h" 33 #include "mes_v11_api_def.h" 34 35 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes.bin"); 36 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes_2.bin"); 37 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes1.bin"); 38 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes.bin"); 39 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes_2.bin"); 40 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes1.bin"); 41 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes.bin"); 42 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes_2.bin"); 43 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin"); 44 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes.bin"); 45 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes_2.bin"); 46 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes1.bin"); 47 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes.bin"); 48 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes_2.bin"); 49 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes1.bin"); 50 51 static int mes_v11_0_hw_fini(void *handle); 52 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev); 53 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev); 54 55 #define MES_EOP_SIZE 2048 56 57 static void mes_v11_0_ring_set_wptr(struct amdgpu_ring *ring) 58 { 59 struct amdgpu_device *adev = ring->adev; 60 61 if (ring->use_doorbell) { 62 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 63 ring->wptr); 64 WDOORBELL64(ring->doorbell_index, ring->wptr); 65 } else { 66 BUG(); 67 } 68 } 69 70 static u64 mes_v11_0_ring_get_rptr(struct amdgpu_ring *ring) 71 { 72 return *ring->rptr_cpu_addr; 73 } 74 75 static u64 mes_v11_0_ring_get_wptr(struct amdgpu_ring *ring) 76 { 77 u64 wptr; 78 79 if (ring->use_doorbell) 80 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 81 else 82 BUG(); 83 return wptr; 84 } 85 86 static const struct amdgpu_ring_funcs mes_v11_0_ring_funcs = { 87 .type = AMDGPU_RING_TYPE_MES, 88 .align_mask = 1, 89 .nop = 0, 90 .support_64bit_ptrs = true, 91 .get_rptr = mes_v11_0_ring_get_rptr, 92 .get_wptr = mes_v11_0_ring_get_wptr, 93 .set_wptr = mes_v11_0_ring_set_wptr, 94 .insert_nop = amdgpu_ring_insert_nop, 95 }; 96 97 static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, 98 void *pkt, int size, 99 int api_status_off) 100 { 101 int ndw = size / 4; 102 signed long r; 103 union MESAPI__ADD_QUEUE *x_pkt = pkt; 104 struct MES_API_STATUS *api_status; 105 struct amdgpu_device *adev = mes->adev; 106 struct amdgpu_ring *ring = &mes->ring; 107 unsigned long flags; 108 signed long timeout = adev->usec_timeout; 109 110 if (amdgpu_emu_mode) { 111 timeout *= 100; 112 } else if (amdgpu_sriov_vf(adev)) { 113 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */ 114 timeout = 15 * 600 * 1000; 115 } 116 BUG_ON(size % 4 != 0); 117 118 spin_lock_irqsave(&mes->ring_lock, flags); 119 if (amdgpu_ring_alloc(ring, ndw)) { 120 spin_unlock_irqrestore(&mes->ring_lock, flags); 121 return -ENOMEM; 122 } 123 124 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off); 125 api_status->api_completion_fence_addr = mes->ring.fence_drv.gpu_addr; 126 api_status->api_completion_fence_value = ++mes->ring.fence_drv.sync_seq; 127 128 amdgpu_ring_write_multiple(ring, pkt, ndw); 129 amdgpu_ring_commit(ring); 130 spin_unlock_irqrestore(&mes->ring_lock, flags); 131 132 DRM_DEBUG("MES msg=%d was emitted\n", x_pkt->header.opcode); 133 134 r = amdgpu_fence_wait_polling(ring, ring->fence_drv.sync_seq, 135 timeout); 136 if (r < 1) { 137 DRM_ERROR("MES failed to response msg=%d\n", 138 x_pkt->header.opcode); 139 140 while (halt_if_hws_hang) 141 schedule(); 142 143 return -ETIMEDOUT; 144 } 145 146 return 0; 147 } 148 149 static int convert_to_mes_queue_type(int queue_type) 150 { 151 if (queue_type == AMDGPU_RING_TYPE_GFX) 152 return MES_QUEUE_TYPE_GFX; 153 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 154 return MES_QUEUE_TYPE_COMPUTE; 155 else if (queue_type == AMDGPU_RING_TYPE_SDMA) 156 return MES_QUEUE_TYPE_SDMA; 157 else 158 BUG(); 159 return -1; 160 } 161 162 static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes, 163 struct mes_add_queue_input *input) 164 { 165 struct amdgpu_device *adev = mes->adev; 166 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 167 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; 168 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl; 169 170 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 171 172 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 173 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 174 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 175 176 mes_add_queue_pkt.process_id = input->process_id; 177 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr; 178 mes_add_queue_pkt.process_va_start = input->process_va_start; 179 mes_add_queue_pkt.process_va_end = input->process_va_end; 180 mes_add_queue_pkt.process_quantum = input->process_quantum; 181 mes_add_queue_pkt.process_context_addr = input->process_context_addr; 182 mes_add_queue_pkt.gang_quantum = input->gang_quantum; 183 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr; 184 mes_add_queue_pkt.inprocess_gang_priority = 185 input->inprocess_gang_priority; 186 mes_add_queue_pkt.gang_global_priority_level = 187 input->gang_global_priority_level; 188 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 189 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 190 191 if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >> 192 AMDGPU_MES_API_VERSION_SHIFT) >= 2) 193 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; 194 else 195 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 196 197 mes_add_queue_pkt.queue_type = 198 convert_to_mes_queue_type(input->queue_type); 199 mes_add_queue_pkt.paging = input->paging; 200 mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl; 201 mes_add_queue_pkt.gws_base = input->gws_base; 202 mes_add_queue_pkt.gws_size = input->gws_size; 203 mes_add_queue_pkt.trap_handler_addr = input->tba_addr; 204 mes_add_queue_pkt.tma_addr = input->tma_addr; 205 mes_add_queue_pkt.trap_en = input->trap_en; 206 mes_add_queue_pkt.skip_process_ctx_clear = input->skip_process_ctx_clear; 207 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process; 208 209 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 210 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 211 mes_add_queue_pkt.gds_size = input->queue_size; 212 213 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 214 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 215 mes_add_queue_pkt.gds_size = input->queue_size; 216 217 return mes_v11_0_submit_pkt_and_poll_completion(mes, 218 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 219 offsetof(union MESAPI__ADD_QUEUE, api_status)); 220 } 221 222 static int mes_v11_0_remove_hw_queue(struct amdgpu_mes *mes, 223 struct mes_remove_queue_input *input) 224 { 225 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 226 227 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 228 229 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 230 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 231 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 232 233 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 234 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; 235 236 return mes_v11_0_submit_pkt_and_poll_completion(mes, 237 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 238 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 239 } 240 241 static int mes_v11_0_unmap_legacy_queue(struct amdgpu_mes *mes, 242 struct mes_unmap_legacy_queue_input *input) 243 { 244 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 245 246 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 247 248 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 249 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 250 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 251 252 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 253 mes_remove_queue_pkt.gang_context_addr = 0; 254 255 mes_remove_queue_pkt.pipe_id = input->pipe_id; 256 mes_remove_queue_pkt.queue_id = input->queue_id; 257 258 if (input->action == PREEMPT_QUEUES_NO_UNMAP) { 259 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1; 260 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr; 261 mes_remove_queue_pkt.tf_data = 262 lower_32_bits(input->trail_fence_data); 263 } else { 264 mes_remove_queue_pkt.unmap_legacy_queue = 1; 265 mes_remove_queue_pkt.queue_type = 266 convert_to_mes_queue_type(input->queue_type); 267 } 268 269 return mes_v11_0_submit_pkt_and_poll_completion(mes, 270 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 271 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 272 } 273 274 static int mes_v11_0_suspend_gang(struct amdgpu_mes *mes, 275 struct mes_suspend_gang_input *input) 276 { 277 return 0; 278 } 279 280 static int mes_v11_0_resume_gang(struct amdgpu_mes *mes, 281 struct mes_resume_gang_input *input) 282 { 283 return 0; 284 } 285 286 static int mes_v11_0_query_sched_status(struct amdgpu_mes *mes) 287 { 288 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 289 290 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 291 292 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 293 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 294 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 295 296 return mes_v11_0_submit_pkt_and_poll_completion(mes, 297 &mes_status_pkt, sizeof(mes_status_pkt), 298 offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); 299 } 300 301 static int mes_v11_0_misc_op(struct amdgpu_mes *mes, 302 struct mes_misc_op_input *input) 303 { 304 union MESAPI__MISC misc_pkt; 305 306 memset(&misc_pkt, 0, sizeof(misc_pkt)); 307 308 misc_pkt.header.type = MES_API_TYPE_SCHEDULER; 309 misc_pkt.header.opcode = MES_SCH_API_MISC; 310 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 311 312 switch (input->op) { 313 case MES_MISC_OP_READ_REG: 314 misc_pkt.opcode = MESAPI_MISC__READ_REG; 315 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset; 316 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr; 317 break; 318 case MES_MISC_OP_WRITE_REG: 319 misc_pkt.opcode = MESAPI_MISC__WRITE_REG; 320 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset; 321 misc_pkt.write_reg.reg_value = input->write_reg.reg_value; 322 break; 323 case MES_MISC_OP_WRM_REG_WAIT: 324 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 325 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; 326 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 327 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 328 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 329 misc_pkt.wait_reg_mem.reg_offset2 = 0; 330 break; 331 case MES_MISC_OP_WRM_REG_WR_WAIT: 332 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 333 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; 334 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 335 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 336 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 337 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; 338 break; 339 case MES_MISC_OP_SET_SHADER_DEBUGGER: 340 misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER; 341 misc_pkt.set_shader_debugger.process_context_addr = 342 input->set_shader_debugger.process_context_addr; 343 misc_pkt.set_shader_debugger.flags.u32all = 344 input->set_shader_debugger.flags.u32all; 345 misc_pkt.set_shader_debugger.spi_gdbg_per_vmid_cntl = 346 input->set_shader_debugger.spi_gdbg_per_vmid_cntl; 347 memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl, 348 input->set_shader_debugger.tcp_watch_cntl, 349 sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl)); 350 misc_pkt.set_shader_debugger.trap_en = input->set_shader_debugger.trap_en; 351 break; 352 default: 353 DRM_ERROR("unsupported misc op (%d) \n", input->op); 354 return -EINVAL; 355 } 356 357 return mes_v11_0_submit_pkt_and_poll_completion(mes, 358 &misc_pkt, sizeof(misc_pkt), 359 offsetof(union MESAPI__MISC, api_status)); 360 } 361 362 static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes) 363 { 364 int i; 365 struct amdgpu_device *adev = mes->adev; 366 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; 367 368 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 369 370 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 371 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC; 372 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 373 374 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; 375 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; 376 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size; 377 mes_set_hw_res_pkt.paging_vmid = 0; 378 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr; 379 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr = 380 mes->query_status_fence_gpu_addr; 381 382 for (i = 0; i < MAX_COMPUTE_PIPES; i++) 383 mes_set_hw_res_pkt.compute_hqd_mask[i] = 384 mes->compute_hqd_mask[i]; 385 386 for (i = 0; i < MAX_GFX_PIPES; i++) 387 mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i]; 388 389 for (i = 0; i < MAX_SDMA_PIPES; i++) 390 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i]; 391 392 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++) 393 mes_set_hw_res_pkt.aggregated_doorbells[i] = 394 mes->aggregated_doorbells[i]; 395 396 for (i = 0; i < 5; i++) { 397 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; 398 mes_set_hw_res_pkt.mmhub_base[i] = 399 adev->reg_offset[MMHUB_HWIP][0][i]; 400 mes_set_hw_res_pkt.osssys_base[i] = 401 adev->reg_offset[OSSSYS_HWIP][0][i]; 402 } 403 404 mes_set_hw_res_pkt.disable_reset = 1; 405 mes_set_hw_res_pkt.disable_mes_log = 1; 406 mes_set_hw_res_pkt.use_different_vmid_compute = 1; 407 mes_set_hw_res_pkt.enable_reg_active_poll = 1; 408 mes_set_hw_res_pkt.oversubscription_timer = 50; 409 410 return mes_v11_0_submit_pkt_and_poll_completion(mes, 411 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 412 offsetof(union MESAPI_SET_HW_RESOURCES, api_status)); 413 } 414 415 static void mes_v11_0_init_aggregated_doorbell(struct amdgpu_mes *mes) 416 { 417 struct amdgpu_device *adev = mes->adev; 418 uint32_t data; 419 420 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1); 421 data &= ~(CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET_MASK | 422 CP_MES_DOORBELL_CONTROL1__DOORBELL_EN_MASK | 423 CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT_MASK); 424 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_LOW] << 425 CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET__SHIFT; 426 data |= 1 << CP_MES_DOORBELL_CONTROL1__DOORBELL_EN__SHIFT; 427 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1, data); 428 429 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2); 430 data &= ~(CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET_MASK | 431 CP_MES_DOORBELL_CONTROL2__DOORBELL_EN_MASK | 432 CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT_MASK); 433 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_NORMAL] << 434 CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET__SHIFT; 435 data |= 1 << CP_MES_DOORBELL_CONTROL2__DOORBELL_EN__SHIFT; 436 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2, data); 437 438 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3); 439 data &= ~(CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET_MASK | 440 CP_MES_DOORBELL_CONTROL3__DOORBELL_EN_MASK | 441 CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT_MASK); 442 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_MEDIUM] << 443 CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET__SHIFT; 444 data |= 1 << CP_MES_DOORBELL_CONTROL3__DOORBELL_EN__SHIFT; 445 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3, data); 446 447 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4); 448 data &= ~(CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET_MASK | 449 CP_MES_DOORBELL_CONTROL4__DOORBELL_EN_MASK | 450 CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT_MASK); 451 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_HIGH] << 452 CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET__SHIFT; 453 data |= 1 << CP_MES_DOORBELL_CONTROL4__DOORBELL_EN__SHIFT; 454 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4, data); 455 456 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5); 457 data &= ~(CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET_MASK | 458 CP_MES_DOORBELL_CONTROL5__DOORBELL_EN_MASK | 459 CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT_MASK); 460 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_REALTIME] << 461 CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET__SHIFT; 462 data |= 1 << CP_MES_DOORBELL_CONTROL5__DOORBELL_EN__SHIFT; 463 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5, data); 464 465 data = 1 << CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT; 466 WREG32_SOC15(GC, 0, regCP_HQD_GFX_CONTROL, data); 467 } 468 469 static const struct amdgpu_mes_funcs mes_v11_0_funcs = { 470 .add_hw_queue = mes_v11_0_add_hw_queue, 471 .remove_hw_queue = mes_v11_0_remove_hw_queue, 472 .unmap_legacy_queue = mes_v11_0_unmap_legacy_queue, 473 .suspend_gang = mes_v11_0_suspend_gang, 474 .resume_gang = mes_v11_0_resume_gang, 475 .misc_op = mes_v11_0_misc_op, 476 }; 477 478 static int mes_v11_0_allocate_ucode_buffer(struct amdgpu_device *adev, 479 enum admgpu_mes_pipe pipe) 480 { 481 int r; 482 const struct mes_firmware_header_v1_0 *mes_hdr; 483 const __le32 *fw_data; 484 unsigned fw_size; 485 486 mes_hdr = (const struct mes_firmware_header_v1_0 *) 487 adev->mes.fw[pipe]->data; 488 489 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 490 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 491 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 492 493 r = amdgpu_bo_create_reserved(adev, fw_size, 494 PAGE_SIZE, 495 AMDGPU_GEM_DOMAIN_VRAM | 496 AMDGPU_GEM_DOMAIN_GTT, 497 &adev->mes.ucode_fw_obj[pipe], 498 &adev->mes.ucode_fw_gpu_addr[pipe], 499 (void **)&adev->mes.ucode_fw_ptr[pipe]); 500 if (r) { 501 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r); 502 return r; 503 } 504 505 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size); 506 507 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]); 508 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]); 509 510 return 0; 511 } 512 513 static int mes_v11_0_allocate_ucode_data_buffer(struct amdgpu_device *adev, 514 enum admgpu_mes_pipe pipe) 515 { 516 int r; 517 const struct mes_firmware_header_v1_0 *mes_hdr; 518 const __le32 *fw_data; 519 unsigned fw_size; 520 521 mes_hdr = (const struct mes_firmware_header_v1_0 *) 522 adev->mes.fw[pipe]->data; 523 524 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 525 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 526 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 527 528 r = amdgpu_bo_create_reserved(adev, fw_size, 529 64 * 1024, 530 AMDGPU_GEM_DOMAIN_VRAM | 531 AMDGPU_GEM_DOMAIN_GTT, 532 &adev->mes.data_fw_obj[pipe], 533 &adev->mes.data_fw_gpu_addr[pipe], 534 (void **)&adev->mes.data_fw_ptr[pipe]); 535 if (r) { 536 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r); 537 return r; 538 } 539 540 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size); 541 542 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]); 543 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]); 544 545 return 0; 546 } 547 548 static void mes_v11_0_free_ucode_buffers(struct amdgpu_device *adev, 549 enum admgpu_mes_pipe pipe) 550 { 551 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe], 552 &adev->mes.data_fw_gpu_addr[pipe], 553 (void **)&adev->mes.data_fw_ptr[pipe]); 554 555 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe], 556 &adev->mes.ucode_fw_gpu_addr[pipe], 557 (void **)&adev->mes.ucode_fw_ptr[pipe]); 558 } 559 560 static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable) 561 { 562 uint64_t ucode_addr; 563 uint32_t pipe, data = 0; 564 565 if (enable) { 566 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 567 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 568 data = REG_SET_FIELD(data, CP_MES_CNTL, 569 MES_PIPE1_RESET, adev->enable_mes_kiq ? 1 : 0); 570 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 571 572 mutex_lock(&adev->srbm_mutex); 573 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 574 if (!adev->enable_mes_kiq && 575 pipe == AMDGPU_MES_KIQ_PIPE) 576 continue; 577 578 soc21_grbm_select(adev, 3, pipe, 0, 0); 579 580 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 581 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 582 lower_32_bits(ucode_addr)); 583 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 584 upper_32_bits(ucode_addr)); 585 } 586 soc21_grbm_select(adev, 0, 0, 0, 0); 587 mutex_unlock(&adev->srbm_mutex); 588 589 /* unhalt MES and activate pipe0 */ 590 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1); 591 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 592 adev->enable_mes_kiq ? 1 : 0); 593 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 594 595 if (amdgpu_emu_mode) 596 msleep(100); 597 else 598 udelay(50); 599 } else { 600 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 601 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0); 602 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0); 603 data = REG_SET_FIELD(data, CP_MES_CNTL, 604 MES_INVALIDATE_ICACHE, 1); 605 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 606 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 607 adev->enable_mes_kiq ? 1 : 0); 608 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1); 609 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 610 } 611 } 612 613 /* This function is for backdoor MES firmware */ 614 static int mes_v11_0_load_microcode(struct amdgpu_device *adev, 615 enum admgpu_mes_pipe pipe, bool prime_icache) 616 { 617 int r; 618 uint32_t data; 619 uint64_t ucode_addr; 620 621 mes_v11_0_enable(adev, false); 622 623 if (!adev->mes.fw[pipe]) 624 return -EINVAL; 625 626 r = mes_v11_0_allocate_ucode_buffer(adev, pipe); 627 if (r) 628 return r; 629 630 r = mes_v11_0_allocate_ucode_data_buffer(adev, pipe); 631 if (r) { 632 mes_v11_0_free_ucode_buffers(adev, pipe); 633 return r; 634 } 635 636 mutex_lock(&adev->srbm_mutex); 637 /* me=3, pipe=0, queue=0 */ 638 soc21_grbm_select(adev, 3, pipe, 0, 0); 639 640 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0); 641 642 /* set ucode start address */ 643 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 644 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 645 lower_32_bits(ucode_addr)); 646 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 647 upper_32_bits(ucode_addr)); 648 649 /* set ucode fimrware address */ 650 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO, 651 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 652 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI, 653 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 654 655 /* set ucode instruction cache boundary to 2M-1 */ 656 WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF); 657 658 /* set ucode data firmware address */ 659 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO, 660 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 661 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI, 662 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 663 664 /* Set 0x3FFFF (256K-1) to CP_MES_MDBOUND_LO */ 665 WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x3FFFF); 666 667 if (prime_icache) { 668 /* invalidate ICACHE */ 669 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 670 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); 671 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); 672 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 673 674 /* prime the ICACHE. */ 675 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 676 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); 677 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 678 } 679 680 soc21_grbm_select(adev, 0, 0, 0, 0); 681 mutex_unlock(&adev->srbm_mutex); 682 683 return 0; 684 } 685 686 static int mes_v11_0_allocate_eop_buf(struct amdgpu_device *adev, 687 enum admgpu_mes_pipe pipe) 688 { 689 int r; 690 u32 *eop; 691 692 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE, 693 AMDGPU_GEM_DOMAIN_GTT, 694 &adev->mes.eop_gpu_obj[pipe], 695 &adev->mes.eop_gpu_addr[pipe], 696 (void **)&eop); 697 if (r) { 698 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r); 699 return r; 700 } 701 702 memset(eop, 0, 703 adev->mes.eop_gpu_obj[pipe]->tbo.base.size); 704 705 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]); 706 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]); 707 708 return 0; 709 } 710 711 static int mes_v11_0_mqd_init(struct amdgpu_ring *ring) 712 { 713 struct v11_compute_mqd *mqd = ring->mqd_ptr; 714 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 715 uint32_t tmp; 716 717 memset(mqd, 0, sizeof(*mqd)); 718 719 mqd->header = 0xC0310800; 720 mqd->compute_pipelinestat_enable = 0x00000001; 721 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 722 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 723 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 724 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 725 mqd->compute_misc_reserved = 0x00000007; 726 727 eop_base_addr = ring->eop_gpu_addr >> 8; 728 729 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 730 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 731 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 732 (order_base_2(MES_EOP_SIZE / 4) - 1)); 733 734 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); 735 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 736 mqd->cp_hqd_eop_control = tmp; 737 738 /* disable the queue if it's active */ 739 ring->wptr = 0; 740 mqd->cp_hqd_pq_rptr = 0; 741 mqd->cp_hqd_pq_wptr_lo = 0; 742 mqd->cp_hqd_pq_wptr_hi = 0; 743 744 /* set the pointer to the MQD */ 745 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 746 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 747 748 /* set MQD vmid to 0 */ 749 tmp = regCP_MQD_CONTROL_DEFAULT; 750 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 751 mqd->cp_mqd_control = tmp; 752 753 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 754 hqd_gpu_addr = ring->gpu_addr >> 8; 755 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); 756 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 757 758 /* set the wb address whether it's enabled or not */ 759 wb_gpu_addr = ring->rptr_gpu_addr; 760 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 761 mqd->cp_hqd_pq_rptr_report_addr_hi = 762 upper_32_bits(wb_gpu_addr) & 0xffff; 763 764 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 765 wb_gpu_addr = ring->wptr_gpu_addr; 766 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; 767 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 768 769 /* set up the HQD, this is similar to CP_RB0_CNTL */ 770 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 771 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 772 (order_base_2(ring->ring_size / 4) - 1)); 773 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 774 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 775 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 776 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 777 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 778 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 779 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); 780 mqd->cp_hqd_pq_control = tmp; 781 782 /* enable doorbell */ 783 tmp = 0; 784 if (ring->use_doorbell) { 785 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 786 DOORBELL_OFFSET, ring->doorbell_index); 787 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 788 DOORBELL_EN, 1); 789 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 790 DOORBELL_SOURCE, 0); 791 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 792 DOORBELL_HIT, 0); 793 } 794 else 795 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 796 DOORBELL_EN, 0); 797 mqd->cp_hqd_pq_doorbell_control = tmp; 798 799 mqd->cp_hqd_vmid = 0; 800 /* activate the queue */ 801 mqd->cp_hqd_active = 1; 802 803 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 804 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, 805 PRELOAD_SIZE, 0x55); 806 mqd->cp_hqd_persistent_state = tmp; 807 808 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT; 809 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT; 810 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT; 811 812 amdgpu_device_flush_hdp(ring->adev, NULL); 813 return 0; 814 } 815 816 static void mes_v11_0_queue_init_register(struct amdgpu_ring *ring) 817 { 818 struct v11_compute_mqd *mqd = ring->mqd_ptr; 819 struct amdgpu_device *adev = ring->adev; 820 uint32_t data = 0; 821 822 mutex_lock(&adev->srbm_mutex); 823 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 824 825 /* set CP_HQD_VMID.VMID = 0. */ 826 data = RREG32_SOC15(GC, 0, regCP_HQD_VMID); 827 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); 828 WREG32_SOC15(GC, 0, regCP_HQD_VMID, data); 829 830 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */ 831 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 832 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 833 DOORBELL_EN, 0); 834 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 835 836 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */ 837 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 838 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 839 840 /* set CP_MQD_CONTROL.VMID=0 */ 841 data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 842 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); 843 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0); 844 845 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */ 846 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 847 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 848 849 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */ 850 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 851 mqd->cp_hqd_pq_rptr_report_addr_lo); 852 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 853 mqd->cp_hqd_pq_rptr_report_addr_hi); 854 855 /* set CP_HQD_PQ_CONTROL */ 856 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); 857 858 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */ 859 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 860 mqd->cp_hqd_pq_wptr_poll_addr_lo); 861 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 862 mqd->cp_hqd_pq_wptr_poll_addr_hi); 863 864 /* set CP_HQD_PQ_DOORBELL_CONTROL */ 865 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 866 mqd->cp_hqd_pq_doorbell_control); 867 868 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */ 869 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); 870 871 /* set CP_HQD_ACTIVE.ACTIVE=1 */ 872 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); 873 874 soc21_grbm_select(adev, 0, 0, 0, 0); 875 mutex_unlock(&adev->srbm_mutex); 876 } 877 878 static int mes_v11_0_kiq_enable_queue(struct amdgpu_device *adev) 879 { 880 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 881 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; 882 int r; 883 884 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 885 return -EINVAL; 886 887 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 888 if (r) { 889 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 890 return r; 891 } 892 893 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring); 894 895 return amdgpu_ring_test_helper(kiq_ring); 896 } 897 898 static int mes_v11_0_queue_init(struct amdgpu_device *adev, 899 enum admgpu_mes_pipe pipe) 900 { 901 struct amdgpu_ring *ring; 902 int r; 903 904 if (pipe == AMDGPU_MES_KIQ_PIPE) 905 ring = &adev->gfx.kiq[0].ring; 906 else if (pipe == AMDGPU_MES_SCHED_PIPE) 907 ring = &adev->mes.ring; 908 else 909 BUG(); 910 911 if ((pipe == AMDGPU_MES_SCHED_PIPE) && 912 (amdgpu_in_reset(adev) || adev->in_suspend)) { 913 *(ring->wptr_cpu_addr) = 0; 914 *(ring->rptr_cpu_addr) = 0; 915 amdgpu_ring_clear_ring(ring); 916 } 917 918 r = mes_v11_0_mqd_init(ring); 919 if (r) 920 return r; 921 922 if (pipe == AMDGPU_MES_SCHED_PIPE) { 923 r = mes_v11_0_kiq_enable_queue(adev); 924 if (r) 925 return r; 926 } else { 927 mes_v11_0_queue_init_register(ring); 928 } 929 930 /* get MES scheduler/KIQ versions */ 931 mutex_lock(&adev->srbm_mutex); 932 soc21_grbm_select(adev, 3, pipe, 0, 0); 933 934 if (pipe == AMDGPU_MES_SCHED_PIPE) 935 adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 936 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) 937 adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 938 939 soc21_grbm_select(adev, 0, 0, 0, 0); 940 mutex_unlock(&adev->srbm_mutex); 941 942 return 0; 943 } 944 945 static int mes_v11_0_ring_init(struct amdgpu_device *adev) 946 { 947 struct amdgpu_ring *ring; 948 949 ring = &adev->mes.ring; 950 951 ring->funcs = &mes_v11_0_ring_funcs; 952 953 ring->me = 3; 954 ring->pipe = 0; 955 ring->queue = 0; 956 957 ring->ring_obj = NULL; 958 ring->use_doorbell = true; 959 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1; 960 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE]; 961 ring->no_scheduler = true; 962 sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue); 963 964 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 965 AMDGPU_RING_PRIO_DEFAULT, NULL); 966 } 967 968 static int mes_v11_0_kiq_ring_init(struct amdgpu_device *adev) 969 { 970 struct amdgpu_ring *ring; 971 972 spin_lock_init(&adev->gfx.kiq[0].ring_lock); 973 974 ring = &adev->gfx.kiq[0].ring; 975 976 ring->me = 3; 977 ring->pipe = 1; 978 ring->queue = 0; 979 980 ring->adev = NULL; 981 ring->ring_obj = NULL; 982 ring->use_doorbell = true; 983 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1; 984 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE]; 985 ring->no_scheduler = true; 986 sprintf(ring->name, "mes_kiq_%d.%d.%d", 987 ring->me, ring->pipe, ring->queue); 988 989 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 990 AMDGPU_RING_PRIO_DEFAULT, NULL); 991 } 992 993 static int mes_v11_0_mqd_sw_init(struct amdgpu_device *adev, 994 enum admgpu_mes_pipe pipe) 995 { 996 int r, mqd_size = sizeof(struct v11_compute_mqd); 997 struct amdgpu_ring *ring; 998 999 if (pipe == AMDGPU_MES_KIQ_PIPE) 1000 ring = &adev->gfx.kiq[0].ring; 1001 else if (pipe == AMDGPU_MES_SCHED_PIPE) 1002 ring = &adev->mes.ring; 1003 else 1004 BUG(); 1005 1006 if (ring->mqd_obj) 1007 return 0; 1008 1009 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 1010 AMDGPU_GEM_DOMAIN_VRAM | 1011 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 1012 &ring->mqd_gpu_addr, &ring->mqd_ptr); 1013 if (r) { 1014 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 1015 return r; 1016 } 1017 1018 memset(ring->mqd_ptr, 0, mqd_size); 1019 1020 /* prepare MQD backup */ 1021 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL); 1022 if (!adev->mes.mqd_backup[pipe]) 1023 dev_warn(adev->dev, 1024 "no memory to create MQD backup for ring %s\n", 1025 ring->name); 1026 1027 return 0; 1028 } 1029 1030 static int mes_v11_0_sw_init(void *handle) 1031 { 1032 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1033 int pipe, r; 1034 1035 adev->mes.funcs = &mes_v11_0_funcs; 1036 adev->mes.kiq_hw_init = &mes_v11_0_kiq_hw_init; 1037 adev->mes.kiq_hw_fini = &mes_v11_0_kiq_hw_fini; 1038 1039 r = amdgpu_mes_init(adev); 1040 if (r) 1041 return r; 1042 1043 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1044 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1045 continue; 1046 1047 r = mes_v11_0_allocate_eop_buf(adev, pipe); 1048 if (r) 1049 return r; 1050 1051 r = mes_v11_0_mqd_sw_init(adev, pipe); 1052 if (r) 1053 return r; 1054 } 1055 1056 if (adev->enable_mes_kiq) { 1057 r = mes_v11_0_kiq_ring_init(adev); 1058 if (r) 1059 return r; 1060 } 1061 1062 r = mes_v11_0_ring_init(adev); 1063 if (r) 1064 return r; 1065 1066 return 0; 1067 } 1068 1069 static int mes_v11_0_sw_fini(void *handle) 1070 { 1071 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1072 int pipe; 1073 1074 amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs); 1075 amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs); 1076 1077 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1078 kfree(adev->mes.mqd_backup[pipe]); 1079 1080 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe], 1081 &adev->mes.eop_gpu_addr[pipe], 1082 NULL); 1083 amdgpu_ucode_release(&adev->mes.fw[pipe]); 1084 } 1085 1086 amdgpu_bo_free_kernel(&adev->gfx.kiq[0].ring.mqd_obj, 1087 &adev->gfx.kiq[0].ring.mqd_gpu_addr, 1088 &adev->gfx.kiq[0].ring.mqd_ptr); 1089 1090 amdgpu_bo_free_kernel(&adev->mes.ring.mqd_obj, 1091 &adev->mes.ring.mqd_gpu_addr, 1092 &adev->mes.ring.mqd_ptr); 1093 1094 amdgpu_ring_fini(&adev->gfx.kiq[0].ring); 1095 amdgpu_ring_fini(&adev->mes.ring); 1096 1097 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1098 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE); 1099 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE); 1100 } 1101 1102 amdgpu_mes_fini(adev); 1103 return 0; 1104 } 1105 1106 static void mes_v11_0_kiq_dequeue(struct amdgpu_ring *ring) 1107 { 1108 uint32_t data; 1109 int i; 1110 struct amdgpu_device *adev = ring->adev; 1111 1112 mutex_lock(&adev->srbm_mutex); 1113 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 1114 1115 /* disable the queue if it's active */ 1116 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 1117 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 1118 for (i = 0; i < adev->usec_timeout; i++) { 1119 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 1120 break; 1121 udelay(1); 1122 } 1123 } 1124 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1125 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1126 DOORBELL_EN, 0); 1127 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1128 DOORBELL_HIT, 1); 1129 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1130 1131 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1132 1133 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0); 1134 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0); 1135 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0); 1136 1137 soc21_grbm_select(adev, 0, 0, 0, 0); 1138 mutex_unlock(&adev->srbm_mutex); 1139 } 1140 1141 static void mes_v11_0_kiq_setting(struct amdgpu_ring *ring) 1142 { 1143 uint32_t tmp; 1144 struct amdgpu_device *adev = ring->adev; 1145 1146 /* tell RLC which is KIQ queue */ 1147 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1148 tmp &= 0xffffff00; 1149 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1150 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1151 tmp |= 0x80; 1152 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1153 } 1154 1155 static void mes_v11_0_kiq_clear(struct amdgpu_device *adev) 1156 { 1157 uint32_t tmp; 1158 1159 /* tell RLC which is KIQ dequeue */ 1160 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1161 tmp &= ~RLC_CP_SCHEDULERS__scheduler0_MASK; 1162 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1163 } 1164 1165 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev) 1166 { 1167 int r = 0; 1168 1169 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1170 1171 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false); 1172 if (r) { 1173 DRM_ERROR("failed to load MES fw, r=%d\n", r); 1174 return r; 1175 } 1176 1177 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true); 1178 if (r) { 1179 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); 1180 return r; 1181 } 1182 1183 } 1184 1185 mes_v11_0_enable(adev, true); 1186 1187 mes_v11_0_kiq_setting(&adev->gfx.kiq[0].ring); 1188 1189 r = mes_v11_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE); 1190 if (r) 1191 goto failure; 1192 1193 return r; 1194 1195 failure: 1196 mes_v11_0_hw_fini(adev); 1197 return r; 1198 } 1199 1200 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev) 1201 { 1202 if (adev->mes.ring.sched.ready) { 1203 mes_v11_0_kiq_dequeue(&adev->mes.ring); 1204 adev->mes.ring.sched.ready = false; 1205 } 1206 1207 if (amdgpu_sriov_vf(adev)) { 1208 mes_v11_0_kiq_dequeue(&adev->gfx.kiq[0].ring); 1209 mes_v11_0_kiq_clear(adev); 1210 } 1211 1212 mes_v11_0_enable(adev, false); 1213 1214 return 0; 1215 } 1216 1217 static int mes_v11_0_hw_init(void *handle) 1218 { 1219 int r; 1220 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1221 1222 if (!adev->enable_mes_kiq) { 1223 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1224 r = mes_v11_0_load_microcode(adev, 1225 AMDGPU_MES_SCHED_PIPE, true); 1226 if (r) { 1227 DRM_ERROR("failed to MES fw, r=%d\n", r); 1228 return r; 1229 } 1230 } 1231 1232 mes_v11_0_enable(adev, true); 1233 } 1234 1235 r = mes_v11_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE); 1236 if (r) 1237 goto failure; 1238 1239 r = mes_v11_0_set_hw_resources(&adev->mes); 1240 if (r) 1241 goto failure; 1242 1243 mes_v11_0_init_aggregated_doorbell(&adev->mes); 1244 1245 r = mes_v11_0_query_sched_status(&adev->mes); 1246 if (r) { 1247 DRM_ERROR("MES is busy\n"); 1248 goto failure; 1249 } 1250 1251 /* 1252 * Disable KIQ ring usage from the driver once MES is enabled. 1253 * MES uses KIQ ring exclusively so driver cannot access KIQ ring 1254 * with MES enabled. 1255 */ 1256 adev->gfx.kiq[0].ring.sched.ready = false; 1257 adev->mes.ring.sched.ready = true; 1258 1259 return 0; 1260 1261 failure: 1262 mes_v11_0_hw_fini(adev); 1263 return r; 1264 } 1265 1266 static int mes_v11_0_hw_fini(void *handle) 1267 { 1268 return 0; 1269 } 1270 1271 static int mes_v11_0_suspend(void *handle) 1272 { 1273 int r; 1274 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1275 1276 r = amdgpu_mes_suspend(adev); 1277 if (r) 1278 return r; 1279 1280 return mes_v11_0_hw_fini(adev); 1281 } 1282 1283 static int mes_v11_0_resume(void *handle) 1284 { 1285 int r; 1286 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1287 1288 r = mes_v11_0_hw_init(adev); 1289 if (r) 1290 return r; 1291 1292 return amdgpu_mes_resume(adev); 1293 } 1294 1295 static int mes_v11_0_early_init(void *handle) 1296 { 1297 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1298 int pipe, r; 1299 1300 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1301 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1302 continue; 1303 r = amdgpu_mes_init_microcode(adev, pipe); 1304 if (r) 1305 return r; 1306 } 1307 1308 return 0; 1309 } 1310 1311 static int mes_v11_0_late_init(void *handle) 1312 { 1313 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1314 1315 /* it's only intended for use in mes_self_test case, not for s0ix and reset */ 1316 if (!amdgpu_in_reset(adev) && !adev->in_s0ix && !adev->in_suspend && 1317 (adev->ip_versions[GC_HWIP][0] != IP_VERSION(11, 0, 3))) 1318 amdgpu_mes_self_test(adev); 1319 1320 return 0; 1321 } 1322 1323 static const struct amd_ip_funcs mes_v11_0_ip_funcs = { 1324 .name = "mes_v11_0", 1325 .early_init = mes_v11_0_early_init, 1326 .late_init = mes_v11_0_late_init, 1327 .sw_init = mes_v11_0_sw_init, 1328 .sw_fini = mes_v11_0_sw_fini, 1329 .hw_init = mes_v11_0_hw_init, 1330 .hw_fini = mes_v11_0_hw_fini, 1331 .suspend = mes_v11_0_suspend, 1332 .resume = mes_v11_0_resume, 1333 }; 1334 1335 const struct amdgpu_ip_block_version mes_v11_0_ip_block = { 1336 .type = AMD_IP_BLOCK_TYPE_MES, 1337 .major = 11, 1338 .minor = 0, 1339 .rev = 0, 1340 .funcs = &mes_v11_0_ip_funcs, 1341 }; 1342