87ccc38e | 24-Jun-2022 |
Serge Semin <Sergey.Semin@baikalelectronics.ru> |
arm64: dts: apm: Harmonize DWC USB3 DT nodes name
In accordance with the DWC USB3 bindings the corresponding node name is suppose to comply with the Generic USB HCD DT schema, which requires the USB
arm64: dts: apm: Harmonize DWC USB3 DT nodes name
In accordance with the DWC USB3 bindings the corresponding node name is suppose to comply with the Generic USB HCD DT schema, which requires the USB nodes to have the name acceptable by the regexp: "^usb(@.*)?" . Make sure the "snps,dwc3"-compatible nodes are correctly named despite of the warning comment about possible backward compatibility issues.
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20220624141622.7149-6-Sergey.Semin@baikalelectronics.ru Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
show more ...
|
e90ac411 | 17-Sep-2020 |
Krzysztof Kozlowski <krzk@kernel.org> |
arm64: dts: apm: add required gpio-cells to DW APB GPIO controller port
The Synopsys DesignWare APB GPIO controller port must have gpio-cells property, as pointed by dtschema:
arch/arm64/boot/dts
arm64: dts: apm: add required gpio-cells to DW APB GPIO controller port
The Synopsys DesignWare APB GPIO controller port must have gpio-cells property, as pointed by dtschema:
arch/arm64/boot/dts/apm/apm-mustang.dt.yaml: gpio@1c024000: gpio-controller@0: '#gpio-cells' is a required property
Link: https://lore.kernel.org/r/20200917165040.22908-2-krzk@kernel.org Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Olof Johansson <olof@lixom.net>
show more ...
|
7c7b08bf | 02-Sep-2016 |
Duc Dang <dhdang@apm.com> |
arm64: dts: apm: Fix interrupt polarity for X-Gene PCIe legacy interrupts
On X-Gene v1 and X-Gene v2, PCIe legacy interrupt should be configured as level-active high.
Signed-off-by: Duc Dang <dhdan
arm64: dts: apm: Fix interrupt polarity for X-Gene PCIe legacy interrupts
On X-Gene v1 and X-Gene v2, PCIe legacy interrupt should be configured as level-active high.
Signed-off-by: Duc Dang <dhdang@apm.com>
show more ...
|