e743f1e5 | 30-Nov-2017 |
Christopher Spinrath <christopher.spinrath@rwth-aachen.de> |
ARM: imx: cm_fx6: remove esdhc init code from board file
Commit 5248930ebf48 ("dm: imx: cm_fx6: Enable more driver model support") enabled driver model support for MMC. Remove the old mmc init code,
ARM: imx: cm_fx6: remove esdhc init code from board file
Commit 5248930ebf48 ("dm: imx: cm_fx6: Enable more driver model support") enabled driver model support for MMC. Remove the old mmc init code, which is no longer used, from the board file.
Signed-off-by: Christopher Spinrath <christopher.spinrath@rwth-aachen.de> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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4f6478d6 | 29-Jul-2017 |
Simon Glass <sjg@chromium.org> |
dm: imx: cm_fx6: Add MMC support for CONFIG_BLK
When CONFIG_BLK is enabled our weak board_mmc_init() will not be called. Since there is no clock driver for MX6 yet, we must manually enable the clock
dm: imx: cm_fx6: Add MMC support for CONFIG_BLK
When CONFIG_BLK is enabled our weak board_mmc_init() will not be called. Since there is no clock driver for MX6 yet, we must manually enable the clocks.
Signed-off-by: Simon Glass <sjg@chromium.org>
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edf00937 | 29-Aug-2016 |
Fabio Estevam <fabio.estevam@nxp.com> |
mx6: ddr: Allow changing REFSEL and REFR fields
Currently MX6 SPL DDR initialization hardcodes the REF_SEL and REFR fields of the MDREF register as 1 and 7, respectively for DDR3 and 0 and 3 for LPD
mx6: ddr: Allow changing REFSEL and REFR fields
Currently MX6 SPL DDR initialization hardcodes the REF_SEL and REFR fields of the MDREF register as 1 and 7, respectively for DDR3 and 0 and 3 for LPDDR2.
Looking at the MDREF initialization done via DCD we see that boards do need to initialize these fields differently:
$ git grep 0x021b0020 board/ board/bachmann/ot1200/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800 board/ccv/xpress/imximage.cfg:DATA 4 0x021b0020 0x00000800 /* MMDC0_MDREF */ board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x7800 board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qsabreauto/mx6dl.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qsabreauto/mx6qp.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6sabresd/mx6dlsabresd.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6slevk/imximage.cfg:DATA 4 0x021b0020 0x00001800 board/freescale/mx6sxsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00000800 board/freescale/mx6sxsabresd/imximage.cfg:DATA 4 0x021b0020 0x00000800 board/warp/imximage.cfg:DATA 4 0x021b0020 0x00001800
So introduce a mechanism for users to be able to configure REFSEL and REFR fields as needed.
Keep all the mx6 SPL users in their current REF_SEL and REFR values, so no functional changes for the existing users.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Eric Nelson <eric@nelint.com>
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ec26c1ee | 29-Oct-2015 |
Nikita Kiryanov <nikita@compulab.co.il> |
arm: mx6: cm-fx6: add splash locations to cm-fx6
Add the following splash locations to cm-fx6: * filesystem formatted mmc * filesystem formatted usb * filesystem formatted sata
Cc: Igor Grinberg <g
arm: mx6: cm-fx6: add splash locations to cm-fx6
Add the following splash locations to cm-fx6: * filesystem formatted mmc * filesystem formatted usb * filesystem formatted sata
Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Tom Rini <trini@konsulko.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
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