1 /* 2 * (C) Copyright 2015 Google, Inc 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <common.h> 8 #include <clk-uclass.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <syscon.h> 12 #include <asm/io.h> 13 #include <asm/arch/clock.h> 14 #include <asm/arch/cru_rk3036.h> 15 #include <asm/arch/hardware.h> 16 #include <dm/lists.h> 17 #include <dt-bindings/clock/rk3036-cru.h> 18 #include <linux/log2.h> 19 20 enum { 21 VCO_MAX_HZ = 2400U * 1000000, 22 VCO_MIN_HZ = 600 * 1000000, 23 OUTPUT_MAX_HZ = 2400U * 1000000, 24 OUTPUT_MIN_HZ = 24 * 1000000, 25 }; 26 27 #define RATE_TO_DIV(input_rate, output_rate) \ 28 ((input_rate) / (output_rate) - 1); 29 30 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) 31 32 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ 33 .refdiv = _refdiv,\ 34 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\ 35 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\ 36 _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\ 37 OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\ 38 #hz "Hz cannot be hit with PLL "\ 39 "divisors on line " __stringify(__LINE__)); 40 41 /* use integer mode*/ 42 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1); 43 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); 44 45 static int rkclk_set_pll(struct rk3036_cru *cru, enum rk_clk_id clk_id, 46 const struct pll_div *div) 47 { 48 int pll_id = rk_pll_id(clk_id); 49 struct rk3036_pll *pll = &cru->pll[pll_id]; 50 51 /* All PLLs have same VCO and output frequency range restrictions. */ 52 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; 53 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; 54 55 debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, postdiv2=%d,\ 56 vco=%u Hz, output=%u Hz\n", 57 pll, div->fbdiv, div->refdiv, div->postdiv1, 58 div->postdiv2, vco_hz, output_hz); 59 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && 60 output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ); 61 62 /* use integer mode */ 63 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); 64 65 rk_clrsetreg(&pll->con0, 66 PLL_POSTDIV1_MASK | PLL_FBDIV_MASK, 67 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv); 68 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, 69 (div->postdiv2 << PLL_POSTDIV2_SHIFT | 70 div->refdiv << PLL_REFDIV_SHIFT)); 71 72 /* waiting for pll lock */ 73 while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT)) 74 udelay(1); 75 76 return 0; 77 } 78 79 static void rkclk_init(struct rk3036_cru *cru) 80 { 81 u32 aclk_div; 82 u32 hclk_div; 83 u32 pclk_div; 84 85 /* pll enter slow-mode */ 86 rk_clrsetreg(&cru->cru_mode_con, 87 GPLL_MODE_MASK | APLL_MODE_MASK, 88 GPLL_MODE_SLOW << GPLL_MODE_SHIFT | 89 APLL_MODE_SLOW << APLL_MODE_SHIFT); 90 91 /* init pll */ 92 rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg); 93 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg); 94 95 /* 96 * select apll as cpu/core clock pll source and 97 * set up dependent divisors for PERI and ACLK clocks. 98 * core hz : apll = 1:1 99 */ 100 aclk_div = APLL_HZ / CORE_ACLK_HZ - 1; 101 assert((aclk_div + 1) * CORE_ACLK_HZ == APLL_HZ && aclk_div < 0x7); 102 103 pclk_div = APLL_HZ / CORE_PERI_HZ - 1; 104 assert((pclk_div + 1) * CORE_PERI_HZ == APLL_HZ && pclk_div < 0xf); 105 106 rk_clrsetreg(&cru->cru_clksel_con[0], 107 CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK, 108 CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT | 109 0 << CORE_DIV_CON_SHIFT); 110 111 rk_clrsetreg(&cru->cru_clksel_con[1], 112 CORE_ACLK_DIV_MASK | CORE_PERI_DIV_MASK, 113 aclk_div << CORE_ACLK_DIV_SHIFT | 114 pclk_div << CORE_PERI_DIV_SHIFT); 115 116 /* 117 * select apll as pd_bus bus clock source and 118 * set up dependent divisors for PCLK/HCLK and ACLK clocks. 119 */ 120 aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1; 121 assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); 122 123 pclk_div = GPLL_HZ / BUS_PCLK_HZ - 1; 124 assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7); 125 126 hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; 127 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); 128 129 rk_clrsetreg(&cru->cru_clksel_con[0], 130 BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK, 131 BUS_ACLK_PLL_SEL_GPLL << BUS_ACLK_PLL_SEL_SHIFT | 132 aclk_div << BUS_ACLK_DIV_SHIFT); 133 134 rk_clrsetreg(&cru->cru_clksel_con[1], 135 BUS_PCLK_DIV_MASK | BUS_HCLK_DIV_MASK, 136 pclk_div << BUS_PCLK_DIV_SHIFT | 137 hclk_div << BUS_HCLK_DIV_SHIFT); 138 139 /* 140 * select gpll as pd_peri bus clock source and 141 * set up dependent divisors for PCLK/HCLK and ACLK clocks. 142 */ 143 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; 144 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); 145 146 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); 147 assert((1 << hclk_div) * PERI_HCLK_HZ == 148 PERI_ACLK_HZ && (hclk_div < 0x4)); 149 150 pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ); 151 assert((1 << pclk_div) * PERI_PCLK_HZ == 152 PERI_ACLK_HZ && pclk_div < 0x8); 153 154 rk_clrsetreg(&cru->cru_clksel_con[10], 155 PERI_PLL_SEL_MASK | PERI_PCLK_DIV_MASK | 156 PERI_HCLK_DIV_MASK | PERI_ACLK_DIV_MASK, 157 PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT | 158 pclk_div << PERI_PCLK_DIV_SHIFT | 159 hclk_div << PERI_HCLK_DIV_SHIFT | 160 aclk_div << PERI_ACLK_DIV_SHIFT); 161 162 /* PLL enter normal-mode */ 163 rk_clrsetreg(&cru->cru_mode_con, 164 GPLL_MODE_MASK | APLL_MODE_MASK, 165 GPLL_MODE_NORM << GPLL_MODE_SHIFT | 166 APLL_MODE_NORM << APLL_MODE_SHIFT); 167 } 168 169 /* Get pll rate by id */ 170 static uint32_t rkclk_pll_get_rate(struct rk3036_cru *cru, 171 enum rk_clk_id clk_id) 172 { 173 uint32_t refdiv, fbdiv, postdiv1, postdiv2; 174 uint32_t con; 175 int pll_id = rk_pll_id(clk_id); 176 struct rk3036_pll *pll = &cru->pll[pll_id]; 177 static u8 clk_shift[CLK_COUNT] = { 178 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, 0xff, 179 GPLL_MODE_SHIFT, 0xff 180 }; 181 static u32 clk_mask[CLK_COUNT] = { 182 0xffffffff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xffffffff, 183 GPLL_MODE_MASK, 0xffffffff 184 }; 185 uint shift; 186 uint mask; 187 188 con = readl(&cru->cru_mode_con); 189 shift = clk_shift[clk_id]; 190 mask = clk_mask[clk_id]; 191 192 switch ((con & mask) >> shift) { 193 case GPLL_MODE_SLOW: 194 return OSC_HZ; 195 case GPLL_MODE_NORM: 196 197 /* normal mode */ 198 con = readl(&pll->con0); 199 postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; 200 fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT; 201 con = readl(&pll->con1); 202 postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; 203 refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; 204 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; 205 case GPLL_MODE_DEEP: 206 default: 207 return 32768; 208 } 209 } 210 211 static ulong rockchip_mmc_get_clk(struct rk3036_cru *cru, uint clk_general_rate, 212 int periph) 213 { 214 uint src_rate; 215 uint div, mux; 216 u32 con; 217 218 switch (periph) { 219 case HCLK_EMMC: 220 case SCLK_EMMC: 221 con = readl(&cru->cru_clksel_con[12]); 222 mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT; 223 div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT; 224 break; 225 case HCLK_SDIO: 226 case SCLK_SDIO: 227 con = readl(&cru->cru_clksel_con[12]); 228 mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT; 229 div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT; 230 break; 231 default: 232 return -EINVAL; 233 } 234 235 src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate; 236 return DIV_TO_RATE(src_rate, div) / 2; 237 } 238 239 static ulong rockchip_mmc_set_clk(struct rk3036_cru *cru, uint clk_general_rate, 240 int periph, uint freq) 241 { 242 int src_clk_div; 243 int mux; 244 245 debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate); 246 247 /* mmc clock auto divide 2 in internal */ 248 src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq); 249 250 if (src_clk_div > 128) { 251 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq); 252 assert(src_clk_div - 1 < 128); 253 mux = EMMC_SEL_24M; 254 } else { 255 mux = EMMC_SEL_GPLL; 256 } 257 258 switch (periph) { 259 case HCLK_EMMC: 260 case SCLK_EMMC: 261 rk_clrsetreg(&cru->cru_clksel_con[12], 262 EMMC_PLL_MASK | EMMC_DIV_MASK, 263 mux << EMMC_PLL_SHIFT | 264 (src_clk_div - 1) << EMMC_DIV_SHIFT); 265 break; 266 case HCLK_SDIO: 267 case SCLK_SDIO: 268 rk_clrsetreg(&cru->cru_clksel_con[11], 269 MMC0_PLL_MASK | MMC0_DIV_MASK, 270 mux << MMC0_PLL_SHIFT | 271 (src_clk_div - 1) << MMC0_DIV_SHIFT); 272 break; 273 default: 274 return -EINVAL; 275 } 276 277 return rockchip_mmc_get_clk(cru, clk_general_rate, periph); 278 } 279 280 static ulong rk3036_clk_get_rate(struct clk *clk) 281 { 282 struct rk3036_clk_priv *priv = dev_get_priv(clk->dev); 283 284 switch (clk->id) { 285 case 0 ... 63: 286 return rkclk_pll_get_rate(priv->cru, clk->id); 287 default: 288 return -ENOENT; 289 } 290 } 291 292 static ulong rk3036_clk_set_rate(struct clk *clk, ulong rate) 293 { 294 struct rk3036_clk_priv *priv = dev_get_priv(clk->dev); 295 ulong new_rate, gclk_rate; 296 297 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); 298 switch (clk->id) { 299 case 0 ... 63: 300 return 0; 301 case HCLK_EMMC: 302 case SCLK_EMMC: 303 new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate, 304 clk->id, rate); 305 break; 306 default: 307 return -ENOENT; 308 } 309 310 return new_rate; 311 } 312 313 static struct clk_ops rk3036_clk_ops = { 314 .get_rate = rk3036_clk_get_rate, 315 .set_rate = rk3036_clk_set_rate, 316 }; 317 318 static int rk3036_clk_ofdata_to_platdata(struct udevice *dev) 319 { 320 struct rk3036_clk_priv *priv = dev_get_priv(dev); 321 322 priv->cru = dev_read_addr_ptr(dev); 323 324 return 0; 325 } 326 327 static int rk3036_clk_probe(struct udevice *dev) 328 { 329 struct rk3036_clk_priv *priv = dev_get_priv(dev); 330 331 rkclk_init(priv->cru); 332 333 return 0; 334 } 335 336 static int rk3036_clk_bind(struct udevice *dev) 337 { 338 int ret; 339 struct udevice *sys_child; 340 struct sysreset_reg *priv; 341 342 /* The reset driver does not have a device node, so bind it here */ 343 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", 344 &sys_child); 345 if (ret) { 346 debug("Warning: No sysreset driver: ret=%d\n", ret); 347 } else { 348 priv = malloc(sizeof(struct sysreset_reg)); 349 priv->glb_srst_fst_value = offsetof(struct rk3036_cru, 350 cru_glb_srst_fst_value); 351 priv->glb_srst_snd_value = offsetof(struct rk3036_cru, 352 cru_glb_srst_snd_value); 353 sys_child->priv = priv; 354 } 355 356 #if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP) 357 ret = offsetof(struct rk3036_cru, cru_softrst_con[0]); 358 ret = rockchip_reset_bind(dev, ret, 9); 359 if (ret) 360 debug("Warning: software reset driver bind faile\n"); 361 #endif 362 363 return 0; 364 } 365 366 static const struct udevice_id rk3036_clk_ids[] = { 367 { .compatible = "rockchip,rk3036-cru" }, 368 { } 369 }; 370 371 U_BOOT_DRIVER(rockchip_rk3036_cru) = { 372 .name = "clk_rk3036", 373 .id = UCLASS_CLK, 374 .of_match = rk3036_clk_ids, 375 .priv_auto_alloc_size = sizeof(struct rk3036_clk_priv), 376 .ofdata_to_platdata = rk3036_clk_ofdata_to_platdata, 377 .ops = &rk3036_clk_ops, 378 .bind = rk3036_clk_bind, 379 .probe = rk3036_clk_probe, 380 }; 381