xref: /openbmc/u-boot/arch/arm/mach-imx/mx7ulp/pcc.c (revision d024236e5a31a2b4b82cbcc98b31b8170fc88d28) 
1 /*
2  * Copyright (C) 2016 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <div64.h>
9 #include <asm/io.h>
10 #include <errno.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/pcc.h>
13 #include <asm/arch/sys_proto.h>
14 
15 #define PCC_CLKSRC_TYPES 2
16 #define PCC_CLKSRC_NUM 7
17 
18 static enum scg_clk pcc_clksrc[PCC_CLKSRC_TYPES][PCC_CLKSRC_NUM] = {
19 	{	SCG_NIC1_BUS_CLK,
20 		SCG_NIC1_CLK,
21 		SCG_DDR_CLK,
22 		SCG_APLL_PFD2_CLK,
23 		SCG_APLL_PFD1_CLK,
24 		SCG_APLL_PFD0_CLK,
25 		USB_PLL_OUT,
26 	},
27 	{	SCG_SOSC_DIV2_CLK,  /* SOSC BUS clock */
28 		MIPI_PLL_OUT,
29 		SCG_FIRC_DIV2_CLK,  /* FIRC BUS clock */
30 		SCG_ROSC_CLK,
31 		SCG_NIC1_BUS_CLK,
32 		SCG_NIC1_CLK,
33 		SCG_APLL_PFD3_CLK,
34 	},
35 };
36 
37 static struct pcc_entry pcc_arrays[] = {
38 	{PCC2_RBASE, DMA1_PCC2_SLOT,		CLKSRC_NO_PCS, PCC_NO_DIV},
39 	{PCC2_RBASE, RGPIO1_PCC2_SLOT,		CLKSRC_NO_PCS, PCC_NO_DIV},
40 	{PCC2_RBASE, FLEXBUS0_PCC2_SLOT,	CLKSRC_NO_PCS, PCC_NO_DIV},
41 	{PCC2_RBASE, SEMA42_1_PCC2_SLOT,	CLKSRC_NO_PCS, PCC_NO_DIV},
42 	{PCC2_RBASE, DMA1_CH_MUX0_PCC2_SLOT,	CLKSRC_NO_PCS, PCC_NO_DIV},
43 	{PCC2_RBASE, SNVS_PCC2_SLOT,		CLKSRC_NO_PCS, PCC_NO_DIV},
44 	{PCC2_RBASE, CAAM_PCC2_SLOT,		CLKSRC_NO_PCS, PCC_NO_DIV},
45 	{PCC2_RBASE, LPTPM4_PCC2_SLOT,		CLKSRC_PER_BUS, PCC_NO_DIV},
46 	{PCC2_RBASE, LPTPM5_PCC2_SLOT,		CLKSRC_PER_BUS, PCC_NO_DIV},
47 	{PCC2_RBASE, LPIT1_PCC2_SLOT,		CLKSRC_PER_BUS, PCC_NO_DIV},
48 	{PCC2_RBASE, LPSPI2_PCC2_SLOT,		CLKSRC_PER_BUS, PCC_NO_DIV},
49 	{PCC2_RBASE, LPSPI3_PCC2_SLOT,		CLKSRC_PER_BUS, PCC_NO_DIV},
50 	{PCC2_RBASE, LPI2C4_PCC2_SLOT,		CLKSRC_PER_BUS, PCC_NO_DIV},
51 	{PCC2_RBASE, LPI2C5_PCC2_SLOT,		CLKSRC_PER_BUS, PCC_NO_DIV},
52 	{PCC2_RBASE, LPUART4_PCC2_SLOT,		CLKSRC_PER_BUS, PCC_NO_DIV},
53 	{PCC2_RBASE, LPUART5_PCC2_SLOT,		CLKSRC_PER_BUS, PCC_NO_DIV},
54 	{PCC2_RBASE, FLEXIO1_PCC2_SLOT,		CLKSRC_PER_BUS, PCC_NO_DIV},
55 	{PCC2_RBASE, USBOTG0_PCC2_SLOT,		CLKSRC_PER_PLAT, PCC_HAS_DIV},
56 	{PCC2_RBASE, USBOTG1_PCC2_SLOT,		CLKSRC_PER_PLAT, PCC_HAS_DIV},
57 	{PCC2_RBASE, USBPHY_PCC2_SLOT,		CLKSRC_NO_PCS, PCC_NO_DIV},
58 	{PCC2_RBASE, USB_PL301_PCC2_SLOT,	CLKSRC_NO_PCS, PCC_NO_DIV},
59 	{PCC2_RBASE, USDHC0_PCC2_SLOT,		CLKSRC_PER_PLAT, PCC_HAS_DIV},
60 	{PCC2_RBASE, USDHC1_PCC2_SLOT,		CLKSRC_PER_PLAT, PCC_HAS_DIV},
61 	{PCC2_RBASE, WDG1_PCC2_SLOT,		CLKSRC_PER_BUS,	PCC_HAS_DIV},
62 	{PCC2_RBASE, WDG2_PCC2_SLOT,		CLKSRC_PER_BUS, PCC_HAS_DIV},
63 
64 	{PCC3_RBASE, LPTPM6_PCC3_SLOT,		CLKSRC_PER_BUS, PCC_NO_DIV},
65 	{PCC3_RBASE, LPTPM7_PCC3_SLOT,		CLKSRC_PER_BUS, PCC_NO_DIV},
66 	{PCC3_RBASE, LPI2C6_PCC3_SLOT,		CLKSRC_PER_BUS, PCC_NO_DIV},
67 	{PCC3_RBASE, LPI2C7_PCC3_SLOT,		CLKSRC_PER_BUS, PCC_NO_DIV},
68 	{PCC3_RBASE, LPUART6_PCC3_SLOT,		CLKSRC_PER_BUS, PCC_NO_DIV},
69 	{PCC3_RBASE, LPUART7_PCC3_SLOT,		CLKSRC_PER_BUS, PCC_NO_DIV},
70 	{PCC3_RBASE, VIU0_PCC3_SLOT,		CLKSRC_NO_PCS, PCC_NO_DIV},
71 	{PCC3_RBASE, DSI0_PCC3_SLOT,		CLKSRC_PER_BUS, PCC_HAS_DIV},
72 	{PCC3_RBASE, LCDIF0_PCC3_SLOT,		CLKSRC_PER_PLAT, PCC_HAS_DIV},
73 	{PCC3_RBASE, MMDC0_PCC3_SLOT,		CLKSRC_NO_PCS, PCC_NO_DIV},
74 	{PCC3_RBASE, PORTC_PCC3_SLOT,		CLKSRC_NO_PCS, PCC_NO_DIV},
75 	{PCC3_RBASE, PORTD_PCC3_SLOT,		CLKSRC_NO_PCS, PCC_NO_DIV},
76 	{PCC3_RBASE, PORTE_PCC3_SLOT,		CLKSRC_NO_PCS, PCC_NO_DIV},
77 	{PCC3_RBASE, PORTF_PCC3_SLOT,		CLKSRC_NO_PCS, PCC_NO_DIV},
78 	{PCC3_RBASE, GPU3D_PCC3_SLOT,		CLKSRC_PER_PLAT, PCC_NO_DIV},
79 	{PCC3_RBASE, GPU2D_PCC3_SLOT,		CLKSRC_PER_PLAT, PCC_NO_DIV},
80 };
81 
82 int pcc_clock_enable(enum pcc_clk clk, bool enable)
83 {
84 	u32 reg, val;
85 
86 	if (clk >= ARRAY_SIZE(pcc_arrays))
87 		return -EINVAL;
88 
89 	reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;
90 
91 	val = readl(reg);
92 
93 	clk_debug("pcc_clock_enable: clk %d, reg 0x%x, val 0x%x, enable %d\n",
94 		  clk, reg, val, enable);
95 
96 	if (!(val & PCC_PR_MASK) || (val & PCC_INUSE_MASK))
97 		return -EPERM;
98 
99 	if (enable)
100 		val |= PCC_CGC_MASK;
101 	else
102 		val &= ~PCC_CGC_MASK;
103 
104 	writel(val, reg);
105 
106 	clk_debug("pcc_clock_enable: val 0x%x\n", val);
107 
108 	return 0;
109 }
110 
111 /* The clock source select needs clock is disabled */
112 int pcc_clock_sel(enum pcc_clk clk, enum scg_clk src)
113 {
114 	u32 reg, val, i, clksrc_type;
115 
116 	if (clk >= ARRAY_SIZE(pcc_arrays))
117 		return -EINVAL;
118 
119 	clksrc_type = pcc_arrays[clk].clksrc;
120 	if (clksrc_type >= CLKSRC_NO_PCS) {
121 		printf("No PCS field for the PCC %d, clksrc type %d\n",
122 		       clk, clksrc_type);
123 		return -EPERM;
124 	}
125 
126 	for (i = 0; i < PCC_CLKSRC_NUM; i++) {
127 		if (pcc_clksrc[clksrc_type][i] == src) {
128 			/* Find the clock src, then set it to PCS */
129 			break;
130 		}
131 	}
132 
133 	if (i == PCC_CLKSRC_NUM) {
134 		printf("Not find the parent scg_clk in PCS of PCC %d, invalid scg_clk %d\n", clk, src);
135 		return -EINVAL;
136 	}
137 
138 	reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;
139 
140 	val = readl(reg);
141 
142 	clk_debug("pcc_clock_sel: clk %d, reg 0x%x, val 0x%x, clksrc_type %d\n",
143 		  clk, reg, val, clksrc_type);
144 
145 	if (!(val & PCC_PR_MASK) || (val & PCC_INUSE_MASK) ||
146 	    (val & PCC_CGC_MASK)) {
147 		printf("Not permit to select clock source val = 0x%x\n", val);
148 		return -EPERM;
149 	}
150 
151 	val &= ~PCC_PCS_MASK;
152 	val |= ((i + 1) << PCC_PCS_OFFSET);
153 
154 	writel(val, reg);
155 
156 	clk_debug("pcc_clock_sel: val 0x%x\n", val);
157 
158 	return 0;
159 }
160 
161 int pcc_clock_div_config(enum pcc_clk clk, bool frac, u8 div)
162 {
163 	u32 reg, val;
164 
165 	if (clk >= ARRAY_SIZE(pcc_arrays) || div > 8 ||
166 	    (div == 1 && frac != 0))
167 		return -EINVAL;
168 
169 	if (pcc_arrays[clk].div >= PCC_NO_DIV) {
170 		printf("No DIV/FRAC field for the PCC %d\n", clk);
171 		return -EPERM;
172 	}
173 
174 	reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;
175 
176 	val = readl(reg);
177 
178 	if (!(val & PCC_PR_MASK) || (val & PCC_INUSE_MASK) ||
179 	    (val & PCC_CGC_MASK)) {
180 		printf("Not permit to set div/frac val = 0x%x\n", val);
181 		return -EPERM;
182 	}
183 
184 	if (frac)
185 		val |= PCC_FRAC_MASK;
186 	else
187 		val &= ~PCC_FRAC_MASK;
188 
189 	val &= ~PCC_PCD_MASK;
190 	val |= (div - 1) & PCC_PCD_MASK;
191 
192 	writel(val, reg);
193 
194 	return 0;
195 }
196 
197 bool pcc_clock_is_enable(enum pcc_clk clk)
198 {
199 	u32 reg, val;
200 
201 	if (clk >= ARRAY_SIZE(pcc_arrays))
202 		return -EINVAL;
203 
204 	reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;
205 	val = readl(reg);
206 
207 	if ((val & PCC_INUSE_MASK) || (val & PCC_CGC_MASK))
208 		return true;
209 
210 	return false;
211 }
212 
213 int pcc_clock_get_clksrc(enum pcc_clk clk, enum scg_clk *src)
214 {
215 	u32 reg, val, clksrc_type;
216 
217 	if (clk >= ARRAY_SIZE(pcc_arrays))
218 		return -EINVAL;
219 
220 	clksrc_type = pcc_arrays[clk].clksrc;
221 	if (clksrc_type >= CLKSRC_NO_PCS) {
222 		printf("No PCS field for the PCC %d, clksrc type %d\n",
223 		       clk, clksrc_type);
224 		return -EPERM;
225 	}
226 
227 	reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;
228 
229 	val = readl(reg);
230 
231 	clk_debug("pcc_clock_get_clksrc: clk %d, reg 0x%x, val 0x%x, type %d\n",
232 		  clk, reg, val, clksrc_type);
233 
234 	if (!(val & PCC_PR_MASK)) {
235 		printf("This pcc slot is not present = 0x%x\n", val);
236 		return -EPERM;
237 	}
238 
239 	val &= PCC_PCS_MASK;
240 	val = (val >> PCC_PCS_OFFSET);
241 
242 	if (!val) {
243 		printf("Clock source is off\n");
244 		return -EIO;
245 	}
246 
247 	*src = pcc_clksrc[clksrc_type][val - 1];
248 
249 	clk_debug("pcc_clock_get_clksrc: parent scg clk %d\n", *src);
250 
251 	return 0;
252 }
253 
254 u32 pcc_clock_get_rate(enum pcc_clk clk)
255 {
256 	u32 reg, val, rate, frac, div;
257 	enum scg_clk parent;
258 	int ret;
259 
260 	ret = pcc_clock_get_clksrc(clk, &parent);
261 	if (ret)
262 		return 0;
263 
264 	rate = scg_clk_get_rate(parent);
265 
266 	clk_debug("pcc_clock_get_rate: parent rate %u\n", rate);
267 
268 	if (pcc_arrays[clk].div == PCC_HAS_DIV) {
269 		reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;
270 		val = readl(reg);
271 
272 		frac = (val & PCC_FRAC_MASK) >> PCC_FRAC_OFFSET;
273 		div = (val & PCC_PCD_MASK) >> PCC_PCD_OFFSET;
274 
275 		/*
276 		 * Theoretically don't have overflow in the calc,
277 		 * the rate won't exceed 2G
278 		 */
279 		rate = rate * (frac + 1) / (div + 1);
280 	}
281 
282 	clk_debug("pcc_clock_get_rate: rate %u\n", rate);
283 	return rate;
284 }
285